SEMTECH SC2542

SC2542 High Performance Wide Input Range Dual Synchronous Buck Controller POWER MANAGEMENT Description Features SC2542 is a high performance dual PWM controller. It is ‹ Independent dual-switcher-outputs designed to convert a widely ranged battery rail down to ‹ Integrated 5V standby output with over 50mA two independent output rails. The PWM operation of the capability two channels are 180 degrees out of phase which can ‹ Wide input voltage range: 6.5V ~ 28V greatly reduce the size and the cost of the input capaci- ‹ Adjustable output voltage down to 0.75V tors. Synchronous buck PWM topology and voltage mode ‹ Light load efficiency enhancement control allow fast transient response and flexible com- ‹ Programmable skip mode operation ponent selection for easy designs. A 5V standby regula- ‹ Flexible power sequencing with enable and power tor is integrated. A 10V internal linear regulator provides good output the bias for the controller, and this voltage is optimized ‹ Synchronous buck topology with voltage mode for gate drivers to deliver high efficiency. control ‹ Out of phase operation to reduce cost of input The light load efficiency can be greatly improved by turn- capacitor ing off the low side MOSFET upon reversal of inductor ‹ 10V internal regulator for gate driver to deliver high current. There is no need for a current sensing resistor efficiency because the MOSFET on resistance is used as the sens- ing element. Under extreme light load conditions, the ‹ Programmable switching frequency: device will operate in a pulse skip mode. The switching 100KHz ~ 300KHz frequency can be dropped significantly to a level pro- ‹ Full protection: UVLO, OVP, and programmable OCP grammed by external resistors. The battery energy is bet- ‹ No need for current sense resistor ter utilized with these efficiency enhancement schemes. ‹ Low standby operating current (200µA typical) ‹ Low shut down current (100nA typical) The power sequencing is fully supported including inde- ‹ 28 lead TSSOP package with exposed die pad pendent start up and power good output. In shutdown (EDP) mode the controller only draws 100nA from the supply. ‹ Fully WEEE package and RoHS Compliant The controller also offers full protection features for the conditions of under voltage, over voltage, and over cur- Applications rent. The switching frequency is adjustable from 100KHz ‹ Notebook computer system power to 300KHz. TSSOP-28-EDP package is offered. ‹ Systems with 6.5V ~ 28V input ‹ Network and telecom systems ‹ Other portable devices Typical Application Circuit VIN+ SC2542 1 28 VIN AGND VCC 5VSBY VO1 2 27 VCC 5VSBY 3 26 ENABLE EN ROSC 4 25 PWGRD STBY MODE STBY PWRGD 5 24 FB1 FB1 FB2 FB2 6 23 ERROUT1 ERROUT2 7 22 MINSET1 MINSET2 8 21 SS1 SS2 VIN+ VIN+ 9 20 ILIM1 ILIM2 10 19 BST1 BST2 11 18 DRVH1 DRVH2 VO1 (3.3V/10A) VO2 (5V/10A) 12 17 PHASE1 PHASE2 13 16 DRVL1 DRVL2 FB1 VCC FB2 14 15 PGND PVCC TH-PAD Revision: August 24, 2005 1 www.semtech.com SC2542 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Sm ymbo Ms aximu Unit BV ST1, BST2 to PGND 3V 8 BST VV IN to PGND 2V 8 IN ILIM1 and ILIM2 to PGND VV IN VCC and PVCC to PGND 1V 4 PGND to AGND ±V 0.3 BST1 to PH1, BST2 to PH2, -V 0.3 to 14 DRVH1 to PH1, DRVH2 to PH2 DRVL1, DRVL2 to PGND -V 0.3 to VCC EN to PGND -V 0.3 to VIN All other pins to AGND -V 0.3 to VCC OT perating Junction Temperature Range -C 40 to +150 ° J ST torage Temperature Range -C 60 to +150 ° STG Thermal Resistance, Junction to Case θ 3W °C/ JC Thermal Resistance, Junction to Ambient θ 3W 5 °C/ JA LT ead Temperature (Soldering) 10 Sec. 2C 60 ° SOLDER PHASE to AGND pulse (100nS) peak voltage -V 3 DRVL to AGND pulse (100nS) peak voltage -V 3 Note: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required. Electrical Characteristics Unless specified: TA = 25°C, VIN = 16V, FS = 200KHz. Ps arameter Tn estCondition Mp i Tx y Mt a Uni Undervoltage Lockout Sg tart Threshold V5 CC risin 55 .2 55 . 5V .7 Us VLO Hysteresis h0 ysteresi 4V 0 m PowerSupply Operating Current (I - I)F SS1/SS2, EN = high,=7 200 KHz 1A2 m IN PVCC S PF VCC Operating Current=4 200KHz, 1nF on TG and BG 1A m S VV CC Regulated >0 12V 1V IN VA CC Load RegulationL2 oad current 0 to 20m % Se tandby Supply Current S0 TBY mod 20 0 3A 5 µ Se hutdown Supply CurrentS1 hutdown mod 00 . 1A µ © 2005 Semtech Corp. 2 www.semtech.com SC2542 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: TA = 25°C, VIN = 16V, FS = 200KHz. Ps arameter Tn estCondition Mp i Tx y Mt a Uni PowerSupply (Cont.) 5A VSBY Regulation 05 A < load current < 50m 45 .8 5V .15 5V VSBY Line Regulation =1 12V ~ 28V % IN 5VSBY Current Limit Threshold 1A 00 m MA inimum 5VSBY Output Capacitance01 A < load current < 50m µF Main SwitcherOutput LV ine Regulation 75 V < VIN < 28 0% . LT oad Regulation 0A < load current < 10A, MINSE 0% .5 pin float O, utput Voltage Accuracy Without feedback attenuation 00 .73505 .75 0V .76 T = -40º C to +85º C A ENABLE EN High Threshold Voltage 2V EN Low Threshold Voltage 0V .6 STBY STBY High Threshold Voltage 2V STBY Low Threshold Voltage 0V .6 SoftStart Soft Start Charge Current 8A 5 µ Soft Start Discharge Current 1A 5 µ Disable Threshold Voltage for DRVL Pull below this level, turning ON 0V .65 Out of Tri-state DRVL (Turn ON low side FET) ErrorAmplifier VT oltage Feedback Reference =5 -40º C to +85º C 00 .7305 .75 0V .76 A Input Bias Current (Source) 2A µ (1) Open Loop Gain 7B 0 d (1) Unity Gain Bandwidth 3z MH Output Source/Sink Current 1A m (1) Slew Rate 10 00pF capacitive loading 1S V/µ (1) PWM Comparator to Output Delay 7S 5 n  2005 Semtech Corp. 3 www.semtech.com SC2542 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: TA = 25°C, VIN = 16V, FS = 200KHz. Ps arameter Tn estCondition Mp i Tx y Ms a Unit Oscillator Frequency Range per Phase 10 00 3z 0 KH OR scillator Frequency per Phase = 73K Ω 10 75 25 1 2z 4 KH OSC Minimum OFF Time 30 004S 0 n Oscillator Ramp Peak Voltage 3V .0 Oscillator Ramp Valley Voltage 1V CurrentLimit ILIM Source Current 90111A µ ILIM Offset Voltage 2V m MINSET MV inimum Pulse Width Set = 16V, R = 107K Ω 1S µ IN MV inimum Pulse Width Set = 8V, R = 107K Ω 2S µ IN MV inimum Pulse Width Set = 16V, R = 53K Ω 5S 00 n IN Duty Cycle PR WM 1 & 2 Maximum Duty Cycle = 73k Ω 9% 0 OSC PR WM 1 & 2 Minimum Duty Cycle = 73k Ω 0% OSC Driver Hk igh Side Gate Drive (Source) S5 ource/Sin 0A . Lk ow Side Gate Drive (Source) S5 ource/Sin 0A . GC ate Drive Rise Time =0 1000pF 3S n OUT GC ate Drive Fall Time =0 1000pF 3S n OUT Dead Time 8S 0 n OVP Oe VP Threshold Voltage F9 eedback voltag 0V .8 PowerGood Tg hreshold Voltage F5 B1 & FB2 risin 0V .67 Tg hreshold Voltage F7 B1 & FB2 fallin 0V .5 PA ower Good Sink CapabilityS4 ink 1m 0V .  2005 Semtech Corp. 4 www.semtech.com SC2542 POWER MANAGEMENT Pin Configuration Ordering Information (1) Pe artNumber Packag Temp.Range (T ) TOP V TOP VI IEW EW A (2) SC2542TETRTT5 SSOP-28-EDP -40 to +8 VI VIN N 1 1 AG AGND ND 28 28 Sd C2542EVB Evaluation Boar VCC VCC 2 2 27 27 5 5VSBY VSBY Notes: EN EN 3 3 26 26 RO ROSC SC (1) Only available in tape and reel packaging. A reel STBY STBY 4 4 25 25 PW PWRG RGD D contains 2500 devices. FB1 FB1 5 5 24 24 FB2 FB2 (2) Lead free product. This product is fully WEEE and RoHS compliant. ERRO ERROUT UT1 1 6 6 23 23 ERRO ERROUT UT2 2 MINSET1 MINSET1 7 7 22 22 MI MIN NS SE ET T2 2 SS1 SS1 8 8 21 21 SS2 SS2 ILI ILIM M1 1 9 9 20 20 IL ILIIM M2 2 BST BST1 1 10 10 19 19 BST2 BST2 DRVH1 DRVH1 11 11 18 18 DRVH2 DRVH2 P PH HASE1 ASE1 12 12 17 17 PHAS PHASE2 E2 DRVL DRVL1 1 13 13 16 16 DRVL DRVL2 2 PG PGN ND D 14 14 15 15 PVCC PVCC ( (2 28 Pi 8 Pin T n TS SSO SOP P- -E ED DP) P) Marking Information (TOP VIEW) SC254 SC2542TE 2TE yy yyww ww xxx xxxxxx xxx yyww = Date Code (Example: 0012) xxxxx = Semtech Lot No. (Example: P94A01) © 2005 Semtech Corp. 5 www.semtech.com SC2542 POWER MANAGEMENT Pin Descriptions Pe in # Pn in Nam Pin Functio 1NV. I Input supply voltage. The range is from 6.5V to 28V 2C VC 10V regulator output. Supply voltage for chip bias and gate drivers. 3E ENABL TTL compatible level. Then ENABLE is low, all outputs are disabled. Typical shitdown current is 100nA. 4Y STB When pulled low the 10V regulator and both switcher outputs are disabled. Only 5VSBY is available. Quiescent current is typically 200µA. 51F. B Negative input of the error amplifier for output 1 61E. RROUT Error amplifier output for buck converter 1 71 MINSET Connect external resistor from this pin to AGND to set the minimum pulse width in discontinuous mode. This also sets the operating frequency in skip mode for a given load. 81 SS An external capacitor connected from this pin to AGND sets the soft-start time. Disable output1 by pulling this pin below 0.65V. 91 ILIM An external resistor connected from this pin to PHASE1 sets the overcurrent shutdown trip point. 11 0 BST Boost capacitor connection for OUTPUT1 high side gate drive. Connect an external capacitor as shown in the Typical Application Circuit. 11 1 DRVH Gate drive for the high side MOSFET of OUTPUT1. 180 degree out of phase with DRVH2. 11 2P. HASE Phase node for output 1 11 3D. RVL Low side gate drive for output 1 1D 4P. GN Power ground of low-side drivers 1C 5P. VC Supply voltage for low-side gate drivers 12 6D. RVL Low-side gate drive for output 2 12 7P. HASE Phase node for output 2 12 8 DRVH Gate drive for the high side MOSFET of OUTPUT2. 180 degree out pf phase with GDRVH1. 12 9 BST Boost capacitor connection for the OUTPUT2 high side gate drive. Connect an external capacitors as shown in the Typical Application Circuit. 22 0 ILIM An external resistor connected from this pin to PHASE2 sets the overcurrent shutdown trip point. 22 1 SS An external capacitor connected from this pin to AGND sets the soft-start time. Disable output 2 by pulling this pin below 0.65V. 22 2 MINSET Connect one external resistor from this pin to AGND to set the minimum pulse width in discontinuous mode. This also sets the operating frequency in skip mode for a given load. 22 3E. RROUT Error amplifier output for buck converter 2 22 4F. B Negative input of the error amplifier for output 2  2005 Semtech Corp. 6 www.semtech.com SC2542 POWER MANAGEMENT Pin Descriptions (Cont.) Pe in # Pn in Nam Pin Functio 2D 5 PWRG Open collector output. Pulls low when eigher output is below the power good threshold level. 2C 6 ROS An external resistor connected from this pin to AGND sets oscillator frequency. 2Y 75. VSB 5V regulator output. Disabled when ENABLE is pulled low 2D 8A. GN Analog signal ground -L THERMA Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected PAD internally.  2005 Semtech Corp. 7 www.semtech.com SC2542 POWER MANAGEMENT Block Diagram (Only Channel-1 shown) PVCC BST1 Protect 1 DRVH1 PHASE1 Ramp1 PHASE1 + Oscillator PVCC ROSC PVCC Ramp PWM generator S Q - DRVL1 CLK1 Minumin R Pulse Generator Protect 1 ERROUT1 FB1 MINSET1 FB1 E/A - VCC OUT Skip 85uA 0.75V 0.65V + Mode + + dector VCC OUT OUT R - - Protect 1 SS1 3R R S/Q 10u A ILIM1 UVLO - OCP OUT 15uA + VCC FB1 VCC + OVP VIN OUT 5VSBY - 0.89V ENABLE 0.75V EN ON/OFF PWRGD 5V Band 10V Band LDO Gap 1 LDO Gap 2 0.75V 0.675V VCC + STBY STBY UVLO FB1 - OUT OVP OCP FB2 AGND - © 2005 Semtech Corp. 8 www.semtech.com SC2542 POWER MANAGEMENT Applications Information General Description DR DRVH 1 VH 1 The SC2542 is a fixed frequency dual voltage mode step- down PWM controller for adapter or battery operated systems. The two channels of the controller operate 180 DRV DRVL 1 L 1 degrees out of phase, which results in lower input cur- rent ripple and reduces the amount of input filtering ca- pacitance needed. PHA PHAS SE 1 E 1 Synchronous and “pulse skip” mode of operation are adopted in both switching channels to increase overall IL 1 IL 1 efficiency. The internal light-load current detection cir- cuit and minimum pulse setting circuit determine the mode of operation and the “pulse skip” duration. To extend battery life, the SC2542 features shutdown mode, where the quiescent current is 100nA (typical), Figure 2. Typical waveforms of SPWM mode. and standby mode, where the 5V linear standby regula- tor is active and quiescent current is typically 200uA. To enhance light-load efficiency, “pulse skip” mode (SKIP) can be enabled by placing a resistor from the RMIN pin The functional block diagram is shown in Figure 1. to ground. For normal loads the controller will operate in SPWM mode, but when the load is light enough, the pulse widths of the top and bottom MOSFETs will be adjusted INPUT by the load condition. The SC2542 employs a simple circuit to detect the load condition by monitoring the EN PHASE node of the circuit. The PHASE node will start to 5VSBY 5V Power in Linear Sequence STBY turn positive if the inductor current begins to reverse (I Regulator L < 0) signaling a light-load condition. VO2 VO1 Channel 1 Channel 2 If a light-load condition is detected the SC2542 will op- SMPS SMPS erate in SKIP mode. Similar to a buck converter in dis- continuous conduction mode (DCM), the converter will PWG try to reduce its duty cycle as the load decreases. For Power Good example, it would start out with continuous conduction mode (CCM) duty cycle values, but as the load decreases, the duty cycle would try to shrink to zero as shown in Figure 1. The functional block diagram. Figure 3. However, the SC2542 clamps the DCM duty cycle to a minimum percentage (set by the RMIN resistor) Skip Mode Operation of the CCM value. If the DCM duty cycle falls below this percentage, SKIP mode will be active. When the RMIN pin is left open, the SC2542 operates as a synchronous PWM (SPWM) controller with the bot- tom MOSFET ON whenever the top MOSFET is OFF. Fig- ure 2 shows the typical SPWM waveforms. © 2005 Semtech Corp. 9 www.semtech.com SC2542 POWER MANAGEMENT Applications Information (Cont.) SKIP mode therefore leads to a reduction in the average switching frequency. MOSFET switching losses and driver Vo Vo Vo Vo losses, both of which are proportional to frequency, are << Duty Duty D D D D significantly reduced at these light loads resulting in in- Vi Vi Vi Vi creased efficiency. SKIP mode also reduces the circulat- No Nom mi in na al l ing currents associated with SPWM mode. The test re- sult (Figure 5) shows the efficiency improvement in SKIP dut duty y D DC CM M CCM CCM mode. Mi Min n. . dut duty y cl cla am mp p 100.00% Iou Iout t 80.00% 60.00% 40.00% Skip Mode Synchronous CCM 20.00% 0.00% Figure 3. Conventional Buck converter duty cycle vs. 10 100 1000 10000 Io(mA) load current. Figure 4 further explains the basic theory of SKIP mode operation. When the load current falls from CCM to DCM, Figure 5. Skip mode improves light load efficiency. the duty cycle of DRVH (output of PWM comparator) will shrink. The programmed minimum pulse width of Figure 6 (a) and (b) show typical waveforms of SKIP mode SC2542 with the DRVH signal to get the TG (top side at different light load conditions. The frequency can ac- MOSFET gate driver) pulse output. The TG output will tually fall very low at very light loads. When the switching maintain at least the programmed minimum pulse width. frequency drops to the acoustic frequency range, very This TG pulse pumps up the output voltage causing the minor acoustic frequency noise might be generated, but Error Amplifier output to decrease as the output voltage the level of the noise is usually very low due to very small moves up. The PWM comparator may skip several cycles flux excursion in the magnetics. The acoustic noise can before sending another pulse when the output voltage be totally avoided by using well constructed magnetics drops down. The BG (bottom side MOSFET gate driver) or by knowing the minimum system loads to program the output will terminate whenever the inductor current SKIP mode operation accordingly. crosses zero. Ram Ramp p Ve Veo o TG TG I I L L BG BG Vo Vo Vo Vo TG TG DRVH DRVH I Inducto nductor r M Mi in n pul pulse se Cu Curr rren ent t DRVL DRVL Figure 4. The waveforms of SKIP mode operation. (a) © 2005 Semtech Corp. 10 www.semtech.com Efficienc 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 SC2542 POWER MANAGEMENT Applications Information (Cont.) 350 TG TG 300 250 BG BG 200 Vo Vo 150 100 I Indu nduc ct to or r 50 Cu Curre rren nt t Rosc(KOHM) (b) Figure 6. Typical waveforms of SKIP mode. Figure 7. Switching frequency versus Rosc. Power on Sequence Frequency Setting After applying the input voltage and with STBY and EN The frequency of the SC2542 is user- programmable. inputs high, Vcc and 5VSTBY will rise. When Vcc rises The oscillator of SC2542 can be programmed with an above the UVLO threshold both switcher outputs will also external resistor from the Rosc pin to ground. The step- ramp up. By pulling the SS pins low, the two switcher down controller is capable of operating up to 300KHz. outputs can be disabled, with Vcc and 5VSTBY maintain- The relationship between oscillation frequency versus ing regulation. Vcc will turn off when STBY is pulled low, oscillation resistor is shown in Figure 7. with 5VSTBY maintaining regulation. And finally 5VSTBY The advantages of using constant frequency operation will turn off when EN is pulled low, and the device will be include simple passive component selection and ease of in shutdown mode. feedback compensation. Before setting the operating fre- quency, the following trade-offs should be considered. Mt ode Logic inpu 1) Passive component size NormalMode: BothPWMrails inregulation Setting ENpinto logic high 2) Circuitry efficiency 5V STBYrailinregulation Setting STBYpinto logic high 3) EMI condition V railinregulation No pulldownofSS CC 4) Minimum switch on time 5) Maximum duty ratio Standby Mode: Setting ENpinto logic high 5V STBYrailinregulation Setting STBYpinto logic high For a given output power, the sizes of the passive com- Shutdown Mode: Setting ENpinto logic low ponents are inversely proportional to the switching frequency, whereas MOSFETs/Diodes switching losses are proportional to the operating frequency. Other issues Soft Start such as heat dissipation, packaging, and cost also need to be considered. The frequency bands for signal trans- During start-up, the reference voltage of the error ampli- mission should be avoided because of EM interference. fier equals 30% of the voltage on Css (soft-start capaci- tor) which is connected between the SS pin and ground. When the controller is enabled (by pulling EN pin or STBY © 2005 Semtech Corp. 11 www.semtech.com Fsw(KHz) SC2542 POWER MANAGEMENT Applications Information (Cont.) is an internal current source that flows out of the ILIM pin high), an internal 84uA current source, Iss, (soft start pin which will generate a voltage drop on the setting resis- current) will charge the soft-start capacitor gradually. The tor. When the sum of the setting resistor voltage and PWM output starts pulsing when the soft start voltage the MOSFET drain to source voltage is less then zero, reaches 1V. the OCP condition will be flagged. This functionality is depicted in Figure 8. This soft start scheme will ensure the duty cycle increases slowly, therefore limiting the in rush current into the out- The following formula is used to set the OCP level: put capacitor and also ensuring the inductor does not saturate. The soft start capacitor will eventually be charged up to 2.5V. 10µAR×= ILIM IL_( PEAK×RDS ON) When OCP is tripped, both high side and low side MOS- The soft-start sequence is initiated when EN pin or STBY FETs will be turned off and this condition is latched. At pin is high and Vcc > 5.5V or during recovery from a fault the same time, the soft start cap will be discharged by condition ( OCP, OVP, or UVLO). the internal current source of 15uA. When the Vss drops bellow 0.65V, the DRVL pin will go high again. The period of start up can be programmed by the soft start capacitor: To avoid switching noise during the phase node commu- CV ×2.5 SS tation, a 100nS blanking time is built in after the low T = SS 84 µA side MOSFET is turned on, as shown in Fig. 9. Shutdown VCC When the EN pin or STBY pin is pulled low, an internal 10uA 15uA current source discharges the soft-start capacitor DRVH and DRVH/DRVL signals stop pulsing. The output volt- OUTPUT age ramps down at a rate determined by the load condi- ILIM + OCP tion. Out - DRVL The SC2542 can also be shutdown by pulling down di- rectly on the SS pin. The designer needs to consider the slope of the SS pin voltage and choose a suitable pull down resistor to prevent the output from undershooting. Shutdown can also be triggered under an OCP condition. Figure 8. Block diagram of over current protection. When an OCP condition is detected, DRVH and DRVL will stop pulsing and enter a “tri-state shutdown” with the output voltage ramping down at a rate determined by T TG G the load condition. The internal 15uA current source will begin discharging the soft-start capacitor and when the soft-start voltage reaches 0.65V, DRVL will go high. I I L L Over Current Protection (OCP) The inductor current is sensed by using the low side 100 100n nS S OC OCP P MOSFET Rds(on). After low side MOSFET is turned on, Bl Bla an nk ki ing ng the OCP comparator starts monitoring the voltage drop across the MOSFET. The OCP trip level is programmed Figure 9. OCP comparator timing chart. by a resistor from the ILIM pin to the phase node. There © 2005 Semtech Corp. 12 www.semtech.com SC2542 POWER MANAGEMENT Applications Information (Cont.) target. External pull up is required for the PWRGD pin, Under Voltage Lock Out (UVLO) and the pull up resistor should be chosen such that the pin does not sink more than 1mA when PWRGD is low. The UVLO circuitry monitors Vcc and the soft start begins once Vcc ramps up above 5.5V. There is a built in 400mV hysteresis voltage for the UVLO ramp down threshold. Main Control Loop Design The gate driver output will be in “tri-state”(both high side and low side MOSFET off) once Vcc ramps down bellow The goal of compensation is to shape the frequency re- 5.1V (typical), and the soft start cap will be discharged by sponse of the buck converter to achieve a better DC internal 15uA current sink. accuracy and a faster transient response, while main- taining the loop stability. The block diagram in Figure 10 represents the control Over Voltage Protection (OVP) loop of a buck converter designed with the SC2542. The control loop consists of a compensator, a PWM modula- The OVP circuitry monitors the feedback voltages, If ei- tor, and an LC filter. ther feedback voltage exceeds 0.89V, the OVP condition is registered. Under this condition, the DRVH pins will be The LC filter and the PWM modulator represent the small pulled low, and the DRVL pins will be pulled high. This will signal model of the buck converter operating at fixed create a “crow bar” condition for the input power rail in switching frequency. The transfer function of the model case the high side MOSFET is failed short. The crow bar is given by: operation may trip the input supply to prevent the load from seeing more voltage. V V 1+ SR C O IN ESR = • 2 V V 1+ SL /R + S LC C m Minimum Pulse Width Setting In skip mode operation, the top FET driver always sends out a pulse which is wider than the DCM pulse to keep REF the load in regulation. This forces the SC2542 to oper- + L Vo PW EA ate in skip mode and improves the light load efficiency. MODULATOR REF - To set minimum pulse, one can use a simple formula: C ERROUT Tpulse • Vin Z Resr Rmin(kΩ ) = 150(pC) Z Setting Tpulse is 80% of normal pulse wide. For example, with 24V input, 5V output and 200khz op- erating frequency. The normal pulse is 1.04 uS. To set Tpulse = 0.83uS, one can use: Figure 10. Block diagram of the control loop. where V is the input voltage, V is the amplitude of the Tpulse • Vin 0.83µS X 24V IN m Rmin = = = 133kΩ internal ramp, and R is the equivalent load. 150(pC) 150(pC) Power Good The model is a second order system with a finite DC gain, a complex pole pair at Fo, and an ESR zero at Fz, as The power good is an open collector output. The PWRGD shown in Figure 11. The locations of the poles and zero pin is pulled low at start up if any of the two feedback are determined by: voltages are below 90% of the regulation level. The ramp down threshold of the signal is 80% of the regulation  2005 Semtech Corp. 13 www.semtech.com SC2542 POWER MANAGEMENT Applications Information (Cont.) A resistive divider is used to program the output voltage. 1 FO = The top resistor, Rtop, of the divider in Figure 12 can be 2π LCO chosen from 20kΩ to 30kΩ. Then the bottom resistor, Rbot, is found from: 1 FZ = 0.75V 2R π ESRCO R = ∗R BOT TOP V − 0.75V O where 0.75V is the internal reference voltage of the The compensator in Figure 10 includes an error ampli- SC2542. fier and compensation networks Zf and Zs. It is imple- The other components of the compensator can be cal- mented by the circuit in Figure 12. The compensator pro- culated using following design procedure: vides an integrator, double poles, and double zeros. As shown in Figure 11, the integrator is used to boost the (1). Plot the converter gain, including LC filter and PWM gain at low frequency. Two zeros are introduced to com- modulator. pensate excessive phase lag at the loop gain crossover (2). Select the open loop crossover frequency Fc located due to the integrator (-90deg) and the complex pole pair at 10% to 20% of the switching frequency. (-180deg). Two high frequency poles are designed to com- (3). Use the first compensator pole Fp1 to cancel the pensate the ESR zero and to attenuate high frequency ESR zero. noise. (4). Have the second compensator pole Fp2 at half the switching frequency to attenuate the switching ripple and high frequency noise. (5). Place the first compensator zero Fz1 at or below 50% of the power stage resonant frequency Fo. (6). Place the second compensator zero Fz2 at or below the power stage resonant frequency Fo. A MathCAD program is available upon request for the calculation of the compensation parameters. Design Procedure for a Step-down Power Converter Selection criteria and design procedures for the follow- ing parameters are described: Figure 11. Bode plots for control loop design. 1) Output inductor (L) type and value 2) Output capacitor (Co) type and value 3) Input capacitor (Cin) type and value C2 4) Power MOSFETs C1 R2 C3 R3 5) Current sensing and limiting circuit 6) Voltage sensing circuit Rtop Vo 7) Loop compensation network - Vc Out + The following step-down converter specifications are E/A needed: Rbot 0.75V Figure 12. Compensation network.  2005 Semtech Corp. 14 www.semtech.com SC2542 POWER MANAGEMENT Applications Information (Cont.) Input voltage range: Vin,min and Vin,max tance value. The inductance varies with temperature and Input voltage ripple (peak-to-peak): DVin DC current. It is a good engineering practice to re-evalu- Output voltage: Vo ate the resultant current ripple at the rated DC output Output voltage accuracy: e current. Output voltage ripple (peak-to-peak): DVo c) Current rating: The saturation current of the inductor Nominal output (load) current: Io should be at least 1.5 times of the peak inductor cur- Maximum output current limit: Io,max rent under all conditions. Output (load) current transient slew rate: dIo/dt (A/s) Output Capacitor (Co) and Vout Ripple η Circuit efficiency: The output capacitor provides output current filtering in Inductor (L) and Ripple Current steady state and serves as a reservoir during load tran- sient. The output capacitor can be modeled as an ideal Both step-down controllers in the SC2542 operate in capacitor in series with its parasitic ESR and ESL as shown synchronous continuous-conduction mode (CCM) in Figure 13. regardless except in light-load mode. The output inductor selection/design is based on the output DC and transient requirements. Both output current and voltage ripples are reduced with larger inductance but it takes longer to change the inductor current during load transients. Conversely smaller inductance results Figure 13. An equivalent circuit of output. in lower DC copper losses but the AC core losses (flux swing) and the winding AC resistance losses are higher. If the current through the branch is ib(t), the voltages A compromise is to choose the inductance such that across the terminals will then be: t peak-to-peak inductor ripple-current is 20% to 30% of 1( dib t) VOO () t=+ V ib() t dt+Lesl +Resrib() t . the rated output load current. ∫ Co dt 0 Assuming that the inductor current ripple (peak-to- peak) value is δ Io, the inductance value will then be: This basic equation illustrates the effects of ESR, ESL, and Co on the output voltage. VD O(1− ) L = δIF OS The first term is the DC voltage across Co at time t = 0. The second term is the voltage variation caused by the The peak current in the inductor becomes: charge balance between the load and the converter out- (1+ δ / 2) * I O put. The third term is voltage ripple due to ESL and the and RMS current is: fourth term is the voltage ripple due to ESR. The total output voltage ripple is then a vector sum of the last 2 δ I = I 1+ three terms. Since the inductor current is a triangular L,rms O 12 waveform with peak-to-peak value ä*Io, the ripple-volt- The followings are to be considered when choosing in- age caused by inductor current ripples is: ductors. δI O a) Inductor core material: For higher efficiency applica- ΔV ≈ , C 8C f O s tions above 300 KHz, ferrite, Kool-Mu and polypermalloy materials should be used. Low-cost powdered iron cores the ripple-voltage due to ESL is: can be used for cost sensitive-applications below 300 δI O ΔV = L f , KHz but with attendant higher core losses. ESL esl s D b) Select inductance value: Sometimes the calculated and the ESR ripple-voltage is: inductance value is not available off-the-shelf. The de- ΔV = R δI ESR esr O signer can choose the adjacent (larger) standard induc-  2005 Semtech Corp. 15 www.semtech.com SC2542 POWER MANAGEMENT Applications Information (Cont.) Remark 1: High frequency ceramic capacitors may not Aluminum capacitors (e.g. electrolytic) have high capaci- carry most of the ripple current. It also depends on the tances and low ESL. The ESR has the dominant effect capacitor value. Only when the capacitor value is set on the output ripple voltage. It is therefore very impor- properly, the effect of ceramic capacitor low ESR starts tant to minimize the ESR. Other types to choose are to be significant. For example, if a 10uF, 4mÙ ceramic solid OS-CON, POSCAP, and tantalum. capacitor is connected in parallel with 2x1500uF, 90mÙ electrolytic capacitors, the ripple current in the ceramic When determining the ESR value, both the steady state capacitor is only about 42% of the current in the electro- ripple-voltage and the dynamic load transient need to be lytic capacitors at the ripple frequency. If a 100uF, 2mÙ considered. To meet the steady state output ripple-volt- ceramic capacitor is used, the ripple current in the ce- age spec, the ESR should satisfy: ramic capacitor will be about 4.2 times of that in the ΔV O R < electrolytic capacitors. When two 100uF, 2mÙ ceramic ESR1 δI O capacitors are used, the current ratio increases to 8.3. To limit the dynamic output voltage overshoot/under- In this case most of the ripple current flows in the ce- shoot within a (say 3%) of the steady state output volt- ramic decoupling capacitor. The ESR of the ceramic ca- age from no load to full load, the ESR value should sat- pacitors will then determine the output ripple-voltage. isfy: Remark 2: The total equivalent capacitance of the filter 3%V O R < ESR2 bank is not simply the sum of all the paralleled capaci- I O tors. The total equivalent ESR is not simply the parallel Then, the required ESR value of the output capacitors combination of all the individual ESR either. Instead they should be: should be calculated using the following formula. 22 22 2 Resr = min{Resr1,Resr2 }. () RR++ ω C C (C+C) 11 AB 1A1B 1A 1B C = EQ() ω 22 2 () RC++ RC ω C C(C+C 11 AA 11 BB 1A1B 1A 1B) The voltage rating of aluminum capacitors should be at 22 2 2 2 least 1.5Vo. The RMS current ripple rating should also RR() R++ R ω C C (R C+R C) 11 AB 1A 1B 1A 1B 1B 1B 1A 1A C = EQ() ω 22 22 2 be greater than: () RR++ ω C C (C+C) δIO 11 AB 1A1B 1A 1B 23 where R1a and C1a are the ESR and capacitance of elec- trolytic capacitors, and R1b and C1b are the ESR and Usually it is necessary to have several capacitors of the capacitance of the ceramic capacitors, respectively (Fig- same type in parallel to satisfy the ESR requirement. The ure 13) voltage ripple caused by the capacitor charge/discharge should be an order of magnitude smaller than the volt- age ripple caused by the ESR. To guarantee this, the ca- pacitance should satisfy: 10 C > O 2π f R C1a C1b Ceq s ESR In many applications, several low ESR ceramic capaci- tors are added in parallel with the aluminum capacitors in order to further reduce ESR and improve high fre- R1a R1b Req quency decoupling. Because the values of capacitance and ESR are usually different in ceramic and aluminum capacitors, the following remarks are made to clarify some practical issues. Figure 14. Equivalent RC branch.  2005 Semtech Corp. 16 www.semtech.com SC2542 POWER MANAGEMENT Applications Information (Cont.) Req and Ceq are both functions of frequency. For rigor- ous design, the equivalent ESR should be evaluated at the ripple frequency for voltage ripple calculation when both ceramic and electrolytic capacitors are used. If R1a = R1b = R1 and C1a = C1b = C1, then Req and Ceq will be frequency-independent and Req = 1/2 R1 and Ceq = 2C1. Input Capacitor (Cin) The input supply to the converter usually comes from a pre-regulator. Since the input supply is not ideal, input capacitors are needed to filter the current pulses at the switching frequency. A simple buck converter is shown in Figure 14. L1 Q1 Figure 15. Typical waveforms at converter input. Rin Resr D1 Co Ro It can be seen that the current in the input capacitor VDC pulses with high di/dt. Capacitors with low ESL should be used. It is also important to place the input capacitor Cin close to the MOSFETs on the PC board to reduce trace inductances around the pulse current loop. Figure 14. A simple model for the converter input. The RMS value of the capacitor current is approximately:  In Figure 14 the DC input voltage source has an internal 2 δ D  2 II=+ D (1 )(1− )+ (1−D) impedance Rin and the input capacitor Cin has an ESR Cin O  12 η  of Resr. MOSFET and input capacitor current waveforms,  ESR voltage ripple and input voltage ripple are shown in The power dissipated in the input capacitors is then: Figure 15. 2 PI = R Cin Cin esr For reliable operation, the maximum power dissipation in the capacitors should not result in more than 10°C of temperature rise. Many manufacturers specify the maxi- mum allowable ripple current (ARMS) rating of the ca- pacitor at a given ripple frequency and ambient tempera- ture. The input capacitance should be high enough to handle the ripple current. It is common practice that mul- tiple capacitors are placed in parallel to increase the ripple current handling capability. Sometimes meeting tight input voltage ripple specifica- tions may require the use of larger input capacitance. At full load, the peak-to-peak input voltage ripple due to  2005 Semtech Corp. 17 www.semtech.com SC2542 POWER MANAGEMENT Applications Information (Cont.) losses and conduction losses of the MOSFET are directly the ESR is: related to the total gate charge (Cg) and channel on-re- δ ΔV = R (1+ ) I sistance (Rds(on)). In order to judge the performance of ESR ESR O 2 MOSFET, the product of the total gate charge and on- The peak-to-peak input voltage ripple due to the capaci- resistance is used as a figure of merit (FOM). Transistors tor is: with the same FOM follow the same curve in Figure 16 DI O ΔV ≈ C C f IN S 50 From these two expressions, CIN can be found to meet the input voltage ripple specification. In a multi-phase 40 converter, channel interleaving can be used to reduce Cg() 100?Rds ripple. The two step-down channels of the SC2542 op- Cg() 200?Rds erate at 180 degrees from each other. If both step-down 20 Cg() 500?Rds channels in the SC2542 are connected to the same in- put rail, the input RMS currents will be reduced. Ripple cancellation effect of interleaving allows the use of 1 0 smaller input capacitors. 0 5 10 15 20 1 Rds 20 When two channels with a common input are inter- On-resistance (mOhm) FOM:100*10^{-12} leaved, the total DC input current is simply the sum of FOM:200*10^{-12} the individual DC input currents. The combined input cur- FOM:500*10^{-12} rent waveform depends on duty ratio and the output current waveform. Assuming that the output current ripple is small, the following formula can be used to esti- Figure 16. Figure of Merit curves. mate the RMS value of the ripple current in the input capacitor. The closer the curve is to the origin, the lower is the FOM. This means lower switching loss or lower conduction loss Let the duty ratio and output current of Channel 1 and or both. It may be difficult to find MOSFET with both low Channel 2 be D1, D2 and Io1, Io2, respectively. Cg and low Rds(on). Usually a trade-off between Rds(on)and Cg has to be made. If D1<0.5 and D2<0.5, then: MOSFET selection also depends on applications. In many applications, either switching loss or conduction loss domi- 2 2 I ≈ D I + D I CIN 1 O1 2 O2 nates for a particular MOSFET. For synchronous buck converters with high input to output voltage ratios, the top MOSFET is hard switched but conducts with very low If D1>0.5 and (D1-0.5) < D2<0.5, then: duty cycle. The bottom switch conducts at high duty cycle 22 but switches at near zero voltage. For such applications, II≈+ 0.5 OO 11 (D−0.5)(I1+IO2)+(D2−D1+0.5)IO2 CIN MOSFET with low Cg are used for the top switch and MOSFET with low Rds(on) are used for the bottom switch. If D1>0.5 and D2 < (D1-0.5) < 0.5, then: MOSFET power dissipation consists of: 22 2 a) conduction loss due to the channel resistance Rds(on); ID ≈ (1+D2−1)(I +I )+− (1 D)I +− (1 D)I CIN O12 O 2 O1 1 O2 b) switching loss due to the switch rise time tr and fall time tf; and c) the gate loss due to the gate resistance RG. Choosing Power MOSFETs Main considerations in selecting the MOSFETs are power dissipation, MOSFETs cost, and packaging. Switching  2005 Semtech Corp. 18 www.semtech.com Gate Charge (nC) SC2542 POWER MANAGEMENT Applications Information (Cont.) Top Switch the switch current to reach its full-scale value Ids,.and Qgd is the charge needed to charge gate-to-drain (Miller) The RMS value of the top switch current is calculated as: capacitance when Vds is falling. 2 Switching losses occur during the time interval [t1, t3]. δ II=+ D(1 ) Qr 1, ms O Defining tr = t3-t1 and tr can be approximated as: 12 () QQ gs2 + R gdgt T = The conduction losses are then: r VV cc − gsp P =I 2 TC Q1,rms R DS(ON) where Rgt is the total resistance from the driver supply Rds(on) varies with temperature and gate-source voltage. rail to the gate of the MOSFET. It includes the gate driver Curves showing Rds(on) variations can be found in manu- internal impedance Rgi, external resistance Rge and the facturers’ data sheet. From the Si4860 datasheet, Rds gate resistance Rg within the MOSFET: (on) is less than 8mΩ when Vgs is greater than 10V. R =R +R +R GT GI GE G However Rds(on) increases by 50% as the junction tem- Vgsp is the Miller plateau voltage shown in Figure17. perature increases from 25°C to 110°C. Similarly an approximate expression for tf is: The switching losses can be estimated using the simple formula: () QQ + R gs2 gd gt T = f V 1 δ gsp P=+ () tt (1+ )I V f TS r f O IN S 22 Only a portion of the total losses Pg = QgVccfs is dissi- where tr is the rise time and tf is the fall time of the pated in the MOSFET package. Here Qg is the total gate switching process. Different manufactures have differ- charge specified in the datasheet. The power dissipated ent definitions and test conditions for tr and tf. To clarify within the MOSFET package is: these, we sketch the typical MOSFET switching charac- R G P = Q V f teristics under clamped inductive mode in Figure 17 TG G CC S R GT The total bottom switch losses are then: P =P +P +P T TC TS TG If the input supply of the power converter varies over a wide range, then it will be necessary to weigh the relative importance of conduction and switching losses. This is because conduction losses are inversely proportional to the input voltage. Switching loss however increases with the input voltage. The total power loss of MOSFET should be calculated and compared for high-line and low-line cases. The worst case is then used for thermal design. Bottom Switch The RMS current in bottom switch is given by: Figure 17. MOSFET switching characteristics 2 δ II=− (1 D)(1+ ) Qr 2, ms O 12 In Figure 17, Qgs1 is the gate charge needed to bring the gate-to-source voltage Vgs to the threshold voltage The conduction losses are then: Vgs_th. Qgs2 is the additional gate charge required for © 2005 Semtech Corp. 19 www.semtech.com SC2542 POWER MANAGEMENT Applications Information (Cont.) 2 PI = R bc Q2,RMS DS(ON) Power Stage 1) Separate the power ground from the signal ground. In where Rds(on) is the channel resistance of bottom MOS- SC2542 design, use an isolated local ground plane for FET. If the input voltage to output voltage ratio is high the controller and tie it to power grand. (e.g. Vin = 12V, Vo = 1.5V), the duty ratio D will be small. Since the bottom switch conducts with duty ratio (1-D), 2) Minimize the size of the high pulse current loop. Keep the corresponding conduction losses can be quite high. the top MOSFET, the bottom MOSFET and the input ca- Due to non-overlapping conduction between the top and pacitors within a small area with short and wide traces. the bottom MOSFET, the internal body diode or the ex- In addition to the aluminum energy storage capacitors, ternal Schottky diode across the drain and source termi- add multi-layer ceramic (MLC) capacitors from the input nals always conducts prior to the turn on of the bottom to the power ground to improve high frequency bypass. MOSFET. The bottom MOSFET switches on with only a diode voltage between its drain and source terminals. 3) Reduce high frequency voltage ringing. Widen and The switching loss is negligible due to near zero-voltage shorten the drain and source traces of the MOSFETs to switching. reduce stray inductances. Add a small RC snubber if nec- essary to reduce the high frequency ringing at the phase The gate losses are estimated as: node. Sometimes slowing down the gate drive signal also R G P = Q V f helps in reducing the high frequency ringing at the phase BG G CC S R GT node if the EMI is a concern for the system. The total bottom switch losses are then: 4) Shorten the gate drive trace. Integrity of the gate drive (voltage level, leading and falling edges) is impor- P =P +P B BC BG tant for circuit operation and efficiency. Short and wide gate drive traces reduce trace inductances. Bond wire Once the power losses for the top and bottom MOSFET inductance is about 2~3nH. If the length of the PCB are known, thermal and package design at component trace from the gate driver to the MOSFET gate is 1 inch, and system level should be done to verify that the maxi- the trace inductance will be about 25nH. If the gate drive mum die junction temperature (Tj,max, usually 125°C) is current is 2A with 10ns rise and falling times, the voltage not exceeded under the worst-case condition. The equiva- drops across the bond wire and the PCB trace will be lent thermal impedance from junction to ambient (θ ) JA 0.6V and 5V respectively. This may slow down the switch- should satisfy: ing transient of the MOSFET. These inductances may also ring with the gate capacitance. TT − JM ,, AX A MAX θ ≤ JA P LOSS 5) Put the decoupling capacitor for the gate drive power supplies (BST and PVCC) close to the IC and power ground. θ depends on the die to substrate bonding, packaging JA material, the thermal contact surface, thermal compound Control Section property, the available effective heat sink area, and the air flow condition (natural or forced convection). Actual 6) The frequency-setting resistor Rosc should be placed temperature measurement of the prototype should be close to Pin 23. Trace length from this resistor to the carried out to verify the thermal design. analog ground should be minimized. PC Board Layout Issues 7) Place the bias decoupling capacitor right across the VCC and analog ground AGND. Circuit board layout is very important for the proper op- eration of high frequency switching power converters. A power ground plane is required to reduce ground bounces. The followings are suggested for proper layout. © 2005 Semtech Corp. 20 www.semtech.com SC2542 POWER MANAGEMENT Typical Applications Schematic SC2542 U1 VIN+ C1 1uF/25V 1 28 VIN AGND 5VSBY 5VSBY C2 1uF/16V VCC C3 4.7uF 2 27 VCC 5VSBY R5 R4 73.2K 3 26 EN EN ROSC 10K 4 25 SB PWGRD STBY PWRGD 5 24 FB1 FB2 FB1 FB2 C4 12nF R6 41.2k R7 41.2k C5 12nF C6 1n F 6 23 C7 1n F ERROUT1 ERROUT2 R8 88.7k 7 22 R9 133k MINSET1 MINSET2 1uF/16V C8 C9 1uF/16V 8 21 SS1 SS2 15K R11 15K R10 9 20 ILIM1 ILIM2 C15 1uF/16V C16 1uF/16V 10 19 BST1 BST2 R12 0 0 R13 11 18 DRVH1 DRVH2 R14 2.2 R15 2.2 12 17 PHASE1 PHASE2 13 16 DRVL1 DRVL2 VCC VIN+ 14 15 VIN+ PGND PVCC C22 C12 C17 TH-PAD C10 C11 C13 C14 1uF/16V R22 Q1 Q2 0 VO1 VO2 4.7uH L2 L1 4.7uH R25 R16 R17 330 R19 R26 C20 C21 Q3 R18 C18 C19 28k Q4 4.7n F FB1 C26 330 2.2/n.p. 28k FB2 2.2/n.p. R20 4.7n F C25 C23 R21 C24 C28 2.2n/n.p. 8.25k 1n/n.p. C27 2.2n/n.p. 1n/n.p. 4.87k  2005 Semtech Corp. 21 www.semtech.com 470uF/4V 470uF/4V 10uF/25V 10uF/25V 0.1uF/25V Si4800 Si4800 GND Si4800 Si4800 0.1uF/25V 10uF/25V 10uF/25V 330uF/6.3V 330uF/6.3V SC2542 POWER MANAGEMENT Typical Applications Schematic - BOM Ry ef Qe t Re eferenc Pr artNumber/Valu Manufacture 11C5 1 1y uF, 25V, X5R, Ceramic, 080 An 26C5 2,C8,C9,C15,C16,C221y uF, 16V, X5R, Ceramic , 080 An 31C6 3 4y .7uF, 16V, X5R, Ceramic 120 An 42C3 4,C5 1y 2nF, Ceramic, 060 An 52C3 6, C7 1y nF, Ceramic 060 An 62C3 10, C170y .1nF, Ceramic 060 An 74C0 11,C12, C13,C141M 0uF, 25V, X5R, Ceramic, 121 Panasonic, ECJ4YB1E106 82Cp 18,C193L 30uF, 6.3V, 18mohm, PosCa Sanyo, 6TPE330MI 92Cp 20,C214L 70uF, 4V, 15mohm, PosCa Sanyo, 4TPE470MF 14 0C. 23, C24, C27, C28 N.P 12 1C3 25,C264y .7nF, Ceramic, 060 An 12 2Lm 1, L247 .7uH, 6.8A, 15moh Sumida, CDRH12 14 3Q0 1, Q2, A3, Q4Sy i480 Visha 11 4R3 4 7y 3.2K, 060 An 11 5R3 5 1y 0K, 060 An 12 6R3 6, R7 4y 1.2K, 060 An 11 7R3 8 8y 8.7K, 060 An 11 8R3 9 1y 33K, 060 An 12 9R3 10,R111y 5K, 060 An 23 0 R0 12, R13,R22 Any 22 1R3 14, R152y .2, 060 An 22 2R3 16,R192y 8K, 060 An 22 3R. 17, R18 N.P 21 4R3 20 8y .25K, 060 An 21 5R3 21 4y .87K, 060 An 22 6R3 25,R263y 30, 060 An 21 7U2 1 Sh C254 Semtec  2005 Semtech Corp. 22 www.semtech.com SC2542 POWER MANAGEMENT Typical Characteristics Gate waveform (SPWM Mode) Gate waveform (SKIP Mode) CH1: TG1 CH1: TG1 CH2: BG1 CH2: BG1 CH2: TG2 CH2: TG2 CH2: BG2 CH2: BG2 Start up Shutdown by pulling down SS pin voltage CH1: TG CH1: Vi CH2: BG CH2: Vcc CH3: Vss CH3: Vss CH4: Vo CH4: Vo Shutdown by pulling down EN/STBY pin voltage Transient response (3 ~ 8A CH1: TG CH1: Vo CH2: BG CH4: Io CH3: Vss CH4: Vo  2005 Semtech Corp. 23 www.semtech.com 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 SC2542 POWER MANAGEMENT Typical Characteristics (Cont.) Over current protection (5A/10mV) CH1: TG CH2: BG CH3: IL CH4: Vo Efficiency curve for Vout = 3.3V Operating frequency vs. Rosc V in=8V V in=16V 350 100% 300 80% 250 200 60% 150 40% 100 20% 50 0% 01 2 3 4 5 6 7 8 9 10 Ro s c( KOHM) Io(A ) Efficiency curve for SPWM Mode vs. SKIP Mode RILIM vs. OCP (Vin = 12V) 9 10 0.00% 8 8 0.00% 7 6 0.00% 6 4 0.00% skip m ode Synch ron iz e 2 0.00% 5 0.00% 4 10 100 10 00 100 00 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 Io(mA) RILIM(KOHM) © 2005 Semtech Corp. 24 www.semtech.com Effic ient Efficiency Fsw(KH z Io (A SC2542 POWER MANAGEMENT Typical Characteristics (Cont.) Icc vs. Vin (Ta = 25 Degree C) Frequency vs. Temp. (Rosc = 75kohm, Vin = 16V) 192 7.0 190 188 6.5 186 184 6.0 182 180 5.5 178 176 5.0 -40 -15 10 35 60 85 110 135 8 1012 1416 1820 2224 26 28 Temp. (Degree C) Vi n(V) Vcc vs. Vin (Ta = 25 Degree C) Minimum pulse width vs. Temp (Ta) 10.3 1060 10.1 1055 9.9 1050 9.7 1045 9.5 1040 12 14 16 18 20 22 24 26 28 -40 -20 0 20 406080 100 120 Vin (V) Temp. (Degree C) Vcc vs. Temp. (Ta = 25 Degree C) Dead time vs. Ta (Vin = 16V, DH falling to DL rising) 10 100 90 9.95 80 9.9 70 9.85 60 9.8 50 -40 -20 0 20 40 60 80 100 120 -40 -20 0 204060 80 100 120 Temp. (Ta Degree C) Ta (Degree C)  2005 Semtech Corp. 25 www.semtech.com Vcc (V) Fs (kHz) Vcc (V) Dead time Min pulse (nS) Icc (mA) SC2542 POWER MANAGEMENT Outline Drawing - TSSOP-28-EDP A D e N DIMENSIONS 2X E/2 INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX E1 E A - - .047 - - 1.20 - - PIN 1 A1 .000 .006 0.00 0.15 INDICATOR A2 .031 - .041 0.80 - 1.05 - - b .007 .012 0.19 0.30 c .003 - .008 0.09 - 0.20 ccc C 13 2 D .378 .382 .386 9.60 9.70 9.80 e/2 E1 .169 .173 .177 4.30 4.40 4.50 2X N/2 TIPS E .252 BSC 6.40 BSC B e .026 BSC 0.65 BSC F .210 .216 .220 5.35 5.50 5.60 H .112 .118 .122 2.85 3.00 3.10 D L .018 .024 .030 0.45 0.60 0.75 aaa C (.039) L1 (1.0) N 28 28 A2 A 01 0° - 8° 0° - 8° SEATING aaa PLANE .004 0.10 C A1 bbb .004 0.10 bxN ccc .008 0.20 bbb C A-B D F SEE DETAIL A SIDE VIEW EXPOSED PAD H H c GAGE PLANE 0.25 L BOTTOM VIEW 01 (L1) DETAIL A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS AND TO BE DETERMINED AT DATUM PLANE -A- -B- -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AET.  2005 Semtech Corp. 26 www.semtech.com SC2542 POWER MANAGEMENT Land Pattern - TSSOP-28-EDP F X DIMENSIONS DIM INCHES MILLIMETERS (.222) (5.65) C F .224 5.70 (C) H G Z G .161 4.10 H .126 3.20 P .026 0.65 Y X .016 0.40 Y .061 1.55 P Z .283 7.20 NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2005 Semtech Corp. 27 www.semtech.com