SEMTECH SC2516

SC2516 Complete Three-in-One DDR Power Solution With BF_CUT POWER MANAGEMENT Description Features The SC2516 is a fully integrated, Three-in-One DDR Con- ‹ Uses Latched BF_Cut from Intel Glue Chip to troller supplying power to the VDDQ, VTT and GMCH control regulators rails. Two synchronous buck controller provide the VDDQ ‹‹‹ External VDDQ divider allows DDRI or DDRII Com- ‹‹ and GMCH at high efficiency, while an internal linear regu- patibility lator supplies the termination voltage with 1.8A(min) ‹ High efficiency VDDQ switcher Source/Sink capability. ‹‹‹ External GMCH divider allows 1.5V or 1.25V pro- ‹‹ gramming ® defined Latched BF_Cut The SC2516 uses the Intel ‹ High efficiency GMCH switcher supplies pro- signal to comply with motherboard state transitions. The grammed output from the 5V or 3.3V rail regulator uses the 5VDUAL rail to supply VDDQ under all ‹ Single chip solution complies fully with ACPI power motherboard states, via the VDDQ switcher. The GMCH sequencing specifications regulator is slaved off the 5V main regulator, using a sepa- ‹ 1.8A (min) VTT Source/Sink capability rate UVLO on that rail. Additional logic and supervisory ‹ High current 1Amp gate driver for VDDQ switcher circuitry complete the functionality of this single chip DDR ‹ Independent thermal shutdown for VTT power solution in compliance with ACPI requirements. ‹ Fast transient response The MLP package with a copper pad provides excellent ‹ Space saving 22-pin MLP package with copper thermal impedance while keeping small footprint. VDDQ thermal pad for heatsinking to PC Board short circuit protection along with VTT current limit as well as two independent thermal shutdown circuits as- Applications sure safe operation under all fault conditions. ‹ Power Solution for DDR memory per Intel motherboard specification Typical Application Circuit ‹ High speed data line termination 12VCC 5Vdual 1 22 COMP PGND 2 21 FBVDDQ FBVDDQ BG VDDQ 3 20 SS/EN SS/EN TG 4 19 VTTGND BST VTT 5 18 5VSBY VTT 5VSBY FBVDDQ VDDQ 6 17 VDDQ COMP_GMCH 7 16 AGND BF_CUT 8 15 3VCC VTTFB TG_GMCH Latched BF_CUT VDDQ 9 14 REFSENS BG_GMCH 10 13 FB_GMCH GND_GMCH 11 12 SS_GMCH POK GMCH SC2516 FB_GMCH ATXPWR_OK FB_GMCH 1 Revision 8, May. 2005 www.semtech.com 23 TH_PAD SC2516 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Sm ymbo Ms aximu Unit SV upply Voltage, BST to AGND 2V 0 BST SV tandby Input Voltage 7V 5VSBY IO nputs I3 /5V VSTBY +0.3, AGND -0. AGND to PGND or LGND 0V .3 VI TT Output Current +A /- 2 O(VTT) o OT perating Ambient Temperature Range 0 to 70 C A o OT perating Junction Temperature 125 C J o Thermal Resistance Junction to Ambient θ 25 C/W JA o Thermal Resistance Junction to Case θ 4 C/W JC o ST torage Temperature Range -65 to 150 C STG TG/BG/TG_GMCH/BG_GMCH DC Voltage BV ST + 0.3, PGND -0.3 TG/BG/TG_GMCH/BG_GMCH AC Voltage BST + 1.0, PGND -4.0 V t < 100 nS (measured from 50% to 50%) ED SD Rating (Human Body Model) E2 S KV Electrical Characteristics o Unless specified: T = 25 C , 5VSBY = 5V A Pl arameter Ss ymbo Cn ondition Mp i Tx y Ms a Unit 5V VSBY Voltage 45 .5 5V .5 5VSBY B2 F_CUT low 16 1 QI uiescent Current mA Q(5VSBY) B8 F_CUT High 10 BF_CUT Threshold 0L .8T4 T 2V . P_OK Threshold 0L .8T4 T 2V . 5O VSBY Under Voltage Lockout UVL 27 .4 23 . V 5VSBY VV DDQ Feedback Reference 15 .23813 .21V .26 REF Vt DDQFI eedback Curren V=2 1.25V -A u FB FB SV S/EN Shutdown Threshold V3 DDQ/VTT @ Shutdown 05 .0V . EN(TH) o TT hermal Shutdown 150 C J-SHDN o Ts hermal ShutdownHT ysteresi 10 C J-HYST © 2005 Semtech Corp. 2 www.semtech.com SC2516 POWER MANAGEMENT Electrical Characteristics (Cont.) o Unless specified: T = 25 C, 5VSBY = 5V. A Pl arameter Ss ymbo Cn ondition Mp i Tx y Ms a Unit Switcher LI oad Regulation =2 0A to 10A 0% . VDDQ Of scillator Frequency 20 2525 5 2z 7 KH OSC SI oft Start Current V=0 800mV 25203A u SS SS Maximum Duty Cycle 70 5 8% OV vercurrent Trip Voltage %0 of VDDQ Setpoint 75708% TRIP TG op Gate Rise Time TG5 ate capacitance = 4000pF 2S n R TG op Gate Fall Time TG5 ate capacitance = 4000pF 2S n F BG ottom Gate Rise Time BG5 ate capacitance = 4000pF 3S n R BG ottom Gate Fall Time BG5 ate capacitance = 4000pF 3S n F Dt ead Time 20 0 508S n d EG rror Amplifier Transconductance 01 .8 1S .2 m m EA rror Amplifier Gain @ DC R=8 open 3B d EA COMP EG rror Amplifier Bandwidth 5z MH BW Error Amplifier Source Current F5 B = 0 , COMP = 1V 50758A u Error Amplifier Sink Current F0 B = 1.5V , COMP = 1V 70901A 1 u IV nternal Ramp P5 eak - to - Peak 0V .5 RAMP VTT LDO OT utput Voltage VV T =5 2.500V 10 .2315 .251V .26 VDDQ SI ource and Sink Currents V=8 2.500V -8 1. +A 1. VTT VDDQ SI ource and Sink Currents V=4 1.500V -4 1. +A 1. VTT VDDQ Load Regulation I=1 +1.8A to -1.8A -1+% ∆VTT/ ∆I VTT EA rror Amplifier Gain 7B 5 d EA_VTT CT urrent Limit VTB3 F_CUT = low A ILIM © 2005 Semtech Corp. 3 www.semtech.com SC2516 POWER MANAGEMENT Electrical Characteristics (Cont.) o Unless specified: T = 25 C,5VSBY = 5V. A Pl arameter Ss ymbo Cn ondition Mp i Tx y Ms a Unit GMCH Switcher GV MCH Feedback Reference 15 .23813 .21V .26 REF_GMCH GI MCH Feedback current V=2 1.25V -A u FB_GMCH FB_GMCH LI oad Regulation =2 0A to 5A 0% . GMCH Of scillator Frequency 20 2525 5 2z 7 KH OSC SI oft start current V=8 200mV 120 1A u SS_GMCH SS Maximum Duty Cycle 70 5 8% TG op Gate Rise Time TG0 ate capacitance = 2000pF 4S n R TG op Gate Fall Time TG0 ate capacitance = 2000pF 4S n F BG ottom Gate Rise Time BG0 ate capacitance = 2000pF 4S n R BG ottom Gate Fall Time BG0 ate capacitance = 2000pF 4S n F Dt ead Time 55 0 801S 2 n d EG rror Amplifier Transconductance 01 .8 1S .2 m m EA rror Amplifier Gain @ DC 3B 8 d EA EG rror Amplifier Bandwidth 1z MH BW EV rror Amplifier Sink/Source Current =0 0 - 1.5V, COMP = 1V 65709A u FB_GMCH IV nternal Ramp P5 eak - to - Peak 0V .5 RAMP Pin Configuration Ordering Information Pe art Numbers Packag (1) SC2516MLTR MLP-22 (1),(2) SC2516MLTRT MLP-22 Notes: (1) Only available in tape and reel packaging. A reel contains 3000 devices. (2) Lead free package. Device is fully WEEE and RoHS compliant. Note: Pin 23 is the thermal Pad on the bottom of the device © 2005 Semtech Corp. 4 www.semtech.com SC2516 POWER MANAGEMENT Pin Descriptions Pe in# Pn inNam PinFunctio 1P COM Compensation pin for the PWM transconductance amplifier for the VDDQ Switcher. 2Q FBVDD Feedback for the VDDQ regulator. Connect to the VDDQ sense at the point of load. 3NS. S/E Soft start capacitor to GND. Pull low to disable controller 4DVT TTGN VT return. Connect to copper plane carrying VTT return current. The trace connecting to this pin must be able to carry 2 Amps. 5T VT VTT Regulator output. Regulates to 1/2 VDDQ. Sources or sinks 1.8 Amps. The trace connecting to this pin must be able to carry 2 Amps. 6QVT DD VDDQ power input to VT LDO. The trace connecting to this pin must be able to carry 2 Amps. 7D AGN Analog ground. Compensation components and the Soft Start Capacitor connect to this ground. 8B VTTF Sense input for the VTT regulator. Connect to Point of Load for the VTT rail. 9S REFSN Sense input for the VDDQ rail. VTT will be regulated to 1/2 of its voltage. Connect to Point of Load, where the VREF for the memory is generated. 1H 0 FB_GMC Sense input for the GMCH. Connect to Point of Load for the GMCH rail. 1H 1 SS_GMC Soft start for GMCH switcher . Connect a capacitor to GND. 1K 2P. O Connect to power OK signal from ATX power 1H 3 GND_GMC Gate Drive return Ground for the GMCH regulator. Connect to Source of bottom FET. 1H 4B. G_GMC Bottom FET Gate drive for the GMCH regulator 1H 5T. G_GMC Top FET Gate drive for the GMCH regulator 1T 6B. F_CU Latched BF_CUT input from Glue Chip 1H 7 COMP_GMC Compensation pin for the PWM transconductance amplifier for the GMCH Switcher 1Y 85. VSB Connect to 5VSTBY input 1T 9 BS The Top and Bottom Gate drive bus.Generated using bootstrap diode/capacitor. An additional diode is also required to trap the peak Bootstrap voltage for the BG drive. (see typical application circuit) 2G 0T. Top FET gate drive 2G 1B. Bottom FET gate drive 2D 2P. GN Gate drive return. Keep this pin close to bottom FET source 2D 3 TH_PA Copper pad on bottom of chip used for heatsinking. It must be connected to ground plane under IC. © 2005 Semtech Corp. 5 www.semtech.com SC2516 POWER MANAGEMENT Block Diagram © 2005 Semtech Corp. 6 www.semtech.com SC2516 POWER MANAGEMENT Timing Diagram VCC_R VCC_Ra ail il ATX _PO ATX _POK K BF_C BF_CUT UT SS SS/E /EN N TG TG BG BG VDDQ VDDQ VTT VTT SS_G SS_GM MCH CH TG TG_ _G GM MC CH H BG_ BG_G GMC MCH H GMC GMCH H S5 S5 S0 S0 S3 S3 S0 S0 S S5 5 © 2005 Semtech Corp. 7 www.semtech.com SC2516 POWER MANAGEMENT Application information Short Circuit Protection Short Circuit Protection Short Circuit Protection Short Circuit Protection Short Circuit Protection Description Short circuit protection is implemented by sensing the The SEMTECH SC2516 DDR power supply controller is VDDQ output voltage. If it falls to 75% (typical) of its the latest and most complete, Three in One switching nominal voltage, as sensed by the FB pin, the TG and BG and linear regulator controller, providing the necessary pins are latched off and the VDDQ switcher is shutdown. functions to comply with S3 and S5 sleep state signals It will shutdown the VTT also, since the VTT regulator is generated by the Desktop Computer Motherboards. The fed from the VDDQ bus. To recover from the short circuit SC2516 uses the Latched BF_CUT input signal which is protection mode, either the 5VSBY rail has to be recycled, R generated externally on Intel P4 Motherboard glue chip or the SS/EN pin must be pulled below 0.3V and to comply with the power sequencing requirements. released to restart VDDQ switcher operation. Logically, the BF_CUT signal can be represented as: GMCH Power Section BF _CUT =S3•P _OK The SC2516 Switching controller supplies a 1.5V or 1. (For details of the Latched BF_CUT signal definition, refer 25V GMCH (Graphic Memory Control Hub) voltage via a to Intel documentation). standard synchronous BUCK converter typically Where S3 is the input to the Silver-box Supply for Suspend connected to the 5VCC or 3.3VCC power rail from Silver- to RAM, (S3=1 for Suspend to RAM) and P_OK is a signal box supply. Base on the basic advantage of switching generated by the Silver-box supply, indicating that all rails mode controller, The GMCH output current can support are within specification. up to 20A. S3 and S5 States S3 and S5 States S3 and S5 States S3 and S5 States S3 and S5 States During S3 and S5 sleep states, The operation of the R Power Sequencing Power Sequencing Power Sequencing Power Sequencing Power Sequencing VDDQ and VTT is governed by the intel specifications Since the Chip-Set supply should come up before the with regards to the BF_CUT signal. The timing diagram Active Memory cycle, the GMCH supply is sequenced with demonstrates the state of the controller and each of the rising edge of the P_OK signal from Sliver-box supply. the VDDQ, VTT and GMCH supplies during S3 and S5 Thus the GMCH regulator drivers are on when P_OK signal transitions is greater than its respective threshold. The external MOSFET gates are pulled low when P_OK signal is lower VDDQ Power Section than its threshold. Thus the GMCH is disabled during S3 SC2516 architecture eliminates the need for the Back- and S5 (See timing diagram). Feed Cut MOSFET, since the VDDQ is always supplied from the same input voltage bus (5V dual). The SC2516 VTT Rail is capable of driving a 4000pf capacitor in 25ns (typical, The VTT termination voltage is supplied via an internal top gate). This drive capability allows 15-20A DC load on sink/source linear regulator when BF_CUT is low, and the VDDQ supply from the 5V main input rail. the P_OK signal has met its threshold voltage and SS/ EN voltage reaches to 1V. When BF_CUT is high, the VTT Power Sequencing Power Sequencing Power Sequencing Power Sequencing Power Sequencing termination voltage is not needed and is thus tri-stated. Once BF_CUT signal low and P_OK signal goes high, The The VTT linear regulator is capable of sourcing and sinking VDDQ supply will be activated with S0 as well. The SS/ 1.8 Amps (Minimum). It is recommended that one should EN pin voltage is charged by internal constant current use at least 470uF low ESR capacitor and 1uF ceramic source. When SS/EN voltage reaches to 0.3V (typical), capacitor (from VTT pin to Ground with short distance) High side driver begins chopping and main power is to ensure the stable operation. activated as an asynchronous Buck converter. When SS/ EN voltage reaches to 1.25V (typical), Low side driver Short Circuit Protection Short Circuit Protection Short Circuit Protection Short Circuit Protection Short Circuit Protection begins chopping and main power is activated as a The VTT regulator has two internal current limit circuits, synchronous Buck converter. one for the sink and one for the source regulators. Both When BF_CUT signal goes high (S3 state), the VDDQ current limits are set at 3Amp (typical). If maintained at switcher is always on and is sourced by 5VSTBY rail during current limit, the internal regulators act like constant this time. current sources, and supply the max current until the When both BF_CUT and P_OK signals are low, The VDDQ device temperature raises above thermal shutdown supply be disabled with S5 as well. Both high side and thresholds, at which point that regulator shuts down. low side drivers are pulled low. © 2005 Semtech Corp. 8 www.semtech.com SC2516 POWER MANAGEMENT The task here is to properly choose the compensation Applications Information (Cont.) network for a nicely shaped loop-gain Bode plot. The Gpwm following design procedures are recommended to accom- L plish the goal: EA R1 (1) Calculate the corner frequency of the output filter: R Rc Vbg Vin Ro 1 Co C R2 F := 1.25Vdc o 2⋅π⋅ LC ⋅ o (2) Calculate the ESR zero frequency of the output filter capacitor: Fig. 1. SC2516 small signal model. 1 F := esr Compensation design of the VDDQ Channel Compensation design of the VDDQ Channel Compensation design of the VDDQ Channel Compensation design of the VDDQ Channel Compensation design of the VDDQ Channel 2⋅π⋅R ⋅C c o The control model of SC2516 VDDQ and GMCH section (3) Check that the ESR zero frequency is not too high. can be depicted in Fig. 1. This model can also be used in Spice kind of simulator to generate loop gain Bode plots. F sw F < esr The bandgap reference is 1.25 V and trimmed to +/-1% 5 accuracy. The desired output voltage can be achieved If this condition is not met, the compensation structure by setting the resistive divider network, R1 and R2. may not provide loop stability. The solution is to add some electrolytic capacitors to the output capacitor bank The error amplifier is transconductance type with fixed to correct the output filter corner frequency and the ESR gain of: zero frequency. In some cases, the filter inductance may 0.001⋅A also need to be adjusted to shift the filter corner G := m V frequency. It is not recommended to use only high fre- quency multi-layer ceramic capacitors for output filter. The compensation network includes a resistor and a ca- pacitor in series, which terminates from the output of (4) Choose the loop gain cross over frequency (0 dB fre- the error amplifier to the ground. The PWM gain is inver- quency). It is recommended that the crossover frequency sion of the ramp amplitude, and this gain is given by: is always less than one fifth of the switching frequency : 1 F sw G pwm F ≤ x_over V ramp 5 where the ramp amplitude (peak-to-peak) is 0.55 volts . If the transient specification is not stringent, it is better to choose a crossover frequency that is less than one The total control loop-gain can then be derived as tenth of the switching frequency for good noise immunity. follows: The resistor in the compensation network can then be calculated as: . . 1sR C . . C 1sR c o . . Ts () T o . . sR C R 2 L c 2 F F V . . . . . 1 ⎛ esr⎞ ⎛ x_over⎞⎛ o⎞ 1s R C s L C 1 c o o R := ⋅ ⋅ ⋅ ⎜ ⎜ ⎜ R R o o G ⋅V ⋅G F F V pwm in m o esr bg ⎝ ⎠ ⎝ ⎠⎝ ⎠ where V when ⎛ bg⎞ T := G ⋅G ⋅V ⋅R⋅ o m pwm in ⎜ V o ⎝ ⎠ F < F < F o esr x_over © 2005 Semtech Corp. 9 www.semtech.com SC2516 POWER MANAGEMENT Step 1. Output filter corner frequency Applications Information (Cont.) or F = 1.6 KHz o 2 F F V 1 ⎛ o⎞ ⎛ x_over⎞⎛ o⎞ R := ⋅ ⋅ ⋅ ⎜ ⎜ ⎜ Step 2. ESR zero frequency: G ⋅V ⋅G F F V pwm in m esr o bg ⎝ ⎠ ⎝ ⎠⎝ ⎠ F = 3.537 KHz esr when Step 3. Check the following condition: F < F < F esr o x_over F sw F < esr (5) The compensation capacitor is determined by choos- 5 ing the compensator zero to be about one fifth of the output filter corner frequency: Which is satisfied in this case. F o Step 4. Choose crossover frequency and calculate F zero compensator R: 5 1 F = 50 KHz C x_over . . . 2 π R F zero R = 15 KΩ (6) The final step is to generate the Bode plot, either by using the simulation model in Fig. 1 or using the equa- Step 5. Calculate the compensator C: tions provided here with Mathcad. The phase margin can then be checked using the Bode plot. Usually, this C = 33 nF design procedure ensures a healthy phase margin. (7) An additional capacitor should be reserved at the Step 6. Generate Bode plot and check the phase margin. o compensation pin to ground to have another high fre- In this case, the phase margin is about 85 C that en- quency pole. sures the loop stability. Fig. 2 shows the Bode plot of the An example is given below to demonstrate the proce- loop. dure introduced above. The parameters of the power Compensation design of the GMCH Channel Compensation design of the GMCH Channel Compensation design of the GMCH Channel Compensation design of the GMCH Channel Compensation design of the GMCH Channel supply (typical for VDDQ section) are given as : The configuration of the PWM comparator of GMCH channel is such that its inverter input is connected to V :=5V ⋅ in Comp_GMCH and the non-inverter input is connected to the internal ramp. The peak voltage of the internal V := 2.5⋅V o ramp is 1.1V and the valley voltage is 0.55V. When COMP_GMCH voltage is below 0.55V, the maximum duty I := 20⋅A o cycle will be generated by PWM comparator. If F := 250⋅KHz COMP_GMCH voltage is over 1.1V then the minimum sw duty cycle will be generated. L := 2.2⋅µH To ensure proper soft start function of the GMCH channel, COMP_GMCH voltage must rise above 1.1V at C := 4500⋅µF o the beginning of soft start period quickly. So a higher compensation gain is required. The following example R := 0.01⋅Ω c shows that by choosing the compensation parameters as 15kOhm and 27nF for a typical output filter with V := 1.25⋅V bg 1~2uH inductor and 2000uF capacitor (ESR of 8~12 mOhm), the circuit will yield smooth soft start, stable V := 0.55⋅V ramp control loop, and satisfactory transient response. The 0.001⋅A measured Bode plot of the loop gain is shown in Figure G := m V 3. © 2005 Semtech Corp. 10 www.semtech.com SC2516 POWER MANAGEMENT Applications Information (Cont.) Loop Gain Mag (dB) 100 50 mag () i 0 50 3 4 5 6 . . . . 10 100 1 10 1 10 1 10 1 10 F i Loop Gain Phase (Degree) 0 45 phase () i 90 135 180 3 4 5 6 . . . . 10 100 1 10 1 10 1 10 1 10 F i Fig. 2. Bode plot of the VDDQ Channel Fig. 3. Bode plot of the GMCH Channel © 2005 Semtech Corp. 11 www.semtech.com 5Vdual 12VCC C1 D1 D2 100p C3 C2 U1 C5 R1 15K C4 33n 1 22 2.2nF Q1 COMP PGND R2 2R2 2 21 FBVDDQ FBVDDQ BG VDDQ 2R2 3 20 R3 D3 SS/EN SS/EN TG 1N4148 C6 4 19 C7 L1 1.5uH VTTGND BST VTT 100n 5 18 5VSBY C8 1uF R4 VTT 5VSBY C10 C11 C12 1uF Q2 1k C9 R5 15K FBVDDQ 27nF C14 C15 VDDQ 6 17 VDDQ COMP_GMCH 1uF C16 7 16 C17 non pop. R6 1uF AGND BF_CUT C13 1k Latched BF_CUT 8 15 1uF VTTFB TG_GMCH VDDQ 9 14 REFSENS BG_GMCH 3VCC C18 10 13 1uF FB_GMCH GND_GMCH 11 12 C19 C20 SS_GMCH POK Q3 C21 SC2516 2R2 1.5V GMCH R7 22nF FB_GMCH ATXPWR_OK L2 1.5uH Q4 R8 C22 C23 200R 2R2 R9 FB_GMCH R10 1K SC2516 POWER MANAGEMENT Typical application Schematic 470uF 23 T H _PAD 1N 4148 1N 4148 IP D 09N 03 IP D 09N 03 IP D 0 9 N 0 3 IP D 09N 03 4.7uF 4.7uF 1500uF 1500uF 1000uF 1500uF 1500uF 1000uF 1500uF © 2005 Semtech Corp. 12 www.semtech.com 5Vdual 12VCC C1 D1 D2 100p C3 C2 U2 C5 R1 Q1 15K C4 33n 1 22 2.2nF COMP PGND R2 2R2 2 21 FBVDDQ FBVDDQ BG 1.8VDDQ 2R2 3 20 R3 D3 SS/EN SS/EN TG 1N4148 C6 4 19 C7 L1 1.2uH VTTGND BST 0.9VTT 100n Q2 5 18 5VSBY C8 1uF R4 VTT 5VSBY C10 C11 C12 1uF C26 C21 442R C9 R5 15K 27nF C14 C15 VDDQ 6 17 VDDQ COMP_GMCH 1uF C16 FBVDDQ 7 16 C17 non pop. R6 1uF AGND BF_CUT C13 1k Latched BF_CUT 8 15 1uF VTTFB TG_GMCH VDDQ 9 14 RE S CH FSEN BG_GM 3VCC C18 10 13 1uF FB_GMCH GND_GMCH 11 12 C19 C20 SS_GMCH POK Q3 C21 SC2516 2R2 1.25V GMCH R7 22nF FB_GMCH ATXPWR_OK L2 1.2uH Q4 R8 C22 C23 C24 C25 0R FB_GMCH 2R2 R9 R10 non. pop. SC2516 POWER MANAGEMENT Application Schematic for Intel Broadwater platform 47 0uF 23 T H _PAD 1N 4 148 1N 4 148 IP D 05 N 03LA IP D 05N 03L A IP D 05N 03 LA IP D 05N 03L A 4.7uF 4.7uF 1500 uF 1500 uF 2 200u F 1500 uF 2 200u F 1500 uF 1 0uF 1500 uF 10 uF 10 uF 1 0uF © 2005 Semtech Corp. 13 www.semtech.com SC2516 POWER MANAGEMENT Outline Drawing - MLP-22 © 2005 Semtech Corp. 14 www.semtech.com SC2516 POWER MANAGEMENT Land Pattern- MLP-22 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 © 2005 Semtech Corp. 15 www.semtech.com