SEMTECH SC2453

SC2453 High Performance Quad Output Switching Regulator POWER MANAGEMENT Description Features The SC2453 is a high performance controller for multi- ‹ Two synchronized converters for low noise output converters that can be configured for a wide vari- ‹ Power up sequencing to prevent latch-up ety of applications. The SC2453 utilizes PWM synchro- ‹ Out of phase operation for low input ripple nous buck topologies where efficiency is most important. ‹ Over current protection It also provides dedicated programmable positive and ‹ Wide input range, 4.5 to 30V negative linear regulators using external transistors. Each ‹ Programmable frequency up to 700KHz of the three positive outputs is adjustable down to 0.5V. ‹ Two synchronous bucks for high efficiency at high The two PWM switchers are synchronized 180° out of current phase reducing input ripple, allowing for fewer input ca- ‹ One dedicated programmable positive linear pacitors. Power up sequencing prevents converter latch- regulator and one dedicated programmable up. negative linear regulator ‹ Output voltage as low as 0.5V The SC2453 can be synchronized to other converters to ‹ Small package TSSOP-28. Also offered in lead free, prevent beat frequencies. The wide range programmable WEEE and RoHS compliant package operating frequency allows users to optimize a converter design. The PWM switchers sense the voltage across the Applications low-side MOSFETs on-resistance to efficiently provide ‹ DSL applications with multiple input voltage re- adjustable current-limit, eliminating costly current-sense quirements resistors. A POK signal is issued when soft-start is com- ‹ Mixed-Signal applications requiring positive and plete on both PWM switchers and their outputs are within negative voltages 10% of the set point. ‹ Cable modem power management Typical Application Circuit ‹ Base station power management Vin: 4.5 - 30V C2 C1 R1 Q1 C3 R3 C4 D2 D1 D3 C5 C6 L1 6 17 C7 SS/SHDN BS T 2 Q2 Vout2: +3.3V 9 18 OSC GD2H R4 7 19 R5 SYNC PH2 (as low as 0.5V) C8 Q3 To Vout2 8 20 C9 POK GD2L 13 R6 FB2 C10 C11 R8 4 12 R7 BD4 EO2 SC 24 53 Q4 C12 26 BS T 1 Vout4: +2.5V Q5 Vout1: +5V 5 25 C13 L2 FB4 GD1H R9 R10 24 PH1 C14 Q6 (as low as 0.5V) 11 23 C15 BD3 GD1L 2 C16 R11 R12 FB1 Vout3: -12V Q7 10 3 FB3 EO1 C19 C17 C18 R13 R14 C20 R15 R16 R17 R18 To Vout2 Revision: July 20, 2005 1 www.semtech.com 15 AGND 16 AVCC 21 PGND 22 PVCC 14 28 ILI M2 BDI 1 27 ILI M1 VIN SC2453 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Ms aximum Unit BST1, BST2 to PGND 3V 5 VIN, BDI to AGND 3V 0 PVCC, AVCC to PGND 7V PGND to AGND ±V 0.3 PH1 to BST1, PH2 to BST2 -V 6 to 0.3 GD1H to PH1, GD2H to PH2 7V GD1L, GD2L to PGND 7V ILIM1, ILIM2 to AGND 7V OSC, SYNC, POK, SS to AGND 7V BD3 to AVCC -V 25 to 0.3 BD4 to AGND 7V FB1, FB2, FB3, FB4, EO1, EO2 to AGND -V 0.3 to 7 GD1H, GD1L, GD2H, DG2L Source or Sink Current 1A Storage Temperature Range -C 60 to +150 ° Junction Temperature -C 40 to +150 ° Lead Temperature (Soldering) 10 Sec. 3C 00 ° Electrical Characteristics Unless specified: V = 5V, fs = 600KHz, SS/SHDN = 5V, SYNC = 0V, T = T = -35°C to 105°C CC A J Ps arameter Tn estCondition Mp i Tx y Mt a Uni PowerSupply QV uiescent Current S8 S/SHDN = 0 35 . 4A . m Od perating Current N9 o loa 1A2 m AV VCC V5 IN > 5.5 45 . 5V .5 PV VCC V5 IN > 5.5 45 . 5V .5 Undervoltage Lockout Start Threshold 43 .05 40 .2 4V .5 UVLO Hysteresis 2V 00 m PWMComparator Delay to Output 7S 0 n  2005 Semtech Corp. 2 www.semtech.com SC2453 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: V = 5V, fs = 600KHz, SS/SHDN = 5V, SYNC = 0V, T = T = -35°C to 105°C CC A J Ps arameter Tn estCondition Mp i Tx y Mt a Uni Positive LinearRegulator Feedback Voltage 05 .47505 . 0V .52 Feedback Input Leakage Current 1A 50 n AV mplifier Transconductance = 0.5V, I = 0.5 to 5mA (sink) -0 2 -V 1 m FB4 BD4 @ 1V output Drive Sink Current 5A m Negative LinearRegulator Feedback Voltage -0 25 2V 5 m Feedback Input Leakage Current 1A 50 n AV mplifier Trandconductance = 0V, I = 0.5 to 5mA (source) -0 5 -V 1 m FB3 BD3 @ -12V output Driver Source Current 5A m PWMErrorAmplifier Feedback Voltage 05 .49 01 . 0V .5 Input Bias Current 2A 00 n Input Offset Voltage 36 mV Open Loop Gain 9B 0 d Unity Gain Bandwidth 3z MH Output Sink Current 2A m Output Source Current 2A m Slew Rate 1S V/µ Oscillator Frequency Range 10 00 7z 0 KH FR requency =0 12.5K 50 4 60 0 6z 6 KH T CT Peak Voltage 3V .0 CT Valley Voltage 0V .1 SYNC Input High Pulse Width 1S 00 n SYNC Rise/Fall Time 5S 0 n SYNC Frequency Range FC OSC FOS kHz +10% SYNC High/Low Threshold 1V .5  2005 Semtech Corp. 3 www.semtech.com SC2453 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: V = 5V, fs = 600KHz, SS/SHDN = 5V, SYNC = 0V, T = T = -35°C to 105°C CC A J Ps arameter Tn estCondition Mp i Tx y Ms a Unit Duty Cycle Pz WM 1 & 2 Maximum Duty Cyclef0 s = 100kH 9% Pz WM 1 & 2 Maximum Duty Cyclef1 s = 700kH 7% PWM 1 & 2 Minimum Duty Cycle 2% CurrentLimit CH1& 2 ILIM Set Voltage 12 .8 2V .2 SoftStart/ShutDown Charge Current 50151A µ Discharge Current 1A m Disable Threshold Voltage 05 .45 05 . 0V .5 Disable Low to Shut Down 5s 0 µ Output GI ate Drive On-Resistance(H) =2 15mA 5 Ω SOURCE GI ate Drive On-Resistance(L) =2 15mA 5 Ω SINK RC ise Time(H) =5 1000pF 1S n OUT FC all Time(H) =5 1000pF 2S n OUT RC ise Time(L) =5 1000pF 1S n OUT FC all Time(L) =5 1000pF 1S n OUT PowerGood FB1 & FB2 Trip Level above FB 20102% Hysteresis 1% FB1 & FB2 Trip Level below FB -0 20 -2 1 -% Hysteresis 1% PK WR OK Output Low LevelP4 ullup resistor = 10 06 . 0V . PK WR OK Output High LeakageP0 ullup resistor = 10 3A µ Note: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required.  2005 Semtech Corp. 4 www.semtech.com SC2453 POWER MANAGEMENT Pin Configuration Ordering Information (1) Pe artNumber Packag Temp.Range (T ) J Top View SC2453ITSTR TC SSOP-28 -35°C to +105° (2) SC2453ITSTRT Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant. (28 Pin TSSOP) Marking Information TOP nnnn = Part Number (Example: 1406) yyww = Date Code (Example: 0012) xxxxx = Semtech Lot No. (Example: P94A01)  2005 Semtech Corp. 5 www.semtech.com SC2453 POWER MANAGEMENT Pin Descriptions Pe in # Pn in Nam Pin Functio 11 ILIM Adjustable current-limit pin set for the PWM switcher1. Connect a resistor from this pin to AGND. 21 FB Voltage mode PWM switcher1 feedback input. Connect to a resistor-divider from output to FB1 to AGND to adjust the output voltage between 0.5V and 0.9 x V as maximum duty cycle IN allowed. The feedback set point is 0.5V. 31 EO The PWM switcher1 loop compensation pin. Connect a compensation network to compensate the control loop. Type 3 compensation network is usually used. 44 BD Open-drain output PNP transistor driver. Internally connected to the drain of an N-channel MOSFET. This pin connects to the base of an external PNP pass transistor to form a positive linear regulator. 54 FB PNP transistor positive linear regulator feedback input. Connect to a resistor-divider between the positive linear regulator and AGND to adjust the output voltage. The feedback set point is 0.5V. 6N SS/SHD The pin provides a soft-start function for the PWM switchers and positive linear regulator. When the pin reaches 0.5V, the regulated 10uA pull-up current source charges the capacitor connected from this pin to AGND. The error amplifier reference voltage of switcher1, switcher2 and positive linear regulators ramps from 0.7V to 2V respectively following the sequence. If the pin is pulled down below 0.5V, the SC2453 is disabled. 7C SYN The pin can be used to synchronize two or more controllers. This pin requires a 10K resistor to AGND when it is not used. 8K PO Open-drain power-good output. POK is low when the output voltage is more than 10% below or above the regulation point. POK is high impedance when the output is in regulation. Connect a resistor between the pin and PVCC. 9C OS Oscillator frequency adjustable input. Connect a resistor between the pin and AGND to set the PWM frequency. 13 0 FB NPN transistor negative linear regulator feedback input. Connect to a resistor-divider between a positive reference voltage and the negative output to adjust the output voltage. The feedback set point is 0V. 13 1 BD Open-drain output NPN transistor driver. Internally connected to the drain of a P-channel MOSFET. This pin connects to the base of an external NPN pass transistor to form a negative linear regulator. 12 2 EO The PWM switcher2 loop compensation pin. Connect a compensation network to compensate the control loop. Type 3 compensation network is usually used. 12 3 FB Voltage mode PWM switcher2 feedback input. Connect to a resistor-divider from output to FB2 to AGND to adjust the output voltage between 0.5V and 0.9 x V as maximum duty cycle IN allowed. The feedback set point is 0.5V. 12 4 ILIM Adjustable current-limit pin set for the PWM switcher2. Connect a resistor from this pin to AGND. 1D 5 AGN This is small signal ground and must be routed separately from the high current ground PGND. All voltage levels are measured with respect to this pin. A ceramic capacitor should be connected right to this pin for noise decoupling.  2005 Semtech Corp. 6 www.semtech.com SC2453 POWER MANAGEMENT Pin Descriptions (Cont.) Pe in # Pn in Nam Pin Functio 1C 6 AVC This pin is connected to the output of the external linear regulator to supply the IC. The IC may be powered directly from a single 5V (±10%) supply at this pin. The pin must be always decoupled to PGND with a minimum of 1uF ceramic capacitor, place very close to the pin. 12 7 BST The pin powers the upper MOSFET driver of PWM switcher2. Connect this pin to the junction of the bootstrap capacitor and cathode of the bootstrap diode. The anode of the bootstrap diode is connected to the PVCC. 1H 8 GD2 Switcher2 upper MOSFET gate driver output. It swings between BST2 and PH2. 12 9 PH The pin is connected to the junction of the upper MOSFET's source, output inductor and lower MOSFET's drain. 2L 0 GD2 Switcher2 lower MOSFET gate driver output. It swings between PVCC and PGND. 2D 1 PGN The pin provides the power ground for the lower gate drivers for both PWM switchers. It should be connected to the sources of the lower MOSFETs and the negative terminal of the input capacitors. 2C 2 PVC This pin is connected to the output of the external linear regulator to supply the internal lower gate drivers for both PWM switchers. It may be powered directly from a single 5V (±10%) supply at this pin. The pin must be always decoupled to PGND with a minimum of 10uF ceramic capacitor, place very close to the pin. 2L 3 GD1 Switcher1 lower MOSFET gate driver output. It swings between PVCC and PGND. 21 4 PH The pin is connected to the junction of the upper MOSFETs source, output inductor and lower MOSFETs drain. 2H 5 GD1 Switcher1 upper MOSFET gate driver output. It swings between BST1 and PH1. 21 6 BST The pin powers the upper MOSFET driver of PWM switcher1. Connect this pin to the junction of the bootstrap capacitor and cathode of the bootstrap diode. The anode of the bootstrap diode is connected to the PVCC. 2N 7 VI The pin is internally connected to the pull-up resistor of an N-channel MOSFET to regulate the bias for the IC. 2I 8 BD The external bias pass PNP transistor driver. Internally connected to the drain of an N-channel MOSFET.  2005 Semtech Corp. 7 www.semtech.com SC2453 POWER MANAGEMENT Block Diagram  2005 Semtech Corp. 8 www.semtech.com SC2453 POWER MANAGEMENT Applications Information Frequency Setting and Synchronization Frequency Setting and Synchronization Frequency Setting and Synchronization Frequency Setting and Synchronization Frequency Setting and Synchronization The SC2453 is designed to control and drive two N-Chan- The internal oscillator free-running frequency of the nel MOSFET PWM synchronous buck switchers and two SC2453 is set by an external resistor using the following positive linear regulators. The two PWM switchers are formula: synchronized 180° out of phase for low input ripple and noise. The switching frequency is programmable to opti- 9 7.9 x 10 R = mize design. The SC2453 PWM switchers feature lossless freq 3 fs − 12 x 10 current sensing and programmable over current limit. The When it is synchronized externally, the applied clock fre- two positive linear regulators output voltages are adjust- quency should be equal or greater than the free-running able. frequency. Power Supplies Power Supplies Power Supplies Power Supplies Power Supplies Setting Current Limit Setting Current Limit Setting Current Limit Setting Current Limit Setting Current Limit Supplies VIN, PVCC and AVCC from the input source are SC2453 monitors the voltage drop in the lower MOSFETs used to power the SC2453. An external PNP transistor Rdson voltage to sense an over current condition. This linear regulator supplies AVCC and PVCC. The AVCC sup- method of current sensing minimizes any unnecessary ply provides the bias for the oscillator, the switchers, the losses due to external sense resistance. linear regulator controllers and the POK circuitry. PVCC is used to drive the low side MOSFET gate. In low shut- The SC2453 utilizes an internal current source and an down current mode, the PNP transistor is turned off, dis- external resistor connected from the ILIM pins to the abling AVCC and PVCC. AGND pin to program a current limit level. This limit is programmable by choosing the resistor relative to the Soft-start, Sequencing and Disabling Soft-start, Sequencing and Disabling Soft-start, Sequencing and Disabling Soft-start, Sequencing and Disabling Soft-start, Sequencing and Disabling level required. The value of the resistor can be selected by the following formula: A 10A current source pulls up on the SS/SHDN pin. When the SS/SHDN pin reaches 0.5V, the first switcher is acti- Rilim = 2000/(IIim* Rdson) vated and the reference input of the error amplifier is ramped up with the soft-start voltage. When the SS/ SHDN pin reaches 2V, the SS/SHDN pin is pulled down Rilim should be between 10K and 100K. to approximately 0.7V and the second switcher begins An internal comparator with a reference from the level to soft-start in an identical fashion to the first switcher. set by the external resistor monitors the voltage drop When the SS/SHDN pin reaches 2V for the second time, across the lower MOSFET. Once the Vdson of the MOSFET the SS/SHDN pin is pulled down to approximately 0.7V exceeds this level, the low side gate is turned on and the again, and then the positive linear regulators ramp up upper MOSFET is turned off in the next switching cycle. with the SS/SHDN pin voltage. The SS/SHDN pin is even- tually pulled up to the supply AVCC. The soft-start time is Gate Drives Gate Drives Gate Drives Gate Drives Gate Drives controlled by the value of the capacitor connected to the SS/SHDN pin. The low side gate driver is supplied from PVCC and pro- vides a peak source/sink current of 1A. The high side If the SS/SHDN pin is pulled down below 0.5V, the gate drive is also capable of sourcing and sinking peak SC2453 is disabled. If the SS/SHDN pin is pulled down currents of 1A. The high side MOSFET gate drive can be below 0.34V, the bias PNP transistor for SC2453 is dis- provided by an external 12V supply that is connected abled and the supply current is only 100uA. from BST to GND. The actual gate to source voltage of the upper MOSFET will approximately equal 7V (12V-VCC). The power-ok circuitry monitors the FB inputs of the If the external 12V supply is not available, a classical error amplifiers of the switchers. If the voltage on bootstrap technique can be implemented from the PVCC these inputs goes above 0.55V or below 0.45V then supply. A bootstrap capacitor is connected from BST to the POK pin is pulled low. The POK pin is held low until Phase while PVCC is connected through a diode (Schottky the end of the start-up sequence. or other fast low VF diode) to the BST. This will provide a gate to source voltage approximately equal to the VCC-  2005 Semtech Corp. 9 www.semtech.com SC2453 POWER MANAGEMENT Applications Information (Cont.) Operating Frequency (f Operating Frequency (f Operating Frequency (f ) ) ) Operating Frequency (f Operating Frequency (f ) ) Vdiode drop. s s s s s The switching frequency in the SC2453 is user- Shoot through control circuitry provides a 30ns dead time programmable. The advantages of using constant to ensure both the upper and lower MOSFET will not turn frequency operation are simple passive component on simultaneously and cause a shoot through condition. selection and ease of feedback compensation. Before setting the operating frequency, the following trade-offs Error Amplifier and PWM Controller Error Amplifier and PWM Controller Error Amplifier and PWM Controller Error Amplifier and PWM Controller Error Amplifier and PWM Controller should be considered. In closed loop operation, the internal oscillator ramp 1) Passive component size ranges from 0.75V to 3.8V. The error amplifier output 2) Circuitry efficiency ranges determines duty-ratio of a converter. The synchro- 3) EMI condition nous continuous-conduction mode of operation allows 4) Minimum switch on time and the SC2453 to regulate the output irrespective of the 5) Maximum duty ratio direction of the load current. For a given output power, the sizes of the passive The SC2453 uses voltage-mode control for good noise components are inversely proportional to the switching immunity and ease of compensation. The low-side frequency, whereas MOSFET’s/Diodes switching losses MOSFET of each channel is turned off at the falling-edge are proportional to the operating frequency. Other issues of the phase timing clock. After a brief non-overlapping such as heat dissipation, packaging and the cost issues time interval of 30ns, the high-side MOSFET is turned are also to be considered. The frequency bands for signal on. The phase inductor current ramps up. When the in- transmission should be avoided because of EM ternal ramp reaches the threshold determined by the interference. error amplifier output, the high-side MOSFET is turned off. As long as phase voltage collapses below 1.5V, the Minimum Switch On Time Consideration Minimum Switch On Time Consideration Minimum Switch On Time Consideration Minimum Switch On Time Consideration Minimum Switch On Time Consideration low-side MOSFET is turned on. In the SC2453, the falling edge of the clock turns on the Buck Converter Buck Converter Buck Converter Buck Converter Buck Converter top MOSFET. The inductor current and the sensed voltage ramp up. After the internal ramp voltage crosses a Buck converter design includes the following specifica- threshold determined by the error amplifier output, the tions: top MOSFET is turned off. The propagation delay time Input voltage range: V ∈ [V ,V ] in in,min in,max from the turn-on of the controlling FET to its turn-off is Input voltage ripple (peak-to-peak): ΔV in the minimum switch on time. The SC2453 has a minimum Output voltage: V o on time of about 50ns at room temperature. This is the Output voltage accuracy: ε shortest on interval of the controlling FET. The controller Output voltage ripple (peak-to-peak): ΔV o either does not turn on the top MOSFET at all or turns it Nominal output (load) current: I o on for at least 50ns. Maximum output current limit: I o,max Output (load) current transient slew rate: dI (A/s) o For a synchronous step-down converter, the operating Circuit efficiency: η duty cycle is V /V . So the required on time for the top O IN MOSFET is V /(V fs). If the frequency is set such that O IN Selection criteria and design procedures for the the required pulse width is less than 50ns, then the following are described. converter will start skipping cycles. Due to minimum on 1) output inductor (L) type and value, time limitation, simultaneously operating at very high 2) output capacitor (C ) type and value, o switching frequency and very short duty cycle is not 3) input capacitor (C ) type and value, in practical. If the voltage conversion ratio V /V and hence O IN 4) power MOSFET’s, the required duty cycle is higher, the switching frequency 5) current sensing and limiting circuit, can be increased to reduce the size of passive 6) voltage sensing circuit, components. 7) loop compensation network.  2005 Semtech Corp. 10 www.semtech.com SC2453 POWER MANAGEMENT Applications Information (Cont.) c) Current rating: The saturation current of the inductor should be at least 1.5 times of the peak inductor current There will not be enough modulation headroom if the on under all conditions. time is simply made equal to the minimum on time of the SC2453. For ease of control, we recommend the required Output Capacitor (C Output Capacitor (C ) and V ) and V Ripple Ripple Output Capacitor (C Output Capacitor (C Output Capacitor (C ) and V ) and V ) and V Ripple Ripple Ripple o o o o o out out out out out pulse width to be at least 1.5 times the minimum on time. The output capacitor provides output current filtering in steady state and serves as a reservoir during load I I I I Inductor (L) and Ripple Current nductor (L) and Ripple Current nductor (L) and Ripple Current nductor (L) and Ripple Current nductor (L) and Ripple Current transient. The output capacitor can be modeled as an ideal capacitor in series with its parasitic ESR (R ) and esr Both step-down controllers in the SC2453 operate in ESL (L ) (Figure 1). esl synchronous continuous-conduction mode (CCM) regardless of the output load. The output inductor Co selection/design is based on the output DC and transient requirements. Both output current and voltage ripples are reduced with larger inductors but it takes longer to Lesl change the inductor current during load transients. Conversely smaller inductors results in lower DC copper losses but the AC core losses (flux swing) and the winding Resr AC resistance losses are higher. A compromise is to choose the inductance such that peak-to-peak inductor ripple-current is 20% to 30% of the rated output load Figure 1. An equivalent circuit of C . o current. Assuming that the inductor current ripple (peak-to-peak) If the current through the branch is i (t), the voltage b value is δ*I , the inductance value will then be: o across the terminals will then be: V (1− D) o t L = 1 di (t) δI f b o s v (t) = V + i (t)dt + L + R i (t) o o b esl esr b ∫ C dt o The peak current in the inductor becomes (1+δ/2)*Io 0 and the RMS current is: This basic equation illustrates the effect of ESR, ESL and C on the output voltage. 2 o δ I = I 1+ L,rms o 12 The first term is the DC voltage across C at time t=0. o The followings are to be considered when choosing The second term is the voltage variation caused by the inductors. charge balance between the load and the converter output. The third term is voltage ripple due to ESL and a) Inductor core material: For high efficiency applications the fourth term is the voltage ripple due to ESR. The above 350KHz, ferrite, Kool-Mu and polypermalloy total output voltage ripple is then a vector sum of the materials should be used. Low-cost powdered iron cores last three terms. can be used for cost sensitive-applications below 350KHz but with attendant higher core losses. Since the inductor current is a triangular waveform with peak-to-peak value δ*I , the ripple-voltage caused by o b) Select inductance value: Sometimes the calculated inductor current ripples is: inductance value is not available off-the-shelf. The δI o designer can choose the adjacent (larger) standard Δv ≈ C 8C f o s inductance value. The inductance varies with the ripple-voltage due to ESL is: temperature and DC current. It is a good engineering practice to re-evaluate the resultant current ripple at δI o Δv = L f ESL esl s the rated DC output current. D and the ESR ripple-voltage is:  2005 Semtech Corp. 11 www.semtech.com SC2453 POWER MANAGEMENT capacitor value. Only when the capacitor value is set Δv = R δI ESR esr o properly, the effect of ceramic capacitor low ESR starts Aluminum capacitors (e.g. electrolytic, solid OS-CON, to be significant. POSCAP, tantalum) have high capacitances and low For example, if a 10µF, 4mΩ ceramic capacitor is ESL’s. The ESR has the dominant effect on the output connected in parallel with 2x1500µF, 90mΩ electrolytic ripple voltage. It is therefore very important to minimize capacitors, the ripple current in the ceramic capacitor is the ESR. only about 42% of the current in the electrolytic capacitors at the ripple frequency. If a 100µF, 2mΩ When determining the ESR value, both the steady state ceramic capacitor is used, the ripple current in the ripple-voltage and the dynamic load transient need to be ceramic capacitor will be about 4.2 times of that in the considered. To keep the steady state output ripple-voltage electrolytic capacitors. When two 100µF, 2mΩ ceramic < ΔV , the ESR should satisfy: o capacitors are used, the current ratio increases to 8.3. ΔV o In this case most of the ripple current flows in the R < esr 1 δI o ceramic decoupling capacitor. The ESR of the ceramic capacitors will then determine the output ripple-voltage. To limit the dynamic output voltage overshoot/ undershoot within α (say 3%) of the steady state output Remark 2: The total equivalent capacitance of the filter voltage) from no load to full load, the ESR value should bank is not simply the sum of all the paralleled capacitors. satisfy: The total equivalent ESR is not simply the parallel αV o R < combination of all the individual ESR’s either. Instead esr 2 I o they should be calculated using the following formulae. Then, the required ESR value of the output capacitors should be: 2 2 2 2 2 (R + R ) ω C C + (C + C ) 1a 1b 1a 1b 1a 1b R = min{R ,R } C (ω) := esr esr1 esr2 eq 2 2 2 (R C + R C )ω C C + (C + C ) 1a 1a 1b 1b 1a 1b 1a 1b The voltage rating of aluminum capacitors should be at least 1.5V . The RMS current ripple rating should also o 2 2 2 2 2 R R (R + R )ω C C + (R C + R C ) 1a 1b 1a 1b 1a 1b 1b 1b 1a 1a be greater than: R (ω) := eq 2 2 2 2 2 (R + R ) ω C C + (C + C ) 1a 1b 1a 1b 1a 1b δI o 2 3 where R and C are the ESR and capacitance of 1a 1a Usually it is necessary to have several capacitors of the electrolytic capacitors, and R and C are the ESR and 1b 1b same type in parallel to satisfy the ESR requirement. capacitance of the ceramic capacitors respectively. The voltage ripple cause by the capacitor charge/ (Figure 2) discharge should be an order of magnitude smaller than the voltage ripple caused by the ESR. To guarantee this, the capacitance should satisfy: 10 C > o 2πf R s esr C1a C1b Ceq R1a R1b Req In many applications, several low ESR ceramic capacitors are added in parallel with the aluminum capacitors in order to further reduce ESR and improve high frequency decoupling. Because the values of capacitance and ESR are usually different in ceramic and aluminum capacitors, Figure 2. Equivalent RC branch. the following remarks are made to clarify some practical issues. Req and Ceq are both functions of frequency. For rigorous design, the equivalent ESR should be evaluated at the Remark 1: High frequency ceramic capacitors may not ripple frequency for voltage ripple calculation when both carry most of the ripple current. It also depends on the ceramic and electrolytic capacitors are used. If R = R 1a 1b  2005 Semtech Corp. 12 www.semtech.com SC2453 POWER MANAGEMENT inductances around the pulse current loop. = R and C = C = C , then R and C will be frequency- 1 1a 1b 1 eq eq independent and The RMS value of the capacitor current is approximately R = 1/2 R and C = 2C 2 eq 1 eq 1 δ D D 2 I = I D[(1+ )(1− ) + (1−D)] Cin o 2 12 η η Input Capacitor (C Input Capacitor (C Input Capacitor (C Input Capacitor (C Input Capacitor (C ) ) ) ) ) in in in in in The power dissipated in the input capacitors is then: The input supply to the converter usually comes from a 2 P = I R pre-regulator. Since the input supply is not ideal, input Cin Cin esr capacitors are needed to filter the current pulses at the For reliable operation, the maximum power dissipation switching frequency. A simple buck converter is shown in o Figure 3. in the capacitors should not result in more than 10 C of temperature rise. Many manufacturers specify the maximum allowable ripple current (ARMS) rating of the capacitor at a given ripple frequency and ambient temperature. The input capacitance should be high enough to handle the ripple current. For higher power applications, multiple capacitors are placed in parallel to increase the ripple current handling capability. Sometimes meeting tight input voltage ripple specifications may require the use of larger input capacitance. At full load, the peak-to-peak input voltage ripple due to the ESR is: Figure 3. A simple model for the converter input δ Δv = R (1+ )I ESR esr o 2 In Figure 3 the DC input voltage source has an internal The peak-to-peak input voltage ripple due to the capacitor impedance R and the input capacitor C has an ESR of in in is: R . MOSFET and input capacitor current waveforms, ESR esr voltage ripple and input voltage ripple are shown in Figure DI o Δv ≈ C 4. C f in s From these two expressions, C can be found to meet IN the input voltage ripple specification. In a multi-phase converter, channel interleaving can be used to reduce ripple. The two step-down channels of the SC2453 operate at 180 degrees from each other. If both step- down channels in the SC2453 are connected in parallel, both the input and the output RMS currents will be reduced. Ripple cancellation effect of interleaving allows the use of smaller input capacitors. When converter outputs are connected in parallel and interleaved, smaller inductors and capacitors can be used for each channel. The total output ripple-voltage remains unchanged. Smaller Figure 4. Typical waveforms at converter input. inductors speeds up output load transient. It can be seen that the current in the input capacitor When two channels with a common input are interleaved, pulses with high di/dt. Capacitors with low ESL should be the total DC input current is simply the sum of the used. It is also important to place the input capacitor individual DC input currents. The combined input current close to the MOSFET’s on the PC board to reduce trace waveform depends on duty ratio and the output current  2005 Semtech Corp. 13 www.semtech.com SC2453 POWER MANAGEMENT waveform. Assuming that the output current ripple is small, the following formula can be used to estimate the 50 RMS value of the ripple current in the input capacitor. 40 Cg() 100, Rds Let the duty ratio and output current of Channel 1 and Cg() 200, Rds Channel 2 be D , D and I , I , respectively. 1 2 o1 o2 20 Cg() 500, Rds If D <0.5 and D <0.5, then: 1 2 1 0 0 5 10 15 20 2 2 I ≈ D I + D I Cin 1 o1 2 o2 1 Rds 20 On-resistance (mOhm) FOM:100*10^{-12} FOM:200*10^{-12} If D >0.5 and (D -0.5) < D <0.5, then: 1 1 2 FOM:500*10^{-12} 2 2 2 I ≈ 0.5I + (D − 0.5)(I + I ) + (D − D + 0.5)I Cin o1 1 o1 o2 2 1 o2 Figure 5. Figure of Merit curves. MOSFET selection also depends on applications. In many If D >0.5 and D < (D -0.5) < 0.5, then: 1 2 1 applications, either switching loss or conduction loss 2 2 2 dominates for a particular MOSFET. For synchronous buck I ≈ 0.5I + D (I + I ) + (D − D − 0.5)I Cin o1 2 o1 o2 1 2 o2 converters with high input to output voltage ratios, the top MOSFET is hard switched but conducts with very low If D >0.5 and D > 0.5, then: 1 2 duty cycle. The bottom switch conducts at high duty cycle but switches at near zero voltage. For such applications, 2 2 2 are used for the top switch and I ≈ (D + D −1)(I + I ) + (1− D )I + (1− D )I MOSFET’s with low C Cin 1 2 o1 o2 2 o1 1 o2 g MOSFET’s with low R are used for the bottom switch. ds(on) Choosing Power MOSFET’s Choosing Power MOSFET’s Choosing Power MOSFET’s Choosing Power MOSFET’s Choosing Power MOSFET’s MOSFET power dissipation consists of a) conduction loss due to the channel resistance R , Main considerations in selecting the MOSFET’s are power ds(on) b) switching loss due to the switch rise time t and fall dissipation, cost and packaging. Switching losses and r time t, and conduction losses of the MOSFET’s are directly related f c) the gate loss due to the gate resistance R . ) and channel on-resistance G to the total gate charge (C g (R ). In order to judge the performance of MOSFET’s, ds(on) Top Switch: the product of the total gate charge and on-resistance is The RMS value of the top switch current is calculated used as a figure of merit (FOM). Transistors with the same as: FOM follow the same curve in Figure 5. 2 δ I = I D(1+ ) Q1,rms o 12 The closer the curve is to the origin, the lower is the FOM. The conduction losses are then: This means lower switching loss or lower conduction loss or both. It may be difficult to find MOSFET’s with both 2 P = I R low C and low R . Usually a trade-off between R tc Q1,rms ds(on) g ds(on ds(on and C has to be made. g R varies with temperature and gate-source voltage. ds(on) Curves showing R variations can be found in ds(on) manufacturers’ data sheet. From the Si4860 datasheet, R is less than 8mW when V is greater than 10V. ds(on) gs However R increases by 50% as the junction ds(on) o o temperature increases from 25 C to 110 C. The switching losses can be estimated using the simple formula  2005 Semtech Corp. 14 www.semtech.com Gate Charge (nC) SC2453 POWER MANAGEMENT specified in the datasheet. The power dissipated within 1 δ P = (t + t )(1+ )I V f ts 2 r f 2 o in s the MOSFET package is: where t is the rise time and t is the fall time of the r f R g switching process. Different manufactures have different P = Q V f tg g cc s R gt definitions and test conditions for t and t . To clarify r f these, we sketch the typical MOSFET switching The total power loss of the top switch is then: characteristics under clamped inductive mode in Figure P = P +P +P t tc ts tg 6. If the input supply of the power converter varies over a wide range, then it will be necessary to weigh the relative importance of conduction and switching losses. This is because conduction losses are inversely proportional to the input voltage. Switching loss how- ever increases with the input voltage. The total power loss of MOSFET should be calculated and compared for high-line and low-line cases. The worst case is then used for thermal design. Bottom Switch: The RMS current in bottom switch can be shown to be: 2 Figure 6. MOSFET switching characteristics δ I = I (1− D)(1+ ) Q2,rms o 12 Where, The conduction losses are then: Q is the gate charge needed to bring the gate-to-source gs1 voltage V to the threshold voltage V , gs gs_th 2 P =I R Q is the additional gate charge required for the switch bc Q2,rms ds(on) gs2 current to reach its full-scale value I and ds . where R is the channel resistance of bottom MOSFET. ds(on) Q is the charge needed to charge gate-to-drain (Miller) gd If the input voltage to output voltage ratio is high (e.g. capacitance when V is falling. ds V =12V, V =1.5V), the duty ratio D will be small. Since Switching losses occur during the time interval [t , t ]. in o 1 3 the bottom switch conducts with duty ratio (1-D), the Defining t = t -t and t can be approximated as: r 3 1 r corresponding conduction losses can be quite high. (Q + Q )R gs2 gd gt Due to non-overlapping conduction between the top and t = r V − V the bottom MOSFET’s, the internal body diode or the cc gsp external Schottky diode across the drain and source where R is the total resistance from the driver supply gt terminals always conducts prior to the turn on of the rail to the gate of the MOSFET. It includes the gate driver bottom MOSFET. The bottom MOSFET switches on with internal impedance R , external resistance R and the gi ge only a diode voltage between its drain and source gate resistance R within the MOSFET i.e.: g terminals. The switching loss is: 1 δ R = R +R +R P = (t + t )(1+ )I V f bs r f o d s gt gi ge g 2 2 is negligible due to near zero-voltage switching. V is the Miller plateau voltage shown in Figure 11. gsp Similarly an approximate expression for t is: The gate losses are estimated as : f R g P = Q V f bg g cc s R gt (Q + Q )R gs2 gd gt t = f The total bottom switch losses are then: V gsp P =P +P +P b bc bs bg Only a portion of the total losses P = Q V f is dissipated g g cc s in the MOSFET package. Here Q is the total gate charge g  2005 Semtech Corp. 15 www.semtech.com SC2453 POWER MANAGEMENT Once the power losses P for the top (P ) and loss t bottom (P ) MOSFET’s are known, thermal and package b Vo (V) 0.6 0.9 15 .2 1. 15 .8 23 . 3. design at component and system level should be done to verify that the maximum die junction temperature (1-h)/h 0.2 0.8 12 .4 24 .6 5.6 o (T , usually 125 C) is not exceeded under the worst- j,max Ro1 (Ohm) 200 806 1K .4K 22K .61K4K .02 5.62 case condition. The equivalent thermal impedance from junction to ambient (θ ) should satisfy: ja Ro2 (Ohm) 1K 1K 1K K 1 1K K 1K 1 T − T j,max a,max θ ≤ ja P loss and its multiples fall into the standard resistor value θ depends on the die to substrate bonding, ja packaging material, the thermal contact surface, thermal chart (1%, 5% or so), it is possible to use standard value compound property, the available effective heat sink resistors to exactly set up the required output voltage value. area and the air flow condition (free or forced convection). The input bias current of the error amplifier also causes Actual temperature measurement of the prototype should be carried out to verify the thermal design. an error in setting the output voltage. The maximum inverting input bias currents of error amplifiers 1 or 2 is Setting the Output Voltage Setting the Output Voltage 200nA. Since the non-inverting input is biased to 0.5V, Setting the Output Voltage Setting the Output Voltage Setting the Output Voltage the percentage error in the second output voltage will be 100%•(0.2uA) R •R /[0.5 • (R +R ) ]. The non-inverting input of the channel-one error ampli- 01 o2 o1 o2 fier is internally tied the 0.5V voltage reference output. A simple voltage divider (R at top and R at bottom) sets o1 o2 Valley Current Sensing for Current-Limit Valley Current Sensing for Current-Limit Valley Current Sensing for Current-Limit Valley Current Sensing for Current-Limit Valley Current Sensing for Current-Limit the converter output voltage. The voltage feedback gain h=0.5/V is related to the divider resistors value as: o The valley current sensing for current limiting is a unique h scheme which could sense the voltage across the bot- R = R o2 o1 − 1 h tom switch MOSFET when it is on. The scheme is robust with good noise immunity due to reference to ground. Once either R or R is chosen, the other can be o1 o2 The current sensing point is at a delay time t before dv calculated for the desired output voltage V . Since the o the beginning of a switching cycle. Therefore, the actual number of standard resistance values is limited, the valley current is: calculated resistance may not be available as a standard value resistor. As a result, there will be a set error in the t t dv dv − − V o τ τ 2 2 I = − (1− e ) + I e converter output voltage. This non-random error is V VS R + R ( ) _ DS ON B L caused by the feedback voltage divider ratio. It cannot be corrected by the feedback loop. where, I is the preset valley current limiting threshold. VS The following table lists a few standard resistor combi- If a sensed current exceeds the threshold, the top switch nations for realizing some commonly used output will keep off in the next cycle until the current goes back voltages. below the threshold. In steady state, since the output voltage is out of regulation in over current condition, the Only the voltages in boldface can be precisely set with control loop will try to make maximum duty cycle for the standard 1% resistors. top switch as it is on, which is usually greater than 80%. Therefore, as the current falls back below the thresh- From this table, one may also observe that when the old, it is on in the next almost full cycle. The peak cur- value: rent is not controlled and only depends upon circuit pa- 1− h V − 0.5 o rameters and operating condition in this cycle. The peak = h 0.5 current I is: P T T − − V −V in o τ τ 1 1 I = (1− e ) + I e P V R + R DS(ON ) _ T L  2005 Semtech Corp. 16 www.semtech.com SC2453 POWER MANAGEMENT Where, T is switching cycle period. C - Output capacitance R - Output capacitor ESR C Because the inductor current ramps up according to Vin V - Input voltage IN –Vo, and down with Vo, a falling output voltage in over current condition moves the inductor “ramp up” current The transfer function of the error amplifier with external up faster and the peak current I larger but the “ramp P compensation network is as follows: down” current slower. As long as the current is still larger than the current limiting threshold, the top switch is held s s (1+ )(1+ ) off. The switching frequency is folded back lower but ω ω ω I Z1 Z2 G (s) = ⋅ COMP average current is relatively still high. s s s (1+ )(1+ ) ω ω An example is shown in Typical Characteristics section P1 P2 with input voltage 12V and output voltage 5V with out- where, put current 3.5A. 1 1 ω = ,ω = Z1 Z2 The preset valley current limit is 5A, which has to be R C (R + R )C 2 1 1 3 2 greater than full load current 3.5. When the output is shorted, the inductor peak current and the load current, 1 1 1 ω = ,ω = ,ω = I P1 P2 both are a function of the input voltage and the output C C R (C + C ) R C 1 3 1 1 3 3 2 R 2 inductance, would be higher than the current limit. There- C + C 1 3 fore, proper thermal management and inductor satura- tion current rating have to be considered at the worst C3 conditions. C2 R3 R2 C1 Loop Compensation Loop Compensation Loop Compensation Loop Compensation Loop Compensation R1 SC2453 is a voltage mode buck controller with high gain - bandwidth error amplifier utilizing external network com- pensation to regulate output voltage. + Vref For a DC/DC converter, it is usually required that the converter has a loop gain of a high crossover frequency Figure 7. Voltage Mode Buck Converter Compensation for fast load response, high DC and low frequency gain Network for low steady state error, and enough phase margin for its operating stability. Often one can not have all these With the compensation, the converter total loop gain is properties at the same time. The purpose of the loop as follows: compensation is to arrange the poles and zeros of the compensation network to meet the requirements for a s 1+ 1 s s 1 specific application. ⋅ ω ⋅ V 1+ 1+ I I V ω ω R ⋅C M Z1 Z2 C 4 T(s) = G ⋅ G (s) ⋅ G (s) = ⋅ ⋅ ⋅ PWM COMP VD s s L s 2 1 1+ ⋅1+ 1+ s + s L C The power stage of a buck converter control-to-output 1 ω ω R P1 P2 transfer function is as shown below: Where: G = PWM gain PWM 1+ sR C C V = 3.0V, ramp peak to valley voltage of SC2453 G (s) = V M VD IN L 2 1+ s + s LC R The design guidelines are as following: where, 1. Set the loop gain crossover frequency ω less than1/ C 5th the switching frequency. 1 ω = O 2. Place an integrator in the origin to increase DC and LC low frequency gains. L - Output inductance  2005 Semtech Corp. 17 www.semtech.com SC2453 POWER MANAGEMENT The maximum voltage to drive an NPN transistor is AVCC 3. Select ω and ω such that they are placed near ω Z1 Z2 O minus the voltage drop across the internal P-MOSFET to dampen peaking; the loop gain has –20dB rate which is the product of On-Resistance and sourcing cur- to go across the 0dB line for obtaining a wide band- rent. The maximum driving voltage with 5mA sourcing width. current is minimum AVCC (4.5V) minus 5mA times maxi- 4. Cancel ω with compensation pole ω (ω = ω ). ESR P1 P1 ESR mum On-Resistance 140Ω, i.e. 3.8V. 5. Place a high frequency compensation pole ω at the P2 half switching frequency to get the maximum attenu- Layout Guidelines Layout Guidelines Layout Guidelines Layout Guidelines Layout Guidelines ation of the switching ripple and the high frequency noise with the adequate phase lag at ω . C In order to achieve optimal electrical, thermal and noise performance for high frequency converters, attention The compensated loop gain will be as given in Figure 8: must be paid to the PCB layouts. The goal of layout opti- mization is to place components properly and identify T( T(ss)) Lo Loop op g ga ai in T n T ( (s s) ) ω ω the high di/dt loops to minimize them. The following guide- z1 z1 ω ω oo ω ω z2 z2 --220d 0dBB//de decc line should be used to ensure proper functions of the Gv Gvdd ω ω cc converters. 0d 0dBB ω ω p1 p1 ω ω p2 p2 P P o ow w e er r s st ta age ge 1. A ground plane is recommended to minimize noises GG (s (s) ) VD VD and copper losses, and maximize heat dissipation. ω ω ESR ESR 2. Start the PCB layout by placing the power compo- --440d 0dBB//de decc nents first. Arrange the power circuit to achieve a clean power flow route. Put all the connections on one side of the PCB with wide copper filled areas if possible. Figure 8. Asymptotic diagram of buck power stage and 3. The PVCC and AVCC bypass capacitors should be its compensated loop gain. placed next to the PVCC, AVCC and PGND, AGND pins respectively. Positive and Negative LDO Controllers Positive and Negative LDO Controllers Positive and Negative LDO Controllers Positive and Negative LDO Controllers Positive and Negative LDO Controllers 4. Separate the power ground from the signal ground. In SC2453, the power ground PGND should be tied The SC2453 provides positive and negative adjustable to the source terminal of lower MOSFETs. The signal linear regulator controllers. The positive linear regulator ground AGND should be tied to the negative termi- uses a PNP transistor to regulate output voltage. This is nal of the output capacitor. set by a voltage divider connected from the output to FB 5. The trace connecting the feedback resistors to the to AGND. Referring to the front page Application Circuit, output should be short, direct and far away from the select R10 in the 5KΩ to 20KΩ range. Calculate R9 with noise sources such as switching node and switching the following equation: components. Minimize the traces between DRXH/ DRXL and the gates of the MOSFETs to reduce their impedance to drive the MOSFETs. V   OUT R =R −1   9 10 7. Minimize the loop including input capacitors, top/bot- 0.5   tom MOSFETs. This loop passes high di/dt current. Make sure the trace width is wide enough to reduce The negative linear regulator uses a NPN transistor to copper losses in this loop. regulate output voltage. This is set by a voltage divider 8. Maximize the trace width of the loop connecting the connected from the output to FB to a positive reference. inductor, bottom MOSFET and the output capacitors. Referring to the front page Application Circuit, select R18 9. Connect the ground of the feedback divider and the in the 5KΩ to 20KΩ range. Calculate R14 with the compensation components directly to the GND pin following equation: of the SC2453 by using a separate ground trace.   Then connect this pin to the ground of the output V OUT   Ρ =Ρ 14 18   capacitor as close as possible. V  REF   2005 Semtech Corp. 18 www.semtech.com SC2453 POWER MANAGEMENT Evaluation Board Schematic  2005 Semtech Corp. 19 www.semtech.com 12V C50 C1 C2 C3 C4 C27 C28 C29 C33 R50 R52 1uF 20K 0 10uF/16V 10uF/16V 10uF/16V 10uF/16V Open Open Open Open Q1 GND FZT749 TP1 C5 C32 R1 R2 10uF 22uF 10K 10 D2 D1 SL04 SL04 POK C6 SYNC 1uF +3.3V/2A D3 C7 B180 SS/SD 10uF C9 C8 0.1uF 6 17 TP3 Q2 2 4 GND 0.1uF SS/SD BST2 R51 SUD50N03-10CP TP4 R4 10K 9 18 1 3 OSC GD2H 3.3V R3 30K TP5 L1 STQ127_1042 2 C10 R5 7 19 SYNC PH2 Q3 6.8nF fs=250KH z TP6 11.5K C11 C30 R6 SUD50N03-10CP 8 20 680uF/4V POK GD2L 22uF R7 C12 Open 0 C31 13 180 2.2nF FB2 +3.3V/2A GND C13 TP7 R9 20K C14 R8 4 12 10uF BD4 EO2 R10 SC2453 1K 5.6nF Q4 26 2.05K BST1 FZT749 TP8 Q5 C15 390pF 5 25 C16 SUD50N03-10CPL2 10uH TP9 FB4 GD1H 2.5V/1A 0.1uF C17 R11 R12 2 R13 TP10 24 5V/2 TP12 40.2K C18 Open 10uF PH1 C19 10K TP11 Q6 C20 C51 R14 3.3nF 11 23 SUD50N03-10CP 470uF/6.3V C52 Open R15 BD3 GD1L R16 22uF GND 0 R17 C21 2 18K R18 Q7 0 1K FB1 Open GND 150 FZT649 10 3 FB3 EO1 -12V/0.25A C22 C23 C24 R19 C53 10uF R20 10uF 2.0K 680pF 100pF 36K R23 R22 GND C25 R21 51K 51K 4.7nF 20K R24 10K TP13 +3.3V/2A TP14 TP15 TP16 15 16 AGND AVCC 21 22 PGND PVCC 14 28 ILIM2 BDI 1 27 ILIM1 VIN SC2453 POWER MANAGEMENT Bill of Materials - Evaluation Board Item Quantity Reference Part Manufacturer Manufacturer # Foot Print 1 4 C1,C2,C3,C4 10uF/16V TDK C3216X5R1C106MT SM/C_1206 2 1 C5 10uF SM/C_0805 3 2 C6,C50 1uF SM/C_0805 4 5 C7,C13,C17,C22,C23 10uF TDK C3216X5R1C106MT SM/C_1206 51 C8 0.1uF SM/R_0805 C16 62 0.1uF SM/C_0805 C9 0.1uF SM/C_0805 7 1 C10 0.01uF SM/C_0805 8 1 C11 680uF/4V SANYO 4TPB680M SM/CT_7343 9 4 C12 Open SM/C_0805 C18 Open SM/C_0805 C21 Open SM/C_0805 C52 Open SM/C_0805 10 1 C14 8.2nF SM/C_0805 11 2 C24 680pF SM/C_0805 C15 680pF SM/C_0805 12 1 C19 3.3nF SM/C_0805 13 1 C20 470uF/6.3V SANYO 6TPB470M SM/CT_7343 14 1 C25 4.7nF SM/C_0805 15 4 C27 Open SM/C_1210 C28 Open SM/C_1210 C29 Open SM/C_1210 C33 Open SM/C_1210 16 3 C30 22uF SM/C_1210 C32 22uF SM/C_1210 C51 22uF SM/C_1210 17 1 C31 2.2nF SM/C_0805 18 1 C53 100pF SM/C_0805 19 2 D2 SL04 VISAY SL04 SOD123 D1 SL04 VISAY SL04 SOD123 20 1 D3 B150 VISAY SS15 SM/_SMB 28 1 L1 STQ127_1042 DELTA STQ127_1042 29 1 L2 10uH COILCRAFT DO5022P-103 DO5022 30 2 Q4 FZT749 ZETEX FZT749TA SM/SOT223 Q1 FZT749 ZETEX FZT749TA SM/SOT223 31 4 Q2 SUD50N03-10CP VISHAY SUD50N03-10CP SM/_DPAK Q3 SUD50N03-10CP VISHAY SUD50N03-10CP SM/_DPAK Q5 SUD50N03-10CP VISHAY SUD50N03-10CP SM/_DPAK Q6 SUD50N03-10CP VISHAY SUD50N03-10CP SM/_DPAK 32 1 Q7 FZT649 ZETEX FZT649 SM/SOT223 33 4 R1 10K SM/R_0805 R13 10K SM/R_0805 R24 10K SM/R_0805 R51 10K SM/R_0805 34 1 R2 10 SM/R_0805 35 1 R3 30K SM/R_0805 36 2 R4 2 SM/R_0805 R12 2 SM/R_0805 37 1 R5 11.3K SM/R_0805  2005 Semtech Corp. 20 www.semtech.com SC2453 POWER MANAGEMENT Bill of Materials - Evaluation Board 38 3 R6 0 SM/R_0805 R14 0 SM/R_0805 R15 0 SM/R_0805 39 1 R7 470 SM/R_0805 40 2 R8 1K SM/R_0805 R17 1K SM/R_0805 41 4 R9 20K SM/R_0805 R16 20K SM/R_0805 R21 20K SM/R_0805 R50 20K SM/R_0805 42 1 R10 2.0K SM/R_0805 43 1 R11 40.2K SM/R_0805 44 1 R18 150 SM/R_0805 45 1 R19 2.21K SM/R_0805 46 1 R20 36K SM/R_0805 47 2 R23 51K SM/R_0805 R22 51K SM/R_0805 48 1 R52 0 SM/R_0805 49 1 U1 SC2453 SEMTECH SC2453 TSSOP-28  2005 Semtech Corp. 21 www.semtech.com SC2453 POWER MANAGEMENT Outline Drawing - TSSOP-28 DIMENSIONS A INCHES MILLIMETERS DIM D e MIN NOM MAX MIN NOM MAX N A - - .047 - - 1.20 A1 .002 - .006 0.05 - 0.15 A2 .031 - .042 0.80 - 1.05 2X E/2 b .007 - .012 0.19 - 0.30 c .003 - .007 0.09 - 0.20 E1 E D .378 .382 .386 9.60 9.70 9.80 PIN 1 E1 .169 .173 .177 4.30 4.40 4.50 INDICATOR E .252 BSC 6.40 BSC e .026 BSC 0.65 BSC L .018 .024 .030 0.45 0.60 0.75 ccc C 13 2 (.039) (1.0) L1 e/2 2X N/2 TIPS N 28 28 - - 01 0° 8° 0° 8° B aaa .004 0.10 bbb .004 0.10 ccc .008 0.20 D aaa C A2 A SEATING PLANE H C A1 bxN bbb C A-B D c GAGE PLANE 0.25 L 01 (L1) DETAIL A SEE DETAIL A SIDE VIEW NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS AND TO BE DETERMINED AT DATUM PLANE -A- -B- -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AE. Land Pattern - TSSOP-28 X DIMENSIONS DIM INCHES MILLIMETERS C (.222) (5.65) G .161 4.10 (C) G Z P .026 0.65 X .016 0.40 Y .061 1.55 Y Z .283 7.20 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2005 Semtech Corp. 22 www.semtech.com