SEMTECH SC2449

SC2449 BI-Phase/Dual Controller POWER MANAGEMENT Features Description The SC2449 can be configured as a dual converter or a � Selectable dual output or bi-phase operation bi-phase converter for high current applications. The part � Direct drive for N-channel MOSFETs is designed for point of use power supplies with 8.5-28V � Undervoltage lockout nominal backplane power sources. Multiple supplies can � Synchronization to external clock be synchronized together to prevent low frequency har- � Multi-converter synchronization monics on the backplane. The power dissipation is con- � Soft start trolled using a novel low voltage supply technique, allow- � Fast transient response ing high speed and integration, with the high drive cur- � Max duty cycle 45% rents to ensure low MOSFET switching loss. � Output over voltage protection The use of high speed switching circuits allows very nar- � Thermal shutdown row PWM outputs down to 15:1 voltage ratios. Single � 28-Pin SO lead free package available. Fully WEEE pin compensation for each channel simplifies develop- and RoHS compliant ment as well as reducing external pin count. Applications Capable of driving MOSFETs via external driver transis- tors for phase currents beyond 20A. � Power supplies for advanced telecoms/datacoms � SO IP, Ethernet and PABX power supplies Typical Application Circuit 1 Revision: January 17, 2007 www.semtech.com SC2449 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Sm ymbol Ms aximu Unit SV upply Voltage 3V 0 IN VV oltage on BST Pins 3V 8 BST (1) Oscillator Frequency 2z MH VCC 8V Thermal Resistance Junction to Case 2W 5 °C/ θ JC Thermal Resistance Junction to Ambient θ 8W 0 °C/ JA OT perating Temperature Range -C 40 to +85 ° A ST torage Temperature Range -C 55 to +150 ° STG LT ead Temperature (Soldering) 10 seconds 3C 00 ° LEAD Note: (1) Maximum frequency and maximum supply voltage could cause excessive power dissipation in the part. Electrical Characteristics Unless specified V = 24V, T = 25°C IN A Ps arameter Cn ondition Mp i Tx y Ms a Unit Supply Voltage, V 88 .5 2V IN S0 upply Current E0 NABLE = 304A m Under Voltage Lockout 5V .8 UVLO Hysteresis 4V 00 m Voltage Regulator Pre Regulator Voltage 67V BC gout Voltage =9 4.7nF 01 .9 1V .01 LOAD Bgout Impedance 3KΩ RI EGDRV Pin Sink Current 5A m REGDRV ErrorAmp Input Offset Voltage 1V 5 m Input Offset Mismatch 6V m Input Impedance 5KΩ Linear Transconductance .V 002 A/ InternalOscillator FR requency =1 30K MHz REF FR requency =0 60K 5z 0 kH REF www.semtech.com  2007 Semtech Corp. 2 SC2449 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified V = 24V, T = 25°C IN A Ps arameter Cn ondition Mp i Tx y Ms a Unit InternalOscillator(Cont.) RV amp Valley to Peak =5 12V 1V . IN RV amp Valley to Peak =3 24V V IN ExternalClock Ds etect Time R2 ise Time < 50n µs Unlock Time 10 0 5s µ Frequency Range 01 .27 MHz High Side Gate Drive Max Duty Cycle 4% 5 PC eak Source =1 10nF A LOAD PC eak Sink =1 10nF A LOAD Low Side Gate Drive PC eak Source =2 10nF A LOAD PC eak Sink =2 10nF A LOAD Sync Drive Timing MC in Non-overlap =0 1nF Fet Drive < 1V 205s n LOAD PF WM Match 50% Duty Cycle,=1 1MHz-1% OSC Logic InputPins IV nput Bias Current =0 0 - 5V -0 1 1A µ IN Logic Threshold 0V .8 FB2 Disable Threshold V-V 0.7V CC OverCurrentProtection OV C+ I/P Bias Current =0 24V 7A 0 µ IN Oe C- I/P Bias Current @0 trip voltag 40506A µ OverVoltage Protection OVP Threshold 1% 20 Thermal Shutdown 1C 50 ° Note: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required.  2007 Semtech Corp. 3 www.semtech.com SC2449 POWER MANAGEMENT Pin Configuration Ordering Information (1) PE artNumber PACKAG T (T ) AMB A Top View SC2449ISWTR SC O-28 -40 - +85° (2) SC2449ISWTRT Sd C2449EVB Evaluation Boar Notes: (1) Only available in tape and reel packaging. A reel contains 1000 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant. (28-Pin SOIC) Block Diagram www.semtech.com  2007 Semtech Corp. 4 SC2449 POWER MANAGEMENT Pin Descriptions Pe in Pn in Nam Pin Functio 11F. B Feedback for channel 1 21C. OMP Compensation for channel 1 3CN. No connection 4GB. 1V reference for error amplifiers, 3K source impedance 52F. B Feedback for channel 2 62C. OMP Compensation for channel 2 7VR. EGDR Regulator drive for external pass transistor 8EE. NABL Enable threshold is 2.05V, connect to ground to disable 92P. HASE Phase node input for channel 2 12 0D. RVH Gate drive for high side channel 2 12 1B. STH Bootstrap input for high side channel 2 12 2D. RVL Gate drive for low side channel 2 12 3B. STL Supply for low side channel 2 1C 4V. C Pre-regulated IC power supply 11 5B. STL Supply for low side channel 1 11 6D. RVL Gate drive for low side channel 1 11 7B. STH Bootstrap input for high side channel 1 11 8D. RVH Gate drive for high side channel 1 11 9P. HASE Phase node input for high side channel 1 2D 0P. GN Power ground 2+ 1O. C Overcurrent comparator inverting input 22 2O. C- Overcurrent comparator non-inverting input for channel 2 21 3O. C- Overcurrent comparator non-inverting input for channel 1 2K 4 EXTCL External clock, converter locks to this input when a valid signal is present. 2T 5 CLKOU Clock out, logic level drive to provide synchronizing signal for other converters. 2C 6N. No connection 2D 7A. GN Analog ground 2F 8 RRE External reference resistor for internal oscillator and ramp generator.  2007 Semtech Corp. 5 www.semtech.com SC2449 POWER MANAGEMENT Typical Application Schematic for Two Channel Operation www.semtech.com  2007 Semtech Corp. 6 SC2449 POWER MANAGEMENT Typical Application (Cont.) Bill of Material for Two Channel Operation Iy tem Qe t Referenc Pr artNumber/Value Manufacture 18C. 1 - C8 0y .47µF, 50V, Cer An 23C6 9,C24,C25 0y .33µF, Cer., 120 An 32C6 10,C11 2y 2nF, Cer., 120 An 41C6 12 0y .1µF, Cer., 120 An 52C6 13,C14 1y 00pF, Cer., 120 An 61C6 15 4y 7pF, Cer., 120 An 76C. 16,C19,C20,C21,C22,C23 2y 2µF, 35V, Tant An 82C. 17,C18 6y 80µF, 35V, Alum An 92C6 26,C27 2y .2nF, Cer., 120 An 13 0C6 28,C29,C50 1y .0nF, Cer., 120 An 11 1C6 30 1y .0µF, Cer., 120 An 11 215C6 31,C32,C33,C36,C37,C40,C41,C42,C43,C44,C41y 0µF, Cer., 120 An 14 3 C34,C35,C38,C39 1y 500µF, 6.3V, Alum. An 14 4 D1,D2,D5,D6 1A, 40V, Schottky, MELF, Any 1N5819M 124 5 D3,D 3y A, 40V, Schottky, 30BQ040 An 12 6Ls 1,L2 I: nductor, 9 turn Magnetics Kool Mu P/N: 77206-A7 14 7 M1,M2,M3,M4 N-Channel MOSFET, TO- Fairchild 263AB P/N: FDB7030BL 11 8 Q1 80V, 1A, NPN, Med. Pwr. BCP56CT SOT-223 12 9R6 1,R3 2y .2, 5%, 120 An 22 0R6 4,R6 4y .7, 5%, 120 An 24 1R6 2,R5,R7,R11 1y .0, 5%, 120 An 21 2R6 8 5y 6k, 5%, 120 An 22 3R6 9,R10 2y .2k, 5%, 120 An 21 4R, 12 Chip resistor Any 0.005, 1W, 1%, 2512  2007 Semtech Corp. 7 www.semtech.com SC2449 POWER MANAGEMENT Typical Application (Cont.) Bill of Material for Two Channel Operation (Cont.) Iy tem Qe t Referenc Pr artNumber/Value Manufacture 24 5 R13,R14,R15,R16 2y .2, 1/4W, 5%, 1210 An 21 6 R17*,R19,R31* Cy hip resistor, 0, 1206 An 22 7R6 20,R21 1y .00k, 1%, 120 An 21 8R6 22 2y .32k, 1%, 120 An 21 9R6 23 4y .02k, 1%, 120 An 32 0R6 26,R27 2y .0k, 5%, 120 An 31 1R6 28 1y 0, 5%, 120 An 31 2R6 29 5y 1, 5%, 120 An 31 3R6 34 1y 5k, 5%, 120 An 31 4R6 36 6y 8.1k, 1%, 120 An 31 5R6 37 1y 0.0k, 1%, 120 An 31 6 SC2449 Bi-Phase/Dual Controller, Semtech Corp. SO-28W P/N: SC2449ISW 805-498-2111 Notes: 1. * Indicates optional parts. 2. Some parts are selected due to availability or lead time, and are not optimized. www.semtech.com  2007 Semtech Corp. 8 SC2449 POWER MANAGEMENT Typical Application (Cont.) Schematic for Bi-Phase Operation  2007 Semtech Corp. 9 www.semtech.com SC2449 POWER MANAGEMENT Electrical Characteristic Curves Two Channel Operation Efficiency in Two-Channel Application Circuit (5V/12A, 3.3V/18A) Overall System Efficiency vs. Overall Load (W) of the 5V and 3.3V channels 95.00% 90.00% 85.00% 80.00% Efficiency 75.00% 70.00% 65.00% 60.00% 0 20 40 60 80 100 120 Output Power (W) Phase Node Waveform of Two-Channel Application Circuit (Vin = 24V, Load Current = 12A for 5V, Load Current = 18A for 3.3V) ch1: Vphase5V; ch2: Vphase3.3V www.semtech.com  2007 Semtech Corp. 10 Efficiency SC2449 POWER MANAGEMENT Electrical Characteristic Curves (Cont.) 3.3V Channel Gate Waveform (Vin = 24V, Load Current = 18A) ch1: VgateH; ch2: VgateL 5.0V Channel Gate Waveform (Vin = 24V, Load Current = 12A) ch1: VgateH; ch2: VgateL  2007 Semtech Corp. 11 www.semtech.com SC2449 POWER MANAGEMENT Electrical Characteristic Curves (Cont.) Start-up (Vin = 24V, Vout1 = 5.0V/12A, Vout2 = 3.3V /18A) ch1: Vout5.0V; ch2: Vout3.3V Bi-Phase Operation (Vout = 3.3V, Max. Load Current = 20A) Efficiency in Bi-Phase Application Circuit (3.3V/20A) Overall System Efficiency vs. iLoad 90.00% 85.00% 80.00% 75.00% Overall Efficiency 70.00% 65.00% 60.00% 0 5 10 15 20 Load Current (A) www.semtech.com  2007 Semtech Corp. 12 Efficiency SC2449 POWER MANAGEMENT Electrical Characteristic Curves (Cont.) Phase Node Waveform (Vin = 24V, Vout = 3.3V, Load Current = 20A) ch1: Vphase1; ch2: Vphase2 Gate Waveform (Vin = 24V, Vout = 3.3V, Load Current = 10A/phase) ch1: VgateL; ch2: VgateH  2007 Semtech Corp. 13 www.semtech.com SC2449 POWER MANAGEMENT Electrical Characteristic Curves (Cont.) Start-up (Vin = 24V, Vout = 3.3V, Load Current = 5A/phase) ch1: Vout Theory of Operation matched timing signal is generated to control the upper The SC2449 employs a voltage mode control with feed and lower gate drives of the two phases. A single Ramp forward to provide fast output response to load and line signal is used to generate the control signals for both of transients. phases, hence the maximum duty cycle is less than 50%. The SC2449 has two outputs, which can be used to gen- erate two separate supply voltages or can be combined Oscillator Frequency Selection in bi-phase operation to generate one single supply volt- age. The internal reference is trimmed to 1 V with +/-1% The sawtooth signal is generated by charging an internal accuracy, and the outputs voltages can be adjusted by capacitor with a current source. The charge current is two external resistors. In bi-phase operation, the dual set by an external resistor connected from the RREF pin switching regulators are operated 180° out of phase. to AGND. The oscillator frequency and the external resis- tance follow an inversely proportional relationship. Load current sharing between phases is normally re- quired, and this can be achieved by using precise feed- back voltage divider resistors (typically 0.1%) to match Feed Forward individual phase output voltage. In addition, small droop- ing resistors ( could be PCB traces) are employed at the The SC2449 incorporates a voltage feed forward scheme to improve line transient immunity when changes of the output of each phase to enhance phase current balance. input voltage occur. As the input voltage changes, the PWM Control ramp valley to peak voltage of the internal oscillator fol- lows this change instantly. As a result the output voltage Changes on the output voltages are fed to the inverting will have minimum disturbance due to the input line change. input of the Error Amplifiers, by the FB1 and FB2 pins, and compared with the internal 1 V reference. The com- pensation to the transconductance amplifier is achieved Synchronized Operation by connecting a capacitor in series with a resistor from the COMP1 and COMP2 pins to AGND respectively. The The internal oscillator can be synchronized to an exter- error signal from the error amplifier is compared to the nal clock operating in the range of 270 kHz to 1 MHz. saw tooth waveform by the PWM comparator, and www.semtech.com  2007 Semtech Corp. 14 SC2449 POWER MANAGEMENT Theory of Operation (Cont.) BG capacitor is being charged through the internal resis- The switching frequency of each channel is one half of tor, the PWM pulse width increases until the bandgap is the oscillator frequency. The oscillator clock is also avail- charged completely. This controlled start up of the PWM able externally through the CLKOUT pin and can be used prevents output voltage overshoot, unnecessary com- to provide synchronization for other converters. ponent stress, and noise generation during start up. Bias Generation Over Current Protection A 6-7 Volt supply voltage is required to power up the The SC2449 current limit provides protection during an SC2449. This voltage could be provided by an external over current condition. A sense resistor or PCB trace power supply or derived from VIN through an external can be used to sense the input supply current. pass transistor. REGDRV is the control signal to the base of the pass transistor that will regulate VCC. The voltage The over current protection trip point is determined by at the VCC pin is compared to the internal voltage refer- the voltage drop across the sense resistor. Once this ence, and the REGDRV pin can sink up to 5mA current to voltage drop exceeds the voltage across the program- regulate the voltage at the VCC pin. ming resistor (50µA through R26), OCP protection circuit will be triggered. Due to component and layout parasitics, Enable filtering might be necessary across the OC+ and OC- pins. It is recommended to use a small RC filter with time con- If the ENABLE pin is connected to logic high, the SC2449 stant around 0.2µS. To clean up the phase node ringing, is enabled, while connecting it to ground will put the de- one usually has to have a ceramic capacitor from the vice into disabled mode. The ENABLE pin can also be top FET drain to the power ground. Too much capaci- configured as input UVLO through input voltage divider tance will bypass the top FET current from the sensing resistors. The controller will be enabled when the EN- resistor hence reducing OCP accuracy, while to little ca- ABLE pin voltage reaches 2.05 V, and will be disabled pacitance will not be able to clean up the phase node with 400mV hysteresis. ringing for full load operation. See application circuits. Under Voltage Lockout Once an over current condition occurs, the lower MOSFET gates are latched on and the upper MOSFET gates are Under Voltage lockout (UVLO) circuitry senses VCC through latched off. The latch is then reset at the beginning of a voltage divider. If this signal falls below 5.8V, with a the next clock cycle. The cycle is repeated indefinitely typical hysteresis of 400 mV, the BG pin is pulled low by until the over current condition is removed. an internal transistor causing the lower MOSFET gate to be on and the upper MOSFET gate off for both phases. Thermal Shutdown Over Voltage Protection In addition to current limit, the SC2449 monitors over temperature condition. The over temperature detection The SC2449 provides OVP protection for each output will shut down the part if the SC2449 die temperature individually. Once the converter output voltage exceeds exceeds 150°C, and will auto reset once the die tem- 120% nominal output voltage, the lower MOSFET gates perature is dropped down. are latched on and the upper MOSFET gates are latched off. The latch is then reset once the OVP condition is Gate Drive removed. The SC2449 integrates high current gate drivers for fast Soft Start switching of large MOSFETs. The high-side gates can be switched with peak currents of 1 Amp, while the larger An external capacitor at the BG pin is used to set up the low-side gates can be switched with peak currents of 2 Soft Start duration. The capacitor value, in conjunction Amps. A cross conduction prevention circuitry ensures a with the internal 3K resistor at the BG pin, control the non-overlapping operation between the upper and lower duration to bring up the bandgap to its final level. As the MOSFETs. This prevents false current limit tripping and provides high efficiency.  2007 Semtech Corp. 15 www.semtech.com SC2449 POWER MANAGEMENT Control Loop Design R2 R1 The task here is to properly choose the compensation network for a nicely shaped loop-gain Bode plot. The 0 following design procedures are recommended to accom- Gpwm Error-Amp plish the goal: L Verror Duty - + (1) Calculate the corner frequency of the output filter: R Rc + + 1 Ro Vin Vbg F o Co C - - . . . 2 π L C o 0 0 0 0 (2) Calculate the ESR zero frequency of the output filter capacitor: Fig. 1. SC2449 control model. 1 F esr The control model of SC2449 can be depicted in Fig. 1. . . . π 2 R C c o This model can also be used in a Spice kind of simulator (3) Check that the ESR zero frequency is not too high. to generate loop gain Bode plots. The bandgap refer- ence is 1 V and trimmed to +/-1% accuracy. The de- F sw sired output voltage can be achieved by setting the re- < F ers 5 sistive divider network, R1 and R2. If this condition is not met, the compensation structure may not provide loop stability. The solution is to add The error amplifier is transconductance type with fixed some electrolytic capacitors to the output capacitor bank gain of: . . . . A . . to correct the output filter corner frequency and the ESR ⋅ G 0.002 error V zero frequency. In some cases, the filter inductance may also need to be adjusted to shift the filter corner fre- The compensation network includes a resistor and a ca- pacitor in series, which terminates from the output of quency. It is not recommended to use only high frequency the error amplifier to the ground. multi-layer ceramic capacitors for output filter. (4) Choose the loop gain cross over frequency (0 dB fre- This device uses voltage mode control with input voltage quency). It is recommended that the crossover frequency feed forward. The peak-to-peak ramp voltage is propor- is always less than one fifth of the switching frequency tional to the input voltage, which results in an excellent or the output ripple frequency in bi-phase mode performance to reject input voltage variation. The PWM operation: gain is inversion of the ramp amplitude, and this gain is F given by: sw F x_over 5 1 G pwm If the transient specification is not stringent, it is better V ramp to choose a crossover frequency that is less than one where the ramp amplitude (peak-to-peak) is 3 volts when tenth of the switching frequency for good noise immu- input voltage is 24 volts. nity. The resistor in the compensation network can then be calculated as: The total control loop-gain can then be derived as fol- 2 lows: F F V 1 esr x_over o . . . R . . . . G V G F F V 1sR C . . 1sR C c o pwm in error o esr bg . . Ts () T o . . sR C R L c 2 . . . . . 1s R C s L C 1 when: c o o R R < < F F F o o o esr x_over where . . . . R 2 . . . . G T G V R o error in pwm R R 1 2 www.semtech.com  2007 Semtech Corp. 16 SC2449 POWER MANAGEMENT Control Loop Design (Cont.) or Step 1. Output filter corner frequency 2 F F V 1 o x_over o . . . F = 1.453 KHz R o . . G V G F F V pwm in error esr o bg Step 2. ESR zero frequency: when F = 2.653 KHz esr F < F < F esr o x_over Step 3. Check the following condition: (5) The compensation capacitor is determined by choos- ing the compensator zero to be about one fifth of the F output filter corner frequency: sw < F ers 5 F o F Which is satisfied in this case. zero 5 Step 4. Choose crossover frequency and calculate 1 C compensator R: . . . π 2 R F zero F = 30 KHz x_over (6) The final step is to generate the Bode plot, either by using the simulation model in Fig. 1 or using the equa- R = 5.89 KΩ tions provided here with Mathcad. The phase margin can then be checked using the Bode plot. Usually, this Step 5. Calculate the compensator C: design procedure ensures a healthy phase margin. C = 92.98 nF An example is given below to demonstrate the proce- dure introduced above. The parameters of the power Step 6. Generate Bode plot and check the phase supply are given as: margin. In this case, the phase margin is about 85°C that ensures the loop stability. Fig. 2 shows the Bode V := 24 V in plot of the loop. V := 2.5 V o I := 20 A o F := 150 KHz sw L := 4 µH C := 3000 µF o R := 0.02 Ω c R := 1.5 KΩ 1 R := 1.0 KΩ 2  2007 Semtech Corp. 17 www.semtech.com SC2449 POWER MANAGEMENT Control Loop Design (Cont.) L oop G ain M ag (dB ) 100 50 mag() i 0 50 3 4 5 6 10 100 1 10 1 10 1 10 1 10 F i L oop G ain P h ase (D egree) 0 45 phase() i 90 135 180 3 4 5 6 10 100 1 10 1 10 1 10 1 10 F i Fig. 2. Bode plot of the loop Layout Guidelines Good layout is necessary for successful implementa- 3). Separate ground planes for analog and power should tion of the SC2449 bi-phase/dual controller. Important be provided. Power current should avoid running over layout guidelines are listed below. the analog ground plane. The AGND is star connected to the PGND at the converter output to provide best pos- 1). The high power parts should be laid out first. The para- sible ground sense. Refer to the application schematics, sitic inductance of the pulsating power current loop (start certain components should be connected directly to the from positive end of the input capacitor, to top MOSFET, AGND. then to bottom MOSFET back to power ground) must be minimized. The high frequency input capacitors and top 4). If a multi-layer PCB is used, power layer and ground MOSFETs should be close to each other. The freewheel- layer are recommended to be adjacent to each other. ing Schottky diode, the bottom MOSFET snubber, and Typically the power layer is on the top, followed by the the bottom MOSFET should be placed close to each other. ground layer. This results in the least parasitic inductance The MOSFET gate drive and current sense loop areas in the MOSFET-capacitor power loop, and reduces the should be minimized. The gate drive trace should be ringing on the phase node. The rest of the layers could short and wide. be used to run DC supply traces and signal traces. 2). The layout of the two phases should be made as sym- An example of a two-layer PCB layout is given below to metrical as possible. The SC2449 controller should be illustrate these layout principles. placed in the center of the two phases. Please see evalu- ation board layout as an example. www.semtech.com  2007 Semtech Corp. 18 SC2449 POWER MANAGEMENT Layout Guidelines (Cont.) Component Side (TOP) Copper (TOP)  2007 Semtech Corp. 19 www.semtech.com SC2449 POWER MANAGEMENT Layout Guidelines (Cont.) PG ND AGND Copper (BOTTOM) www.semtech.com  2007 Semtech Corp. 20 SC2449 POWER MANAGEMENT Outline Drawing - SO-28 DIMENSIONS A D INCHES MILLIMETERS e N DIM MIN NOM MAX MIN NOM MAX - - A .093 .104 2.35 2.65 A1 .004 - .012 0.10 - 0.30 A2 .081 - .100 2.05 - 2.55 2X E/2 - - b .012 .020 0.31 0.51 c - - .008 .013 0.20 0.33 D .701 .705 .709 17.80 17.90 18.00 E1 .291 .295 .299 7.40 7.50 7.60 E1 E E .406 BSC 10.30 BSC e .050 BSC 1.27 BSC h .010 - .030 0.25 - 0.75 - - L .016 .041 0.40 1.04 (.041) (1.04) L1 N 28 28 01 0° - 8° 0° - 8° 1 2 3 ccc C aaa .004 0.10 2X N/2 TIPS bbb .010 0.25 e/2 ccc .013 0.33 B D aaa C A2 A h SEATING PLANE h bxN A1 C H bbb C A-B D c GAGE PLANE 0.25 L SEE DETAIL A 01 SIDE VIEW (L1) NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). DETAIL A 2. DATUMS AND TO BE DETERMINED AT DATUM PLANE -A- -B- -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-013, VARIATION AE. Land Pattern - SO-28 X DIMENSIONS DIM INCHES MILLIMETERS C (.362) (9.20) (C) G Z G .276 7.00 .050 P 1.27 X .024 0.60 Y .087 2.20 Z .449 11.40 Y P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A, RLP NO. 307A. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2007 Semtech Corp. 21 www.semtech.com