SEMTECH SC2446

SC2446 Dual-Phase Single or Two Output Synchronous Step-Down Controllers POWER MANAGEMENT Features Description ‹‹‹‹‹ 2-Phase synchronous continuous conduction mode The SC2446 is a high-frequency dual synchronous step- down switching power supply controller. It provides out- for high efficiency step-down converters of-phase high-current output gate drives to all N-chan- ‹‹‹‹‹ Out of phase operation for low input current ripples nel MOSFET power stages. The SC2446 operates in syn- ‹‹‹‹‹ Output source and sink currents chronous continuous-conduction mode. Both phases are ‹‹‹ Fixed frequency peak current-mode control ‹‹ capable of maintaining regulation with sourcing or sink- ‹‹‹‹‹ 75mV/-110mV maximum current sense voltage ing load currents, making the SC2446 suitable for gen- ‹‹‹‹‹ Synthesized MOSFET R current-sensing for DS(ON) erating both V and the tracking V for DDR applica- DDQ TT low-cost applications tions. ‹‹‹‹‹ Optional resistor current-sensing for precise current- The SC2446 employs fixed frequency peak current-mode limit control for the ease of frequency compensation and fast ‹‹‹ Dual outputs or 2-phase single output operation ‹‹ transient response. ‹‹‹‹‹ Excellent current sharing between individual phases The dual-phase step-down controllers of the SC2446 can ‹‹‹‹‹ Wide input voltage range: 4.7V to 16V be configured to provide two individually controlled and ‹‹‹‹‹ Individual soft-start, overload shutdown and enable regulated outputs or a single output with shared current ‹‹‹‹‹ Duty cycle up to 88% in each phase. The Step-down controllers operate from an input of at least 4.7V and are capable of regulating out- ‹‹‹ 0.5V feedback voltage for low-voltage outputs ‹‹ puts as low as 0.5V ‹‹‹‹‹ External reference input for DDR applications The step-down controllers in the SC2446 have the pro- ‹‹‹‹‹ Buffered V /2 output DDQ vision to sense a synthesized MOSFET R for cur- DS(ON) ‹‹‹‹‹ Programmable frequency up to 1 MHz per phase rent-mode control. This sensing scheme (U.S. patent ‹‹‹‹‹ External synchronization 6,441,597) eliminates the need of the current-sense re- ‹‹‹ Industrial temperature range ‹‹ sistor and is more noise-immune than direct sensing of ‹‹‹‹‹ 28-lead TSSOP - EDP package the high-side or the low-side MOSFET voltage. Precise cur- rent-sensing with sense resistor is optional. Applications Individual soft-start and overload shutdown timer is in- cluded in each step-down controller. The SC2446 imple- ‹‹‹‹‹ Telecommunication power supplies ments hiccup overload protection. In two-phase single- ‹‹‹ DDR memory power supplies ‹‹ output configuration, the master timer controls the soft- ‹‹‹‹‹ Graphic power supplies start and overload shutdown functions of both control- ‹‹‹‹‹ Servers and base stations lers. Typical Application Circuit VIN C92 D11 D12 PVCC Q21 Q22 BST2 BST1 R73 R74 GDH2 GDH1 VO2 VO1 L11 C93 C94 L12 C99 C95 Q23 Q24 C98 C100 CFILTER R77 R78 CFILTER + + GDL2 GDL1 C96 R75 R76 C97 R79 RFILTER RFILTER R80 PGND VPN2 VPN1 RCS+ RCS+ CS2+ CS1+ RCS- RCS- CS2- CS1- R81 R82 IN2- IN1- C101 C102 COMP2 COMP1 R83 C103 REF C104 C105 R84 REFIN REF VIN VIN2 AGND SYNC R85 SYNC Rosc VIN SS1/EN1 AVCC SS2/EN2 REFOUT C106 C107 C108 C109 U1 SC2446 Figure 1 Dual Independant Outputs 1 Revision: September 9, 2004 U.S. Patent No. 6,441,597, www.semtech.com SC2446 POWER MANAGEMENT Absolute Maximum Rating Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Ss ymboMs aximum Rating Unit SC upply Voltage For Step-Down ControllersA0 VCC, PVC -V 0.3 to 2 IV nput Voltage For the Second Converter -V 0.3 to 20 IN2 High-Side Driver Supply Voltages -0.3 to 32 (steady state) V V V BST1, BST2 -0.3 to 40 (for <10ns @ freq. < 500kHz) VPN -0.3 to 20 (steady state) V V VPN -0.3 to 26 (for <10ns @ freq. < 500kHz) IV N1-, IN2- Voltages ,V -V 0.3 to AVCC+0.3 IN1- IN2- REF, REFVV oltages ,V -V 0.3 to 6 OUT REF REFOUT REFVV oltage -V 0.3 to AVCC+0.3 IN REFIN CV OMP1, COMP2 Voltages V -V 0.3 to AVCC+0.3 COMP1, COMP2 CV S1+, CS1-, CS2+ and CS2- Voltages V V V-V 0.3 to AVCC+0.3 CS1+, CS1-, CS2+, CS2- SV YNC Voltage -V 0.3 to AVCC+0.3 SYNC SV S1/EN1 AND SS2/EN2 Voltages V -V 0.3 to 6 SS1, SS2 PI eak Gate Drive Currents , I , I , I 3A GDH1 GDH2 GDL1 GDL2 PI eak VPN1 and VPN2 Output Currents , I 1A 00 m VPN1 VPN2 AT mbient Temperature Range -C 40 to 85 ° A Thermal Resistance Junction to Case (TSSOP-28) 1W 3 °C/ θ JC Thermal Resistance Junction to Ambient (TSSOP-28) 8W 4 °C/ θ JA ST torage Temperature Range -C 60 to 150 ° STG LT ead Temperature (Soldering) 10 sec 2C 60 ° LEAD MT aximum Junction Temperature 1C 50 ° J Electrical Characteristics Unless specified: AVCC = PVCC = V =12V, V = V = 12V, SYNC= 0, R = 51.1kΩ, -40°C < T = T < 85°C IN2 BST1 BST2 OSC A J Pl arameter Ss ymboCn ondition Mp i Tx y Ms a Unit Undervoltage Lockout AC VCC Start Threshold AVC 47 .5 4V . Ag VCC Increasin TH AC VCC Start Hysteresis AVC 0V .17 HYST AI VCC Operating Current A2 VCC= 12V 161A m CC AC VCC Quiescent Current in UVLO AVCC = AVC-7 0.2V 1A . m TH Channel 1 Error Amplifier NV on-inverting Input Voltage 00 .49000 .500V .51 IN1+ NC on-inverting Input Line Regulation AVC<2 AVCC< 15V 0V .0 %/ TH Input Offset Voltage 13±V m II nverting Input Bias Current -0 100-A 25 n IN1- −1 AG mplifier Transconductance 260 µΩ M1 Aa mplifier Open-Loop Gain 6d 5 Β OL1 Amplifier Unity Gain Bandwidth 5 ΜΗz V = V = 0 CS1+ CS1- Minimum COMP1 Switching Threshold 2V .2 V Increasing SS1 www.semtech.com  2004 Semtech Corp. 2 SC2446 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: AVCC = PVCC = V =12V, V = V = 12V, SYNC= 0, R = 51.1kΩ, -40°C < T = T < 85°C IN2 BST1 BST2 OSC A J Pl arameter Ss ymboCn ondition Mp i Tx y Ms a Unit AV mplifier Output Sink Current = 1V, V=6 2.5V 1 µA IN1- COMP1 AV mplifier Output Source Current = 0, V=2 2.5V 1 µA IN1- COMP1 Channel 2 Error Amplifier Input Common-mode Voltage Range (Note 1) 03V I) nverting Input Voltage Range (0 Note 1 AV VCC Input Offset Voltage 13 .5 ±V m NI on-inverting Input Bias Current -0 150-A 38 n IN2+ II nverting Input Bias Current -0 100-A 25 n IN2- Inverting Input Voltage for 2-Phase Single 2V .5 Output Operation −1 AG mplifier Transconductance 260 µΩ M2 Aa mplifier Open-Loop Gain 6d 5 Β OL2 Amplifier Unity Gain Bandwidth 5z MH V = V = 0 CS2+ CS2- Minimum COMP2 Switching Threshold 2V .2 V Increasing SS2 Amplifier Output Sink Current 16 V = 2.5V µA COMP2 Amplifier Output Source Current V = 2.5V 12 µA COMP2 Oscillator Cf hannel Frequency f 40 5050 0 5z 5 KH CH1, CH2 S) ynchronizing Frequency (f Note 1 2.1 KHz CH SYNC Input High Voltage 1V .5 SYNC Input Low Voltage 0V .5 V = 0.2V 1 SYNC SI YNC Input Current µA SYNC V = 2V 100 SYNC CD hannel Maximum Duty Cycle D 8% 8 MAX1, MAX2 CD hannel Minimum Duty Cycle D 0% MIN1, MIN2 Current-limit Comparators Input Common-Mode Range 01 AVCC - V V V = V = 0.5V, ILIM1+, CS1- CS2- Cycle-by-cycle Peak Current Limit 65 0 709V m V Sourcing Mode ILIM2+ Valley Current Overload Shutdown V = V = 0.5V, CS1- CS2- V V -0 85-0 11 -V 13 m ILIM1-, ILIM2- Threshold Sinking Mode V =V = 0 CS1+ CS1- PI ositive Current-Sense Input Bias Current I -2 0.7 - µA CS1+, CS2+ V =V = 0 CS2- CS2- Negative Current-Sense Input Bias V =V = 0 CS1+ CS1- I I -2 0.7 - µA CS1-, CS2- Current V =V = 0 CS2+ CS2- Gate Drivers High-side Gate Drive Peak Source V ,V=5 12V 1A . BST1 BST2 Current HV igh-side Gate Drive Peak Sink Current ,V=1 12V A BST1 BST2  2004 Semtech Corp. 3 www.semtech.com SC2446 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: AVCC = PVCC = V =12V, V = V = 12V, SYNC= 0, R = 51.1kΩ, -40°C < T = T < 85°C IN2 BST1 BST2 OSC A J Pl arameter Ss ymboCn ondition Mp i Tx y Ms a Unit Low-side Gate Drive Peak Source A5 VCC = PVCC =12V 1A . Current Low-side Gate Drive Peak Sink Current A1 VCC = PVCC =12V A GC ate Drive Rise Time =0 2200pF 2s n L Gate Drive Fall Time C=0 2200pF 2s n L Low-side Gate Drive to High-side Gate C=0 0 9s n L Drive Non-overlapping Delay High-side Gate Drive to Low-side Gate C=0 0 9s n L Drive Non-overlapping Delay MC inimum On-Time T0 A = 25° 1s 5 n Soft-Start, Overload Latchoff and Enable SI oft-Start Charging Current I V =V =V12 .5 µA SS1, SS2 SS1 SS2 Overload Latchoff Enabling Soft-Start V aV ndI2 ncreasing 3V . SS1 SS2 Voltage OV verload Latchoff IN1- Threshold = 3.8V, VDV ecreasing 0.75 V SS1 IN1- REF 0.72 X OV verload Latchoff IN2- Threshold = 3.8V, V Decreasing V SS2 IN2- V REFIN V =V 0.5 , IN1- REF I SS1(DIS), Soft-Start Discharge Current V =V 0.5 , 1.4 µA IN2- REFIN I SS2(DIS) V =V =V 3.8 SS1 SS2 Overload Latchoff Recovery Soft-Start V SSRCV1, V aV ndD3 ecreasing 05 . 07 . 0V . SS1 SS2 Voltage V SSRCV2 Gate Drive Disable SS/EN Voltage 09 .70V . Gate Drive Enable SS/EN Voltage 15 .2 1V . Channel 1 Virtual Phase Node Voltage OV utput High Voltage I = -100µA, V=V 24V-V 0.05 VPN1H VPN1 BST1 PVCC OV utput Low Voltage I = 100µA, V=0 24V 2V m VPN1L VPN1 BST1 V = 24V, BST1 Output Sourcing Current 7A m V = V - 0.2V VPN1 PVCC OV utput Sinking Current = 24V, V=7 0.2V mA BST1 VPN1 Channel 2 Virtual Phase Node Voltage OV utput High Voltage I = -100µA, V=V 24V-V 0.05 VPN2H VPN2 BST2 IN2 OV utput Low Voltage I = 100µA, V=0 24V 2V m VPN2L VPN2 BST2 V = 24V, BST2 Output Sourcing Current 7A m V = V - 0.2V VPN2 IN2 Output Sinking Current V = 24V, V=7 0.2V mA BST2 VPN2 External Reference Buffer EV xternal Reference Input Voltage Range 04V REFIN V -0.01 V +0.01 BV uffered Output Voltage V =1.25V, I = -1mA V V REFIN REFIN REFOUT REFIN REFOUT REFIN www.semtech.com  2004 Semtech Corp. 4 SC2446 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: AVCC = PVCC = V =12V, V = V = 12V, SYNC= 0, R = 51.1kΩ, -40°C < T = T < 85°C IN2 BST1 BST2 OSC A J Pl arameter Ss ymboCn ondition Mp i Tx y Ms a Unit LI oad Regulation 0 <<2 -5mA 0A .0 %/m REFOUT Internal 0.5V Reference Buffer OV utput Voltage I=0 -1mA 40 9 50 0 5V 1 m REF REF LI oad Regulation 0 <<5 -5mA 0A .0 %/m REF Notes: (1) Guaranteed by design not tested in production. (2) This device is ESD sensitive. Use of standard ESD handling precautions is required. Pin Configurations Ordering Information (TOP VIEW) (1) De evice Packag Temp. Range( T ) A CS1+ SS1/EN1 (2) SC2446ITETRTTC SSOP-28-EDP -40 to 85° CS1- VPN1 BST1 ROSC Sd C2446EVB Evaluation Boar IN1- GDH1 COMP1 GDL1 Notes: PVCC SYNC (1) Only available in tape and reel packaging. A reel AGND PGND contains 2500 devices for TSSOP package. REF GDL2 (2) Lead free product. GDH2 REF OUT REF BST2 IN COMP2 VPN2 IN2- VIN2 CS2- AVCC CS2+ SS2/EN2 (28-Pin TSSOP) Figure 2  2004 Semtech Corp. 5 www.semtech.com SC2446 POWER MANAGEMENT Pin Descriptions TSSOP Package Pe inPn in Nam Pin Functio 1+ CS1 The Non-inverting Input of the Current-sense Amplifier/Comparator for the Controller 1. The Inverting Input of the Current-sense Amplifier/Comparator for the Controller 1. Normally 2- CS1 tied to the output of the converter. 3C ROS An external resistor connected from this pin to GND sets the oscillator frequency. Inverting Input of the Error Amplifier for the Step-down Controller 1. Tie an external resistive 4- IN1 divider between OUTPUT1 and the ground for output voltage sensing. The Error Amplifier Output for Step-down Controller 1. This pin is used for loop 51 COMP compensation. Edge-triggered Synchronization Input. When not synchronized, tie this pin to a voltage above 6C SYN 1.5V or the ground. An external clock (frequency > frequency set with ROSC) at this pin synchronizes the controllers. 7DA. GN Analog Signal Ground Buffered Output of the Internal 0.5V Reference. The non-inverting input of the error amplifier 8F RE for the step-down converter 1 is internally connected to this pin . 9F RE Buffered output of the external voltage applied to Pin 10. OUT An external Reference voltage is applied to this pin.The non-inverting input of the error 1F 0 RE IN amplifier for the step-down converter 2 is internally connected to this pin. The Error Amplifier Output for Step-down Controller 2. This pin is used for loop 12 1 COMP compensation. Inverting Input of the Error Amplifier for the Step-down Controller 2. Tie an external resistive 1- 2 IN2 divider between output2 and the ground for output voltage sensing. Tie to AVCC for two-phase single output applications The Inverting Input of the Current-sense Amplifier/Comparator for the Controller 2. Normally 1- 3 CS2 tied to the output of the converter. 1+ 4 CS2 The Non-inverting Input of the Current-sense Amplifier/Comparator for the Controller 2 An external capacitor tied to this pin sets (i) the soft-start time (ii) output overload latch off 12 5 SS2/EN time for step-down converter 2. Pulling this pin below 0.7V shuts off the gate drivers for the second controller. Leave open for two-phase single output applications. 1C 6 AVC Power Supply Voltage for the Analog Portion of the Controllers. This pin is tied to the voltage supplying the drain of the high side power MOSFET of converter 12 7 VIN 2. This pin is used only in "Combi" current sense. The Second Step-down Converter Virtual Phase Node (Unloaded). Used for "Combi" current 12 8 VPN sense only. This pin is left open when sensing current with a sense resistor at the converter output. Bootstrapped Supply for the High-side Gate Drive 2. Connect to a bootstrap capacitor and an 12 9 BST external diode as described in application information. Gate Drive Output for the High-side N-channel MOSFET of Output 2. Gate drive voltage 22 0 GDH swings from ground to VBST2. www.semtech.com  2004 Semtech Corp. 6 SC2446 POWER MANAGEMENT Pin Descriptions Pe inPn in Nam Pin Functio Gate Drive Output for the Low-side N-channel MOSFET of Output 2. Gate drive voltage 22 1 GDL swings from ground to PVCC. 2D 2P. GN Ground Supply for All the Gate drivers 2C 3P. VC Power Supply Voltage for Low-side MOSFET Drivers Gate Drive Output for the Low-side N-channel MOSFET of Output 1. Gate drive voltage 21 4 GDL swings from ground to PVCC. Gate Drive Output for the High-side N-channel MOSFET of Output 1. Gate drive voltage 21 5 GDH swings from ground to VBST1. Bootstrapped Supply for the High-side Gate Drive 1. Connect to a bootstrap capacitor and an 21 6 BST external diode as described in application information. The First Step-down Converter Virtual Phase Node (Unloaded). Used for "Combi" current 21 7 VPN sense only. This pin is left open when sensing current with a sense resistor at the converter output. An external capacitor tied to this pin sets (i) the soft-start time (ii) output overload latch off 21 8 SS1/EN time for buck converter 1. Pulling this pin below 0.7V shuts off the gate drivers for the first controller.  2004 Semtech Corp. 7 www.semtech.com SC2446 POWER MANAGEMENT Block Diagram SYNC AVCC 6 CLK2 16 REFERENCE OSCILLATOR RO SC CLK1 UVLO 3 4.3/4.5V BST1 CO M P1 26 5 IN1- GDH 1 4 25 - R EA1 REF/IN1+ - PWM Q Non-Overlapping + 8 S PVCC + Conduction 0.5V 23 Control + GD L1 UVLO - 24 0.75 VREF VPN1 SLOPE CS1 + CO M P 27 OL Soft-Start And 1 + PGND + + DSBL CS1 - Ove rload ISEN Σ 22 2 - Hiccup SS1/EN1 Control 28 + ILIM+ - GDH 2 75mV 20 - OCN VIN2 ILIM- 110mV 17 + CO M P2 VPN2 11 18 IN2- 12 - EA2 GD L2 REF /IN2+ IN + 21 10 + REF OUT - 9 0.72 VREF AG N D OUT 7 Figure 3. SC2446 Block Diagram (Channel 1 PWM Control Only) OCN IN- - S 0.75(V ) REF + 2µΑ OL Q / 0.72(V ) REFOUT R SS/EN 0.5V/3.2V DSBL UVLO 0.9V/1.2V 3.4µΑ Figure 4. Soft-Start and Overload Hiccup Control Circuit www.semtech.com  2004 Semtech Corp. 8 SC2446 POWER MANAGEMENT Operation Overview The SC2446 is a constant frequency 2–phase current- inductor current reaches the threshold determined by mode step-down PWM switching controller driving all N- the error amplifier output and ramp compensation, the channel MOSFET’s. The two channels of the controller high-side MOSFET is turned off. After a non-overlapping operate at 180 degrees out of phase from each other. conduction time of 90ns, the low-side MOSFET is turned Since input currents are interleaved in a two-phase on. converter, input ripple current is lower and smaller input capacitor can be used for filtering. Also, with lower The supply voltages for the high-side gate drivers are inductor current and smaller inductor ripple current per obtained from two diode-capacitor bootstrap circuits. If the 2 phase, overall I R losses are reduced. bootstrap capacitor is charged from V , the high-side gate CC drive voltage swing will be from approximately 2V to the CC The SC2446 operates in synchronous continuous- ground. The power dissipated in the high-side gate driver conduction mode. It can be configured either as two is not higher with higher voltage swing because the gate- independent step-down controllers producing two source voltage of the high-side MOSFET still swing from separate outputs or as a dual-phase single-output zero to V .The outputs of the low-side gate drivers swing CC controller by tying the IN2- pin to V . In single output from V to the ground. CC C operation, the channel one error amplifier controls both channels and the channel two error amplifier is disabled. The SC2446 has internal ramp-compensation to prevent Soft-start and overload hiccup of both channels is sub-harmonic oscillation when operating above 50% duty synchronized to channel one. cycle. There is enough ramp internally for a sensed voltage ripple between ¼ to 1/3 of the full-scale sensed Frequency Setting and Synchronization voltage limit of 75mV. The maximum sensed voltage limit is unaffected by the compensation ramp. The internal oscillator of the SC2446 runs at twice the phase frequency. The free-running frequency of the Current-Sensing oscillator can be programmed with an external resistor from the ROSC pin to the ground. The step-down controllers There are two ways to sense the inductor current for are capable of operating up to 1 MHz. It is necessary to current-mode control with the SC2446. Since the peak consider the operating duty-ratio before deciding the inductor current corresponds to 75mV of sensed voltage switching frequency. See Applications Information section (CS+ - CS-), resistor current sensing can be used at the for more details. output without resulting in excessive power dissipation. Although accurate and far easier to lay out than high- When synchronized externally, the applied clock frequency side resistor sensing, a pair of precision sense resistors should be twice the desired phase frequency. The adds cost to the converter. The SC2446 has provision to synchronizing clock frequency should also be between 1- reconstruct a differential voltage proportional to the 1.33 times the set free-running frequency. inductor current at the output of the converter (U.S. patent 6,441,597). The voltage to current ratio or the equivalent Control Loop sense resistance R is a combination of high-side and low- eq side MOSFET R ’s and the inductor series resistance DS(ON) The SC2446 uses peak current-mode control for fast (hence the name “Combi-Sense”). The SC2446 provides transient response, ease of compensation and current the virtual phase voltages VPN1 and VPN2 (these are sharing in single output operation. The low-side MOSFET of each channel is turned off at the falling-edge of the phase timing clock. After a brief non-overlapping time interval of 90ns, the high-side MOSFET is turned on. The phase inductor current ramps up. When the sensed  2004 Semtech Corp. 9 www.semtech.com SC2446 POWER MANAGEMENT Operation (Cont.) unloaded versions of their respective power phase Soft-Start and Overload Protection voltages) for current sensing. This method does not require any precision sense resistor. It is cheaper to The undervoltage lockout circuit discharges the SS/EN implement but is less accurate than resistor current capacitors. After V rises above 4.5V, the SS/EN capacitors CC sensing. Since the sensed voltage is developed at the are slowly charged by internal 2µA current source. With output of the step-down converter, it is less prone to internal PNP transistors, the SS/EN voltages clamp the switching transient spikes. This method will be described error amplifier outputs. When the error amplifier output in more details in the Applications Information section. rises to 2.2V, the high-side MOSFET starts to switch. As the SS/EN capacitor continues to be charged, the COMP Error Amplifiers voltage follows. The converter gradually delivers increasing power to the output. The inductor current follows the COMP In closed loop operation, the error amplifier output ranges voltage envelope until the output goes into regulation. The from 1.1V to 3.5V. The upper output operating range of SS/EN clamp on COMP is then released. either error amplifier is reserved for positive current- sense voltage (CS+ - CS-) and corresponds to positive After the SS/EN capacitor is charged above 3.2V (high (sourcing) output current. If the amplifier swings to its enough for the error amplifier to provide full load current), lower operating range, the amplifier will still modulate the overload detection circuit is activated. If the output the high-side gate drive duty-ratio. However the peak voltage falls below 70% of its set value or the valley current-sense voltage (hence the peak inductor current) current-sense voltage exceeds –110mV, an overload latch will be limited to a negative value. The error amplifier will be set and both the top and the bottom MOSFETs will output is about 2.2V when the peak sense-voltage is zero. be turned off. The SS/EN capacitor is slowly discharged The built-in offset in the current sense amplifier together with an internal 1.4µA current sink. The overload latch is with synchronous continuous-conduction mode of reset when the SS/EN capacitor is discharged below 0.5V. operation allows the SC2446 to regulate the output The SS/EN capacitor is then recharged with the 2µA current irrespective of the direction of the load current. source and the converter undergoes soft-start. If overload persists, the SC2446 will undergo repetitive shutdown and The non-inverting input of the first feedback amplifier is restart (Figure 3). tied to the internal 0.5V voltage reference. Both the non- inverting and the inverting inputs of the second error If the output is short-circuited, the inductor current will amplifier are brought out as device pins so that the output not increase indefinitely between the time the inductor of the second converter can be made to track the output current reaching its current limit and the instant the of the first channel. For example in DDR applications, converter shuts down. This is due to cycle skipping Channel 1 can be used to generate V (2.5V) from the reduces the actual operating frequency. DDQ input (5V or 12V) and channel 2 is used to produce a tracking V (1.25V) with V being its input. The SS/EN pin can also be used as the enable input for TT DDQ that channel. Both the high-side and the low-side Current-Limit MOSFETs will be turned off if the SS/EN pin is pulled below 0.7V. The maximum current sense voltage of +75mV is the cycle-by-cycle peak current limit when the load is drawing current from the converter. There is no cycle-by-cycle current limiting when the inductor current flows in the negative direction. However once the valley of the current sense voltage exceeds –110mV, the corresponding channel will undergo shutdown and restart (hiccup). www.semtech.com  2004 Semtech Corp. 10 SC2446 POWER MANAGEMENT Application Information SC2446 consists of two current-mode synchronous buck 1) Passive component size controllers with many integrated functions. By proper 2) Circuitry efficiency application circuitry configuration, SC2446 can be used 3) EMI condition to generate 4) Minimum switch on time and 1) two independent outputs from a common input or two 5) Maximum duty ratio different inputs or 2) dual phase output with current sharing, For a given output power, the sizes of the passive 3) current sourcing/sinking from common or separate components are inversely proportional to the switching inputs as in DDR (I and II) memory application. frequency, whereas MOSFET’s/Diodes switching losses are The application information related to the converter design proportional to the operating frequency. Other issues such using SC2446 is described in the following. as heat dissipation, packaging and the cost issues are also to be considered. The frequency bands for signal Step-down Converter transmission should be avoided because of EM interference. Starting from the following step-down converter specifications, Minimum Switch On Time Consideration Input voltage range: V ∈ [V ,V ] in in,min in,max In the SC2446 the falling edge of the clock turns on the Input voltage ripple (peak-to-peak): ΔV in top MOSFET. The inductor current and the sensed voltage Output voltage: V o ramp up. After the sensed voltage crosses a threshold Output voltage accuracy: ε determined by the error amplifier output, the top MOSFET Output voltage ripple (peak-to-peak): ΔV o is turned off. The propagation delay time from the turn- Nominal output (load) current: I o on of the controlling FET to its turn-off is the minimum Maximum output current limit: I o,max switch on time. The SC2446 has a minimum on time of Output (load) current transient slew rate: dI (A/s) o about 150ns at room temperature. This is the shortest Circuit efficiency: η on interval of the controlling FET. The controller either does Selection criteria and design procedures for the following not turn on the top MOSFET at all or turns it on for at least are described. 150ns. 1) output inductor (L) type and value, For a synchronous step-down converter, the operating duty 2) output capacitor (C ) type and value, o cycle is V /V . So the required on time for the top MOSFET O IN 3) input capacitor (C ) type and value, in is V /(V fs). If the frequency is set such that the required O IN 4) power MOSFET’s, pulse width is less than 150ns, then the converter will 5) current sensing and limiting circuit, start skipping cycles. Due to minimum on time limitation, 6) voltage sensing circuit, simultaneously operating at very high switching frequency 7) loop compensation network. and very short duty cycle is not practical. If the voltage conversion ratio V /V and hence the required duty cycle O IN Operating Frequency (f ) s is higher, the switching frequency can be increased to reduce the sizes of passive components. The switching frequency in the SC2446 is user- There will not be enough modulation headroom if the on programmable. The advantages of using constant time is simply made equal to the minimum on time of the frequency operation are simple passive component SC2446. For ease of control, we recommend the required selection and ease of feedback compensation. Before pulse width to be at least 1.5 times the minimum on time. setting the operating frequency, the following trade-offs should be considered.  2004 Semtech Corp. 11 www.semtech.com SC2446 POWER MANAGEMENT Application Information (Cont.) The followings are to be considered when choosing Setting the Switching Frequency inductors. a) Inductor core material: For high efficiency applications The switching frequency is set with an external resistor above 350KHz, ferrite, Kool-Mu and polypermalloy connected from Pin 3 to the ground. The set frequency materials should be used. Low-cost powdered iron cores is inversely proportional to the resistor value (Figure 5). can be used for cost sensitive-applications below 350KHz but with attendant higher core losses. b) Select inductance value: Sometimes the calculated 800 inductance value is not available off-the-shelf. The 700 designer can choose the adjacent (larger) standard 600 inductance value. The inductance varies with 500 temperature and DC current. It is a good engineering 400 practice to re-evaluate the resultant current ripple at 300 the rated DC output current. c) Current rating: The saturation current of the inductor 200 should be at least 1.5 times of the peak inductor current 100 under all conditions. 0 0 50 100 150 200 250 Output Capacitor (C ) and V Ripple o out Rosc (k Ohm) The output capacitor provides output current filtering in steady state and serves as a reservoir during load transient. Figure 5. Free running frequency vs. R . OSC The output capacitor can be modeled as an ideal capacitor in series with its parasitic ESR (R ) and ESL (L ) (Figure esr esl Inductor (L) and Ripple Current 6). Both step-down controllers in the SC2446 operate in Co synchronous continuous-conduction mode (CCM) regardless of the output load. The output inductor selection/design is based on the output DC and transient requirements. Lesl Both output current and voltage ripples are reduced with larger inductors but it takes longer to change the inductor current during load transients. Conversely smaller inductors Resr results in lower DC copper losses but the AC core losses (flux swing) and the winding AC resistance losses are higher. A compromise is to choose the inductance such Figure 6. An equivalent circuit of C . o that peak-to-peak inductor ripple-current is 20% to 30% of the rated output load current. If the current through the branch is i (t), the voltage across b Assuming that the inductor current ripple (peak-to-peak) the terminals will then be value is δ*I , the inductance value will then be o t 1 di (t) b V (1− D) v (t) = V + i (t)dt + L + R i (t). o o o b esl esr b ∫ L = . C dt o 0 δI f o s This basic equation illustrates the effect of ESR, ESL and The peak current in the inductor becomes (1+δ/2)*Io C on the output voltage. and the RMS current is o 2 δ The first term is the DC voltage across C at time t=0. The o I = I 1+ . L,rms o 12 second term is the voltage variation caused by the charge balance between the load and the converter output. The www.semtech.com  2004 Semtech Corp. 12 fs (kHz) SC2446 POWER MANAGEMENT Application Information (Cont.) should be an order of magnitude smaller than the voltage third term is voltage ripple due to ESL and the fourth ripple caused by the ESR. To guarantee this, the term is the voltage ripple due to ESR. The total output capacitance should satisfy voltage ripple is then a vector sum of the last three 10 C > . terms. o 2πf R s esr Since the inductor current is a triangular waveform with In many applications, several low ESR ceramic capacitors peak-to-peak value δ*I , the ripple-voltage caused by o are added in parallel with the aluminum capacitors in inductor current ripples is order to further reduce ESR and improve high frequency δI o decoupling. Because the values of capacitance and ESR Δv ≈ , C 8C f o s are usually different in ceramic and aluminum capacitors, the ripple-voltage due to ESL is the following remarks are made to clarify some practical issues. δI o Δv = L f , ESL esl s D Remark 1: High frequency ceramic capacitors may not carry most of the ripple current. It also depends on the capacitor and the ESR ripple-voltage is value. Only when the capacitor value is set properly, the effect of ceramic capacitor low ESR starts to be significant. Δv = R δI . ESR esr o For example, if a 10µF, 4mΩ ceramic capacitor is connected in parallel with 2x1500µF, 90mΩ electrolytic Aluminum capacitors (e.g. electrolytic, solid OS-CON, capacitors, the ripple current in the ceramic capacitor is POSCAP, tantalum) have high capacitances and low ESL’s. only about 42% of the current in the electrolytic capacitors The ESR has the dominant effect on the output ripple at the ripple frequency. If a 100µF, 2mΩ ceramic capacitor voltage. It is therefore very important to minimize the ESR. is used, the ripple current in the ceramic capacitor will be When determining the ESR value, both the steady state about 4.2 times of that in the electrolytic capacitors. When ripple-voltage and the dynamic load transient need to be two 100µF, 2mΩ ceramic capacitors are used, the current considered. To keep the steady state output ripple-voltage ratio increases to 8.3. In this case most of the ripple < ΔV , the ESR should satisfy current flows in the ceramic decoupling capacitor. The ESR o of the ceramic capacitors will then determine the output ΔV o R < . esr1 ripple-voltage. δI o To limit the dynamic output voltage overshoot/undershoot Remark 2: The total equivalent capacitance of the filter within α (say 3%) of the steady state output voltage) from bank is not simply the sum of all the paralleled capacitors. no load to full load, the ESR value should satisfy The total equivalent ESR is not simply the parallel αV o combination of all the individual ESR’s either. Instead they < R . esr2 I should be calculated using the following formulae. o Then, the required ESR value of the output capacitors 2 2 2 2 2 should be (R + R ) ω C C + (C + C ) 1a 1b 1a 1b 1a 1b C (ω) := eq R = min{R ,R }. 2 2 2 esr esr1 esr2 (R C + R C )ω C C + (C + C ) 1a 1a 1b 1b 1a 1b 1a 1b The voltage rating of aluminum capacitors should be at 2 2 2 2 2 least 1.5V . The RMS current ripple rating should also be o R R (R + R )ω C C + (R C + R C ) 1a 1b 1a 1b 1a 1b 1b 1b 1a 1a R (ω) := eq greater than 2 2 2 2 2 (R + R ) ω C C + (C + C ) 1a 1b 1a 1b 1a 1b δI o . 2 3 where R and C are the ESR and capacitance of 1a 1a Usually it is necessary to have several capacitors of the electrolytic capacitors, and R and C are the ESR and 1b 1b same type in parallel to satisfy the ESR requirement. The capacitance of the ceramic capacitors respectively. (Figure voltage ripple cause by the capacitor charge/discharge 7)  2004 Semtech Corp. 13 www.semtech.com SC2446 POWER MANAGEMENT Application Information (Cont.) C1a C1b Ceq R1a R1b Req Figure 7. Equivalent RC branch. Req and Ceq are both functions of frequency. For rigorous design, the equivalent ESR should be evaluated at the ripple frequency for voltage ripple calculation when both ceramic and electrolytic capacitors are used. If R = R = 1a 1b R and C = C = C , then R and C will be frequency- 1 1a 1b 1 eq eq Figure 9. Typical waveforms at converter input. independent and It can be seen that the current in the input capacitor pulses R = 1/2 R and C = 2C . eq 1 eq 1 with high di/dt. Capacitors with low ESL should be used. It is also important to place the input capacitor close to the Input Capacitor (C ) in MOSFET’s on the PC board to reduce trace inductances around the pulse current loop. The input supply to the converter usually comes from a pre-regulator. Since the input supply is not ideal, input The RMS value of the capacitor current is approximately capacitors are needed to filter the current pulses at the 2 switching frequency. A simple buck converter is shown in δ D D 2 I = I D[(1+ )(1− ) + (1− D)]. Cin o 2 Figure 8. 12 η η The power dissipated in the input capacitors is then 2 P = I R . Cin Cin esr For reliable operation, the maximum power dissipation in o the capacitors should not result in more than 10 C of temperature rise. Many manufacturers specify the maximum allowable ripple current (ARMS) rating of the capacitor at a given ripple frequency and ambient temperature. The input capacitance should be high enough to handle the ripple current. For higher power applications, Figure 8. A simple model for the converter input multiple capacitors are placed in parallel to increase the ripple current handling capability. In Figure 8 the DC input voltage source has an internal impedance R and the input capacitor C has an ESR of in in R . MOSFET and input capacitor current waveforms, ESR esr voltage ripple and input voltage ripple are shown in Figure 9. www.semtech.com  2004 Semtech Corp. 14 SC2446 POWER MANAGEMENT Application Information (Cont.) 2 2 2 Sometimes meeting tight input voltage ripple I ≈ 0.5I + D (I + I ) + (D − D − 0.5)I . Cin o1 2 o1 o2 1 2 o2 specifications may require the use of larger input capacitance. At full load, the peak-to-peak input voltage If D >0.5 and D > 0.5, then 1 2 ripple due to the ESR is δ 2 2 2 Δv = R (1+ )I . I ≈ (D + D −1)(I + I ) + (1− D )I + (1− D )I . ESR esr o Cin 1 2 o1 o2 2 o1 1 o2 2 The peak-to-peak input voltage ripple due to the capacitor Choosing Power MOSFET’s is DI o Main considerations in selecting the MOSFET’s are power Δv ≈ , C C f in s dissipation, cost and packaging. Switching losses and conduction losses of the MOSFET’s are directly related to the total gate charge (C ) and channel on-resistance From these two expressions, C can be found to meet the IN g (R ). In order to judge the performance of MOSFET’s, input voltage ripple specification. In a multi-phase ds(on) the product of the total gate charge and on-resistance is converter, channel interleaving can be used to reduce ripple. The two step-down channels of the SC2446 operate at used as a figure of merit (FOM). Transistors with the same FOM follow the same curve in Figure 10. 180 degrees from each other. If both step-down channels in the SC2446 are connected in parallel, both the input and the output RMS currents will be reduced. 50 40 Ripple cancellation effect of interleaving allows the use of Cg() 100, Rds smaller input capacitors. When converter outputs are Cg() 200, Rds connected in parallel and interleaved, smaller inductors 20 Cg() 500, Rds and capacitors can be used for each channel. The total output ripple-voltage remains unchanged. Smaller inductors speeds up output load transient. 1 0 0 5 10 15 20 1 Rds 20 When two channels with a common input are interleaved, On-resistance (mOhm) FOM:100*10^{-12} the total DC input current is simply the sum of the individual FOM:200*10^{-12} DC input currents. The combined input current waveform FOM:500*10^{-12} depends on duty ratio and the output current waveform. Assuming that the output current ripple is small, the Figure 10. Figure of Merit curves. following formula can be used to estimate the RMS value of the ripple current in the input capacitor. The closer the curve is to the origin, the lower is the FOM. This means lower switching loss or lower conduction loss Let the duty ratio and output current of Channel 1 and or both. It may be difficult to find MOSFET’s with both low , D and I , I , respectively. Channel 2 be D 1 2 o1 o2 C and low R . Usually a trade-off between R and C g ds(on ds(on g has to be made. If D <0.5 and D <0.5, then 1 2 MOSFET selection also depends on applications. In many 2 2 applications, either switching loss or conduction loss I ≈ D I + D I . Cin 1 o1 2 o2 dominates for a particular MOSFET. For synchronous buck converters with high input to output voltage ratios, the top If D >0.5 and (D -0.5) < D <0.5, then 1 1 2 MOSFET is hard switched but conducts with very low duty cycle. The bottom switch conducts at high duty cycle but 2 2 2 I ≈ 0.5I + (D − 0.5)(I + I ) + (D − D + 0.5)I . switches at near zero voltage. For such applications, Cin o1 1 o1 o2 2 1 o2 MOSFET’s with low C are used for the top switch and g If D >0.5 and D < (D -0.5) < 0.5, then 1 2 1  2004 Semtech Corp. 15 www.semtech.com Gate Charge (nC) SC2446 POWER MANAGEMENT Application Information (Cont.) Q is the additional gate charge required for the switch MOSFET’s with low R are used for the bottom switch. gs2 ds(on) current to reach its full-scale value I and ds . Q is the charge needed to charge gate-to-drain (Miller) MOSFET power dissipation consists of gd capacitance when V is falling. ds a) conduction loss due to the channel resistance R , ds(on) Switching losses occur during the time interval [t , t ]. b) switching loss due to the switch rise time t and fall time 1 3 r Defining t = t -t and t can be approximated as t , and r 3 1 r f c) the gate loss due to the gate resistance R . (Q + Q )R G gs2 gd gt t = . r V − V cc gsp Top Switch: where R is the total resistance from the driver supply rail gt The RMS value of the top switch current is calculated as to the gate of the MOSFET. It includes the gate driver internal 2 δ I = I D(1+ ). impedance R , external resistance R and the gate Q1,rms o 12 gi ge resistance R within the MOSFET i.e. g The conduction losses are then 2 R = R +R +R . P = I R . gt gi ge g tc Q1,rms ds(on) V is the Miller plateau voltage shown in Figure 11. R varies with temperature and gate-source voltage. gsp ds(on) Similarly an approximate expression for t is Curves showing R variations can be found in f ds(on) manufacturers’ data sheet. From the Si4860 datasheet, is less than 8mΩ when V is greater than 10V. R ds(on) gs However R increases by 50% as the junction (Q + Q )R ds(on) gs2 gd gt o o t = . f temperature increases from 25 C to 110 C. V gsp The switching losses can be estimated using the simple Only a portion of the total losses P = Q V f is dissipated in formula g g cc s the MOSFET package. Here Q is the total gate charge g 1 δ P = (t + t )(1+ )I V f . ts r f o in s 2 2 specified in the datasheet. The power dissipated within where t is the rise time and t is the fall time of the switching the MOSFET package is r f process. Different manufactures have different definitions R g P = Q V f . and test conditions for t and t . To clarify these, we sketch tg g cc s r f R gt the typical MOSFET switching characteristics under clamped The total power loss of the top switch is then inductive mode in Figure 11. P = P +P +P . t tc ts tg If the input supply of the power converter varies over a wide range, then it will be necessary to weigh the relative importance of conduction and switching losses. This is because conduction losses are inversely proportional to the input voltage. Switching loss however increases with the input voltage. The total power loss of MOSFET should be calculated and compared for high-line and low-line cases. The worst case is then used for thermal design. Gate charge Bottom Switch: Figure 11. MOSFET switching characteristics The RMS current in bottom switch can be shown to be 2 δ In Figure 11, I = I (1− D)(1+ ). Q2,rms o 12 Q is the gate charge needed to bring the gate-to-source gs1 voltage V to the threshold voltage V , gs gs_th www.semtech.com  2004 Semtech Corp. 16 SC2446 POWER MANAGEMENT Application Information (Cont.) The conduction losses are then Integrated Power MOSFET Drivers In SC2446 there are four internally integrated gate 2 P =I R . drivers to drive all the MOSFETs in dual channels. With bc Q2,rms ds(on) the device bipolar process, emitter-follower based where R is the channel resistance of bottom MOSFET. Darlington bipolar transistors are used for the output ds(on) If the input voltage to output voltage ratio is high (e.g. stage. The key advantage of the Darlington configuration V =12V, V =1.5V), the duty ratio D will be small. Since the is that the total current gain is greatly improved which in o bottom switch conducts with duty ratio (1-D), the leads to larger driving current I . This in turn will help gs corresponding conduction losses can be quite high. reduce the MOSFETs switching losses. In order to Due to non-overlapping conduction between the top and estimate the losses associated with the gate driver, we the bottom MOSFET’s, the internal body diode or the first measured the gate driver waveform (typical external Schottky diode across the drain and source waveforms of V and I ) as shown in Figure12. ce gs terminals always conducts prior to the turn on of the bottom MOSFET. The bottom MOSFET switches on with only a diode voltage between its drain and source terminals. The switching loss 1 δ P = (t + t )(1+ )I V f bs r f o d s 2 2 is negligible due to near zero-voltage switching. The gate losses are estimated as R g P = Q V f . bg g cc s R gt The total bottom switch losses are then Figure 12. Measured gate driver output waveforms P =P +P +P . b bc bs bg with 2.2Ω current limit resistor. Once the power losses P for the top (P ) and bottom (P ) loss t b MOSFET’s are known, thermal and package design at It is clear that the saturation voltage is not a constant. It component and system level should be done to verify that changes with the driving current in a nonlinear fashion. the maximum die junction temperature (T , usually A simple formula to calculate the losses with a reasonable j,max o 125 C) is not exceeded under the worst-case condition. accuracy is not available. But, we use a curve fitting The equivalent thermal impedance from junction to technique to estimate the power losses in gate driver. ambient (θ ) should satisfy First, the saturation voltage v (t) is approximated as ja ce T − T j,max a,max θ ≤ . 1 t ja 2 − ( ) P loss T 2 1 v (t) = V 2 . ce cc θ depends on the die to substrate bonding, packaging ja material, the thermal contact surface, thermal compound Where, V is the gate driver collector voltage, T is a time cc 1 property, the available effective heat sink area and the air constant related to the fall time of v . For the example ce flow condition (free or forced convection). Actual temperature in Fig. 12, V =12V, T =0.5T with T being measured as cc 1 f f measurement of the prototype should be carried out to ~50 ns. With these parameters, the approximated v (t) is ce verify the thermal design. plotted as in Figure 13 a).  2004 Semtech Corp. 17 www.semtech.com SC2446 POWER MANAGEMENT Application Information (Cont.) T s 1 P = v (t)i (t)dt. gd ce gs ∫ T s 20 0 12 For SC2446, there are 4 gate drivers, the total gate driver v () t 10 losses is then 4P . For the example in Figure 12, the ce gd power losses for each gate driver is estimated as 122 mW when the operating frequency is about 300kHz. The 0 total losses for the 4 gate drivers is then about 488 0 8 . 05 10 mW. − 7 0t 11⋅ 0 time (s) Remark 3: It is beneficial to select low gate charge MOSFET’s for lower switching losses in the MOSFET package and lower power dissipation in the gate-driving Figure 13 a). Approximated gate driver v (t) waveform. IC. Once the MOSFET is chosen with a specified input gate ce charge, one can adjust the gate driving resistor to balance Similarly, the gate drive current is approximated as the driver IC losses and the power MOSFET switching losses. To the first order of approximation, smaller gate resistance t leads to higher gate driving current and faster MOSFET 2 −( ) t 2 T 2 i (t) = I ( switching. But, the driver incurs more power losses. On ) e . gs gsp T 2 the other hand, larger gate drive resistance limits the gate drive current, which leads to low V and less power losses. ce Where, I is a scaling parameter proportional to the gate But, the MOSFET suffers more switching losses. gsp drive peak current, T is a time constant proportional to Using low gate charge MOSFET’s reduces switching loss. 2 the fall time of v . For the example in Figure 13, To prevent shoot-through between the top and the bottom ce I =3.15A, T =0.77T with T being measured as ~50 ns. MOSFET’s during commutation, one MOSFET should be gsp 2 f f completely turned off before the other is turned on. In the SC2446 the top and the bottom gate drive pulses are 1.5 1.158 made non-overlapping. When not driving any load, the non- overlapping commutation intervals from the top to the 1 bottom and from the bottom to the top gate drives are set i () t gs at 90ns. If MOSFET’s are driven from the SC2446, the 0.5 non-overlapping commutation times will decrease due to finite gate-source voltage rise and fall times. The gate- 0 0 source voltage waveforms of the MOSFET’s should not 8 . 05 10 overlap above their respective thresholds when driven from − 7 0t 11⋅ 0 the SC2446. Use of low gate charge MOSFET’s reduces time (s) transition times and the tendency of shoot-through. The combined rise and fall times during both commutations should be less than the preset non-overlapping intervals. Figure 13 b). Approximated gate drive current i (t) gs waveform. Current Sensing (Combi-Sense) Inductor current sensing is required for the current-mode control. Although the inductor current can be sensed with With these parameters, the approximated i (t) is plotted gs a precision resistor in series with the inductor, a novel as in Figure 13 b). lossless Combi-sense technique is used in the SC2446. Based on the approximation formulae of v (t) and i (t), ce gs This SEMTECH proprietary technique has the advantages one can calculate the power losses for each gate driver of pair as www.semtech.com  2004 Semtech Corp. 18 igs (A) vce (V) SC2446 POWER MANAGEMENT Application Information (Cont.) 1) lossless current sensing, 2) higher signal-to-noise ratio, and 3) preventing thermal run-away. Vin Rds1 iL(t) L RL The basic arrangement of the Combi-sense is shown in PN Figure 14. Cin Rs Cs Vo VPN Cout Rload Where, R is the equivalent series resistance of the output vC(t) L inductor. The added R and C form a RC branch for s s inductor current sensing. This branch is driven from a small totem pole driver (Q3 and Q4) integrated within SC2446. The base driving signals Vbe3 and Vbe4 Figure 15 a). Equivalent sub-circuit. Vin Q1 Vgs1 iL(t) L RL PN Cin Rs Cs Vo Vin Q2 Cou t Rload vC (t) Vgs2 iL(t) L RL PN Ci n Rs Cs Vo VPN Vbe3 Q3 Cout Rds2 Rload vC(t) VP N Q4 Vbe4 Figure 15 b). Equivalent sub-circuit. Figure 14. The basic structure of Combi-Sense. are designed to follow the gate drive signals Vgs1 and Vgs2, respectively, with minimal delay drive. Ideally, the V =[D(Rds1+RL)+(1-D)(Rds2+RL)]I , Cs o leading and falling edges of the Virtual Phase Node (VPN) follow that of the Phase Node (PN) when Q1~Q4 switch or equivalently accordingly. Specifically, when Q1/Q3 are ON and Q2/Q4 are OFF, V =[D Rds1+(1-D)Rds2+RL]I =R I . Cs o eq o the equivalent circuit of Figure 14 reduces to Figure 15 a). Where, Rds1 is the on-resistance of the top MOSFET. It is noted that the DC value of V is independent of the Cs The two branches, consisting of {(Rds1+RL), L} and {R , value of L, R and C . This means that, if only the average s s s C }, are in parallel. The DC voltage drop (Rds1+RL)I load current information is needed (such as in average S o equals V . In this way, the output current is sensed from current mode control), this current sensing method is Cs V when (Rds1+RL) is known. effective without time constant matching requirement. Cs In the current mode control as implemented in SC2446, When Q1/Q3 are OFF and Q2/Q4 are ON, the equivalent the voltage ripple on C is critical for PWM operation. In s circuit of Figure 14 becomes the sub-circuit as shown in fact, the AC voltage ripple peak-to-peak value of V Cs Figure 15 b). Where, Rds2 is the channel resistance of (denoted as ΔV ) directly effects the signal-to-noise ratio Cs the bottom MOSFET. In this case, the branch {R ,C } is in of the PWM operation. In general, smaller ΔV leads to s s Cs parallel with {(Rds2+RL), L} and V =(Rds2+RL)I . In lower signal-to-noise ratio and more noise sensitive Cs o average, leads to more circuit (power stage) operation. Larger ΔV Cs  2004 Semtech Corp. 19 www.semtech.com SC2446 POWER MANAGEMENT Application Information (Cont.) parameter sensitive operation. A good engineering In the following design steps, the capacitor C in the S compromise is to make current sensing part is commonly selected in the range ΔV ~R δI . of 22nF ~ 68nF. Cs eq o The prerequisite for such relation is the so called time constant matching condition Vin Q1 L Vgs1 ≈ R C . s s iL(t) L RL R eq PN Cin Rs Rs1 Vo When Rds1=Rds2, the above relations become Q2 Cs Cout Rload Vgs2 equations. vC(t) For an example of application circuit, L=1.3µH, RL=1.56mΩ and Rds1=Rds2=8mΩ , the time constant Vbe3 Q3 R C should be set as 136µs. If one selects C =33 nF, VPN s s s then R =4.12 kΩ. Vbe4 Q4 s Scaling the Current Limit 1 + Rs2 2 - I SEN Rs3 Over-current is handled differently in the SC2446 depending on the direction of the inductor current. If the differential sense voltage between CS+ and CS- exceeds Figure 16. Scaling the equivalent current limit. +75mV, the top MOSFET will be turned off and the bottom MOSFET will be turned on to limit the inductor current. a) When the required current limit value I is greater This +75mV is the cycle-by-cycle peak current limit when LM than I , one just needs to remove R , and solve the the load is drawing current from the converter. There is LMcp s3 following equations no cycle-by-cycle current limit when the inductor current flows in the reverse direction. If the voltage between CS1+ and CS- falls below -113mV, the controller will L (R //R ) C = , s s1 s undergo overload shutdown and time-out with both the R eq top and the bottom MOSFETs shut off. (See the section Overload Protection and Hiccup). R s1 I R = 75mV, LM eq In the circuit of Figure 14, the equivalent inductor current + R R s s1 limits are set according to 75mV and R = R //R . I = , s2 s s1 LMcp R eq for R ,R and R . s s1 s2 when the load is sourcing current from the converter and Note that R is selected as R //R in order to reduce 110mV S2 S S1 I = − , LMcn the bias current effect of the current amplifier in SC2446. R eq If the current limit is to be set to I = 15A with the existing LM power circuit parameter and C = 33nF, it is calculated s when the load is forcing current back to the input power that R = 4.12 kΩ, R = 7.87 kΩ and R = 8.66 kΩ. s2 s s1 source. If R = 9.56mW, then I = 7.8/-11.8A. The circuit eq LM b) When the required current limit I is less than I , LM LMcp in Figure 16 allows the user to scale the equivalent current one just needs to remove R and solve s1 limit with the same R . eq www.semtech.com  2004 Semtech Corp. 20 SC2446 POWER MANAGEMENT Application Information (Cont.) off until it is no longer overloaded. This hiccup mode of overload protection is a form of foldback current limiting. L R C = , s s The following calculations estimate the average inductor R eq current when the converter output is shorted to the ground. R s I R + V = 75mV, LM eq O R s3 a) The time taken to discharge the capacitor from 3.2V to 0.5V for R and R . s S3 (3.2 − 0.5)V t = C . ssf 32 R is then obtained from s2 1.4µA R R s3 s If C = 0.1µF, t is calculated as 193ms. R = . 32 ssf s2 R − R s3 s b) The soft start time from 0.5V to 3.2V (3.2 − 0.5)V t = C . ssr 32 If the current limit is to be set to I = 5A with the existing LM 2µA power circuit parameter and C , it is calculated that s R =4.12 kΩ, R =190 kΩ and R =4.22 kΩ. s s3 s2 When C = 0.1µF, t is calculated as 135ms. Note that 32 ssr Similar steps and equations apply to the current limit during soft start, the converter only starts switching when setting and scaling for current sinking mode. the voltage at SS/EN exceeds 1.2V. c) The effective start-up time is Remark 4: When the current limit I is lower than I , LM LMcp the designer has the freedom of selecting higher Rds(ON) MOSFETs to reduce cost. As a result, R is increased (3.2 −1.2)V eg t = C . sso 32 and I is reduced. Although the use of low-cost 2µA LMcp MOSFET’s is always preferred, the current-limit setting technique described above allows quick adjustment on a The average inductor current is then well-tested prototype without the need to replace the power MOSFETs. t sso I = I . Leff LMcp t + t ssf ssr Overload Protection and Hiccup During start-up, the capacitor from the SS/EN pin to ground functions as a soft-start capacitor. After the I ≈ 0.30 I and is independent of the soft start Leff LMcp converter starts and enters regulation, the same capacitor value. The converter will not overheat in hiccup. capacitor operates as an overload shutoff timing capacitor. As the load current increases, the cycle-by- cycle current-limit comparator will first limit the inductor Setting the Output Voltage current. Further increase in loading will cause the output voltage (hence the feedback voltage) to fall. If the The non-inverting input of the channel-one error amplifier feedback voltage falls to less than (75% for Ch1, 72% is internally tied the 0.5V voltage reference output (Pin for Ch2) of the reference voltage, the controller will shut 8). The non-inverting input of the channel-two error off both the top and the bottom MOSFET’s. Meanwhile amplifier is brought out as a device pin (Pin 10) to which an internal 1.4µA current source discharges the soft-start the user can connect Pin 8 or an external voltage capacitor C (C ) connected to the SS/EN pin. reference. A simple voltage divider (R at top and R at 32 33 o1 o2 bottom) sets the converter output voltage. The voltage When the capacitor is discharged to 0.5V, a 2µA current feedback gain h=0.5/V is related to the divider resistors o source recharges the SS/EN capacitor and converter value as restarts. If overload persists, the controller will shut down h the converter when the soft start capacitor voltage R = R o2 o1. 1− h exceeds 3.2V. The converter will repeatedly start and shut  2004 Semtech Corp. 21 www.semtech.com SC2446 POWER MANAGEMENT Application Information (Cont.) complex high-Q poles of the output LC networks is split Once either R or R is chosen, the other can be o1 o2 into a dominant pole determined by the output capacitor calculated for the desired output voltage V . Since the o and the load resistance and a high frequency pole. This number of standard resistance values is limited, the pole-splitting property of current-mode control greatly calculated resistance may not be available as a standard simplifies loop compensation. value resistor. As a result, there will be a set error in the The inner current-loop is unstable (sub-harmonic converter output voltage. This non-random error is oscillation) unless the inductor current up-slope is steeper caused by the feedback voltage divider ratio. It cannot than the inductor current down-slope. For stable be corrected by the feedback loop. operation above 50% duty-cycle, a compensation ramp The following table lists a few standard resistor is added to the sensed-current. In the SC2446 the combinations for realizing some commonly used output compensation ramp is made duty-ratio dependent. The voltages. compensation ramp is approximately 1.76D I = De * 30µA. ramp Vo (V) 0.6 0.915 .2 1. 15 .8 23 . 3. (1-h)/h 0.2 0.8 12 .4 24 .6 5.6 The slope of the compensation ramp is then 1.76D S = (1+1.76D)e f * 30µA. Ro1 (Ohm) 200 8061K .4K 22K .61K4K .02 5.62 e s Ro2 (Ohm) 1K 1K 1K K 1 1K K 1K 1 The slope of the internal compensation ramp is well above the minimal slope requirement for current loop stability and is sufficient for all the applications. Only the voltages in boldface can be precisely set with With the inner current loop stable, the output voltage is standard 1% resistors. then regulated with the outer voltage feedback loop. A From this table, one may also observe that when the simplified equivalent circuit model of the synchronous value Buck converter with current mode control is shown in Figure 17. − 1− h V 0.5 o = h 0.5 and its multiples fall into the standard resistor value chart (1%, 5% or so), it is possible to use standard value resistors to exactly set up the required output voltage value. The input bias current of the error amplifier also causes an error in setting the output voltage. The maximum inverting input bias currents of error amplifiers 1 and 2 is -250nA. Since the non-inverting input is biased to 0.5V, the percentage error in the second output voltage will be –100% · (0.25µA) · R R /[0.5 · (R +R ) ]. To keep k o1 o2 o1 o2 this error below 0.2%, R < 4kΩ. o2 Loop Compensation SC2446 uses current-mode control for both step-down channels. Current-mode control is a dual-loop control system in which the inductor peak current is loosely controlled by the inner current-loop. The higher gain outer loop regulates the output voltage. Since the current loop Figure 17. A simple model of synchronous buck converter makes the inductor appear as a current source, the with current mode control. www.semtech.com  2004 Semtech Corp. 22 SC2446 POWER MANAGEMENT Application Information (Cont.) The transconductance error amplifier (in the SC2446) 1 s = , z2 has a gain g of 260µA/V. The target of the compensation m R C 2 2 design is to select the compensation network consisting and of C , C and R , along with the feedback resistors R , 2 3 2 o1 R and the current sensing gain, such that the converter 1 o2 s = . p2 output voltage is regulated with satisfactory dynamic C C 2 3 R 2 performance. C + C 2 3 With the output voltage V known, the feedback gain h o and the feedback resistor values are determined using The loop transfer function is then the equations given in the “Output Voltage Setting” section with T(s)=G (s)C(s). vc 0.5 h = . V To simplify design, we assume that C < 2 Date: Monday, March 15, 2004 Sheet11 of SC2446 POWER MANAGEMENT Evaluation Board - Bill of Materials Ry efQe tRe eferencPr art Number/Valu Manufacture 12Cp 1,C44M 7uF, 16V, 70 mohm, PosCa Sanyo P/N: 16TPB47 24C6 2,C3,C6,C381M 0uF, 16V, X5R, Ceramic 120 Taiyo Yuden P/N: EMK316BJ106M 32Cp 8,C126M 80uF, 4V, PosCa Sanyo P/N: 4TPB680 46 C9,C10,C11,1M 00uF, 6.3V, Ceramic 1210 TDK P/N: C3225XR5R0J107 C13,C14,C15, 51C5 161M uF, 16V, X5R , Ceramic 080 Taiyo Yuden P/N: EMK316BJ105M 62C6 17,C180T .33uF, 50V, X5R, 120 Vishay P/N: VJ1206Y334KXAA 72C5 18,C192y .2nF, Ceramic, 080 An 82C5 20,C212y 2nF, Ceramic, 080 An 94C6 22,C24,C25,C261M 0uF, 4V, X5R, Ceramic, 120 Taiyo Yuden P/N: AMK325BJ106M 12 0C5 27,C286y 8pF, Ceramic, 080 An 13 1C5 29,C34,C350y .1uF, Ceramic, 080 An 11 2C5 30 1y nF, Ceramic, 080 An 11 3C5 31 2y .2nF, Ceramic, 080 An 12 4C5 32,C331y 00nF, Ceramic, 080 An 12 5Dy 1,D24F 0V, 1A, Schottk General Semi. P/N: 1N5819M, MEL or Motorola P/N: MBRS140T3 12 6Dy 7,D104A 0V, 3A, Schottk Diodes Inc. P/N: B340 11 7D- 11 6.2V, 500mW, 5%, Zener, SOD ZMM5234B 123 12 8L, 1,L2 1.8uH, 14A, 3.3 mohm (1.8uH Panasonic P/N: ETQP6F1R8BFA, or 15.5A, 3.4 mohm) Sumdia P/N: CEP1251R8MC-SJ 16 9Q8 2,Q3,Q5,Q6,Q73Y 0V, 16A, 8 mohm, 18nC, SO- Vishay P/N: Si4860D 22 0R5 CS+1,RCS+24y 9.9k, 080 An 22 1R5 CS-1,RCS-21y 00k. 080 An 24 2R5 3,R4,R7,R81y .0 ohm, 5%, 080 An 22 3R5 5,R62y 0k, 080 An 21 4R5 9 3y .40k, 1%, 080 An 22 5R5 10,R135y .1, 080 An  2004 Semtech Corp. 33 www.semtech.com SC2446 POWER MANAGEMENT Evaluation Board - Bill of Materials Ry efQe tRe eferencPr art Number/Valu Manufacture 21 5R5 11 4y .02k, 1%, 080 An 23 6R5 15,R23,R270y ohm, 080 An 21 7R5 16 1y k, 1%, 080 An 21 8R5 17 1y .3k, 1%, 80 An 22 9R5 18,R192y 0k, 080 An 31 0R% 20 9y 5.3k, 1 An 31 1 R1 21 5y . An 31 2R6 31 1y 10, 5%, 120 An 31 3R6 32 3y 00, 5%, 120 An 31 4U6 1S. C244 Semtech Corp www.semtech.com  2004 Semtech Corp. 34 SC2446 POWER MANAGEMENT Typical Characteristics Channel 1: Vo=2.5V @ 15A Typical waveforms in the evaluation board circuit #2A Over current protection Output short applied Steady state Load transient response Output short removed Loading: 0A to 15A Un-loading: 15A to 0A  2004 Semtech Corp. 35 www.semtech.com SC2446 POWER MANAGEMENT Typical Characteristics (Cont.) Channel 2: Vo=1.8V @ 15A Typical waveforms in the evaluation board circuit #2A Load transient response Loading: 0A to 15A Steady state Un-loading: 15A to 0A www.semtech.com  2004 Semtech Corp. 36 SC2446 POWER MANAGEMENT Typical Characteristics (Cont.) Over current protection Output short applied Output short removed  2004 Semtech Corp. 37 www.semtech.com SC2446 POWER MANAGEMENT Outline Drawing - TSSOP-28-EDP A D e N DIMENSIONS 2X E/2 INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX - - - - E1 E A .047 1.20 - - PIN 1 A1 .002 .006 0.05 0.15 INDICATOR .031 - .042 0.80 - 1.05 A2 b .007 - .012 0.19 - 0.30 c .003 - .007 0.09 - 0.20 ccc C 13 2 D .378 .382 .386 9.60 9.70 9.80 e/2 E1 .169 .173 .177 4.30 4.40 4.50 2X N/2 TIPS E .252 BSC 6.40 BSC B e .026 BSC 0.65 BSC F .210 .216 .220 5.35 5.50 5.60 H .112 .118 .122 2.85 3.00 3.10 D L .018 .024 .030 0.45 0.60 0.75 aaa C L1 (.039) (1.0) N 28 28 A2 A 01 0° - 8° 0° - 8° SEATING aaa PLANE .004 0.10 C A1 bbb .004 0.10 bxN ccc .008 0.20 bbb C A-B D F A SEE DETAIL SIDE VIEW EXPOSED PAD H H c GAGE PLANE 0.25 L BOTTOM VIEW 01 (L1) DETAIL A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS AND TO BE DETERMINED AT DATUM PLANE -A- -B- -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AE. Land Pattern - TSSOP-28-EDP F X DIMENSIONS DIM INCHES MILLIMETERS C (.222) (5.65) (C) F .224 5.70 H G Z G .161 4.10 H .126 3.20 P .026 0.65 Y X .016 0.40 Y .061 1.55 P Z .283 7.20 NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 www.semtech.com  2004 Semtech Corp. 38