SEMTECH SC2441A

SC2441A 1.8V to 20V Input 2-Phase Synchronous Step-down Controllers with Step-up Converter POWER MANAGEMENT Features Description The SC2441A is a programmable frequency dual 2-Phase Synchronous Step-down Controllers independent or dual/multiple phase single output peak � 2-Phase Synchronous Continuous Conduction Mode current-mode step-down switching regulator controller. It � Out of Phase Operation for Low Input Current Ripple is capable of operating from 1.8V to 20V input. A 0.6A � Operates up to 1MHz Per Channel step-up converter in the SC2441A generates an auxiliary � Excellent Current Sharing Between Phases gate drive supply when VIN is below 4.5V. This makes the � Duty Cycle Up to 90% SC2441A well suited for applications where a low-voltage � 0.5V Feedback voltages for Low-Voltage Outputs input (<3.3V) is to be stepped down for lower voltage logic, � Starts into Pre-biased Outputs yet the input is too low to drive power MOSFETs � Adaptive Shoot-through Protection efficiently. � Lossless Inductor DCR Current Sensing � 23mV Current-limit Threshold The SC2441A employs a phase-locked synchronizing circuit that allows the step-up converter to operate at � Individual Soft-start, Overload Hiccup and Enable twice the switching frequency of the step-down Step-up Regulator controllers for miniaturization. The clock output signal � 0.27V V Switch at 0.6A CESAT enables two or more SC2441As to be daisy chained with � Fixed frequency Current-mode Control programmable phase shift. Common Features � Wide input Voltage Range: 1.8V to 20V Tying the FB2 pin to VIN makes the second step-down � Synchronizing Frequency Equal to that of the Step- channel a slave of the first. Operating in this mode, the down Converters SC2441A regulates a single output with shared current in � 28-lead TSSOP-EDP Lead-free package, fully WEEE each channel. Each step-down controller has its own soft- and RoHS compliant start and overload shutdown timer for hiccup overload Applications protection. In the single-output mode, the channel 1 timer controls the soft-start and overload hiccup of both � Low voltage distributed DC-DC converters controllers. � Telecommunication power supplies Typical Application Circuit � Servers and base stations Vin VCC C1 VCC R1 R2 D1 C2 C3 R3 R4 C4 D2 L1 R5 C5 U1 D3 1 7 IN FB3 8 R6 COMP3 27 SW3 R7 21 28 VCC CKOUT C6 C7 25 18 Q1 BST1 BST2 Q2 23 19 R9 GDH1 GDH2 L2 VOUT1 VOUT2 R8 L3 C8 D4 Q3 R10 C11 C12 C13 R13 D5 R11 Q4 22 20 R12 GDL1 GDL2 C9 24 R15 PGND1 R16 RCS+1 RCS+2 26 2 PGND2 PLLF 4 16 CS1+ CS2+ 5 15 CS1- CS2- 11 14 FB1 FB2 C20 C19 12 13 COMP1 COMP2 R18 R19 R20 C21 C22 R21 10 6 ROSC SYNC/SHDN Vin C23 R23 R26 3 R24 R25 SS1/EN1 VCC 9 17 GND SS2/EN2 R27 C26 C25 Power Signal C24 Ground Ground SC2441A Figure 1 Revision: February 04, 2009 1 www.semtech.com SC2441A POWER MANAGEMENT Absolute Maximum Rating Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Ss ymbo Ms aximumRating Unit IV nput Voltage -V 0.3 to 20 IN SV upply Voltage For Step-DownController -V 0.3 to 20 CC HV igh-Side Driver Supply Voltages , V -V 0.3 to 28 BST1 BST2 FV B1, FB2 Voltage , V -V 0.3 to 20 FB1 FB2 CV OMP1, COMP2 Voltages , V -V 0.3 to 4.5 COMP1 COMP2 CS1(+), CS1(-), CS2(+) and CS2(-) V V , V ,V -0.3 to V V CS1(+), CS1(-) CS2(+) CS2(-) CC Voltages SV YNC/SHDNVoltage -0.3 to V +V 1 S/S IN RV OSC Voltage -V 0.3 to 2 ROSC SV S1/EN1 AND SS2/EN2 Voltages , V -V 0.3 to 4 SS1 SS2 FV B3 Voltage 4V FB3 SV W3 Voltage -V 0.3 to 30 SW3 MT aximumJunctionTemperature 1C 50 ° J Thermal Resistance Junctionto Case θ 2W °C/ JC Thermal Resistance Junctionto Ambient θ 3W 7 °C/ JA ST torage Temperature Range -C 60 to 150 ° STG LT ead Temperature (Soldering) 10 sec 3C 00 ° LEAD ED SD Ratings (HumanBody Model) E0 S 2V 00 Electrical Characteristics Unless specified: V = 2V, V = V = V =8V, SYNC/SHDN =2V, ROSC = 51.1kΩ, -40°C < T = T < 105°C IN CC BST1 BST2 A J Pl arameter Ss ymbo Cn ondition Mp i Tx y Ms a Unit Undervoltage Lockout V SV tartThreshold V I5 ncreasing 45 .4 4V .5 CC CCTH CC V UV VLOHysteresis V D0 ecreasing 1V 5 m CC CCTL CC V = 8V,V = 2V 10 15 mA CC S/S V II nputCurrent V = 4V,V ,V = 2V 0.05 1.0 CC CCTL S/S CC CC V = 8V,V = 0V (2) 8 11 CC S/S Channel1 and 2 ErrorAmplifiers FV eedback Voltage V V =V 3V, 5V< <4 10V 00 .49 06 .50 0V .50 FB1, FB2 IN CC V =V 3V, 5V< < 10V, 00 .495 05 .50 0V .50 IN CC -40°C to 85°C I -0 60 -A 20 n FB1 Feedback PinInputBias Current I -0 280 -A 50 n FB2 −1 AG mplifier Transconductance G 315 µΩ M1, M2 Oa penLoop Voltage Gain ,a 7B 5 d o1 o2 A) mplifier UnityGainBandwidth (5 Note 1 MHz AV mplifier OutputSink Current = 1V,V = 2.5V 146 29 2 µA FB1,2 COMP1,2 AV mplifier OutputSource Current = 0V,V =9 2.5V 16 3 1 µA FB1,2 COMP1,2 www.semtech.com  2006 Semtech Corp. 2 SC2441A POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: V = 2V, V = V = V =8V, SYNC/SHDN =2V, ROSC = 51.1kΩ, -40°C < T = T < 105°C IN CC BST1 BST2 A J Pl arameter Ss ymboCn ondition Mp i Tx y Ms a Unit V =V = 0 CS1(+) CS1(-) COMP Threshold for PWM Operation 15 .6715 .8 2V .0 V =V = 0 CS2(+) CS2(-) FB2 Voltage For 2-Phase Single Output 1V .55 Mode of Operation Oscillator and Phase-Locked Loop Ff ree Running Frequency T = 25°C; V>0 1V 40 5 50 0 5z 5 KH CCO J PLLF MV inimum Locking Frequency o0 pen 2z 4 KH PLLF Free Running Frequency / Minimum Locking T=7 25°C 10 . 2. J Frequency CI harge Pump Output Current V=0 1V 1510 2 µA PLLF PLLF D MAX1, Maximum Duty Cycle 80 89% D MAX2 MD inimum Duty Cycle D 0% MIN1, MIN2 SV YNC/SHDN Input High Voltage 1V .5 S/SH SV YNC/SHDN Input Low Voltage 0V .5 S/SL V = 0.2V 1 S/S SI YNC/SHDN Input Current µA S/S V=0 2V 4 60 S/S Shutdown Delay (5 Note 1) 8 µs I = -80µA618 .1V . CT lock Output High Voltage CKOU CKOUT H CT lock Output Low Voltage CKOU I = 200µA40V . L CKOUT Current-Sense Amplifiers, PWM and Current-Limit Comparators Input Common Mode Range 0V-V 1 CC V = 8V CC CV urrent Limit Threshold V 13 8 282V m ILIM1, ILIM2 V =V = 0V CS1(-) CS2(-) V = 8V CC CV urrent Limit Threshold V 13 8 282V m ILIM1, ILIM2 V =V = 5V CS1(-) CS2(-) V =V = 0 CS1(+) CS1(-) PI ositive Current-Sense Input Bias Current I -8 0.4 -0. µA CS1(+), CS2(+) V =V = 0 CS2(-) CS2(-) V =V = 0 CS1(+) CS1(-) NI egative Current-Sense Input Bias Current I -5 40 -7 µA CS1(-), CS2(-) V =V = 0 CS2(+) CS2(-) Minimum PWM On-time 1s 80 n T=° 25 C, (Note 1) A Gate Drivers High-Side Gate Drive Peak Source Current (2 Note 1) A High-Side Gate Drive Peak Sink Current (2 Note 1) A Low-Side Gate Drive Peak Source Current (2 Note 1) A  2006 Semtech Corp. 3 www.semtech.com SC2441A POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: V = 2V, V = V = V =8V, SYNC/SHDN =2V, ROSC = 51.1kΩ, -40°C < T = T < 105°C IN CC BST1 BST2 A J Pl arameter Ss ymboCn ondition Mp i Tx y Ms a Unit Low-Side Gate Drive Peak Sink Current (2 Note 1) A GC ate Drive Rise Time =0 3300pF 3s n L GC ate Drive Fall Time =0 3300pF 3s n L Soft-Start, Overload Shutoff and Enable Soft-Start Voltage to Enable Overload V SSEN1, V aV ndI3 ncreasing 3V . SS1 SS2 Hiccup V SSEN2 V = 3.5V SS1, 2 V FBOL1, Overload Hiccup FB Threshold 08 .3501 .3 0V .4 V FBOL2 FBaB nd F Decreasing 1 2 I V =V =V 0.3 SS1(DIS), FB1 FB2 Soft-Start Discharge Current 69 12 µA I V =V =V 3 SS2(DIS) SS1 SS2 Soft-Start Voltage to Restart After V SSRST1, V aV ndD5 ecreasing 0V . SS1 SS2 Overload Shutdown V SSRST2 Channel Disable SS/EN Voltage 0V .6 V = V = 0 CS1(+) CS1(-) SS/EN Threshold for PWM Operation 18 .2313 .2 1V .3 V = V = 0 CS2(+) CS2(-) Boost Converter VSV tart Threshold VI3 ncreasing 16 .7 1V .7 IN INTH IN VHV ysteresis 1V 00 m IN INTL FI eedback Pin Bias Current 40 0 2A 5 n FB3 FV eedback Voltage 1.8V < V<5 16.5V 10 .2215 .251V .27 FB3 IN -1 FG eedback Amplifier Transconductance 70 µΩ M3 Fa eedback Amplifier Open-Loop Gain 5B 0 d o3 Boost Converter Switching Frequency 1z MH f OSC3 MD aximum Switch Duty Cycle 82 5 9 % MAX3 BV oost Converter Switch Saturation Voltage I=7 0.6A 0V .2 CESAT SW BI oost Switch Leakage Current V=5 12V µA LEAKAGE SW BI oost Switch Current Limit 08 .60A . LIMIT Thermal Shutdown 1C 55 ° Thermal Shutdown Hysteresis 1C 0 ° Notes: (1) Guaranteed by design not tested in production. (2) Input current is dominated by the equivalent gate drive current to external MOSFETs in active switching condition. www.semtech.com  2006 Semtech Corp. 4 SC2441A POWER MANAGEMENT Pin Configurations Ordering Information Temperature De evice Packag Range ( T ) A Top View (1,2) SC2441ATETRTTC SSOP-28-EDP -40 to 85° Sd C2441AEVB Evaluation Boar IN 1 28 CKOUT PLLF 2 27 SW3 Notes: (1) Only available in tape and reel packaging. A reel SS1/EN1 3 26 PGND2 contains 2500 devices for the TSSOP-28-EDP CS1+ 4 25 BST1 package. (2) Lead free product. This product is fully WEEE and CS1- 5 24 PGND1 RoHS compliant. SYNC/SHDN 6 23 GDH1 FB3 7 22 GDL1 COMP3 8 21 VCC GND 9 20 GDL2 ROSC 10 19 GDH2 FB1 11 18 BST2 COMP1 12 17 SS2/EN2 COMP2 13 16 CS2+ FB2 14 15 CS2- TSSOP-28 EDP  2006 Semtech Corp. 5 www.semtech.com SC2441A POWER MANAGEMENT Pin Descriptions Pe in Pn in Nam Pin Functio Supply Voltage for the Boost Converter. Tie to VCC if boost converter is not used to generate 1N I auxiliarysupply. 2F P. LL CompensationPinfor the Phase Lock Loop An external resistor and an external capacitor tied to this pin set the first step-down converter 31 SS1/EN soft-starttime and its overload hiccup cycle time.Pulling this pinbelow0.6V shuts offchannel1 gate drivers. 4+ CS1 The Non-inverting Inputto the Channel1 Current-sense Amplifier/Comparator. The Inverting Input to the Channel 1 Current-sense Amplifier/Comparator. Normally tied to the 5- CS1 outputofthe converter. SynchronizationandShutdownInput.TiethispintoIN(Pin1)ortoavoltageabove1.5Vtoenable the SC2441A. Pulling this pin below 0.5V shuts off both step-down controllers and the boost 6N SYNC/SHD regulator.DrivingthispinwithanexternalclocksynchronizestheSC2441A.Theboostconverter runs at twice of the external clock frequency whereas the step-down controllers operate at the clock frequency. The Inverting Inputto BoostErrorAmplifier. FB3 is tied to anexternalresistive dividerforOUT3 73 FB voltage setting. BoostConverterErrorAmplifierOutput.Usedforloopcompensation.Pullingthispinbelow0.4V 83 COMP disables the step-up converter. 9D G. N Analog Ground 1C 0 ROS Anexternalresistor connected from this pinto GND sets the oscillator free-running frequency. The Inverting Input to the Channel 1 Error Amplifier. Tie to anexternal resistive divider between 11 1 FB OUT1 and the ground for outputvoltage sensing. 11 2 COMP Channel1 Error Amplifier Output. Used for loop compensation. 12 3 COMP Channel2 Error Amplifier Output. Used for loop compensation. The Inverting Input to the Channel 2 Error Amplifier. Tie to anexternal resistive divider between 12 4 FB OUT2 and the ground for output voltage sensing. Tie to IN or VCC for two-phase single output operation. The Inverting Input to the Channel 2 Current-sense Amplifier/Comparator. Normally tied to the 1- 5 CS2 outputofthe converter. 1+ 6 CS2 The Non-inverting Inputto the Channel1 Current-sense Amplifier/Comparator. Anexternalresistorandanexternalcapacitortiedtothispinsetthesecondstep-downconverter 12 7 SS2/EN soft-starttime and its overload hiccup cycle time.Pulling this pinbelow0.6V shuts offchannel2 gate drivers.Leave openfor two-phase single outputoperation. BootstrappedSupplyforChannel2UpperGateDrive. Connecttoabootstrapcapacitorandan 12 8 BST externaldiode. Gate Drive Output for Channel 2 Upper MOSFET. Gate drive voltage swings from ground to 12 9 GDH VBST2. www.semtech.com  2006 Semtech Corp. 6 SC2441A POWER MANAGEMENT Pin Descriptions (Cont.) Gate Drive OutputforChannel2 Synchronous MOSFET.Gate drive voltage swings from 22 0 GDL ground to VCC. SupplyVoltageforBothStep-downControllersandtheSynchronousMOSFETGateDrivers. The boostconverter generates VCC ifVINis nothighenoughto fullyenhance the power MOSFETs 2C 1 VC and the boost converter provides an auxiliarysupplyvoltage for the step-down controllers. Tie VCC to VINifthe boostconverteris notneeded. Gate Drive OutputforChannel1 Synchronous MOSFET.Gate drive voltage swings from 21 2 GDL ground to VCC. Gate Drive OutputforChannel1 UpperMOSFET. Gate drive voltage swings fromground to 21 3 GDH VBST1. 21 4 PGND PowerGround Returnofthe Gate Drivers. BootstrappedSupplyforChannel1UpperGateDrive. Connecttoabootstrapcapacitorandan 21 5 BST externaldiode. 22 6 PGND BoostSwitchEmitter. 23 7 SW BoostSwitchCollector. Connectto a boostinductorand freewheeling diode. 2T 8 C. KOU Clock output.See timing diagraminFigure 5(b) Exposed PAD Mustbe properlysoldered to the signalground plane to enhance thermalconduction.  2006 Semtech Corp. 7 www.semtech.com + + SC2441A POWER MANAGEMENT Block Diagram CKOUT IN 28 VIN UVLO 1 1.25V REFERENCE PLLF 1.6/1 .7V 2 SYNC/SHDN CLK2 OSCILLATOR 0.5V 0.35V VCC 6 FREQUENCY AND DIVIDER CLK1 21 ROSC PHASE 10 DETECTOR BST1 CLK FAULT UVLO SLOPE COMP 4.3V/4.5V 25 COMP1 SHDN SHDN 12 GDH1 SLOPE2 23 0.5V + R FB1 + EA1 - Q 11 PWM1 - Adaptive S + Shoot-through Protection TG1ON SS1/EN1 GDL1 3 22 1.25V - A2 GND 2R OL1 9 1.25V Soft-Start PGND1 And R DSBL1 SLOPE1 24 CS1+ Overload 4 Hiccup + + + CS1- ISEN1 �� Control 1 5 - � CH 1 CH 2 + 25mV ILIM1 B A - SEL MUX Y BST2 1.25V - CLK2 18 A1 SEL + GDH2 ANALOG COMP2 SWITCH 19 13 R - 0.5V + Q PWM2 Adaptive S FB2 EA2 + + Shoot-through 14 - VCC Protection TG2ON SS2/EN2 GDL2 17 20 1.25V - A3 2R OL2 Soft-Start 1.25V And R DSBL2 CS2+ Overload 16 + Hiccup + CS2- ISEN2 �� Control 2 15 - � + SLOPE2 + ILIM2 I - 25mV Figure 2 Functional Diagram of the Step-down Controllers www.semtech.com  2006 Semtech Corp. 8 SC2441A POWER MANAGEMENT Block Diagram SW3 COMP3 27 8 CLK FB3 7 - R EA3 - + Q PWM3 1.25V S + + ILIM3 - SLOPE I-LIMIT R COMP SENSE + + + ISEN3 Σ - PGND2 26 Figure 3. Step-up Converter Functional Diagram VCC FB + C3 0.35V - S R OL SS Q (OVERLOAD) C1 SS/EN R HICCUP TURN OFF DISABLE L1 0.5V/3.3V GATE DRIVES C SS - C2 S 0.8V + Q DSBL R L2 UV FAULT TGON Q1 10µA SHDN UV = “1” IF VCC < 4.5V SHDN = “1” IF SYNC/SHDN < 0.5V Soft-Start and Overload Hiccup Control Figure 2 Figure 4 Details of Soft-Start and Overload Hiccup Control Circuit www.semtech.com  2006 Semtech Corp. 9 SC2441A POWER MANAGEMENT Block Diagram 1.5V INTERNAL CLAMP EXT CLOCK CURRENT- � BUFFER PLLF CONTROLLED PLLF 1K OSCILLATOR SYNC/SHDN 2 XCLK QU S1 6 PHASE / FREQUENCY DETECTOR QD V/I 0.4V S2 ROSC 10 C2 R2 R1 � PLLF ROSC C1 OPTIONAL RESISTOR FOR SETS FREE - SETTING PHASE EXTERNAL PLL RUNNNG SHIFT COMPENSATION FREQUENCY CKOUT QT 28 CLK TOGGLE QT FLIP-FLOP CLK1 CLK2 (a) CLK XCLK QT QT CKOUT CLK1 CLK2 GDH1 GDH2 (b) Figure 5. Phase-Locked Loop (a) and Its Timing Diagram in Locked Condition (R not Used) (b). 2 www.semtech.com  2006 Semtech Corp. 10 - + + SC2441A POWER MANAGEMENT Vcc 4.5V V SOFT-START 3.3V Enable Hiccup V COMP 1.85V V OUT 1.25V PWM Figure 6a. SC2441A Start-up Timing Diagram V 3.3V SOFT-START-CAP Enable Hiccup V COMP V O 1.85V V 1.25V 0.8V O 70% X V Setpoint O PWM 0.5V Disable Hiccup restart Figure 6b. SC2441A Overload Hiccup Operation Timing Diagram  2006 Semtech Corp. 11 www.semtech.com SC2441A POWER MANAGEMENT Typical Characteristics Step-down Channel Feedback Step-down Channel Switching Frequency vs Temperature vs Temperature 0.55 650 R = 40.2K OSC � 0.53 600 550 0.51 R = 51.1K � OSC 500 0.49 450 0.47 R = 66.5K OSC � 400 V = 3V V = 8V IN CC 0.45 350 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Feedback Pin Input Bias Current vs Percenatge Frequency Deviation Temperature From Nominal vs Temperature 5 400 R = 66.5K OSC � 4 350 V = 3V Channel 2 COMP2 3 300 2 250 1 R = 40.2K OSC � 200 0 -1 150 V = 3V Channel 1 COMP1 -2 100 -3 50 -4 R = 51.1K� OSC 0 -5 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Amplifier Transconductance vs Temperature Amplifier Open Loop Gain vs Temperature 400 80 380 79 360 78 340 77 320 76 300 75 280 74 260 73 240 72 220 71 200 70 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) www.semtech.com  2006 Semtech Corp. 12 Deviation (%) Reference Voltage (V) �� Amplifier Transconductance ( ) �� Frequency (KHz) Feedback Pin Input Bias Current (nA) Amplifier Open Loop Gain (dB) SC2441A POWER MANAGEMENT Typical Characteristics Charge Pump Current I vs Temperature SYNC/SHDN Input Voltage vs Temperature PLLF 20.0 V = 1V PLLF 1.5 19.0 18.0 1.4 17.0 16.0 1.3 15.0 SYNC/SHDN Input High 14.0 1.2 13.0 1.1 12.0 11.0 1.0 10.0 SYNC/SHDN Input Low -50-25 0 25 50 75100 125 0.9 Temperature (°C) -50 -25 0 25 50 75 100 125 Temperature (°C) Clock Output High Voltage vs Temperature Clock Output Low Voltage vs Temperature 2.00 0.08 1.95 1.90 I = - 80 A 0.07 CLK_OUT µ 1.85 1.80 0.06 1.75 I = 200 µA CLK_OUT 1.70 0.05 1.65 1.60 0.04 1.55 1.50 0.03 -50 -25 0 25 50 75 100 125 -50-25 0 25 50 75100 125 Temperature (°C) Temperature (°C) Current Sense Amplifier Input Bias Current vs Temperature (Non-inverting Pin) -0.40 -0.45 -0.50 -0.55 V = 8V, V = V = 0V CC CS1 (-) CS2 (-) -0.60 -50 -25 0 25 50 75 100 125 Temperature (°C) www.semtech.com  2006 Semtech Corp. 13 Charge Pump Current I ( A) PLLF µ Clock Output High Voltage (V) Current Sense Amplifier Input Bias Current ( A) µ SYNC/SHDN Input High Voltage (V) Clock Output Low Voltage (V) SC2441A POWER MANAGEMENT Typical Characteristics Soft-Start Voltage Threshold (to Enable Overload Current Sense Amplifier Input Bias Current vs Overload Hiccup Threshold vs Temperature Hiccup Protection) vs Temperature Temperature (Inverting Pin) -25 0.400 4.0 0.395 0.390 3.8 0.385 -30 0.380 3.6 0.375 3.4 0.370 -35 0.365 0.360 3.2 V = 8V, V = V = 0V V = 3.5V CC CS1 (-) CS2 (-) SS1,2 0.355 -40 0.350 3.0 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Temperature (°C) Soft-Start Discharge Current vs Temperature Soft-Start Voltage (to Restart Overload Shutdown) Soft-Start Disable Voltage vs Temperature vs Temperature 0.60 9.0 0.83 0.58 8.5 0.81 0.56 8.0 0.79 0.54 7.5 0.77 0.52 V =V =0.3V, V =V =3V FB1 FB2 SS1 SS2 V =V =0.45V, V =V =2V FB1 FB2 COMP1 COMP2 7.0 0.50 0.75 -50 -25 0 25 50 75 100 125 -50 -25 0 255075 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Temperature (°C) Soft-Start Threshold Voltage (to Eable PWM V Hysteresis Voltage vs Temperature V Start-up Threshold Voltage vs Temperature IN IN Operation) vs Temperature 0.110 1.30 1.75 0.105 1.28 1.74 0.100 1.26 1.73 0.095 0.090 1.24 1.72 0.085 1.71 1.22 0.080 V =V =0.03V FB1 FB2 0.075 1.20 1.70 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 -50-25 0 25 50 75100 125 Temperature (°C) Temperature (°C) Temperature (°C) www.semtech.com  2006 Semtech Corp. 14 Soft-Start Threshold Voltage (to Current Sense Amplifier Input Bias Soft-Start Discharge Current ( µA) Eable PWM Operation) (V) Current ( A) µ Soft-Start Voltage (to Restart VIN Start-up Threshold Voltage (V) Overload Shutdown) (V) Overload Hiccup Threshold (V) Soft-Start Voltage Threshold (to Soft-Start Voltage (to Restart Overload Enable Overload Hiccup Shutdown) (V) VIN Hysteresis Voltage (V) Protection) (V) SC2441A POWER MANAGEMENT Typical Characteristics Boost Section Feedback Pin Bias Current vs Boost Section Feedback Voltage vs Temperature Boost Section Amplifier Transconductance vs Temperature Temperature 105 65 1.28 60 95 55 1.26 50 85 45 1.24 75 40 35 1.22 65 1.8V < V < 16.5V IN 30 25 1.20 55 -50 -25 0 25 50 75 100 125 -50 -25 0 255075 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Temperature (°C) Boost Section Switch Current Limit vs Boost Section Switch Saturation Voltage vs Boost Section Amplifier Open Loop Gain vs Temperature Temperature Temperature 0.90 0.35 56 0.85 55 0.33 0.80 54 0.31 0.75 53 0.29 52 0.70 0.27 0.65 51 I 0.6A SW = 50 0.60 0.25 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Temperature (°C) Bottom Gate Driver Transition Time vs Load Bottom Gate Driver Transition Time vs Load Capacitance Capacitance 100 100 V = 5V CC V = 12V CC 80 t f 80 t f 60 60 t r 40 40 t r 20 20 25°C 25°C 0 0 01 10 01 10 Load Capacitance (nF) Load Capacitance (nF)  2006 Semtech Corp. 15 www.semtech.com Boost Section Amplifier Open Boost Section Feedback Pin Bias Loop Gain (dB) Current (nA) Transition Time (nS) Boost Section Reference Voltage (V) Boost Section Switch Current Limit (A) Transition Time (nS) Boost Section Switch Saturation Boost Section Amplifier �� Voltage (V) Transconductance ( ) �� SC2441A POWER MANAGEMENT Typical Characteristics Percentage Deviation In Phase Shift vs Temperature Phase Shift vs Temperature Phase Shift vs Temperature 225 25 225 20 R = 47.5K 2 � R = 36.5K� 180 2 180 15 R = 36.5K 2 � 10 R = 34.8K 2 � R = 47.5K 2 � 135 135 5 R = 71.5K� 2 0 R = 46.4K� 2 R = 71.5K� 2 90 90 -5 R = 68.1K -10 2 � R = 143K 2 � 45 45 -15 R = 51.1K� OSC R = 40.2K� OSC R = 40.2K OSC � R = 140K� 2 -20 f = 400KHz f = 500KHz SYNC SYNC f = 500KHz SYNC R = 143K� 2 0 0 -25 -50 -25 0 255075 100 125 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Temperature (°C) Percentage Deviation In Percentage Deviation In Phase Shift vs Temperature Phase Shift vs Temperature Phase Shift vs Temperature 30 20 225 20 R = 68.1K� 2 R = 31.6K 180 � 2 10 10 0 R = 31.6K� 2 R = 41.2K 2 � 135 R = 41.2K� 2 -10 0 R = 46.4K R = 140K 2 � 2 � -20 R = 61.9K� 2 90 R = 61.9K� 2 -30 -10 -40 R = 121K� 2 R = 121K 45 2 � R = 51.1K� OSC R = 66.5K R = 66.5K� OSC � OSC -50 f = 300KHz f = 300KHz f = 400KHz SYNC SYNC SYNC R = 34.8K� 2 -60 0 -20 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 -50 -25 0 255075 100 125 Temperature (°C) Temperature (°C) Temperature (°C) Upper Gate Driver Transition Time vs Load Upper Gate Driver Transition Time vs Load Capacitance Capacitance 100 100 V = 12V V = 5V CC CC 80 80 t f t f 60 60 t r 40 40 20 20 tr 25°C 25°C 0 0 01 10 01 10 Load Capacitance (nF) Load Capacitance (nF) www.semtech.com  2006 Semtech Corp. 16 Phase Deviation (%) Phase (deg) Transition Time (nS) Phase (deg) Phase Deviation (%) Transition Time (nS) Phase Deviation (%) Phase (deg) SC2441A POWER MANAGEMENT Operation necessary to consider the operating duty-ratio range Overview before deciding the switching frequency. See Applications Information section for more details.   The SC2441A is a constant-frequency switching regulator Consider the detailed block diagram of the PLL in Figure capable of operating from 1.8V to 20V input. It consists of 5. The phase/frequency detector compares the buffered two current-mode step-down switch-mode PWM controllers driving all N-channel MOSFETs and an auxiliary step-up external clock XCLK with the output of the toggle flip- Q T current-mode converter with an integrated 0.6A power flop. If the rising edge of XCLK leads that of , then Q Q switch. A local supply (>5V) can be generated from a low T U will go high between the two corresponding rising edges. voltage input (3.3V, 2.5V or 1.8V) to provide sufficient gate Switch S is closed, charge is delivered to the loop filter drives for the step-down converters. 1 and the voltage at the PLLF pin increases. This in turn   causes the current output of the voltage to current converter The two step-down channels of the SC2441A operate at (V/I) and the switching frequency of the current-controlled 180 degrees out of phase from each other. Input currents are interleaved in a two-phase converter so input ripple oscillator (CCO) to increase. If rises before XCLK, then Q T current is lower and lower input capacitance can be used Q will go high from the rising edge of Q to the rising D T for filtering. edge of XCLK. Switch S is closed, charge is drawn from 2   the loop filter and the PLLF voltage falls. The switching The step-down controllers of the SC2441A operate in frequency of the current-controlled oscillator (CCO) synchronous continuous-conduction mode. They can decreases. When the PLL is in lock, the rising edges of function either as two independent step-down controllers producing two separate outputs or as a dual-phase single- XCLK and Q are aligned. Q and Q will go high for only a T U D output controller by tying the FB2 pin to V (Figure 2). In few gate delays. The PLLF stabilizes to a constant DC IN single output mode, the channel 1 error amplifier controls voltage and the CCO runs at the same frequency as the both channels and the channel 2 error amplifier is external clock. disabled. Soft-start and overload hiccup of both channels   are also controlled by channel 1. In Figure 2 the output In the absence of an external clock, S is closed and the 2 SEL of the comparator A1 determines which error amplifier PLL loop filter is continuously discharged. Not shown in outputs and fault signals are routed to channel 2. The Figure 5 is an internal PLLF lower clamp circuit that limits minimum required FB2 voltage for single output mode is the minimum voltage at the PLLF pin to 0.17V. This sets 1.55V. the lowest operating frequency and thus the lower bound of the PLL lock-range. The V/I in Figure 5 is shown with Phase-Locked Loop and Synchronization two non-inverting inputs. The lower voltage non-inverting   input takes control of the V/I. If the PLLF pin is tied to VIN The SC2441A utilizes a phase-locked oscillator (Figure 5) (>1.8V) through a current-limiting resistor, then the 0.4V for clock generation and external synchronization. The input of the V/I will predominate. The 0.4V input therefore advantages of using a phase-locked loop (PLL) are: (i) when sets the upper excursion limit of the V/I and the maximum the step-down channels are synchronized, the auxiliary step- operating frequency of the PLL at a given ROSC. The up regulator in the SC2441A can be made to run at twice maximum PLL frequency to the minimum locking frequency the external clock frequency to reduce component size and ratio is about 2. When the SC2441A is not synchronized (ii) two or more SC2441A can be daisy chained using the externally, the PLLF pin should be tied high through a clock output (pin 28) and interleaved with programmable resistor. The CCO will then run at its maximum frequency. phase shift. Each step-down controller within a SC2441A   operates at 180 degrees out of phase from the other step- When two SC2441As are used in a master-slave down controller. The switching frequency of the step-down configuration, the PLLF pin of the master SC2441A is tied controllers can be set with an external resistor ROSC. The high and its free running frequency is set with the resistor boost regulator and the step-down controllers are capable ROSC. CKOUT of the master is then tied to the SYNC/ SHDN of operating up to 2 MHz and 1 MHz respectively. It is input of the slave SC2441A. The free running and the  2006 Semtech Corp. 17 www.semtech.com SC2441A POWER MANAGEMENT Operation (Cont.) Current-Sensing minimum locking frequencies of the slave should be selected to accommodate the variation in the master’s   frequency. Phase shift between the master and the slave The inductor current needs to be sensed for use as PWM can be programmed with an optional resistor (Figure 5). modulating ramp. Either sense resistor or inductor series More detailed discussion can be found in the Application resistance (DCR) can be used as the sensing element for Information. the step-down controllers. Since the maximum current- sense voltage (CSP-CSN) is only 25mV, a precision sense resistor in series with the inductor can be used at the output Pulling the pin below 0.5V shuts off the SYNC/ SHDN without resulting in excessive power dissipation. SC2441A after 85µs time delay. Alternatively the DCR of the inductor can also be used. Both methods are less sensitive to supply and ground Control Loop transients than high-side or low-side sensing because the   sensed voltage is developed at the output of the step- The step-down controllers and the boost regulator in the down converter. DCR sensing will be described in more SC2441A use peak current-mode control for fast transient details in the Applications Information section. response and current sharing in single output operation.   Current-mode switching regulators utilize a dual-loop Boost switch current is sensed with an integrated sense feedback control system. The error amplifier output controls resistor with a minimum current-limit of 0.6A. the peak inductor current of that channel. This is the inner current loop. The double reactive poles of the output LC Error Amplifiers filter are reduced to a single real pole by the inner current loop, easing loop compensation. Fast transient response All error amplifiers in the SC2441A are of transconductance can be obtained with a simple Type-2 compensation type. Converters are compensated with series RC network network. In the outer loop, the error amplifier regulates from the COMP pins to the ground. An additional small the output voltage. parallel capacitor may be required for stability.   Referring to the block diagrams in Figures 2 and 3, the In Figure 2 the error amplifiers EA1 and EA2 are shown sensed inductor current is summed with the slope- with two non-inverting inputs. The non-inverting input with compensating ramp before compared to the output of the lower voltage predominates. One positive input is biased error amplifier. The PWM comparator trip point determines to a 0.5V precision reference. The other non-inverting input the switch turn-on pulse width. The current-limit comparator of the error amplifier is tied to a voltage equal to ILIM turns off the power switch when the sensed current exceeds the corresponding current-limit threshold. ILIM (VSS/EN - 1.25V)/3. therefore provides cycle-by-cycle current limit. All three converters in the SC2441A have internal ramp- During converter start up, the effective positive input of compensation to prevent sub-harmonic oscillation when the error amplifier stays at 0 until the soft-start capacitor operating above 50% duty cycle. The internal compensating at the SS/EN pin is charged above 1.25V. The ramp is designed for an inductor ripple-current between corresponding COMP pin is also pulled low by the comparator A or A . After the SS/EN voltage exceeds 1 2 3 and of the maximum inductor current and the peak- 1.25V, the COMP pin is released. Both the upper and the 4 lower gate drives remain low until the COMP voltage to-peak current-sense voltage (CSP-CSN of the step-down exceeds 1.85V. If the soft-start capacitor charging time is sufficiently long, then both the FB and the output controllers) between and of the current-limit voltage will track the divided SS/EN voltage on their way threshold (25mV). The current-limits of all three to regulation. If the starting output voltage is non-zero, converters are unaffected by the compensation ramps. then the COMP voltage and the corresponding gate drives will remain low until the divided SS/EN voltage exceeds the feedback voltage. Starting into a pre-existing output is seamless. www.semtech.com  2006 Semtech Corp. 18 SC2441A POWER MANAGEMENT Operation (Cont.) In closed loop operation, EA1 and EA2 output voltage during start up. As mentioned above, there is no PWM vary from 1.2V to 3.5V with the range 1.2V to 1.85V (=TGON) pulse until C is above 1.25V and the SS corresponding to negative peak sense voltages. Both gate corresponding COMP rises above 1.85V. Once the first drives are kept off until the COMP voltage exceeds 1.85V TGON pulse appears, L is reset and both gate drivers of 2 in start up. that channel are enabled. The error amplifier of the step-up converter has a 1.25V After C is charged above 3.3V, C output goes low. SS 1 reference voltage. Its output voltage excursion is from 0.8V Hiccup is armed. If the output voltage is less than 70% to 1V in closed-loop operation. of the set value due to improper start up or output overload, then C will set the overload latch L . Both gate 3 1 Current-Limit drivers of the channel are turned off and the 10µA current source discharges C . R must be large enough SS SS The 25mV maximum current sense voltage is the cycle-by- to ensure full discharge of C down to 0.5V. Soft-start SS cycle peak current limit of the step-down controller. process should be slow enough to allow the output to reach 70% of its final value before hiccup is armed. The Gate Drivers overload latch L is reset when the C capacitor is 1 SS discharged below 0.5V. The 10µA current source turns The SC2441A uses an adaptive non-overlapping control off. C capacitor is recharged by R and the converter SS SS scheme to switch the upper and the synchronous undergoes soft-start. If overload persists, the step-down MOSFETs. The synchronous MOSFET of each step-down converters will undergo repetitive shutdown and restart channel is turned off at the falling-edge of the phase (hiccup). clock. The control (upper) MOSFET is not turned on until the synchronous gate drive goes low. The phase inductor If the output is short-circuited, the inductor current will current ramps up. When the sensed inductor current not increase indefinitely between the times the inductor reaches the threshold determined by the error amplifier current reaching its current limit and shutdown. This is output and ramp compensation, the control MOSFET is due to cycle skipping reduces the actual operating turned off. The synchronous MOSFET is not turned on frequency. until the upper gate drive goes low. Pulling the SS/EN pin below 0.8V with an open-collector The supply voltage for the upper gate driver is obtained transistor sets the disable latch L and turns off the gate 2 from a diode-capacitor bootstrap circuit. If the bootstrap drives. The SS/EN pin can be used as the enable input for , then the high-side gate drive capacitor is charged from V the controller. CC voltage will swing from approximately 2V to ground. The CC synchronous gate drive swings from V to ground. The soft start timing diagram and the hiccup operation CC timing diagram are shown in Figures 6a and 6b Soft-Start and Overload Protection respectively. Figure 4 shows the functional diagram of the soft-start and overload protection circuit. The soft-start capacitor C and its charging resistor R are tied to the SS/EN pin. SS SS Together they set the soft-start time. Before V rises to CC 4.5V, the undervoltage lockout circuit discharges C to SS ground. After V rises above 4.5V, Q turns off and C is CC 1 SS slowly charged by R . Comparator C and latch L first SS 2 2 disable both the upper and lower gate drives. Hysteretic comparator C resets the latch L so that hiccup is disabled 1 1  2006 Semtech Corp. 19 www.semtech.com SC2441A POWER MANAGEMENT Applications Information Operating Frequency (f ) s The switching frequency in the SC2441A is user- R vs. Step-down Channel Switching Frequency Rosc vs Single Channel Switching Frequency OSC programmable. The advantages of constant frequency 150 operation are simple passive component selection and 130 fast transient response with simple frequency compensation. Before setting the operating frequency, 110 the following trade-offs should be considered. 90 70 1) passive component sizes 50 2) converter efficiency 3) EMI 30 4) Minimum switch on time and 10 100 300 500 700 900 1100 5) Maximum duty ratio Switching Frequency (KHz) For a given output power, the sizes of the passive components are inversely proportional to the switching Figure 7. R vs. Step-down Channel Free-running OSC frequency, whereas MOSFET’s/Diodes switching losses Frequency are proportional to the operating frequency. Other issues such as heat dissipation, packaging and the cost issues Minimum Switch On Time Limitation should be considered. The frequency bands for signal transmission should be avoided because of EM In both step-down controllers, the falling edge of the interference. clock turns on the top MOSFET. The inductor current ramps up so does the sensed voltage. After the sensed The switching frequency of both step-down controllers is voltage crosses a threshold determined by the error set with an external resistor from Pin 10 to the signal amplifier output, the top MOSFET is turned off. The ground. The set frequency is inversely proportional to the propagation delay time from the turn-on of the controlling resistor value (Figure 7) and can be approximated as: FET to its turn-off is the minimum switch on time. The SC2441A has a minimum on time of about 180ns at �1.22 R � 101618�F OSC SW room temperature. This is the shortest on interval of the controlling FET. The controller either does not turn on R is in KΩ and F is in KHz. OSC SW the top MOSFET at all or turns it on for at least 180ns. For a synchronous step-down converter, the operating The internal oscillator starts to operate once V exceeds IN duty cycle is V /V . So the required on time for the top O IN its UVLO threshold. The oscillator output, CLK, (see Figure MOSFET is V /(V f ). If the frequency is set such that the O IN S 2) clocks the step-up converter. The frequency divider required pulse width is less than 180ns, then the generates two out-of-phase clocks, CLK1 and CLK2, at converter will start skipping cycles. Due to minimum on a half of CLK frequency. CLK1 and CLK2 clock the step- time limitation, simultaneously operating at very high down channels. The switching frequency of the step-up converter is twice those of the step-down controllers. If both step-down channels are running at 250KHz, then the boost section will be running at 500KHz. www.semtech.com  2006 Semtech Corp. 20 ROSC (K�) SC2441A POWER MANAGEMENT Applications Information switching frequency and very short duty cycle is not C 2 practical. If the input voltage is 3.3V and the operating GND frequency is 1MHz, the lowest output voltage will be 0.6V. 9 V There will not be enough modulation headroom if the on IN 1 R 2 time is simply made equal to the minimum on time of the SC2441A SC2441A. For ease of control, we recommend that the V required pulse width be at least 1.5 times the minimum CC 21 R PGND1 6 on time. 24 Maximum Duty-cycle Consideration C 8 The top MOSFET turns off for at least 200ns every cycle regardless of the switching frequency. This places an Figure 8. RC Network Connections for V and V pins IN CC upper bound on the voltage conversion ratio at a given switching frequency. Step-Up Converter If the desired output voltage requires high operating duty- The SC2441A features a step-up regulator and two step- cycle, then operating frequency will have to be lowered down controllers. to allow modulating headroom. The boost section of the SC2441A comprises of pins 7, and V pins RC Filtering network for V 8, 26 and 27. Pin 26 is the independent power ground CC IN for the boost converter section, which should be A RC filtering network is recommended for the SC2441A separated from the step-down section power ground pin V and V pin connections. As shown in Figure 1, R plus 24 in layout to minimize the noise influence. The boost CC IN 6 C and R plus C are the filtering networks for V pin section in SC2441A has an internal reference set at 8 2 2 CC and V pin respectively. The value of the R and R ranges 1.25V. The output of the boost section can be IN 6 2 from 3.3Ω to 5.11Ω. C and C should be larger than programmed with external resistors R and R as shown 8 2 1 4 in Figure 1. 1µF. R �R 1 4 C and C are the decoupling capacitors for the V pin V �1.25V� 8 2 CC BOOST R and V pin. They should be placed as close as possible 4 IN to the pins of the SC2441A to achieve the best SC2441A utilizes a transconductance error amplifier for decoupling performance. Due to the different the step-up controller and it can be compensated with functionalities of the V pin and V pin, C should be CC IN 2 C , R and C as shown in Figure 1. The step-up controller placed between the V pin and the signal ground of the 3 5 5 IN in the SC2441A employs cycle-by-cycle peak current limit SC2441A. And C should be placed between the V pin 8 CC to protect the internal switching transistor. Current limit and the power ground of the SC2441A. The threshold is typically 0.8A. recommended connections for the V pin and V pin are CC IN illustrated in Figure 8. In the applications where only low input voltage is available, the step-up converter in the SC2441A is very useful for generating an auxiliary output to power the gate drive of the step-down controllers.  2006 Semtech Corp. 21 www.semtech.com SC2441A POWER MANAGEMENT Applications Information Assuming that the efficiency of the boost converter is η and the boost converter is running in CCM with duty ratio V D. The peak inductor current is IN V �I V 1 o3 o3 in I � � �D�T� L1PEAK V �� L 2 in 1 L 1 The saturation current rating of the selected inductor 27 should be at least 1.2 times of the calculated peak SW3 current value. Small D SC2441A 1 Loop Step-up Converter Capacitor Selection 24 PGND1 PGND2 26 C 1 Input capacitor: : :: : The input capacitance should be large V CC such that the input transients due to both the step-up 21 and the step-down converters do not trip the UVLO C 2 threshold 1.71V. Since the SC2441A controls a 2-phase R low input voltage step-down converter, the input 1 capacitance is sized to handle the input ripple current of the buck converter. This is usually sufficient for the Figure 9. Step-Up Section Layout Illustration auxiliary boost converter because the input current in a boost converter is continuous. As shown in Figure 9, to minimize the switching noise generated by the step-up converter, the loop formed by Output capacitor: Unlike buck converter, pulse current D , C , SW3 and PGND2 should be as small as possible. 1 1 is delivered to the output of a boost converter. To reduce And the PGND2 pin should be tied to PGND1 at one the output ripple voltage, low ESR capacitors should be spot close to the PGND1 pin. used. The output capacitor should also be able handle the output ripple current. The SC2441A is designed to use multi-layer ceramic capacitor as the sole output capacitor. Step-up Converter Inductor Selection For a specified inductor current ripple ratio δ (peak-to- 3 Maximum Output Current of the Step-up Converter peak current ripple v.s. actual input current I ), the IN inductor value is Figure 3 shows that the boost switch current is sensed with an internal sense resistor Rs and it is internally limited at 0.6A. So the maximum output current can be V V V in in in L � (1� ) . 1 given as (η is the efficiency of the step-up section): f � I V V s3 3 o3 o3 o3 � V �� 3 in I � (0.6A � )� o3,max 2 V o3 Typically, select δ <2 for a Continous Conduction Mode 3 (CCM) operation. If V = 3.3V, V = 5V and I = 100mA with δ = 1.6 and in o3 o3 3 f = 1MHz, then, L = 4.7µH. s3 1 www.semtech.com  2006 Semtech Corp. 22 SC2441A POWER MANAGEMENT Applications Information Soft-Starting the Step-Down Controllers Loop Compensation for the Step-Up Converter The soft-start of the two step-down converters are A simple small signal model for current-mode boost independently controlled through SS1 pin and SS2 pin. converter in continuous-conduction mode is shown in As lillustrated in Figure 4, if V is below 4.5V, Q will be Figure 10. CC 1 on, keeping C discharged. When FAULT goes low, Q is SS 1 turned off, C gets charged via R from V . Values of SS SS CC R and C set different start-up times. SS SS As shown in Figure 4, if the output falls below 70% of its setpoint, the Css will be discharged with a 10µA current sink. R must be large enough to allow the soft-start SS a capacitor to be discharged below 0.5V. Soft-start process should be long enough to allow the output to reach 70% of its final value before hiccup is armed. Coincident Soft-Start The step-down controllers can be made to start b coincidently. The method is shown in Figure 11. V CC R D SS1 1 SS1/EN1 3 Figure 10. Small signal model of Boost converter. C SS1 SC2441A In Figure 10, C and R are the capacitance and the o3 esr3 ESR of the output capacitor, g is the error amplifier m3 transconductance and k is the current loop gain. If one C 3 SS specifies the loop crossover frequency f , the c V CC compensation component values are readily calculated as R D SS2 2 SS2/EN2 R f 1 R o3 c esr3 17 C � h g k (1� D ) | 1� | , 4 3 m3 3 3 C SS2 2 f 2�f R � 0.5R z1 c esr3 o3 1 R o3 R � C (R � ) 4 o3 esr3 C 2 4 and Figure 11. Coincident Soft-Start for Step-Down 2R Converters esr3 C � C 5 4 R o3 The capacitance of C , as shown above, should be more 2 SS (1� D ) R 3 o3 f � . than 3 times of the capacitance of the C and C . z1 SS1 SS2 2�L 3 R b h � 3 R � R a b  2006 Semtech Corp. 23 www.semtech.com SC2441A POWER MANAGEMENT Applications Information DCR Current Sensing V Voltage on C --- V (t) 1 C1 Either precision sense resistor or inductor DCR can be V used as the inductor current sensing element. C1.PEAK R I 1 L1.PEAK V IN R I 1 O V C1.VALLEY R I 1 L1.VALLEY SW1 L R 1 1 Voltage Drop on R --- I (t)R 1 L1 1 0t R V 2 C1 - + SW2 C 1 C Figure 13. Voltage Waveform C and R OUT R 1 1 LOAD R 3 I + CS+ In Figure 12, R and R resistive divider attenuates the 2 3 CS sensed signals when I . The time - I constant resulting from L and its DCR R is: CS- 1 1 SC2441A Define R : EQU Figure 12. Current Sensing Circuit. In Figure 12 SW1 and SW2 represent the MOSFET The time constant of the DCR sensing network is: switches. CS is the current sense amplifier. I and I CS+ CS- are the input bias currents of the CS. L is the output 1 inductor. R is the DC resistance of L . R , R and C If τ = τ , then the peak and valley voltages across 1 1 2 3 1 C1 L1 constitute the DCR current sensing network. will be: C 1 Assuming that CS input bias currents are zero and that R is not used, if the time constant L /R is made equal 3 1 1 to the time constant R C , then the voltage across the 2 1 R �R � �I � 3 1 inductor DCR, R , will be replicated across C in the steady L1 1 1 V � I �R � � I � � � C1�VALLEY CS� EQU O (R �R ) 2 state (see Figure 13). The following equations apply: � � 2 3 I therefore introduces an offset error to the sensed I . � I ��I /2 CS+ L1 PEAK O L 1 voltage. To reduce this error, R must be minimized. EQU I . � I ��I /2 L1 VALLEY O L 1 Suppose V =5V; V =2.5V; D=50%; I =20A; IN OUT OUT V (t) � I (t) � R C1 L1 1 F =500KHz; L =0.5µH; R =2mΩ; I =1µA. The output SW 1 1 CS+ where, I is the output current and �I is the peak-to- current limit is set at 28A. The time constant formed by L1 O L and R is peak L current ripple. The inductor current can therefore 1 1 1 be sensed by monitoring C voltage. L should be selected 1 R �R L 1 2 3 � � � 0.25ms � � C L1 1 so that the is between 25% to 33% of the I . O R R � R 1 2 3 �I � 5A However CS input bias currents are not zero. I and I L CS+ CS- 1 are typically 0.4µA and 40µA respectively (see electrical R �R I � � � characteristics) and can not be ignored. 3 1 L1 V � I �R � � 28A � � 25mV � � C1�PEAK CS� EQU (R � R ) 2 � � 2 3 www.semtech.com  2006 Semtech Corp. 24 SC2441A POWER MANAGEMENT Applications Information In Figure 14, V is the external power supply pre-biasing S R �R V . D blocks the output of the power module under test 2 3 O 1 � C � 0.25ms 1 from V during soft-start. R is the resistive load of the R � R S LOAD 2 3 module under test. Before power-up the module, monitor V to ensure that it is the desired pre-biased output O R �R R �R � 5A � 3 2 3 1 1µA � � � 28A � � 25mV � � voltage. Then power-up the module. V should rise O (R � R ) (R � R ) 2 � � 2 3 2 3 smoothly. R �R 2 3 Free-running Operation With an arbitrary selection of , we can � 3.01K� R � R 2 3 The internal oscillator of the SC2441A can either free- get C =83nF. Since 83nF is not a standard capacitance 1 run or it can be phase-locked to an external clock. value, we use 100nF capacitor for C . Consequently, 1 R �R In free-running mode, the internal phase-locked loop is 2 3 � 2.5K� . And we can also derive: disabled by tying an external resistor from the PLLF pin R � R 2 3 to V . The external resistor ROSC (see figure 5(a)) IN programs the channel frequency. The PLLF pull-up resistor R 5A � � 1 1µA�2.5K�� �2.5K� 28A � � 25mV � � should be carefully selected so that the voltage at the R 2 � � 2 PLLF pin is above 1V. A value between 20KΩ to 50KΩ is recommended. R � 6.80K� 2 R � 3.92K� 3 Pull-up resistor can also be tied to V if V is present CC CC before the SC2441A starts to switch. The advantage tying the pull-up resistor to V is because that the V is a CC CC regulated output from either a boost converter or a sepic Pre-biased Start Up converter. The resistor from the PLLF pin can be tied to V if V is from a boost converter output. The reason is CC CC that the V will be powered up from the input V before CC IN Sometimes the step-down converter is to start into a output of the boost converter reaches the setpoint. pre-biased output load. The pre-biased voltage is normally However, in some applications, a SEPIC converter is lower than the output setpoint of the step-down due to the wide input voltage employed to get stable V CC converter. range. In this case, the resistor from the PLLF pin should not be connected to the V due to the presence of a DC CC As described earlier, pre-bias startup process with the blocking capacitor in the converter. The SC2441A will not SC2441A is seamless. The testing setup of the pre-biased switch if the PLLF pin is at zero volt. start-up is shown as in Figure 14. Applying more than 2.1V at the PLLF pin activates the diode clamp circuit (see Figure 5(a)). The filtering D1 + V components (R ,R , C and C in Figure 5(a)) are not O 1 2 1 2 Module V needed while free-running. The clamp activation will have Blocking Diode s under no effect on the PLL if V >1V. R LOAD PLLF Test - External The internal clock is brought out to the CKOUT pin. The Voltage signal at CKOUT pin can be used as the synchronizing Source clock for other SC2441As in a master-slave configuration. Figure 14. Test Setup for Pre-biased Start Up  2006 Semtech Corp. 25 www.semtech.com SC2441A POWER MANAGEMENT Applications Information As shown in Figure 15, the CKOUT signal of the master Master - Slave Mode Configuration SC2441A is the input sync signal for the slave SC2441A. The R , C and C constitute the filtering circuit stabilizing 1 1 2 The configuration for SC2441A master-slave mode the phase lock loop in the slave SC2441A. R2 (between operation is shown in Figure 15. The master is made 30kΩ and 150kΩ) determines the phase shift between free running, the master clock frequency should be within the slave CKOUT and its SYNC input. the synchronizing range of the slave. PLL Frequency Compensation In the Master-Slave mode, the SS2441A can be synchronized to an external clock signal applied to the Applying synchronizing clock with step change in frequency adjust compensation components until overshoot and SYNC pin. External filtering componets (R , R , C and C ) 1 2 1 2 ringing at PLLF pin is minimized. on the PLLF pin are necessary for the slave SC2441A . The PLLF pull-up resistor is not necessary for the slave Output Inductor and Ripple Current in Step-down converter. Sections Phase shift between the master and the slave is the Both step-down controllers in the SC2441A operate in phase lag measured between the sync input and the clock synchronous continuous-conduction mode (CCM) output of the slave. Typical relationship between the phase regardless of the output load. The output inductor shift and the slave value of the resistor R is shown in 2 selection/design is based on the output DC and transient the “Typical Characteristics”. requirements. Both output current and voltage ripples are reduced with larger inductors but it takes longer to For the SC2441A running at slave mode, its free-runing change the inductor current during load transients. frequency (internal switching frequency) set with ROSC Conversely smaller inductors results in lower DC copper should be programmed 20% higher than the external losses but the AC core losses (flux swing) and the winding synchronization frequency. AC resistance losses are higher. A compromise is to choose the inductance such that the peak to peak VIN inductor ripple current is 20% to 30% of the rated output current. Assume that the inductor current ripple (peak-to-peak) is δ∗Ι Then the inductance will be SYNC ο R4 PLLF R3 V (1�D) Master o L � . SC2441A �I f o s The peak current in the inductor becomes (1+δ/2)*Io CKOUT and the RMS current is 2 � I �I 1� . L,rms o 12 SYNC PLLF The followings are to be considered when choosing R1 Slave SC2441A inductors. C2 R2 C1 CKOUT a) Inductor core material: For high efficiency applications above 350KHz, ferrite, Kool-Mu and polypermalloy materials should be used. Low-cost powdered iron cores can be used for cost sensitive-applications below 350KHz Figure 15. Master-Slave Synchronization but with attendant higher core losses. www.semtech.com  2006 Semtech Corp. 26 SC2441A POWER MANAGEMENT Applications Information Since the inductor current is a triangular waveform with b) Select inductance value: Sometimes the calculated peak-to-peak value δ * I , the ripple-voltage caused by inductance value is not available off-the-shelf. The o inductor current ripples is designer can choose the adjacent (larger) standard inductance value. The inductance varies with �I o �v � . C temperature and DC current. It is a good engineering 8C f o s practice to re-evaluate the resultant current ripple at the rated DC output current. The ripple-voltage due to ESL is c) Current rating: The saturation current of the inductor �I should be at least 1.5 times of the peak inductor current o �v � L f ESL esl s under all conditions. D Output Capacitor (C ) and V Ripple in Step-down o out and the ESR ripple-voltage is Sections �v � R �I . ESR esr o The output capacitor provides output current filtering in Aluminum capacitors (e.g. electrolytic, solid OS-CON, steady state and serves as a reservoir during load POSCAP, tantalum) have high capacitances and low transient. The output capacitor can be modeled as an ESL’s. The ESR has the dominant effect on the output ideal capacitor in series with its parasitic ESR (R ) and esr ripple voltage. It is therefore very important to minimize ESL (L ) (Figure 16). esl the ESR. Co When determining the ESR value, both the steady state ripple-voltage and the dynamic load transient need to be considered. To keep the steady state output ripple-voltage Lesl i (t) b < ΔV , the ESR should satisfy o �V o R � . esr1 �I o Resr To limit the dynamic output voltage overshoot/ undershoot within α (say 3%) of the steady state output Figure 16. C equivalent circuit o voltage) under 0 to full load current swing, the ESR value should be If the current through the branch is i (t), the voltage b �V across the terminals will then be o R � . esr2 I o t 1 di (t) b v (t)� V � i (t)dt� L � R i (t). o o b esl esr b � C dt The required ESR value of the output capacitors should o 0 be This basic equation illustrates the effects of ESR, ESL R = min{R ,R }. esr esr1 esr2 and C on the output voltage. o In the aluminum capacitor selection, the working voltage The first term is the DC voltage across C at time t=0. o rating is normally suggested to be greater than 1.5V . o The second term is the ripple-voltage caused by the The allowable current ripple (RMS) should be greater than inductor ripple-current. The third term is the voltage ripple due to ESL and the fourth term is the voltage ripple due to ESR. The total output voltage ripple is then a vector sum of the last three terms.  2006 Semtech Corp. 27 www.semtech.com SC2441A POWER MANAGEMENT Applications Information 2 2 2 2 2 R R (R � R )� C C � (R C � R C ) 1a 1b 1a 1b 1a 1b 1b 1b 1a 1a R (�) :� eq �I 2 2 2 2 2 o (R � R ) � C C � (C � C ) . 1a 1b 1a 1b 1a 1b 2 3 Usually it is necessary to have several capacitors of the where R and C are the ESR and capacitance of 1a 1a same type in parallel to satisfy the ESR requirement. electrolytic capacitors, and R and C are the ESR and 1b 1b The voltage ripple cause by the capacitor charge/ capacitance of the ceramic capacitors respectively discharge should be an order of magnitude smaller than (Figure 17). the voltage ripple caused by the ESR. To guarantee this, the capacitance should satisfy 10 C � . o 2�f R s esr C1a C1b Ceq In many application circuits, several low ESR ceramic R1a R1b Req capacitors are added in parallel with the aluminum capacitors to further reduce ESR and improve high frequency decoupling. Since the capacitances and the ESR’s of ceramic and aluminum capacitors are different, Figure 17. Equivalent RC branch. the following remarks are made to clarify some practical issues. R and C are both functions of frequency. For rigorous eq eq Remark 1: High frequency ceramic capacitors may not design, the equivalent ESR should be evaluated at the carry most of the ripple current. It also depends on the ripple frequency for voltage ripple calculation when both capacitor value. Only when the capacitor value is set ceramic and electrolytic capacitors are used. If R = R 1a 1b properly, the effect of ceramic capacitor low ESR starts = R and C = C = C , then R and C will be frequency- 1 1a 1b 1 eq eq to be significant. independent and For example, if a 10µF, 4mΩ ceramic capacitor is R = 1/2 R and C = 2C . connected in parallel with 2x1500µF, 90mΩ electrolytic eq 1 eq 1 capacitors, the ripple current in the ceramic capacitor is Input Capacitor (C ) in Step-down Sections only about 42% of the current in the electrolytic in capacitors at the ripple frequency. If a 100µF, 2mΩ The input supply to the converter usually comes from a ceramic capacitor is used, the ripple current in the pre-regulator. Since the input supply is not ideal, input ceramic capacitor will be about 4.2 times of that in the capacitors are needed to filter the current pulses at the electrolytic capacitors. When two 100µF, 2mΩ ceramic switching frequency. A simple buck converter is shown in capacitors are used, the current ratio increases to 8.3. Figure 18. In this case most of the ripple current flows in the ceramic decoupling capacitor. The ESR of the ceramic capacitors will then determine the output ripple-voltage. Remark 2: The total equivalent capacitance of the filter bank is not simply the sum of all the paralleled capacitors. The total equivalent ESR is not simply the parallel combination of all the individual ESR’s either. Instead they should be calculated using the following formulae. 2 2 2 2 2 Figure 18. Buck converter input model (R � R ) � C C � (C � C ) 1a 1b 1a 1b 1a 1b C (�) :� eq 2 2 2 (R C � R C )� C C � (C � C ) 1a 1a 1b 1b 1a 1b 1a 1b As shown in Fig. 18, the internal DC input voltage source www.semtech.com  2006 Semtech Corp. 28 SC2441A POWER MANAGEMENT Applications Information impedance is R and the input capacitor C has an ESR in in � �v � R (1� )I . denoted as R . MOSFET and input capacitor current ESR esr o esr 2 waveforms, ESR voltage ripple and input voltage ripple The peak-to-peak input voltage ripple due to the capacitor are shown in Figure 19. is DI o �v � . C C f in s From these two expressions, C can be found to meet in the input voltage ripple specification. In a multi-phase converter, channel interleaving can be used to reduce ripple. The two step-down channels of the SC2441A operate at 180 degrees from each other. If both step- down channels in the SC2441A are connected in parallel, both the input and the output RMS currents will be reduced. Ripple cancellation effect of interleaving allows the use Figure 19. Typical waveforms at the input of a of smaller input capacitors. When converter outputs are buck converter. connected in parallel and interleaved, smaller inductors and capacitors can be used for each channel. The total It can be seen that the current in the input capacitor output ripple-voltage remains unchanged. Smaller pulses with high di/dt. Capacitors with low ESL should be inductors speeds up output load transient. used. It is also important to place the input capacitor close to the MOSFET’s on the PC board to reduce trace When two channels with a common input are interleaved, inductances around the pulse current loop. the total DC input current is simply the sum of the individual DC input currents. The combined input current The RMS value of the capacitor current is approximately waveform depends on duty ratio and the output current 2 waveform. Assuming that the output current ripple is � D D 2 I � I D[(1� )(1� ) � (1� D)]. Cin o 2 small, the following formula can be used to estimate the 12 � � RMS value of the ripple current in the input capacitor. The power losses at the input capacitors is then Let the duty ratios and output currents of Channel 1 and 2 P = I R . Cin Cin esr Channel 2 be D , D and I , I respectively. 1 2 o1 o2 For reliable operation, the maximum power dissipation If D <0.5 and D <0.5, then 1 2 o in the capacitors should not result in more than 10 C of temperature rise. Many manufacturers specify the 2 2 maximum allowable ripple current (ARMS) rating of the I � D I � D I . Cin 1 o1 2 o2 capacitor at a given ripple frequency and ambient temperature. The input capacitance should be high If D >0.5 and (D -0.5) < D <0.5, then 1 1 2 enough to handle the ripple current. For higher power applications, multiple capacitors are placed in parallel to 2 2 2 I � 0.5I � (D � 0.5)(I � I ) � (D � D � 0.5)I . increase the ripple current handling capability. Cin o1 1 o1 o2 2 1 o2 Sometimes meeting tight input voltage ripple If D >0.5 and D < (D -0.5) < 0.5, then 1 2 1 specifications may require the use of larger input capacitance. At full load, the peak-to-peak input voltage 2 2 ripple due to the ESR is 2 I � 0.5I � D (I � I ) � (D � D � 0.5)I . Cin o1 2 o1 o2 1 2 o2  2006 Semtech Corp. 29 www.semtech.com SC2441A POWER MANAGEMENT Applications Information The losses in power MOSFET’s consist of If D >0.5 and D > 0.5, then 1 2 a) conduction loss due to the channel resistance R , ds(on) b) switching loss due to the switch rise time t and fall r 2 2 2 I � (D � D �1)(I � I ) � (1� D )I � (1� D )I . time t and Cin 1 2 o1 o2 2 o1 1 o2 f c) the gate loss due to the gate resistance R . G Power MOSFET Selection and Gate Drive Top Switch: The RMS value of the top switch current is Main considerations in selecting the MOSFET’s are power 2 dissipation, cost and packaging. Switching losses and � I � I D(1� ). Q1,rms o 12 conduction losses of the MOSFET’s are directly related Its conduction loss is then to the total gate charge (C ) and channel on-resistance g (R ). In order to judge the performance of MOSFET’s, ds(on) 2 P = I R . the product of the total gate charge and on-resistance is tc Q1,rms ds(on) used as a figure of merit (FOM). Transistors with the same R varies with temperature and gate-source voltage. FOM follow the same curve in Figure 20. ds(on) Curves showing R variations can be found in ds(on) manufacturers’ data sheet. From the Si7882DP 50 datasheet, R is less than 4.5mOhm when V is greater ds(on) gs 40 than 5V. However R increases by nearly 40% as the Cg() 100�Rds ds(on) junction temperature increases from 25°C to 125°C. Cg() 200�Rds 20 Cg() 500�Rds The switching losses can be estimated using the simple formula 1 0 0 5 10 15 20 � 1 P � (t � t )(1� )I V f . ts r f o in s 2 2 1 Rds 20 On-resistance (mOhm) FOM:100*10^{-12} where t is the rise time and t is the fall time of the FOM:200*10^{-12} r f FOM:500*10^{-12} switching process. To clarify these, we sketch the typical MOSFET switching characteristics under clamped inductive mode in Figure 21. Figure 20. Figure of merit curves. The closer the curve is to the origin, the lower is the FOM. This means lower switching loss or lower conduction loss or both. It is difficult to find MOSFET’s with both low C g and low R . Usually a trade-off between R and C ds(on) ds(on) g has to be made. MOSFET selection also depends on applications. In many applications, either switching loss or conduction loss dominates for a particular MOSFET. For synchronous buck converters with high input to output voltage ratios, the top MOSFET is hard switched but conducts with very low duty cycle. The bottom switch conducts at high duty cycle Figure 21. MOSFET switching characteristics but switches at near zero voltage. For such applications, MOSFET’s with low C are used for the top switch and g MOSFET’s with low R are used for the bottom switch. ds(on) www.semtech.com  2006 Semtech Corp. 30 Gate Charge (nC) SC2441A POWER MANAGEMENT Applications Information 2 In Figure 21, � I �I (1�D)(1� ). Q2,rms o 12 The conduction loss is then Q is the gate charge needed to bring the gate-to-source gs1 voltage V to the threshold V , gs gs_th 2 P =I R , Q is the additional gate charge required for the switch bc Q2,rms ds(on) gs2 current to reach its full-scale value I and ds . where R is the channel resistance of bottom MOSFET. Q is the charge needed to charge gate-to-drain (Miller) ds(on) gd If the input voltage to output voltage ratio is high (e.g. capacitance when V is falling. ds V =12V, V =1.5V), the duty ratio D will be small. Since Switching losses occur during the time interval [t , t ]. in o 1 3 the bottom switch conducts with duty ratio (1-D), the Defining t = t -t . t can be approximated as r 3 1 r corresponding conduction losses can be quite high. (Q �Q )R gs2 gd gt Due to non-overlapping conduction between the top and t � . r V �V cc gsp the bottom MOSFET’s, the internal body diode or the external Schottky diode across the drain and source where R is the total resistance from the driver supply gt terminals always conducts prior to the turn on of the rail to the gate of the MOSFET. It includes the gate driver bottom MOSFET. The bottom MOSFET switches on with internal impedance R , external resistance R and the gi ge only a diode voltage between its drain and source gate resistance R within the MOSFET i.e. g terminals. The switching loss 1 � R = R +R +R . P � (t �t )(1� )I V f gt gi ge g bs r f o d s 2 2 is negligible due to near zero-voltage switching. V is the Miller plateau voltage shown in Figure 21. gsp Similarly an approximate expression for t is f The gate loss is estimated as R g P � Q V f . (Q �Q )R bg g cc s gs2 gd gt R t � . gt f V gsp The total bottom switch loss is then Only a portion of the total losses P = Q V f is dissipated g g cc s P =P +P +P . b bc bs bg in the MOSFET package. Here Q is the total gate charge g specified in the datasheet. The power dissipated within Once the power losses P for the top (P) and bottom loss t the MOSFET package is (P ) MOSFET’s are known, thermal and package design b R at component and system level should be done to verify g P � Q V f . tg g cc s that the maximum die junction temperature (T , usually R j,max gt o 125 C) is not exceeded under the worst-case conditions. The total power loss of the top switch is then The equivalent thermal impedance from junction to P = P +P +P . t tc ts tg ambient (θ ) should satisfy ja T �T j,max a,max If the input supply of the power converter varies over a � � . ja P wide range, then it will be necessary to weigh the relative loss importance of conduction and switching losses. This is θ depends on the die to substrate bonding, packaging ja because conduction loss is inversely proportional to the material, the thermal contact surface, thermal compound input voltage. Switching loss however increases with the property, the available effective heat sink area and the input voltage. The total power loss of MOSFET should be air flow condition (free or forced convection). Actual calculated and compared for high-line and low-line cases. temperature measurement of the prototype should be The worst case is then used for thermal design. carried out to verify the thermal design. Bottom Switch: Integrated Power MOSFET Drivers The RMS current in bottom switch can be calculated There are four internal MOSFET drivers in a dual- channel step-down converter.  2006 Semtech Corp. 31 www.semtech.com SC2441A POWER MANAGEMENT Applications Information Once either R or R is chosen, the other can be o1 o2 Using low gate charge MOSFETs reduces switching loss. calculated for the desired output voltage V . Since the o It is possible to trade driver IC losses for MOSFET number of standard resistance values is limited, the switching losses by adjusting the gate resistance. Lower calculated resistance may not be available as a standard gate resistance results in higher gate driving current and value resistor. As a result, there will be a set error in the faster MOSFET switching. However the driver incurs converter output voltage. This non-random error is higher losses. Conversely higher gate drive resistance limits the gate drive current, thus lowering the driver The following table lists a few standard resistor dissipation. MOSFET switching loss is higher. combinations for realizing some commonly used output voltages. To prevent shoot-through between the top and the bottom MOSFETs during commutation, one MOSFET should be completely turned off before the other is turned on. The SC2441A uses adaptive non-overlapping timing Vo (V) 0.6 0.9 15 .2 1. 15 .8 23 . 3. to prevent shoot-through. (1-h)/h 0.2 0.8 12 .4 24 .6 5.6 Optimize MOSFET Driving Voltage Ro1 (Ohm) 200 806 1K .4K 2 2K .61K 4K .02 5.62 The on-state DC resistance of a MOSFET, R , is DS_ON Ro2 (Ohm) 1K 1K 1K K 1 1K K 1K 1 determined by its gate to source voltage. The higher the V , the lower the R will be. Once the gate-source GS DS_ON voltage exceeds a certain level, the R becomes DS_ON relatively constant. There is no benefit except higher Only the voltages in boldface can be precisely set with dissipation if you further increase the MOSFET gate drive standard 1% resistors. voltage. It is recommended to select gate drive voltage (V pin) of the SC2441A in between 5V to 7V. CC The input bias current of the error amplifier also causes an error in the output voltage. The inverting input bias Setting the Output Voltage of the Step-down Section currents of error amplifiers 1 and 2 are –60nA and –280nA respectively. Since the non-inverting input is The non-inverting inputs of the error amplifiers are biased to 0.5V, the percentage error in the second output internally biased to 0.5V voltage reference. A simple voltage will be –100% · (0.28µA) · R R /[0.5 · voltage divider (R at top and R at bottom) sets the o1 o2 o1 o2 (R +R )]. To keep this error below 0.2%, R < 4kΩ. converter output voltage. R can be expressed as a o2 o1 o2 o2 function of the voltage feedback gain h=0.5/V and R o o1 Loop Compensation in Step-down Section h R � R o2 o1. 1� h The SC2441A uses current-mode control for both step- caused by the feedback voltage divider ratio. It cannot down channels. Current-mode control is a dual-loop be corrected by the feedback loop. control system in which the inductor peak current is loosely controlled by the inner current-loop. The higher gain outer loop regulates the output voltage. Since the current loop makes the inductor appear as a current source, the complex high-Q poles of the output LC networks is split into a dominant pole determined by the output capacitor and the load resistance and a high frequency pole. This pole-splitting property of current- mode control greatly simplifies loop compensation. www.semtech.com  2006 Semtech Corp. 32 SC2441A POWER MANAGEMENT Applications Information The inner current-loop is unstable (sub-harmonic oscillation) unless the inductor current up-slope is steeper x 29 CS+ + than the inductor current down-slope. For stable + - + operation above 50% duty-cycle, a compensation ramp CS- is added to the sensed-current. In the SC2441A the Slope Compensation compensation ramp is made duty-ratio dependent. The Voltage + - compensation ramp is approximately Comp PWM 0.734�D V (D) � 230mV �D� e SLOPE FB EA V +1.13V - BE D is the duty ratio. - + + 0.5V The slope compensation voltage vs duty ratio is as shown Compensation in Figure 22. Network 0.5 0.4 Figure 23. Control Flow Chart with Slope Compensation 0.3 0.2 0.1 0.0 0.00.2 0.40.6 0.81.0 Duty Ratio (D) k Figure 22. Slope Compensation Voltage Waveform Illustrated as the picture above, as the duty ratio increases, the slope compensation voltage added into the control loop increases too. And the control loop including the slope compensation is shown in Figure 23. The voltage transconductance error amplifier (shown in Figure 24. A simple model of current-mode buck Figure 24) has a g of 315µA/V. C , C and R construct m 2 3 2 converter the compensation network for stable operation with optimized load transient response. For the rated output current I , the first-order gain k is o determined as The feedback gain h and the resistor values are �I o determined using the equations given in the “Setting the k � . �V c Output Voltage” section with k is the product of equivalent current sensing Rs and 0.5 h� . current amplifier gain Gca=29. Furthermore the transfer V o  2006 Semtech Corp. 33 www.semtech.com Slope Compensation Voltage (V) SC2441A POWER MANAGEMENT Applications Information P is a pole for suppressing high-frequency switching 2 function from the voltage error amplifier output v to c noise. So P >> Z . To simplify design, one usually assumes 2 2 the converter output v can be derived from Figure 24. o that C <