SEMTECH SC2441

SC2441 Very Low Input Voltage 2-Phase Synchronous Step-down Controllers with Step-up Converter POWER MANAGEMENT Features Description 2-Phase Synchronous step-down controllers The SC2441 is a high-frequency triple output switching regulator controller. It consists of a dual out-of-phase ‹ 2-Phase Synchronous Continuous Conduction Mode For High Efficiency Step-down Converters synchronous step-down PWM controller with high-current output gate drives and a 1.7A integrated step-up switch- ‹ Out of Phase Operation For Low Input Current Ripples ing regulator. ‹ Operates Up To 1MHz Per Channel ‹ Configurable Dual Outputs Or 2-Phase Single Output The dual-phase step-down controller of the SC2441 can Operation with Peak Current Mode Control be configured to provide two individually controlled and ‹ Excellent Current Sharing Between Phases regulated outputs or a single output with shared current ‹ Wide Input Voltage Range: 1.8V to 15V in each phase. The buck controller can operate from an ‹ Duty Cycle Up to 90% input voltage of at least 4.72V or they can run off a supply ‹ 0.5V Feedback Voltages For Low-Voltage Outputs generated locally with the integrated boost regulator. This ‹ Precision 50mV Current-Limit Threshold makes the SC2441 ideally suited for applications where a ‹ Patented Combi-sense Technique for High SNR of Cur- low-voltage input (3.3V, 2.5V, or 1.8V) is to be stepped rent-Sensing down for lower voltage logic yet the input is too low to ‹ Individual Soft-Start, Overload Shutdown and Enable drive power MOSFET’s efficiently. The boost regulator can Step-up Regulator be used to provide a third auxiliary output while generat- ‹ Wide Input Voltage Range: 1.8V to 15V ing the bias for the buck controllers. ‹ Operates At Twice The Individual Channel Frequency Both the step-down controllers and the step-up regulator Of The Buck Controllers employ fixed frequency peak current-mode control for fast ‹ 0.23V V Switch at 1A CESAT transient response. The master oscillator frequency can ‹ Fixed Frequency with Current-Mode Control be programmed by the user. Common Features ‹ External Synchronization Individual soft-start and overload shutdown timer are em- ‹ Industrial Temperature Range ployed in each step-down controller for hiccup overload protection. In single-output configuration, the channel 1 Applications timer controls the soft-start and overload shutdown func- ‹ Low Voltage Distributed DC-DC Converters tions of both controllers. ‹ Telecommunication Power Supplies Typical Application Circuit ‹ Servers and base stations VIN VINGND + C38 R12 D1 D2 R14 VIN VIN D3 L3 C36 7 FB3 R28 1 IN 8 COMP3 C3 C1 + + C4 C18 27 C2 VIN PH3 C17 28 PVIN 18 25 BST2 BST1 Q2 R3 R4 Q1 19 23 VO1 GDH2 GDH1 L2 VO2 L1 C19 C8 C25 C20 R5 D7 SC2441 C23 C15 C24 R7 D10 + Q6 R8 + Q7 R10 20 22 VO1GND R9 GDL2 GDL1 R6 C21 VO2GND 24 PGND R11 R13 2 26 VPN2 VPN1 RCS+1 RCS+2 16 4 CS2+ CS1+ 15 5 CS2- CS1- RCS-2 RCS-1 14 11 FB2 FB1 C27 C28 13 12 COMP2 COMP1 C30 R18 C31 R19 R16 9 GND R17 6 10 SY NC Rosc R20 3 21 SS1/EN1 VCC 17 SS2/EN2 C32 C33 U1 Figure 1 Revision: January 10, 2005 1 www.semtech.com US patent 6,441,597 SC2441 POWER MANAGEMENT Absolute Maximum Rating Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Ss ymbo Ms aximum Rating Unit IV nput Voltages ,V -V 0.3 to 20 IN PVIN SV upply Voltage For Step-Down Controller -V 0.3 to 20 CC HV igh-Side Driver Supply Voltages , V -V 0.3 to 20 BST1 BST2 FV B1, FB2 Voltage , V -V 0.3 to 20 FB1 FB2 CV OMP1, COMP2 Voltages , V -V 0.3 to 4.5 COMP1 COMP2 CS1(+), CS1(-), CS2(+) and CS2(-) V V , V ,V -V 0.3 to 20 CS1(+), CS1(-) CS2(+) CS2(-) Voltages SV YNC/SHDN Voltage -V 0.3 to 20 S/S RV OSC Voltage -V 0.3 to 5 ROSC SV S1/EN1 AND SS2/EN2 Voltages , V -V 0.3 to 6 SS1 SS2 PI eak Gate Drive Current , I , I , I 3A GDH1 GDH2 GDL1 GDL2 PI eak VPN1 and VPN2 Output Currents , I 1A 00 m VPN1 VPN2 FV B3 Voltage 4V FB3 CV OMP3 Voltage -V 0.3 to 2 COMP3 PV H3 Voltage -V 0.3 to 35 PH3 AT mbient Temperature -C 40 to 85 ° A Thermal Resistance Junction to Case 1W 3 °C/ θ JC Thermal Resistance Junction to Ambient θ 8W 4 °C/ JA ST torage Temperature Range -C 60 to 150 ° STG LT ead Temperature (Soldering) 10 sec 2C 60 ° LEAD Electrical Characteristics Unless specified: V = 2V, V = V = V =8V, SYNC/SHDN =2V, R = 51.1kΩ, -40°C < T = T < 85°C IN CC BST1 BST1 OSC A J Pl arameter Ss ymboCn ondition Mp i Tx y Ms a Unit Undervoltage Lockout VSV tart Threshold VI5 ncreasing 42 .6 4V .7 CC CCTH CC VUV VLO Threshold VD4 ecreasing 45 .34V .4 CC CCTL CC V = 8V, V = 2V 14 21 mA CC S/S VOI perating Current V < V , V = 2V 0.15 0.25 CC CC CC CCTL S/S V = 8V, V = 0V 10 13 CC S/S Channel 1 and 2 Error Amplifiers V = 3V IN V < V < 10V FV eedback Voltage V 06 .48707 .490V .50 CCTL CC FB1, FB2 -° 40 C frequency set with ROSC). The boost converter runs at the external clock CLK frequency whereas the step-down controllers operate at half the clock frequency. The Inverting Input of the Error Amplifier for the Boost Converter. FB3 is tied to an external 73 FB resistive divider for output3 voltage setting. The Error Amplifier Output of the Boost Converter. This pin is used for loop compensation. 83 COMP Pulling this pin below 0.4V disables the step-up converter. 9DG. N Analog Signal Ground 1C 0 ROS An external resistor connected from this pin to GND sets the oscillator frequency. The Inverting Input of the Error Amplifier for the Step-down Controller 1. Tie to an external 11 1 FB resistive divider between OUTPUT1 and the ground for output voltage sensing. The Error Amplifier Output for Step-down Controller 1. This pin is used for loop compensation. 11 2 COMP The Error Amplifier Output for Step-down Controller 2. This pin is used for loop compensation. 12 3 COMP The Inverting Input of the Error Amplifier for the Step-down Controller 2. Tie to an external 12 4 FB resistive divider between output2 and the ground for output voltage sensing. Tie to IN or VCC for two-phase single output applications The Inverting Input of the Current-sense Amplifier/Comparator for the Step-down Controller 2. 1- 5 CS2 Normally tied to the output of the converter. The Non-inverting Input of the Current-sense Amplifier/Comparator for the Step-down 1+ 6 CS2 Controller 2 An external capacitor tied to this pin sets (i) the soft-start time (ii) output overload latch off time 12 7 SS2/EN for step-down converter 2. Pulling this pin below 0.5V shuts off the gate drivers for the second controller. Leave open for two-phase single output applications. Bootstrapped Supply for the High-side Gate Drive 2. Connect to a bootstrap capacitor and an 12 8 BST external diode as described in application information. Gate Drive Output for the High-side N-channel MOSFET of Output 2. Gate drive voltage 12 9 GDH swings from ground to VBST2. Gate Drive Output for the Low-side N-channel MOSFET of Output 2. Gate drive voltage 22 0 GDL swings from ground to VCC. www.semtech.com  2005 Semtech Corp. 6 SC2441 POWER MANAGEMENT Pin Descriptions Supply Voltage for Both Step-down Controllers and the Low-side Gate Drivers. The boost converter output is tied to VCC if VIN in not high enough to fully enhance the power MOSFET's 2C 1 VC and the boost converter provides an auxiliary supply voltage for the step-down controllers. Tie VCC to VIN if the boost converter is not needed. Gate Drive Output for the Low-side N-channel MOSFET of Output 1. Gate drive voltage 21 2 GDL swings from ground to VCC. Gate Drive Output for the High-side N-channel MOSFET of Output 1. Gate drive voltage 21 3 GDH swings from ground to VBST1. Ground Supply of the High-side and the Low-side Gate Drivers of Both Step-down Controllers. 2D 4 PGN It is also the emitter of the boost switch. Bootstrapped Supply for the High-side Gate Drive 1. Connect to a bootstrap capacitor and an 21 5 BST external diode as described in application information. The Virtual Phase (Unloaded) Node of the First Step-down Converter. Used for "Combi" 21 6 VPN current sense only. This pin is left open when sensing current with a sense resistor at the converter output. 23 7 PH Boost Switch Collector. Connect to a boost inductor and a rectifying diode. 2N 8 PVI Power Supply Voltage for the Boost Switch and the Virtual Phase Node Drivers.  2005 Semtech Corp. 7 www.semtech.com SC2441 POWER MANAGEMENT Block Diagram IN VIN UVLO 1.25V REFERENCE 1 1.60/1 .74V CLK PVIN SYNC/SHDN 28 CLK2 6 0.5V 0.36V VCC FREQUENCY OSCILLATOR ROSC CLK1 DIVIDER 21 10 BST1 UVLO SLOPE COMP 4.45/4.65V 25 COMP1 SHDN 12 SHDN GDH1 FB1 SLOPE2 23 11 - R EA1 - Q PWM1 + 0.5V VPN1 Non-Overlapping S + Conduction 26 SLOPE1 Control GDL1 CS1+ FAULT 22 4 + + + CS1- ISEN1 Σ 5 - OL Soft-Start PGND + And DSBL ILIM I 1 24 Overload - SS1/EN1 Hiccup 50mV 3 Control 1 1.25V - B A + BST2 SEL ANALOG SWITCH Y CLK2 18 SEL COMP2 13 GDH2 FB2 19 14 - R PVIN EA2 - Q + PWM2 0.5V VPN2 Non-Overlapping S + Conduction 2 SLOPE2 VCC Control GDL2 CS2+ FAULT 16 + 20 + + CS2- ISEN2 Σ 15 - OL Soft-Start + And DSBL ILIM2 I Overload - SS2/EN2 Hiccup 50mV GND 17 Control 2 9 Step-down Controllers Functional Diagram Figure 2 www.semtech.com  2005 Semtech Corp. 8 SC2441 POWER MANAGEMENT Block Diagram PH3 COMP3 27 8 CLK FB3 7 - R EA3 - Q + PWM3 1.25V S + + ILIM3 14mV - SLOPE 7mΩ COMP + + + Σ ISEN3 - 24 PGND Step-up Converter Functional Diagram Figure 3 FB + 0.36V S - OL Q 2µΑ SS/EN R 0.47V/3.25V DSBL FAULT 0.6V/0.9V 3µΑ Details of the Soft-start and Overload Hiccup Control Circuit Figure 4  2005 Semtech Corp. 9 www.semtech.com SC2441 POWER MANAGEMENT Typical Performance Characteristics VIN START AND UVLO THRESHOLD FB1 AND FB2 VOLTAGES vs TEMPERATURE FB3 VOLTAGE vs TEMPERATURE VOLTAGES vs TEMPERATURE 2 0.5 1.3 V = 2V IN V = 5V CC 1.9 0.498 1.28 0.496 1.8 1.26 V START IN 0.494 1.7 1.24 V UVLO IN 0.492 1.6 1.22 0.49 1.2 1.5 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 TEMPERATURE (ºC) TEMPERATURE (ºC) TEMPERATURE (ºC) STEP-UP CONVERTER SWITCHING STEP-DOWN CHANNEL SWITCHING VCC START AND UVLO THRESHOLD FREQUENCY vs TEMPERATURE VOLTAGES vs TEMPERATURE FREQUENCY vs TEMPERATURE 1050 5 520 1040 R = 51.1K OSC Ω R = 51.1KΩ OSC 515 1030 4.8 510 V START CC 1020 505 1010 4.6 V UVLO CC 1000 500 990 4.4 495 980 490 970 4.2 485 960 950 4 480 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 TEMPERATURE (ºC) TEMPERATURE (ºC) TEMPERATURE (ºC) STEP-UP SWITCH MAXIMUM DUTY- CYCLE MAXIMUM DUTY- CYCLE OF STEP-DOWN STEP-DOWN CONTROLLER CURRENT-LIMIT vs TEMPERATURE CHANNEL vs TEMPERATURE THRESHOLD vs TEMPERATURE 90 95 50 R = 51.1KΩ OSC R = 51.1KΩ CS(-) = 0 OSC 88 93 48 86 CS(-) = 5V 91 46 84 89 44 82 87 42 VCC = 8V 85 80 40 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 TEMPERATURE (ºC) TEMPERATURE (ºC) TEMPERATURE (ºC) www.semtech.com  2005 Semtech Corp. 10 DUTY CYCLE (%) VOLTAGES (V) VOLTAGE (V) DUTY CYCLE (%) FREQUENCY (KHz) VOLTAGE (V) VOLTAGES (mV) FREQUENCY (KHz) VOLTAGES (V) SC2441 POWER MANAGEMENT Operation should also be between 1-1.33 times the set free-running Overview frequency. The SC2441 is a constant frequency triple-output If not synchronized, the SYNC/SHDN pin should be tied switching regulator especially designed for operating from to the input. Pulling the SYNC/SHDN pin below 0.5V shuts input voltages as low as 1.8V. It consists of two current- off the SC2441 after 85µs time delay. mode step-down switch-mode PWM controllers driving all N-channel MOSFET’s and a 1.7A step-up current-mode Control Loop controller with integrated 1.7A power switch. A low voltage input (3.3V, 2.5V or 1.8V) can be stepped up to The step-down controllers and the boost regulator in the 5V-10V locally using the boost regulator to provide SC2441 use peak current-mode control for fast transient sufficient gate drives for the step-down converters. The response, ease of compensation and current sharing in boost converter can also be used to generate a third single output operation. The low-side MOSFET of each output. step-down channel is turned off at the falling-edge of the phase clock. After a brief non-overlapping conduction The two step-down channels of the SC2441 operate at interval of 74ns, the high-side MOSFET is turned on. The 180 degrees out of phase from each other. Since input phase inductor current ramps up. When the sensed currents are interleaved in a two-phase converter, input inductor current reaches the threshold determined by ripple current is lower and smaller input capacitor can be the error amplifier output and ramp compensation, the used for filtering. high-side MOSFET is turned off. After a non-overlapping delay of 62ns, the low-side MOSFET is turned on. The step-down controllers of the SC2441 operate in synchronous continuous-conduction mode. They can be The supply voltages for the high-side gate drivers are configured either as two independent step-down obtained from two diode-capacitor bootstrap circuits. If controllers producing two separate outputs or as a dual- the bootstrap capacitor is charged from V , then the CC phase single-output controller by tying the FB2 pin to V . high-side gate drive voltage will swing from approximately CC In single output operation, the channel-one error amplifier 2V to the ground. The outputs of the low-side gate CC controls both channels and the channel-two error drivers swing from V to the ground. CC amplifier is disabled. Soft-start and overload hiccup of both channels is also synchronized to channel one. All three converters in the SC2441 have internal ramp- compensation to prevent sub-harmonic oscillation when Frequency Setting and Synchronization operating above 50% duty cycle. The internal compensating ramp is designed for an inductor ripple- The step-up regulator in the SC2441 runs at twice the current of between ¼ to 1/3 of the maximum inductor frequency of step-down controllers. Each step-down current and the peak-to-peak current-sense voltage (CSP- controller runs at one-half of the oscillator frequency and CSN of the step-down controllers) of between ¼ to 1/3 is 180 degrees out of phase from the other step-down of the current-limit threshold (50mV). The current-limits controller. The switching frequency of the step-up of all three converters are unaffected by the regulator is the oscillator frequency and can be set with compensation ramps. an external resistor from the R pin to the ground. The OSC boost regulator and the step-down controllers are capable Current-Sensing of operating up to 2 MHz and 1 MHz respectively. It is necessary to consider the operating duty-ratio range Since the inductor current ramp is used as the modulating before deciding the switching frequency. See Applications ramp in current-mode control, the inductor current needs Information section for more details. to be sensed. There are two current sensing methods for the step-down controllers. Since the maximum current- When synchronized externally, the applied clock frequency sense voltage (CSP-CSN) is only 50mV, a precision sense (hence switching frequency of the step-up converter) resistor in series with the inductor can be used at the should be twice the individual phase frequency of the output without resulting in excessive power dissipation. step-down controllers. The synchronizing clock frequency  2005 Semtech Corp. 11 www.semtech.com SC2441 POWER MANAGEMENT Operation (Cont.) Current-Limit Although accurate and far easier to lay out than high- side resistor sensing, a pair of precision sense resistors The maximum current sense voltage of +50mV is the adds cost to the converter. The SC2441 has provision to cycle-by-cycle peak current limit when the load is drawing reconstruct a differential voltage proportional to the current from the converter. inductor current at the output of the converter. The voltage to current ratio or the equivalent sense resistance Soft-Start and Overload Protection R is a combination of high-side and low-side MOSFET eq R ’s and the inductor series resistance (hence the DS(ON) The undervoltage lockout circuit discharges the SS/EN name “combi-sense”). The SC2441 provides the virtual capacitors. After V rises above 4.65V, the SS/EN phase voltages VPN1 and VPN2 (these are unloaded CC capacitors are slowly charged by internal 2.3µA current versions of their respective phase voltages) for current sources. With internal PNP transistors, the SS/EN voltages sensing. This method does not require precision sense clamp the error amplifier outputs. When the error amplifier resistor. It is cheaper to implement but is less accurate output rises to 1.7V, the high-side MOSFET starts to switch. than resistor current sensing. Since the sensed voltage As the SS/EN capacitor continues to charge, the COMP is developed at the output of the step-down converter, it voltage follows. The converter gradually delivers increasing is less prone to switching transient spikes. This method power to the output. The inductor current follows the COMP will be described in more details in the Applications voltage envelope until the output goes into regulation. The Information section. SS/EN clamp on COMP is released. Boost switch current is sensed with an integrated sense After the SS/EN capacitor is charged above 3.25V (high resistor with a current-limit of 1.7A. enough for the error amplifier to provide full load current), the overload detection circuit is activated. If the output Error Amplifiers voltage falls below 70% of its set value, an overload latch will be set and both the top and the bottom MOSFET’s All error amplifiers in the SC2441 are transconductance will be turned off. The SS/EN capacitor is slowly amplifiers. Converters are compensated with series RC discharged with an internal 1.4µA current sink. The network from the COMP pins to the ground. An additional overload latch is reset when the SS/EN capacitor is small parallel capacitor may be required for stability. discharged below 0.47V. The SS/EN capacitor is then recharged with the 2.3µA current source and the converter In closed loop operation, the step-down error amplifiers undergoes soft-start. If overload persists, the step-down output range from 1.7V to 3.5V. There is no control (high- converters will undergo repetitive shutdown and restart side) gate drive until the COMP voltage exceeds 1.6V. (hiccup). Soft-start process should be slow enough to allow Both non-inverting inputs of the feedback amplifiers are the output to reach 70% of its final value before the SS/ tied to an internal 0.5V voltage reference. EN capacitor is charged above 3.25V (see Figure 4). The error amplifier of the step-up converter has 1.25V If the output is short-circuited, the inductor current will as its reference voltage. Its output voltage ranges from not increase indefinitely between the time the inductor 0.8V to 1.35V in closed-loop operation. current reaching its current limit and shutdown. This is due to cycle skipping reduces the actual operating frequency. The SS/EN pin can also be used as the enable input for that channel. Both the high-side and the low-side MOSFET’s will be turned off if the SS/EN pin is pulled below 0.5V. www.semtech.com  2005 Semtech Corp. 12 SC2441 POWER MANAGEMENT Applications Information 1) passive component sizes The SC2441 consists of two current-mode synchronous 2) converter efficiency buck controllers and an auxiliary boost converter. The 3) EMI SC2441 can be used to generate 4) Minimum switch on time and 1) two independent step-down outputs or 5) Maximum duty ratio 2) dual phase single output with current sharing and 3) a step-up output For a given output power, the sizes of the passive components are inversely proportional to the switching The application information using SC2441 for the control frequency, whereas MOSFET’s/Diodes switching losses are of step-down and step-up converters are described below. proportional to the operating frequency. Other issues such as heat dissipation, packaging and the cost issues are Step-down Converter also to be considered. The frequency bands for signal transmission should be avoided because of EM Specifications of a step-down converter are given by the interference. followings Input voltage range: V ∈ [V ,V ] in in,min in,max Minimum Switch On Time Limitation Input voltage ripple (peak-to-peak): ΔV in Output voltage: V o In both step-down controllers, the falling edge of the Output voltage accuracy: ε clock turns on the top MOSFET. The inductor current Output voltage ripple (peak-to-peak): ΔV o ramps up so does the sensed voltage. After the sensed Nominal output (load) current: I o voltage crosses a threshold determined by the error Maximum output current limit: I o,max amplifier output, the top MOSFET is turned off. The Output (load) current transient slew rate: dI (A/s) o propagation delay time from the turn-on of the controlling Circuit efficiency: η. FET to its turn-off is the minimum switch on time. The SC2441 has a minimum on time of about 180ns at room Based on these converter specifications, selection criteria temperature. This is the shortest on interval of the and design procedures for the following components are controlling FET. The controller either does not turn on the described. top MOSFET at all or turns it on for at least 180ns. 1) output inductor (L) type and value, 2) output capacitor (C ) type and value, o For a synchronous step-down converter, the operating 3) input capacitor (C ) type and value, in duty cycle is V /V . So the required on time for the top o IN 4) power switch MOSFET’s, MOSFET is V /(V f ). If the frequency is set such that S o IN 5) current sensing and limiting circuitry, the required pulse width is less than 180ns, then the 6) voltage sensing circuitry, converter will start skipping cycles. Due to minimum on 7) loop compensation circuitry. time limitation, simultaneously operating at very high switching frequency and very short duty cycle is not To illustrate the design process, the following example is practical. If the input voltage is 3.3V and the operating used: frequency is 1MHz, the lowest output voltage will be 0.6V. V =3.3V, V =1.2V, I =4A, f =500kHz. in o o s There will not be enough modulation headroom if the on time is simply made equal to the minimum on time of the Operating Frequency (f ) s SC2441. For ease of control, we recommend the required pulse width to be at least 1.5 times the minimum on time. The switching frequency in the SC2441 is user- programmable. The advantages of constant frequency Maximum Duty-cycle Consideration operation are simple passive component selection and fast transient response with simple frequency compensation. When operating at 500KHz, the maximum top MOSFET Before setting the operating frequency, the following trade- on duty-cycle is 90%. The top MOSFET therefore turns off offs should be considered. for at least 200ns every cycle regardless of the switching frequency. This places an upper bound on the voltage  2005 Semtech Corp. 13 www.semtech.com SC2441 POWER MANAGEMENT Applications Information (Cont.) conversion ratio at a given switching frequency. If the V (1− D) o L = . desired output voltage requires high operating duty-cycle, δI f o s then operating frequency will have to be lowered to allow The peak current in the inductor becomes (1+δ/2)*Io modulating headroom. and the RMS current is Setting the Step-down Channel Frequency 2 δ I = I 1+ . L,rms o 12 The switching frequency of both step-down controllers is set with an external resistor from Pin 10 to the ground. The followings are to be considered when choosing The set frequency is inversely proportional to the resistor inductors. value (Figure 5). a) Inductor core material: For high efficiency applications above 350KHz, ferrite, Kool-Mu and polypermalloy materials should be used. Low-cost powdered iron cores 800 can be used for cost sensitive-applications below 350KHz 700 but with attendant higher core losses. 600 b) Select inductance value: Sometimes the calculated 500 inductance value is not available off-the-shelf. The designer can choose the adjacent (larger) standard inductance 400 value. The inductance varies with temperature and DC 300 current. It is a good engineering practice to re-evaluate 200 the resultant current ripple at the rated DC output current. 100 c) Current rating: The saturation current of the inductor 0 should be at least 1.5 times of the peak inductor current 0 50 100 150 200 250 under all conditions. Rosc (k Ohm) Output Capacitor (C ) and V Ripple o out The output capacitor provides output current filtering in Figure 5. Step-down Channel Free-running frequency vs. steady state and serves as a reservoir during load transient. R . OSC The output capacitor can be modeled as an ideal capacitor in series with its parasitic ESR (R ) and ESL (L ) (Figure esr esl 6). Inductor (L) and Ripple Current Co Both step-down controllers in the SC2441 operate in synchronous continuous-conduction mode (CCM) regardless of the output load. The output inductor selection/design Lesl is based on the output DC and transient requirements. Both output current and voltage ripples are reduced with larger inductors but it takes longer to change the inductor Resr current during load transients. Conversely smaller inductors results in lower DC copper losses but the AC core losses (flux swing) and the winding AC resistance losses are Figure 6. C equivalent circuit o higher. A compromise is to choose the inductance such that peak-to-peak inductor ripple-current is 20% to 30% of If the current through the branch is i (t), the voltage across b the terminals will then be the rated output load current. Assuming that the inductor current ripple (peak-to-peak) is δ*I , the inductance will then be o www.semtech.com  2005 Semtech Corp. 14 fs (kHz) SC2441 POWER MANAGEMENT Applications Information (Cont.) t δI o 1 di (t) b . v (t) = V + i (t)dt + L + R i (t). o o b esl esr b ∫ 2 3 C dt o 0 Usually it is necessary to have several capacitors of the This basic equation illustrates the effects of ESR, ESL and same type in parallel to satisfy the ESR requirement. The C on the output voltage. o voltage ripple cause by the capacitor charge/discharge The first term is the DC voltage across C at time t=0. The o should be an order of magnitude smaller than the voltage second term is the ripple-voltage caused by the inductor ripple caused by the ESR. To guarantee this, the ripple-current. The third term is the voltage ripple due to capacitance should satisfy ESL and the fourth term is the voltage ripple due to ESR. 10 The total output voltage ripple is then a vector sum of the C > . o 2πf R last three terms. s esr Since the inductor current is a triangular waveform with peak-to-peak value δ*I , the ripple-voltage caused by In many application circuits, several low ESR ceramic o inductor current ripples is capacitors are added in parallel with the aluminum capacitors to further reduce ESR and improve high δI o Δv ≈ . C frequency decoupling. Since the capacitances and the 8C f o s ESR’s of ceramic and aluminum capacitors are different, The ripple-voltage due to ESL is the following remarks are made to clarify some practical δI issues. o Δv = L f ESL esl s D Remark 1: High frequency ceramic capacitors may not carry and the ESR ripple-voltage is most of the ripple current. It also depends on the capacitor Δv = R δI . ESR esr o value. Only when the capacitor value is set properly, the Aluminum capacitors (e.g. electrolytic, solid OS-CON, effect of ceramic capacitor low ESR starts to be significant. POSCAP, tantalum) have high capacitances and low ESL’s. For example, if a 10µF, 4mΩ ceramic capacitor is The ESR has the dominant effect on the output ripple connected in parallel with 2x1500µF, 90mΩ electrolytic voltage. It is therefore very important to minimize the ESR. capacitors, the ripple current in the ceramic capacitor is only about 42% of the current in the electrolytic capacitors When determining the ESR value, both the steady state at the ripple frequency. If a 100µF, 2mΩ ceramic capacitor ripple-voltage and the dynamic load transient need to be is used, the ripple current in the ceramic capacitor will be considered. To keep the steady state output ripple-voltage about 4.2 times of that in the electrolytic capacitors. When , the ESR should satisfy < ΔV o two 100µF, 2mΩ ceramic capacitors are used, the current ΔV o ratio increases to 8.3. In this case most of the ripple R < . esr1 δI o current flows in the ceramic decoupling capacitor. The ESR of the ceramic capacitors will then determine the output To limit the dynamic output voltage overshoot/undershoot ripple-voltage. within α (say 3%) of the steady state output voltage) under 0 to full load current swing, the ESR value should be Remark 2: The total equivalent capacitance of the filter αV o R < . bank is not simply the sum of all the paralleled capacitors. esr2 I o The total equivalent ESR is not simply the parallel The required ESR value of the output capacitors should combination of all the individual ESR’s either. Instead they be should be calculated using the following formulae. R = min{R ,R }. esr esr1 esr2 2 2 2 2 2 (R + R ) ω C C + (C + C ) 1a 1b 1a 1b 1a 1b In the aluminum capacitor selection, the working voltage ω = C ( ) : eq 2 2 2 + ω + + (R C R C ) C C (C C ) rating is normally suggested to be greater than 1.5V . 1a 1a 1b 1b 1a 1b 1a 1b o The allowable current ripple (RMS) should be greater than  2005 Semtech Corp. 15 www.semtech.com SC2441 POWER MANAGEMENT Applications Information (Cont.) In Figure 8 the DC input voltage source has an internal impedance R and the input capacitor C has an ESR 2 2 2 2 2 in in R R (R + R )ω C C + (R C + R C ) 1a 1b 1a 1b 1a 1b 1b 1b 1a 1a R (ω) := denoted as R . MOSFET and input capacitor current eq esr 2 2 2 2 2 (R + R ) ω C C + (C + C ) 1a 1b 1a 1b 1a 1b waveforms, ESR voltage ripple and input voltage ripple are shown in Figure 9. where R and C are the ESR and capacitance of 1a 1a electrolytic capacitors, and R and C are the ESR and 1b 1b capacitance of the ceramic capacitors respectively (Figure 7). C1a C1b Ceq R1a R1b Req Figure 9. Typical waveforms at the input of a buck Figure 7. Equivalent RC branch. converter. Req and Ceq are both functions of frequency. For rigorous It can be seen that the current in the input capacitor pulses design, the equivalent ESR should be evaluated at the with high di/dt. Capacitors with low ESL should be used. It ripple frequency for voltage ripple calculation when both is also important to place the input capacitor close to the ceramic and electrolytic capacitors are used. If R = R = 1a 1b MOSFET’s on the PC board to reduce trace inductances R and C = C = C , then R and C will be frequency- 1 1a 1b 1 eq eq around the pulse current loop. independent and The RMS value of the capacitor current is approximately R = 1/2 R and C = 2C . eq 1 eq 1 2 δ D D 2 I = I D[(1+ )(1− ) + (1− D)]. Input Capacitor (C ) Cin o 2 in 12 η η The power losses at the input capacitors is then The input supply to the converter usually comes from a pre-regulator. Since the input supply is not ideal, input 2 P = I R . capacitors are needed to filter the current pulses at the Cin Cin esr switching frequency. A simple buck converter is shown in For reliable operation, the maximum power dissipation in Figure 8. o the capacitors should not result in more than 10 C of temperature rise. Many manufacturers specify the maximum allowable ripple current (ARMS) rating of the capacitor at a given ripple frequency and ambient temperature. The input capacitance should be high enough to handle the ripple current. For higher power applications, multiple capacitors are placed in parallel to increase the ripple current handling capability. Sometimes meeting tight input voltage ripple specifications Figure 8. Buck converter input model may require the use of larger input capacitance. At full load, the peak-to-peak input voltage ripple due to the ESR is www.semtech.com  2005 Semtech Corp. 16 SC2441 POWER MANAGEMENT Applications Information (Cont.) δ Δv = R (1+ )I . If D >0.5 and D > 0.5, then ESR esr o 1 2 2 The peak-to-peak input voltage ripple due to the capacitor 2 2 2 is I ≈ (D + D −1)(I + I ) + (1− D )I + (1− D )I . Cin 1 2 o1 o2 2 o1 1 o2 DI o Δv ≈ . C Power MOSFET Selection and Gate Drive C f in s Main considerations in selecting the MOSFET’s are power From these two expressions, C can be found to meet the IN dissipation, cost and packaging. Switching losses and input voltage ripple specification. In a multi-phase conduction losses of the MOSFET’s are directly related to converter, channel interleaving can be used to reduce ripple. the total gate charge (C ) and channel on-resistance g The two step-down channels of the SC2441 operate at (R ). In order to judge the performance of MOSFET’s, ds(on) 180 degrees from each other. If both step-down channels the product of the total gate charge and on-resistance is in the SC2441 are connected in parallel, both the input used as a figure of merit (FOM). Transistors with the same and the output RMS currents will be reduced. FOM follow the same curve in Figure 10. Ripple cancellation effect of interleaving allows the use of smaller input capacitors. When converter outputs are 50 connected in parallel and interleaved, smaller inductors 40 and capacitors can be used for each channel. The total Cg() 100, Rds output ripple-voltage remains unchanged. Smaller Cg() 200, Rds inductors speeds up output load transient. 20 Cg() 500, Rds When two channels with a common input are interleaved, 1 0 the total DC input current is simply the sum of the individual 0 5 10 15 20 DC input currents. The combined input current waveform 1 Rds 20 On-resistance (mOhm) depends on duty ratio and the output current waveform. FOM:100*10^{-12} Assuming that the output current ripple is small, the FOM:200*10^{-12} FOM:500*10^{-12} following formula can be used to estimate the RMS value of the ripple current in the input capacitor. Figure 10. Figure of merit curves. Let the duty ratios and output currents of Channel 1 and Channel 2 be D , D and I , I respectively. The closer the curve is to the origin, the lower is the FOM. 1 2 o1 o2 This means lower switching loss or lower conduction loss If D <0.5 and D <0.5, then or both. It may be difficult to find MOSFET’s with both low 1 2 C and low R . Usually a trade-off between R and C g ds(on ds(on g 2 2 has to be made. I ≈ D I + D I . Cin 1 o1 2 o2 MOSFET selection also depends on applications. In many If D >0.5 and (D -0.5) < D <0.5, then 1 1 2 applications, either switching loss or conduction loss dominates for a particular MOSFET. For synchronous buck 2 2 2 converters with high input to output voltage ratios, the top ≈ + − + + − + I 0.5I (D 0.5)(I I ) (D D 0.5)I . Cin o1 1 o1 o2 2 1 o2 MOSFET is hard switched but conducts with very low duty cycle. The bottom switch conducts at high duty cycle but If D >0.5 and D < (D -0.5) < 0.5, then 1 2 1 switches at near zero voltage. For such applications, MOSFET’s with low C are used for the top switch and g MOSFET’s with low R are used for the bottom switch. ds(on) 2 2 2 I ≈ 0.5I + D (I + I ) + (D − D − 0.5)I . Cin o1 2 o1 o2 1 2 o2  2005 Semtech Corp. 17 www.semtech.com Gate Charge (nC) SC2441 POWER MANAGEMENT Applications Information (Cont.) The losses in power MOSFET’s consist of In Figure 11, a) conduction loss due to the channel resistance R , Q is the gate charge needed to bring the gate-to-source ds(on) gs1 voltage V to the threshold V , b) switching loss due to the switch rise time t and fall time r gs gs_th Q is the additional gate charge required for the switch t and f gs2 c) the gate loss due to the gate resistance R . current to reach its full-scale value I and ds G . Q is the charge needed to charge gate-to-drain (Miller) gd Top Switch: capacitance when V is falling. ds Switching losses occur during the time interval [t , t ]. The RMS value of the top switch current is 1 3 Defining t = t -t . t can be approximated as 2 r 3 1 r δ I = I D(1+ ). Q1,rms o 12 (Q + Q )R gs2 gd gt t = . Its conduction loss is then r V − V cc gsp 2 where R is the total resistance from the driver supply rail P = I R . gt tc Q1,rms ds(on) to the gate of the MOSFET. It includes the gate driver internal impedance R , external resistance R and the gate R varies with temperature and gate-source voltage. gi ge ds(on) resistance R within the MOSFET i.e. Curves showing R variations can be found in ds(on) g manufacturers’ data sheet. From the Si7882DP datasheet, R is less than 4.5mΩ when V is greater than 5V. R = R +R +R . ds(on) gs gt gi ge g However R increases by nearly 40% as the junction ds(on) temperature increases from 25°C to 125°C. V is the Miller plateau voltage shown in Figure 11. gsp Similarly an approximate expression for t is f The switching losses can be estimated using the simple formula (Q + Q )R gs2 gd gt t = . 1 δ f P = (t + t )(1+ )I V f . V ts 2 r f 2 o in s gsp where t is the rise time and t is the fall time of the switching r f process. Different manufactures have different definitions Only a portion of the total losses P = Q V f is dissipated in g g cc s and test conditions for t and t . To clarify these, we sketch the MOSFET package. Here Q is the total gate charge r f g the typical MOSFET switching characteristics under clamped specified in the datasheet. The power dissipated within inductive mode in Figure 11. the MOSFET package is R g P = Q V f . tg g cc s R gt The total power loss of the top switch is then P = P +P +P . t tc ts tg If the input supply of the power converter varies over a wide range, then it will be necessary to weigh the relative importance of conduction and switching losses. This is because conduction loss is inversely proportional to the input voltage. Switching loss however increases with the input voltage. The total power loss of MOSFET should be calculated and compared for high-line and low-line cases. The worst case is then used for thermal design. charge Bottom Switch: Figure 11. MOSFET switching characteristics The RMS current in bottom switch can be shown to be 2 δ I = I (1− D)(1+ ). Q2,rms o 12 www.semtech.com  2005 Semtech Corp. 18 SC2441 POWER MANAGEMENT Applications Information (Cont.) The conduction loss is then Using low gate charge MOSFET’s reduces switching loss. It is possible to trade driver IC losses for MOSFET 2 P =I R , switching losses by adjusting the gate resistance. Lower bc Q2,rms ds(on) gate resistance results in higher gate driving current and where R is the channel resistance of bottom MOSFET. faster MOSFET switching. However the driver incurs ds(on) If the input voltage to output voltage ratio is high (e.g. higher losses. Conversely higher gate drive resistance V =12V, V =1.5V), the duty ratio D will be small. Since the limits the gate drive current, thus lowering the driver in o bottom switch conducts with duty ratio (1-D), the dissipation. MOSFET switching loss is higher. corresponding conduction losses can be quite high. Due to non-overlapping conduction between the top and To prevent shoot-through between the top and the bottom the bottom MOSFET’s, the internal body diode or the MOSFET’s during commutation, one MOSFET should be external Schottky diode across the drain and source completely turned off before the other is turned on. In the terminals always conducts prior to the turn on of the bottom SC2441 the top and the bottom gate drive pulses are made MOSFET. The bottom MOSFET switches on with only a diode non-overlapping. When not driving any load, the non- voltage between its drain and source terminals. The overlapping commutation intervals from the top to the switching loss bottom and from the bottom to the top gate drives are set 1 δ at 62ns and 74ns respectively. If MOSFET’s are driven from P = (t + t )(1+ )I V f bs 2 r f 2 o d s the SC2441, the non-overlapping commutation times will is negligible due to near zero-voltage switching. decrease due to finite gate-source voltage rise and fall times. The gate-source voltage waveforms of the MOSFET’s should The gate loss is estimated as not overlap above their respective thresholds when driven R g from the SC2441. Use of low gate charge MOSFET’s reduces P = Q V f . bg g cc s R transition times and the tendency of shoot-through. The gt combined rise and fall times during both commutations The total bottom switch loss is then should be less than the preset non-overlapping intervals P =P +P +P . b bc bs bg Current Sensing (Combi-Sense) Once the power losses P for the top (P ) and bottom (P ) loss t b Inductor current sensing is required for the current-mode MOSFET’s are known, thermal and package design at control. Although the inductor current can be sensed with component and system level should be done to verify that a precision resistor in series with the inductor, a novel the maximum die junction temperature (T , usually j,max o (US patent 6,441,597) lossless combi-sense technique 125 C) is not exceeded under the worst-case conditions. can also be used in the SC2441. This Semtech proprietary The equivalent thermal impedance from junction to technique has the following advantages ambient (θ ) should satisfy ja T − T j,max a,max 1) lossless current sensing θ ≤ . ja P loss 2) higher signal-to-noise ratio and 3) preventing thermal run-away. θ depends on the die to substrate bonding, packaging ja material, the thermal contact surface, thermal compound The basic arrangement of the combi-sense is shown in property, the available effective heat sink area and the air Figure 12. flow condition (free or forced convection). Actual temperature measurement of the prototype should be carried out to In Figure 12 R is the equivalent series resistance of the verify the thermal design. L output inductor. R and C form a RC network for inductor s s current sensing. This branch is driven from a small totem Integrated Power MOSFET Drivers pole driver (Q3 and Q4) within the SC2441. The base driving signals Vbe3 and Vbe4 There are four internal MOSFET drivers in step-down section of the SC2441 for driving all the MOSFET’s in a dual-channel step-down converter.  2005 Semtech Corp. 19 www.semtech.com SC2441 POWER MANAGEMENT Applications Information (Cont.) Vin Q1 Vin Vgs1 iL(t) L RL PN Cin iL(t) L RL Rs Cs PN Ci n Vo Rs Cs Q2 Cou t Rload vC (t) Vgs2 Vo VPN Cout Rds2 Rload vC(t) Vbe3 Q3 VP N Figure 13. b) Equivalent sub-circuit. Q4 Vbe4 Figure 12. The basic structure of combi-sense. V =[D(Rds1+RL)+(1-D)(Rds2+RL)]I Cs o follow the gate drive signals Vgs1 and Vgs2 respectively or with minimal delay. The transition edges at the Virtual Phase Node (VPN) therefore matches closely to those of V =[D Rds1+(1-D)Rds2+RL]I :=R I . Cs o eq o the Phase Node (PN). The DC voltage across V is independent of L, R and C . If Cs s s When Q1/Q3 are on and Q2/Q4 are off, the circuit in Figure only the average load current is needed (as in average 12 is reduced to that of Figure 13 a). Here Rds1 is the on- current-mode control), this current sensing method will be resistance of the top MOSFET. The branches {(Rds1+RL), sufficient without any additional time-constant matching L} and {R , C }, are in parallel. The DC voltage across L and constraint. s S the DC current through C are both zero. There is no DC S In peak current-mode control, the voltage ripple on C is s voltage across R either. Therefore on average, the voltage s used as the modulating ramp. The V peak-to-peak Cs drop (Rds1+RL)I equals V . The DC inductor current can o Cs amplitude (denoted as ΔV ) directly affects the signal- Cs be sensed from V if (Rds1+RL) is known. to-noise ratio of the PWM operation. Small ΔV leads to Cs Cs lower signal-to-noise ratio and more jittery operation. When Q1/Q3 are off and Q2/Q4 are on, the equivalent Large ΔV leads to more circuit (power stage) sensitive Cs circuit of Figure 12 reduces to the sub-circuit in Figure operation. A good compromise is to make 13b). Here Rds2 is the channel resistance of the bottom ΔV ~R δI . Cs eq o MOSFET. In this case, the branch {R , C } is in parallel with s s {(Rds2+RL), L} and V =(Rds2+RL)I . Averaging over one Cs o The above condition holds if the following time-constants switching cycle, are made equal. L ≈ R C . s s R Vin eq Rds1 iL(t) L RL If Rds1=Rds2, then R = Rds1+ RL. For example, in the PN eq Cin application circuit, L=1.3µH, RL=1.56mΩ and Rs Cs Vo Rds1=Rds2=8mΩ , the time constant R C should be set VPN s s Cout Rload vC(t) as 136µs. If C =33nF, then R =4.12kΩ. s s Figure 13. a) Equivalent sub-circuit. www.semtech.com  2005 Semtech Corp. 20 SC2441 POWER MANAGEMENT Applications Information (Cont.) Setting the Current Limit R =11.8kΩ and R =6.36kΩ. s s1 When the voltage difference between CS1+(CS2+) and b) The required current limit I is less than I . R is LM LMcp s1 CS1- (CS2-) exceeds 50 mV, the top MOSFET will be deleted from Figure 14. R is given by s turned OFF and the bottom MOSFET will be turned ON to L R C = , limit the output inductor current. In the circuit of Figure s s R eq 12, the converter output current limit is R is obtained from s3 50mV I = . LMcp R s R eq I R + V = 50mV, LM eq O R s3 In the application circuit, R = 9.56mΩ so I = 5.23A. In eq LM Lastly R is computed from other applications, different current limits may be required. s2 The circuit in Figure 14 allows the user to set current-limit R R s3 s R = . s2 different from 50mV/R . R − R eq s3 s If the current limit is to be set to I =2.5A with V =1.2V LM o and C =33nF in the same example, then R =4.12 kΩ, s s Vin R =190 kΩ and R =4.21 kΩ. s3 s2 Q1 Vgs1 iL(t) L RL Remark 3: If the current limit I is lower than I , the LM LMcp PN Cin circuit designer will have the option to use MOSFET’s with Rs Rs1 Vo higher R to reduce the cost. As a result, R is increased ds(ON) eq Q2 Cs Cout Rload and I is reduced. Although the use of low-cost MOSFET’s LMcp Vgs2 vC(t) is always preferred, the current-limit setting technique described above allows quick adjustment on a well-tested Vbe3 Q3 prototype without the need to replace the power MOSFET’s. VPN Vbe4 Q4 Over Current Protection and Hiccup Mode 1 + Rs2 During start-up, the capacitor from the SS/EN pin to ground 2 - I SEN functions as a soft-start capacitor. After the converter starts Rs3 and enters regulation, the same capacitor operates as overload shutoff timing capacitor. As the load current increases, the cycle-by-cycle current-limit comparator will Figure 14. Circuit for setting current-limit different first limit the inductor current. Further increase in loading from 50mV/R eq will cause the output voltage (hence the feedback voltage) a) The required current limit I is higher than I . R is LM LMcp s3 to fall. If the feedback voltage falls to less than 70% of the deleted from Figure 14. R is given by s2 normal, the controller will shut off both the top and the L bottom MOSFET’s. Meanwhile an internal current source R C = , s2 s R eq (1.4µA) discharges the soft start capacitor C (C ) 32 33 connected to the SS/EN pin. R is obtained from s R s2 I R = 50mV, When the capacitor is discharged to 0.47V, a 2.3µA LM eq R s current source recharges the SS/EN capacitor and the R is then computed from controller re-initiates soft-start. If the overload persists, s1 the controller will shut down the converter as the soft R R s2 s R = . s1 start capacitor voltage exceeds 3.25V. The converter will R − R s s2 repeatedly start and shut off until it is no longer If the current limit is to be set to I =15A in the example LM overloaded. This hiccup mode of overload protection is a given in last section with C =33nF, then R =4.12kΩ, s s2  2005 Semtech Corp. 21 www.semtech.com SC2441 POWER MANAGEMENT Applications Information (Cont.) resistance may not be available as a standard value form of foldback current limiting. The following resistor. As a result, there will be a set error in the calculations estimate the average inductor current when converter output voltage. This non-random error is the converter output is shorted to the ground. caused by the feedback voltage divider ratio. It cannot be corrected by the feedback loop. a) The time taken to discharge the capacitor from 3.25V to 0.47V is The following table lists a few standard resistor (3.25 − 0.47)V combinations for realizing some commonly used output t = C . ssf 32 1.4µA voltages. If C = 0.1µF, t will then be 200ms. 32 ssf Vo (V) 0.6 0.9 15 .2 1. 15 .8 23 . 3. b) The soft-start time from 0.47V to 3.25V is (1-h)/h 0.2 0.8 12 .4 24 .6 5.6 (3.25 − 0.47)V Ro1 (Ohm) 200 806 1K .4K 22K .61K4K .02 5.62 t = C . ssr 32 2.3µA Ro2 (Ohm) 1K 1K 1K K 1 1K K 1K 1 If C = 0.1µF, t will then be 121ms. Note that during 32 ssr soft-start, the converter only starts switching when the Only the voltages in boldface can be precisely set with voltage at SS/EN exceeds 1.3V. standard 1% resistors. c) The effective start-up time is The input bias current of the error amplifier also causes (3.25 −1.3)V t = C . an error in the output voltage. The inverting input bias sso 32 2.3µA currents of error amplifiers 1 and 2 are –160nA and – 260nA respectively. Since the non-inverting input is biased The average inductor current is then to 0.5V, the percentage error in the second output voltage will be –100% · (0.26µA) · R R /[0.5 · (R +R )]. To o1 o2 o1 o2 Ω. keep this error below 0.2%, R < 4k t sso o2 I = I . Leff LMcp t + t ssf ssr Loop Compensation I = 0.27I and is independent of the soft start Leff LMcp The SC2441 uses current-mode control for both step-down capacitance. The converter will not overheat in hiccup. channels. Current-mode control is a dual-loop control system in which the inductor peak current is loosely Setting the Output Voltage controlled by the inner current-loop. The higher gain outer loop regulates the output voltage. Since the current loop The non-inverting inputs of the error amplifiers are makes the inductor appear as a current source, the complex internally biased to 0.5V voltage reference. A simple high-Q poles of the output LC networks is split into a voltage divider (R at top and R at bottom) sets the o1 o2 dominant pole determined by the output capacitor and converter output voltage. R can be expressed as a o2 the load resistance and a high frequency pole. This pole- function of the voltage feedback gain h=0.5/V and R o o1 splitting property of current-mode control greatly simplifies h loop compensation. R = R o2 o1. 1− h The inner current-loop is unstable (sub-harmonic oscillation) Once either R or R is chosen, the other can be calculated o1 o2 unless the inductor current up-slope is steeper than the for the desired output voltage V . Since the number of o inductor current down-slope. For stable operation above standard resistance values is limited, the calculated 50% duty-cycle, a compensation ramp is added to the www.semtech.com  2005 Semtech Corp. 22 SC2441 POWER MANAGEMENT Applications Information (Cont.) sensed-current. In the SC2441 the compensation ramp For the rated output current I , the first-order gain k is o is made duty-ratio dependent. The compensation ramp determined as is approximately ΔI o k = . 1.1D ΔV c I = De * 4.8µA. ramp Furthermore the transfer function from the voltage error The incremental slope of such current ramp is then amplifier output v to the converter output v can be 1.1D c o S = (1+1.1D)e f * 4.8µA. e s derived from Figure 15. s Once the inner current loop is stabilized, the output voltage 1+ V (s) s o z1 is then regulated with the outer voltage feedback loop. An := G (s) = kR , vc o s V (s) equivalent circuit of current-mode Buck converter is shown c 1+ s in Figure 15. p1 where the single dominant-pole is 1 s = p1 (R + R )C o oesr o and the zero associated with the output capacitor ESR is 1 s = . z1 R C oesr o The dominant-pole changes with the converter output load. k The controller transfer function (from the converter output v to the voltage error amplifier output v ) is o c s 1+ g h s m z2 C(s) = , s s(C + C ) 2 3 1+ s p2 where Figure 15. A simple model of current-mode buck converter 1 s = z2 The voltage transconductance error amplifier (in the R C 2 2 SC2441) has a g of 400µA/V. C , C and R of the m 2 3 2 and compensation network are to be determined for stable operation with optimized load transient response. 1 s = . p2 C C 2 3 R 2 The feedback gain h and the resistor values are determined C + C 2 3 using the equations given in the “Setting the Output Voltage” section with The loop transfer function is then 0.5 h = . V T(s)=G (s)C(s). o vc  2005 Semtech Corp. 23 www.semtech.com SC2441 POWER MANAGEMENT Applications Information (Cont.) P is a pole for suppressing high-frequency switching 2 noise. So P >> Z . To simplify design, one usually assumes 2 2 that C <