SEMTECH SC2434

SC2434 TriPhase Current Mode Controller with Power Good POWER MANAGEMENT Description Features ! 12V input The SC2434, a tri-phase, current mode controller is ! Input sensing current mode control designed to work with Semtech smart synchronous drivers, such as the SC1205, SC1206, and SC1207 to ! Selectable 2 or 3 phase operation provide the DC/DC converter solution for the most ! Precision, pulse by pulse phase current matching demanding Microprocessor applications. Input current ! Active drooping allows for best transient response ! Programmable internal oscillator to 1.5 MHz sensing is used to guarantee precision phase to phase ! Programmable DAC step size/offset allows compli- current matching using a single sense resistor on the input power line. This topology reduces the power loss ance with VRM9.0 and VRM9.2 and complexity associated with output current sense ! VID 11111 Inhibit (No CPU) methods. Multi phase operation allows significant ! Externally programmable soft-start ! 0% minimum duty cycle improves transient reduction in input/output ripple while enhancing response transient response. Two or three phase operation is selectable. The DAC step size and range are program- ! Cycle by cycle current limiting plus hiccup mable with external components thus allowing compliance ! Power good signal with new and emerging VID ranges. A novel approach Applications implements active droop to minimize output capacitors ! Intel Pentium-4 microprocessors during load transients. ! ! ! ! ! High performance desktop systems Typical Application Circuit L1 +12V_ATX R1 3m +12V 600nH + + + C5 C6 R2 D1 C4 C75 0.33uF C1 C2 C3 1uF 2200uF/16v 2200uF/16v 2200uF/16v 4.7uF 4.7uF 2R2 1N4148 M1 L2 VOUT R5 20 R4 1R 1 8 600nH DRN PGND R3 2 7 VCCVID_PWRGD(Open Collector Input) TG BG 2R2 3 6 D4 BST VS 4 5 1N4148 R6 C7 CO EN 1 1500uF/6.3V R29 M2 SM/R_1206 100 U1 C8 C11 C10 SC1205 1uF C9 1500uF/6.3V 1nF 2.2nF VID4 Differential C12 1uF C14 C15 C16 Pair +12V 1500uF/6.3V VID3 1uF 4.7uF R9 D2 C17 VID2 R8 1uF C76 0.33uF C18 NO POP 2R2 1N4148 M3 1500uF/6.3V VID1 L3 U2 VID0 1 20 R10 C19 VID4 VCC 1500uF/6.3V 2 19 1 8 1R 600nH VID3 BGOUT DRN PGND 2 7 +5V_ATX TG BG +5V 3 18 C13 3 6 D5 C20 VID2 OUT1 BST VS 10nF 4 5 1N4148 R11 1500uF/6.3V CO EN 4 17 1 VID1 OUT2 M4 SM/R_1206 5 16 U3 C21 VID0 OUT3 C23 1500uF/6.3V SC1205 6 15 C22 PGIN PC 1nF 2.2nF R13 7 14 C25 V_PULL_UP ERROUT AGND C24 1uF 5.1K 1500uF/6.3V 8 13 PGOUT OC- 9 12 +12V C26 FB OC+ 1500uF/6.3V PWR_GOOD 10 11 R14 D3 C27 OSCREF DACREF 1uF C77 0.33uF 2R2 1N4148 M5 C28 SC2434 R15 L4 1500uF/6.3V C29 R_COMP 1K 100nF R_OSC R_DAC R16 R_DRP 75K 31.6K 37.4K 1R C30 1 8 600nH 1500uF/6.3V DRN PGND 187K C31 2 7 TG BG C_COMP 470pF 3 6 D6 BST VS 4 5 1N4148 R17 C32 CO EN 18pF 1 1500uF/6.3V M6 SM/R_1206 U4 +5V C34 SC1205 C33 R_OS R_FB R19 R20 1nF 2.2nF PGND 750 1K 46.4K 10K C35 1uF Differential Pair AGND May 18, 2005 1 www.semtech.com + + + + + + + + + + + + SC2434 POWER MANAGEMENT PRELIMINARY Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Sm ymboMs aximu Unit IV nput DC Rail Voltage to GND 1V 8 IN AT mbient Temperature Range 0C to 70 ° A JT unction Temperature 0C to 125 ° J Thermal Resistance Junction to Case θ 2W 0 °C/ JC Thermal Resistance Junction to Ambient 6W 0 °C/ θ JA ST torage Temperature Range -C 65 to +150 ° STG LT ead Temperature (Soldering) 10 Sec. 3C 00 ° LEAD Electrical Characteristics Unless specified: V = +12V, T = 25°C, R = 37.4kΩ, R = 28.5kΩ. See Typical Application Circuit CC AMB DAC OSC Ps arameter Cn ondition Mp i Tx y Mt a Uni Chip_Supply IC Supply Voltage 12 0 141V IV C Supply Current =V10 2.0 151A m CC Reference Section BC andgap Output =5 4.7nF 1V . BG Source Impedance 6kΩ SV upply Rejection =5 10.0V ~ 14.0V .V mV/ CC VR ID Step =k 10 Ω, R =k 37.4 Ω 2V 5 m FB DAC TT emperature Stability 0°C <<5 70°C 0% . AMB VT oltage Accuracy 0°C <<8 70°C-8 0. +% 0. AMB Oscillator Section Frequency Range 30 00 1z 50 kH FV requency Accuracy =5 12.0V 60 7 75 5 8z 2 kH IN TT emperature Stability 0°C <<5 70°C ±% AMB Voltage Error Amplifier Input Offset Voltage ±V 5 m Input Offset Current 0A .1 µ OV pen Loop Gain 1V <<0 4V 9B d ERROUT PV SRR =0 9 - 14V 8B d CC OV utput Sink Current =5 1V 2A . m ERROUT OV utput Source Current =2 4V mA ERROUT UI nity Gain Bandwidth <6 100µA 1z . MH O SI lew Rate <0 100µA 1/ VµS O  2005 Semtech Corp. 2 www.semtech.com SC2434 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: V = +12V, T = 25°C, R = 37.4kΩ, R = 28.5kΩ. See Typical Application Circuit CC AMB DAC OSC Ps arameter Tn est Condition Mp i Tx y Mt a Uni Current Sense Amplifier AV mplifier Gain ( - - V)9 < 120mV 13 8. 17 9. 1V 9. V/ OC OC+ Input Offset Voltage, Input (V --V )<1V 204 m mV OC OC+ Referred CV MRR =9~1@ 4VD0 C 8B d ICM PV SRR =9~1@ 4VD0 C 8B d CC Input Common Mode Range V±V 0.3 CC Max Differential Signal/Current V -V 1V 20 m OC- OC+ Limit Threshold I, -Limit Delay Current limit activation to OUT1 6s 0 n OUT2 & OUT3 switching off Vcc UVLO Ramp-up Threshold 7V .5 Ramp-down Threshold 7V .25 Outputs (OUT1, OUT2, OUT3) MF ax Duty Cycle Per Phase=1 500kHz, PC pin floating 3% OSC F=7 500kHz, PC pin grounded 4% OSC OR utput Voltage = 10kΩ,5 high 2V . L R = 10kΩ,8 low 0. L R = 100kΩ,3 high 3V . L R = 100kΩ,2 low 0. L Logic Input (1) (2) VID Logic Threshold 02 .8 V VV ID Logic ImpedanceI5 nternal pull-up = 2.5 2kΩ Phase Control (2) Logic Threshold 02 .8 V It nternal Pull-up P5 C pin open circui 2V . Internal Pull-up Impedance 2k 5 Ω Power Good Signal Oh ff Leakage CurrentP2 WRGOOD = Logic hig µA PD ower Good Max Sink Current P< WRGOO04 .8V mA Power Good Threshold 0V .8 Notes: 1. If VIDs are left open, no external pull-up is required. When external pull-up is needed, use 3.3V. 2. Max logic input is recommended to be less than 5.5V.  2005 Semtech Corp. 3 www.semtech.com SC2434 POWER MANAGEMENT PRELIMINARY Pin Configuration Ordering Information Top View Temp. Range De evice Packag (T ) A (1) o SC2434SWTRS0 OIC-20 0 - 7 C VID4 VCC (1) o VID3 SC2434TSTRT0 SSOP-20 0 - 7 C BGOUT VID2 OUT1 (1,2) o SC2434SWTRTS0 OIC-20 0 - 7 C VID1 OUT2 (1,2) o SC2434TSTRTT0 SSOP-20 0 - 7 C VID0 OUT3 PGIN (3) PC SC2434EVB Evaluation Board ERROUT AGND Note: PGOUT OC- (1) Only available in tape and reel packaging. A reel FB OC+ contains 1000 devices for the SOIC-20 and 2500 devices OSCREF for the TSSOP-20 package. DACREF (2) Lead free package. Devices are fully WEEE and RoHS compliant. (3) Specify SOIC-20 or TSSOP-20 package. (20-Pin SOIC or TSSOP) Pin Descriptions Pe in#Pn in Nam Pin Functio 14VB ID MS 23 VID 32 VID 41 VID 50VB ID LS 6N PGI Power good input. Connect this pin to regulator output through a resistor divider. 7TE. RROU Error-amplifier output 8TP. GOU Power good output signal (open collector) 9BF. Error-amplifier inverting input 1F 0O. SCRE Oscillator frequency setting 1F 1D. ACRE DAC current setting 1+ 2O. C Supply input current sense, positive input 1- 3O. C Supply input current sense, negative input 1D 4A. GN Analog ground pin 1C 5 P Phase control. Leave it floating or high for 3 phase operaton. Ground it for 2 phase operation. 13 6 OUT PWM output for phase 3. When PC pin is grounded OUT3 is disabled. 12 7O. UT PWM output for phase 2 11 8O. UT PWM output for phase 1 1T 9B. GOU Bandgap reference 2C 0V. C Chip positive supply  2005 Semtech Corp. 4 www.semtech.com SC2434 POWER MANAGEMENT Block Diagram Applications Information- Output Voltage Output Voltage Unless specified: 0 = GND; 1 = High (or Floating). T = 25°C, V = 12V, 3-Phase operation . V A CC CCCORE V3 ID4 V2 ID V1 ID V0 ID V) ID (VDC 1 1 1 1 1 Output Off 1 1 1 1 0 1.1 1 1 1 0 1 1.125 1 1 1 0 0 1.15 1 1 0 1 1 1.175 1 1 0 1 0 1.2 1 1 0 0 1 1.225 1 1 0 0 0 1.25 1 0 1 1 1 1.275 1 0 1 1 0 1.3 1 0 1 0 1 1.325 1 0 1 0 0 1.35 1 0 0 1 1 1.375 1 0 0 1 0 1.4 1 0 0 0 1 1.425 1 0 0 0 0 1.45 0 1 1 1 1 1.475 0 1 1 1 0 1.5 0 1 1 0 1 1.525 0 1 1 0 0 1.55 0 1 0 1 1 1.575 0 1 0 1 0 1.6 0 1 0 0 1 1.625 0 1 0 0 0 1.65 0 0 1 1 1 1.675 0 0 1 1 0 1.7 0 0 1 0 1 1.725 0 0 1 0 0 1.75 0 0 0 1 1 1.775 0 0 0 1 0 1.8 0 0 0 0 1 1.825 0 0 0 0 0 1.85  2005 Semtech Corp. 5 www.semtech.com SC2434 POWER MANAGEMENT PRELIMINARY Applications Information Theory of Operation Flexible VID The simplified voltage regulator (VR) based on SC2434 The VID circuitry reads the 5 bit digital command and is depicted in Fig. 1. The key timing chart is also shown converts it into a current flowing into the inverting input in the same picture. The 12V input power passes through pin of the error amplifier. The output current of the DAC the input filter establishing the input power rail. The cur- produces a voltage offset on the feedback resistor, R FB rent sensing resistor located at positive input rail moni- (see Fig. 1), which changes the set point of the converter tors the top FET currents of all the phases. An internal output voltage for different VID combinations. differential amplifier amplifies the voltage across the current sensing resistor. The output of the current am- Active Voltage Positioning plifier and an internally generated saw tooth ramp signal By programming the gain of the error amplifier, one can are added together to be the PWM carrier signal. This easily and accurately implement adaptive output voltage signal meets the output of the error amplifier at the pulse positioning. This is equivalent to programming the VR width modulator (PWM). The output of the PWM is then output impedance in an active manner. The advantage divided into three phases alternately to be the inputs of of allowing the VR certain output impedance (typically the synchronous drivers. 1~3 mOhm) is that one can use a minimum amount of high quality output bulk capacitors to meet the voltage Feedback and Regulation regulation requirement. Hence, the cost and the size of The feedback circuitry reads the regulator output volt- the VR solution can be significantly reduced. age and compares it with an accurately trimmed bandgap voltage reference, which is 1.5V with less then 0.8% tol- erance. The compensation network allows optimization of the control-loop for system stability and fast transient responses. SC2434 Fig.1 - The simplified voltage regulator based on SC2434.  2005 Semtech Corp. 6 www.semtech.com SC2434 POWER MANAGEMENT Applications Information (Cont.) Input Phase Current Balance voltage Input One of the fundamental challenges for multi-phase solu- voltage tions is to balance the phase currents to achieve the best possible electrical and thermal performance. It is quite Output easy to use the SC2434 control topology to achieve very Output voltage voltage good phase current balance. Since the current of all the phases passes through the same current sensing compo- nent and the same current current of all the phases are well balanced on pulse by pulse basis. This control results in small and even output voltage ripple and evenly distrib- voltage. Fig. 3 shows the measured waveforms of power uted thermal load. Additional advantages of using input up and power down. current mode are less sensing circuitry, less IC pins, and Fig. 3 - Shows the measured waveforms of power up and power less power loss on the sensing resistor comparing sensing down. inductor current on the output side. Fig. 2 shows the wave- form of inductor currents under heavy load conditions, Over Current Protection (OCP) which clearly demonstrates the excellent performance of When sensed current signal across the differential input SC2434 on balancing the phase current. of the current amplifier exceeds 120mV typical value, OCP circuitry will pull down the error amplifier output voltage and also discharge the soft start capacitor. The pull down of the error amplifier will not be released until the soft capacitor is discharged bellow 0.3V. At this point, the PWM outputs are reactivated and the soft start capacitor begins to charge up again through the internal 6 Kohm resistor. The VR will try to bring up the output voltage until the over load or short circuit condition is removed. The hiccup mode OCP can significantly reduce the average out- put current under overload conditions. The hiccup timing is controlled by the soft start time constant. Please also notice that the OCP threshold has less than 10% toler- ance, hence, the onset of the OCP is quite accurate. The advantage is that the VR designer does not need to re- serve big thermal headroom to deal with the worst-case operation when load is over 100% but the OCP has yet not Fig. 2 - Measured inductor currents of SC2434 3-phase VR been triggered. An RC filter is needed to filter out the under heavy load condition. leading edge voltage spike across the current sensing re- sistor to prevent false triggering of the OCP. The time con- Under Voltage Lockout (UVLO) stant should be around 200nS (please see application During power up, when UVLO circuitry detects the chip schematic). supply (Vcc) be bigger than 7.5V (typical value with proper hysteresis), the bandgap voltage reference starts to charge the external soft start capacitor through a 6 Kohm inter- Power Good SC2434 features a power good input and an open collec- nal resistor. When soft start capacitor voltage reaches tor power good output. The VR output voltage is scaled 0.5V, the output voltage starts to build up which follows the exponential voltage profile of the soft start capacitor. down through a resistive divider and this signal is fed into The soft start process ensures that the output voltage will PGIN (power good input) pin. The scaled VR output volt- have no over shoot. During power down, UVLO will dis- age has to be bigger than 0.8V otherwise the power good output pin is pulled down. A 5 Kohm pull-up resistor and charge the soft start capacitor to shut of the PWM. The a 0.1uF capacitor to ground are recommended to prevent load will absorb the energy in the output filter and no reso- nance will occur. Hence, the CPU will not see any negative false trigger during logic transition.  2005 Semtech Corp. 7 www.semtech.com SC2434 POWER MANAGEMENT PRELIMINARY Applications Information (Cont.) Program The Controller full-load operation be 75% of the given OCP threshold: Please refer to Fig. 1 and the application schematics in 75% "120mV this data sheet for the discussion. The resistor from pin R sense I 10 to ground, R , programs the switching frequency. The peak OSC resistor from pin 11 to ground, R , sets the DAC current where I is the peak current of the output inductor. Since DAC peak step size. The resistors, R , R , and R set the DAC the choice of sensing resistor values are limited, typically 3 FB OS DRP step size, the output voltage set point, and the droop, mOhm, 4 mOhm, or 5 mOhm, it is recommended to choose respectively. the sensing resistor with a bigger value than that was cal- culated, and to use a resistive divider to get the equiva- MathCAD programs are available to calculate the required lent R value. The two attenuation resistors should sense parameters upon request. have value of 20 Ohm in parallel. A filter capacitor of 10nF is also needed to be across the OC+ and OC- pins of Programming The Switching Frequency the controller IC. Please refer the application circuit sche- The oscillator frequency can be selected first by setting the matic. value of R as given below: OSC . Programming The Dynamic (Active) Droop 750 KHz . . R 28.5 KΩ OSC F To optimize transient responses, the SC2434 actively regu- osc lates output voltage as a function of output current. At The per phase switching frequency is 1/3 of the oscilla- zero current the output is positioned to the upper limit of tor frequency in three-phase mode. It is recommended the regulation window. As the load increases, the output that per phase switching frequency is 200~300KHz for “droops” towards the lower limit. This makes optimum good trade off of efficiency vs. transient responses. use of the output voltage error band, yielding minimum output capacitor size and cost. Programming The DAC Step Size The SC2434 allows programming of the output voltage The droop is adjusted by setting the DC gain of the error and the DAC step size by selecting external resistors. The amplifier. This is done by choosing the resistor from the LSB of the DAC current is given by: ERROUT pin to the FB pin (R ) of the controller. While DRP V 1 bg the optimum value of R may be derived experimentally, DRP . I DAC_LSB 16 R the following equation can provide the first order calcula- DAC tion for given droop slope: where V is the trimmed voltage reference (V = 1.5V) bg bg . . R R G ∆I and R is the resistor from pin 11 to ground. For the FB sense ca out DAC . R drp given VID step size (25mV for VRM9.0 and VRM9.2 speci- N ∆V out phase fications), the feedback resistor can be calculated accord- where R is the current sensing resistance after taken sense ing to the LSB of DAC current: into account of attenuation, and G is the gain of the ca VID step current amplifier while N is number of phases being phase R FB used. I DAC_LSB The above two equations are for choosing R and R Any output interconnection impedance not within the feed- DAC FB simultaneously. The advantage of this method is that new back loop can contribute to additional drooping. This ef- VID step size can be accommodated by modifying external fect has to be taken into account. Usually, when testing components while maintaining the required precision. the regulation at different CPU pins, the results may vary slightly by same token. Choose Current Sensing Resistor According To The Threshold Of OCP It is important to use surface mount current sensing resis- tor to minimize the parasitic inductance for accurate cor- The SC2434 controller has an over current protection (OCP) relation between the above equation and the test results. threshold of 120mV. The normal practice is to let the peak voltage across the sensing resistor corresponding to This is because the inductive contribution, which may also  2005 Semtech Corp. 8 www.semtech.com SC2434 POWER MANAGEMENT Applications Information (Cont.) . Loop() s, R H () sR , H () s be caused by layout inductances, may alter the PWM p_ccm c comparator trip point. The value of R may have to be DRP adjusted to compensate for such parasitic effects. It must be noted that the current amplifier gain is quite 1/(R*C) precise, with greater than 80dB of Common Mode POWER -1 Vin/( VR*N phase) STAGE Rejection Ratio (CMRR). Thus the droop accuracy is Fsw/2 Power Stage 1/(ESRC) primarily based upon external components tolerances. By Rdrp -2 Rdrp/R fb employing 1% current sensing element with very low Pol e Compensator temperature coefficient, this topology is proved to be the Ccomp Rcomp 1/(R*C) Ccomp Zero best comparing the schemes of using R sensing and Vout dson Copam -1 using inductor winding resistance sensing. The accurate Loop Gain 0dB Err_Amp - drooping translates into minimum amount output bulk Fsw/2 Verror + capacitor needed to meet the voltage regulation specifica- 0 -2 tions and the least system cost. Programming The DC Level Of The Output Voltage Kirchoff’s current law can be applied to the error amplifier’s inverting input (see Fig. 1) to calculate R , OS Fig. 4 - Loop gain and compensation of the current mode con- the DC level setting resistor. For given output voltage set troller. point and VID setting, the resistance can be calculated by: where C is the equivalent internal capacitor across the opam error amplifier output and the inverting input with a value V bg of 11pF. R os V V V V set bg eo bg . N I DAC_STEP DAC_LSB The power stage transfer function under continuous R R FB drp conduction mode can be approximated by: where N is the number of VID steps down from the . . 1sC R DAC_STEP c . H () sR , G highest set point (VID=00000). For example, when VID p_ccm pwm 2 s s [4:1]=00100, N = 4. V is the error amplifier . . . . DAC_STEP EO (1sR C) 1 1.5 . . output voltage and, as a first approximation, it is equal to π F π F s s 1..7V. Again, V = Precision Reference Voltage = 1.5V. BG The final value of R may need to be fine tuned OS where G is the low frequency gain of the power stage. experimentally after the droop resistor has been chosen. PWM The power stage has an ESR zero, a dominant pole at low frequency, and a pair of complex pole located at one Control Loop Compensation half of the switching frequency. The parameter used here The current mode control yields a power supply easy to are defined as below: compensate because the power stage has first order (single C = output bulk capacitance pole) behavior. The SC2434 provides internal slope R = load resistance compensation to avoid sub harmonic oscillation of the R = ESR of output bulk capacitor current loop. The added ramp signal has 300mV peak-to- C F = switching frequency peak amplitude and the ramp frequency is as same as SW the oscillator frequency. The PWM gain is defined as: As depicted in Fig. 4, the gain for the voltage feedback R ! N phase loop can be expressed as a product of the power stage G pw m R G gain and the compensator gain: sense· CA  2005 Semtech Corp. 9 www.semtech.com SC2434 POWER MANAGEMENT PRELIMINARY Applications Information (Cont.) The compensator transfer function has two poles and one L L Loop oop oop- - -G G Ga a ai i in n n ( ( (d d dB B B) ) ) 40 40 40 zero: 20 20 20 s m m ma a ag g g_L _L _Loop oop oop () () () i i i ,,, R R R 1 0 0 0 0 0 0 R ω drp z . H () s 20 20 20 c R s s FB . 1 1 40 40 40 3 3 3 4 4 4 5 5 5 6 6 6 ω ω ... ... ... ... 100 100 100 1 1 1 10 10 10 1 1 1 10 10 10 1 1 1 10 10 10 1 1 1 10 10 10 p1 p2 F F F i i i L Lo oopG opGa ai in n ( (D De eg gr re ee e) ) 180 180 To optimize the transient responses, it is recommended 90 90 that: p ph has ase_ e_L Lo oo op p() () i i ,, R R 0 0 · To use the first compensator pole to cancel the power 90 90 stage ESR zero; · To place the compensator zero at one half of the 180 180 3 3 3 4 4 4 5 5 5 6 6 6 ... ... ... ... 100 100 100 1 1 1 10 10 10 1 1 1 10 10 10 1 1 1 10 10 10 1 1 1 10 10 10 F F i i switching frequency; · And to place the second compensator pole at high Fig. 5 - Loop gain Bode plot based on control loop model. frequency. The Bode plots based this model and those obtained from experiment are depicted in Fig. 5 and Fig. 6, respectively. It can be seen that the model agrees well with the experiment. The control model provides us physical insight of the loop dynamics and helps the designer to achieve good transient responses and system stability. Here are few comments: · The loop crossover frequency (0dB frequency) should be lower than one fifth (20%) of the switch frequency to avoid noise pick up and the phase lag introduced by the complex pole located at one half of the switching frequency; · A >20KHz crossover frequency is adequate to assure good transient response when the VR output impedance, or droop impedance, is programmed to be equal to the output capacitor ESR. The ESR frequency for the output bulk capacitor is usually less Fig. 6 - Measured loop gain Bode plots. than 20KHz, and beyond that frequency the capacitor behaves like a resistor up to few hundred KHz, which is desired for dynamic droop. There is no point to demand the control loop to have much higher crossover frequency beyond the ESR zero frequency.  2005 Semtech Corp. 10 www.semtech.com SC2434 POWER MANAGEMENT Applications Information (Cont.) PCB Layout Consideration Good layout is necessary for successful implementation of the SC2434 based 3 tri-phase topology. There are few general rules: · Reserve enough PCB space for the power supply (1.2~1.5 square inch for every 10A of load current); · Place enough high frequency ceramic capacitors inside and around the CPU socket (please follow CPU manufacture’s decoupling guideline); · Place bulk output capacitors around the CPU socket as uniformly as possible. The connection copper between these capacitors and the CPU socket must be short and wide to minimize inductance and resistance; · Always place the high power parts first; · Always use a ground plane or ground planes; · Always try to minimize the stray inductance of the high pulsating current loop which is formed by input capacitors and the MOSFET half-bridges. The following layout guideline gives details on how to achieve a good layout: · Input filter should contain mixed electrolytic capacitors and MLC capacitors. For every 20A of load current, use about 10uF of MLC caps. Put MLC caps close to current sensing resistor; · Use surface mount current sensing resistor (typically 3~5 mOhm in surface mount package with low temperature coefficient and low package inductance, typically less than 0.3nH); · Try to minimize the stray inductance from the current sensing resistor to the drains of the top FETs by using wide trace (>0.5” wide and no more than 3” long). This trace can run on inner1 layer, for example, if the inner2 layer is the ground plane, assuming the FETs are on the top layer. This arrangement forms so called strip line structure for the pulsating power current, which yields least amount of stray inductance. The concept is depicted in Fig. 7; · Keep the layout as electrically symmetrical as possible, as shown in Fig. 8, to avoid very uneven stray inductance from the sensing resistor to the drains of the top FETs; · Use a pair of closely paralleled traces to pick up the sensing voltage across the sensing resistor. The sensing traces server as differential input to the OC+ and OC- pins of the SC2434 controller. These traces should run on a routing layer (e.g., bottom layer for 4 layer PCB case) to avoid picking up strong AC magnetic field due to power current flow. In this case, the differential sensing traces are shielded by the ground layer. The filter cap across the OC+ and OC- pins should be placed as close as possible to the controller. Pay close attention that never allow power current flowing on or running close by the sensing traces. Please see Fig. 8; · Separate power ground from analog ground to prevent power current from running over the analog ground plane. The SC2434 controller should be placed on the quite analog ground area. The analog ground should be single- point connected to the PGND near the output capacitor or the CPU socket to provide best possible ground sense. Refer to the application schematics for those components should be connected directly to the AGND (Vcc decoupling caps, cap on BGOUT pin, resistors on OSCREF pin, DACREF pin, FB pin, and PGIN pin). Rsense MLC SD S D TOP FET BOT FET VIA VIA Ground Plane Fig. 7 - Use MLC capacitors and strip line structure to minimize the stray inductance for the switching current loop.  2005 Semtech Corp. 11 www.semtech.com SC2434 POWER MANAGEMENT PRELIMINARY Applications Information (Cont.) Fig. 8 - Layout concept for input current sensing: (a) use MLC input capacitors; (b) minimize inductance; (c) keep electrical symmetry; and (d) use differential sensing traces. A Reference Design Example For Intel Pentium IV Processor Brief specifications of this design are listed below: • V =12V in • V =1.725V +/- 25mV at 0A load out • V droop slope is 1.5 mOhm out • V tolerance is +/-25mV for all load conditions out • I = 60A max out • VID [4:0] = 00100 The schematic is shown on the cover page of this data sheet.  2005 Semtech Corp. 12 www.semtech.com SC2434 POWER MANAGEMENT Bill of Materials - Reference Design I. temQe tyRe eferencV. aluDe escription/Part No Pr ackag Vendo 11CF _COMP4T 7p13 0V, X7R,MLCC,VJ603Y470KXXA 0Y 60 VISHA 21CF 10T .33u25 5V, X7R,MLCC,VJ805Y334KXXA 0Y 80 VISHA 33CF 2,C3,C42p 200u1/ 5V Al. Elec. ca CPCYL/D.400 Sanyo LS.200/.034 48 C5,C9,C13,1D uF15 6V, Y5V,MLCC,PCC1849CT-N 0c 80 Panasoni C15,C18, C26,C30,C38 53CF 6,C7,C164D .7u16 6V, Y5V,MLCC,PCC1900CT-N 1c 20 Panasoni 621, C8,C10,C141Z 500uF6/ .3V Al. Cap Rybucon MB CPCYL/D.325 Rubicon C19,C20,C22, LS.125/.034 C23,C27,C28, C31,C33,C35 73CF 11,C24,C361T n13 6V, X7R,MLCC,VJ603Y102KXXA 0Y 60 VISHA 83CF 12,C25,C372T .2n55 0V, X7R,MLCC,VJ805Y222KXXA 0Y 80 VISHA 92CF 17,C290T .33u25 5V, X7R,MLCC,VJ803Y334KXXA 0Y 80 VISHA 111 0CF 21T 0n13 0V, X7R,MLCC,VJ603Y103KXXA 0Y 60 VISHA 11 1CF 321T 00n13 6V, X7R,MLCC,VJ603Y104KXXA 0Y 60 VISHA 114 2CF 34T 70p13 0V, X7R,MLCC,VJ603Y471KXXA 0Y 60 VISHA 16 3 D1,D2,D3,D4,3D A3C 0V SM Schottly DL4148MSCT-NDY O213A DIGI-KE D5,D6 14 4LH 1,L2,L3,L468 38n60 38nH, 20A , Inductor TTIF1305-63Io N/L500/W400/.1 Falc 13 5ML 1,M3,M5FT DB6036BMB OSFE Td O-263A Fairchil 12 6ML 2,M4FT DB7045MB OSFE Td O-263A Fairchil 11 7ML 6FT DP7045MB OSFE Td O-263A Fairchil 11 8RK _COMP2F 9.4S3 M 1% CRCW06032942 0Y 60 VISHA 11 9RK _DAC3F 7.4S3 M 1% CRCW06033742 0Y 60 VISHA 21 0RK _DRP1F 87S3 M 1% CRCW06031873 0Y 60 VISHA 21 1RK _FB1F 0.0S3 M 1% CRCW06031002 0Y 60 VISHA 21 2RK _OS4F 6.4S3 M 1% CRCW06034642 0Y 60 VISHA 21 3RK _OSC3F 1.6S3 M 1% CRCW06033162 0Y 60 VISHA 21 4Rm 1 3WS2 M Sensing R 1% RL7520 2C 51 CYNTE 24 5R2 2,R5,R8,R132F RS3 M 1% CRCW06032R2 0Y 60 VISHA 21 6R0 3 2FS3 M 1% CRCW060320R0 0Y 60 VISHA 23 7R0 4,R10,R151F RS3 M 1% CRCW060331R0 0Y 60 VISHA 21 8R0 6 1F 0S3 M 1% CRCW06031000 0Y 60 VISHA 23 9R0 7,R11,R161F RS6 M 1% CRCW12061R0 1Y 20 VISHA  2005 Semtech Corp. 13 www.semtech.com SC2434 POWER MANAGEMENT PRELIMINARY Bill of Materials - Reference Design (Cont.) I. temQe tyRe eferencV. aluDe escription/Part No Pr ackag Vendo 31 0RP 9NF O POS3 M 1% CRCW06031R0 0Y 60 VISHA 31 1RK 125F .1S3 M 1% CRCW06035111 0Y 60 VISHA 32 2RK 14,R181F .0S3 M 1% CRCW06031001 0Y 60 VISHA 31 3R0 177F 5S3 M 1% CRCW06037500 0Y 60 VISHA 33 4U5 1, U3, U4Sr C120D8 ual FET Drive SH OIC- SEMTEC 31 5U4 2Sr C243 Tri-Phase Current Mode Controlle SOIC-20 or SEMTECH w/ Power Good TSSOP-20 Note 1: Magnetic Cool Mu 77041, 5 turns AWG #16 (800nH@0A, 600nH@25A)  2005 Semtech Corp. 14 www.semtech.com SC2434 POWER MANAGEMENT Applications Information (Cont.) Typical Performance Of The Reference Design The reference design implemented 1.5mOhm output droop impedance as shown in Fig. 9. Load Line (Vin=12V, VID=00100) 1.76 1.74 1.72 Vo 1.7 Spec_H 1.68 Spec_L 1.66 1.64 1.62 1.6 0 10 20 3040 5060 I (A) Fig. 9 - Measured output drooping characteristics of the 60A design. The efficiency of the design is depends on the MOSFET being used and thermal management requirements of controlling the PCB temperature and the MOSFET junction temperature. The following efficiency curve is corresponding to 4mOhm bottom FET, while the top FET has 12 mOhm Rdson. Efficency (%) 95.00 90.00 85.00 80.00 75.00 70.00 65.00 0 102030 40506070 I_out(A) Fig. 10 - Typical efficiency curve for 12 mOhm top FETs and 4 Ohm bottom FETs.  2005 Semtech Corp. 15 www.semtech.com Vo(V) SC2434 POWER MANAGEMENT PRELIMINARY Applications Information (Cont.) The typical phase node voltage and the output voltage ripple waveform is shown in Fig. 11 under 60A full load operation, where one can see the output ripple is very small and even with a frequency three times of the switching frequency. Fig. 11 - The typical phase node voltage and the output voltage ripple waveform under 60A full load operation. The typical gate waveform for the top and bottom MOSFETs is also shown here, well-controlled dead time is demonstrated which ensures high efficiency operation of the VR. Ch2: HS Gate Ch3: Phase Node Ch4: LS Gate Fig. 12 - The typical gate waveform for the top and bottom MOSFETs.  2005 Semtech Corp. 16 www.semtech.com SC2434 POWER MANAGEMENT Applications Information (Cont.) The transient response for a maximum load step changes (10A to 60A) is shown in Fig. 14, where one can see that accurate drooping will help to reduce the amount of output capacitance needed. Please notice that using more multilayer ceramic capacitors for better high frequency decoupling can reduce the narrow voltage spikes. Output Voltage Load Current Fig. 13 - Transient response and the test condition: Step Load from 10A to 60A Output Capacitors: 14 units of 560uF OSCON caps, 38 units of 10uF ceramic caps Ch1: Output Voltage Ch4: Output Current (1A = 27.5mV di/dt = 370A/uS) Meet Intel P-4 spec  2005 Semtech Corp. 17 www.semtech.com SC2434 POWER MANAGEMENT PRELIMINARY Outline Drawing - TSSOP-20 DIMENSIONS INCHES MILLIMETERS A DIM D e MIN NOM MAX MIN NOM MAX - - - - A .047 1.20 N A1 .002 - .006 0.05 - 0.15 .031 - .042 0.80 - 1.05 A2 2X E/2 - - b .007 .012 0.19 0.30 c - - .003 .007 0.09 0.20 E1 D .251 .255 .259 6.40 6.50 6.60 E .169 .173 4.30 4.40 4.50 E1 .177 PIN 1 E .252 BSC 6.40 BSC INDICATOR e .026 BSC 0.65 BSC L .018 .024 .030 0.45 0.60 0.75 L1 (.039) (1.0) ccc C 1 2 3 e/2 N 20 20 2X N/2 TIPS - - 01 0° 8° 0° 8° B aaa .004 0.10 bbb .004 0.10 ccc .008 0.20 D aaa C A2 A SEATING PLANE H C A1 bxN c bbb C A-B D GAGE PLANE 0.25 L 01 (L1) DETAIL A SEE DETAIL A SIDE VIEW NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS - A - AND -B - TO BE DETERMINED AT DATUM PLANE -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AC. Land Pattern - TSSOP-20 X DIMENSIONS DIM INCHES MILLIMETERS (.222) (5.65) C G .161 4.10 (C) G Z P .026 0.65 X .016 0.40 Y .061 1.55 Y Z .283 7.20 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.  2005 Semtech Corp. 18 www.semtech.com SC2434 POWER MANAGEMENT Outline Drawing - SOIC-20 DIMENSIONS A D INCHES MILLIMETERS e N DIM MIN NOM MAX MIN NOM MAX - - A .093 .104 2.35 2.65 - - A1 .004 .012 0.10 0.30 A2 .081 - .100 2.05 - 2.55 2X E/2 b .012 - .020 0.31 - 0.51 c .008 - .013 0.20 - 0.33 D .500 .504 .508 12.70 12.80 12.90 E1 .291 .295 .299 7.40 7.50 7.60 E1 E E .406 BSC 10.30 BSC e .050 BSC 1.27 BSC h .010 - .030 0.25 - 0.75 - - L .016 .041 0.40 1.04 (.041) (1.04) L1 N 20 20 01 0° - 8° 0° - 8° 13 2 ccc C aaa .004 0.10 2X N/2 TIPS bbb .010 0.25 e/2 ccc .013 0.33 B D h aaa C A2 A h SEATING H PLANE bxN A1 C bbb C A-B D c GAGE PLANE 0.25 L 01 (L1) SEE DETAIL A SIDE VIEW DETAIL A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A - AND -B - TO BE DETERMINED AT DATUM PLANE -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-013, VARIATION AC. Land Pattern - SOIC-20 X DIMENSIONS DIM INCHES MILLIMETERS (.362) (9.20) C (C) G Z G .276 7.00 P .050 1.27 X .024 0.60 Y .087 2.20 Z .449 11.40 Y P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A, RLP NO. 307A. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2005 Semtech Corp. 19 www.semtech.com