SEMTECH SC183C

SC183C 2.5MHz, 2A Synchronous Step-Down Regulator POWER MANAGEMENT Features Description The SC183C is a 2A synchronous step-down regulator  V Range: 2.9 – 5.5V IN designed to operate with an input voltage range of 2.9 to  V Options: 0.8 - 3.3V OUT 5.5 Volts. The device offers fifteen pre-determined outputs  Up to 2A Output Current voltages via four control pins programmable from 0.8 to  Ultra-Small Footprint, <1mm Height Solution 3.3 Volts. The control pins allow for on-the-fly voltage  2.5MHz Switching Frequency changes, enabling system designers to implement  Efficiency Up to 93% dynamic power savings. The SC183C is also capable of adjusting output voltage via an external resistor divider.  Low Output Noise Across Load Range  Excellent Transient Response The device operates with a fixed 2.5MHz oscillator fre-  Start Up into Pre-Bias Output quency, allowing the use of small surface mount external  100% Duty-Cycle Low Dropout Operation components.  <1µA Shutdown Current  Internal Soft Start Connecting CTL0 — CTL3 to logic low forces the device into shutdown mode reducing the supply current to less  Input Under-Voltage Lockout than 1µA. Connecting any of the control pins to logic  Output Over-Voltage, Current Limit Protection high enables the converter and sets the output voltage  Over-Temperature Protection according to Table 1. Other features include under-  Adjustable Output Voltage voltage lockout, soft-start to limit in-rush current, and  3mm x 3mm x 0.6mm thermally enhanced over-temperature protection. MLPQ-UT16 package  Pb-free, Halogen free, and RoHS/WEEE compliant The SC183C is available in a thermally-enhanced, 3mm x 3mm x 0.6mm MLPQ-UT16 package. Applications  Office Automation and Computing  Set-Top Box  LCD TV  Network Cards  Printer Typical Application Circuit L 1.0µH V V LX PVIN OUT IN 1.50V / 2.0A C IN SC183C C R OUT 10µF AVIN 22µF 10 VOUT AVIN C AVIN 1µF CTL0 CTL0 CTL1 CTL1 CTL2 CTL2 PGND CTL3 CTL3 AGND November 19, 2010 SC183C Pin Configuration Ordering Information Device Package (2)(3) SC183CULTRT 3mm x 3mm x 0.6mm MLPQ-UT16 (4) SC183CEVB Evaluation Board 16 15 14 13 Notes: (1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB 1 12 PGND PVIN with thermal vias under the exposed pad per JESD51 standards. TOP VIEW (2) Available in tape and reel only. A reel contains 3,000 devices. (3) Device is Pb-free, Halogen free, and RoHS/WEEE compliant. 2 11 PGND PVIN (4) Please specify the VOUT when ordering. VOUT AGND 3 10 T 4 9 NC AVIN 5 6 7 8 3mm x 3mm x 0.6mm MLPQ-UT16 Table 1 – Output Voltage Settings (1) θ = 40°C/W JA CTL3 CTL2 CTL1 CTL0 Output Voltage 0 0 0 0 Shutdown 0 0 0 1 0.80 Marking Information 0 0 1 0 1.00 0 0 1 1 1.025 0 1 0 0 1.05 0 1 0 1 1.20 0 1 1 0 1.25 0 1 1 1 1.30 1 0 0 0 1.50 1 0 0 1 1.80 1 0 1 0 2.20 1 0 1 1 2.50 Marking for 3mm x 3mm MLPQ-UT 16 Lead Package: yyww = Datecode (Example: 0852) 1 1 0 0 2.60 xxxx = Semtech Lot number (Example: E901) 1 1 0 1 2.80 1 1 1 0 3.00 1 1 1 1 3.30 © 2010 Semtech Corp. www.semtech.com 2 LX CTL0 LX CTL1 LX CTL2 PGND CTL3 SC183C Recommended Operating Conditions Absolute Maximum Ratings Supply Voltage PVIN and AVIN …………………… 2.9 to 5.5V PVIN and AVIN Supply Voltages ………………… -0.3 to 6.0V Maximum Output Current ………………………………… 2.0A LX Voltage ………….. -1 to PVIN+1V, -3V (20ns Max), 6V Max Input Capacitor ………………………………………… 10uF VOUT Voltage …………………………… -0.3 to AVIN+0.3V Output Capacitor ……………………………………… 22uF CTLx Voltage …………………………… -0.3 to AVIN+0.3V Output Inductor ……………………………………… 2.2uH Operating Junction Temperature ….…….….… -40 to +125 °C Peak IR Reflow Temperature …………………………. 260°C (2) Thermal Information ESD Protection Level …………………………………. 2.5kV (1) Thermal Resistance, Junction to Ambient ………… 40 °C/W Maximum Junction Temperature …………………… +150 °C Storage Temperature Range ………………… -65 to +150 °C Exceeding the absolute maximum ratings may result in permanent damage to the device and/or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. (2) Tested according to JEDEC standard JESD22-A114-B. Electrical Characteristics Unless specified: PVIN= AVIN= 5.0V, VOUT= 1.50V, C = 10µF, C = 22µF, L= 2.2µH, -40°C≤ T ≤ +125 °C. Unless otherwise noted typical values are IN OUT J T = +25 °C. A Parameter Symbol Conditions Min Typ Max Units Rising AVIN, PVIN=AVIN 2.70 2.80 2.90 V Under-Voltage Lockout UVLO Hysteresis 240 300 mV (1) Output Voltage Tolerance ΔV PVIN= AVIN= 2.9 to 5.5V; I =0A -2.0 +2.0 % OUT OUT Current Limit I Peak LX current 2.5 3.0 3.75 A LIMIT Supply Current I No load 10 mA Q Shutdown Current I CTL = AGND 1 10 µA SHDN 0-3 I = 100mA, T = 25 °C 0.10 0.125 LX J High Side Switch Resistance R DSON_P I = 100mA, T = 125 °C 0.14 0.18 LX J Ω I = -100mA, T = 25 °C 0.09 0.115 LX J (2) Low Side Switch Resistance R DSON_N I = -100mA, T = 125 °C 0.125 0.160 LX J PVIN= AVIN= 5.5V; LX= 0V; CTL = AGND 1 10 0-3 (2) L Leakage Current I µA X LK(LX) PVIN= AVIN= 5.5V; LX= 5.0V; CTL = AGND -10 -1 0-3 Load Regulation ΔV PVIN= AVIN= 5.0V; I =1mA to 2A ±0.5 ±1.0 % LOAD-REG OUT Oscillator Frequency f 2.125 2.500 2.875 MHz OSC (2) Soft-Start Time t I = 0 to 2A 50 850 980 µs SS OUT (2) CTLx Input High Current I CTL =AVIN -2.0 2.0 µA EN_HI 0-3 (2) CTLx Input Low Current I CTL =AGND -2.0 2.0 µA EN_LO 0-3 © 2010 Semtech Corp. www.semtech.com 3 SC183C Electrical Characteristics (continued) Parameter Symbol Conditions Min Typ Max Units CTLx Input High Threshold V 1.2 V EN_HI CTLx Input Low Threshold V 0.4 V EN_LO V Over Voltage Protection V 110 115 120 % OUT OVP Thermal Shutdown Temperature T 160 °C SD Thermal Shutdown Hysteresis T 10 °C SD_HYS Notes: (1) The “Output Voltage Tolerance” includes output voltage accuracy, voltage drift over temperature and the line regulation. (2) The negative current means the current flows through into the pin and the positive current means the current flows through out from the pin. © 2010 Semtech Corp. www.semtech.com 4 SC183C Typical Characteristics Circuit Conditions: C = 10mF/6.3V, C = 22mF/6.3V. Unless otherwise noted, L= 2.2mH (TOKO: 1127AS-2R2M). IN OUT Efficiency Efficiency vs. Load C Efficurr ienc en y t (V =1.5V) Efficiency vs. Load Current (V =3.3V) OUT OUT 100% 100% L=1127AS-2R2 (40m_typ) L=1127AS-2R2 (40m_typ) 95% 95% L=1071AS-1R0 (33m_typ) 90% 90% 85% 85% L=1071AS-1R0 (33m_typ) 80% 80% 75% 75% L=1071AS-2R2 (50m_typ) 70% 70% V = 5.0V IN V = 5.0V IN V = 3.3V V = 1.5V OUT OUT 65% 65% L=1071AS-2R2 (50m_typ) T =25°C T =25°C A A 60% 60% 0.0 0.4 0.8 1.2 1.6 2.0 0.0 0.4 0.8 1.2 1.6 2.0 Output Current (A) Output Current (A) Total Loss vs. Load Current (V =3.3V) Total Loss vs. Load Current (V =1.5V) OUT OUT Total Loss Total Loss 1000 1000 V = 5.0V V = 5.0V IN IN V = 3.3V V = 1.5V OUT OUT L=1071AS-2R2 (50m_typ) 800 800 T =25°C T =25°C A A L=1071AS-2R2 (50m_typ) 600 600 L=1071AS-1R0 (33m_typ) L=1071AS-1R0 (33m_typ) 400 400 200 200 L=1127AS-2R2 (40m_typ) L=1127AS-2R2 (40m_typ) 0 0 0.0 0.4 0.8 1.2 1.6 2.0 0.0 0.4 0.8 1.2 1.6 2.0 Output Current (A) Output Current (A) Load Regula Loation d Regu (lV ation=1.5V) Load Regulation (V =3.3V) Load Regulation OUT OUT 0.5% 0.5% V = 1.5V V = 5.0V OUT IN 0.4% 0.4% T =25°C V = 3.3V OUT A 0.3% 0.3% T =25°C A 0.2% 0.2% 0.1% 0.1% V = 3.3V 0.0% IN 0.0% -0.1% -0.1% -0.2% -0.2% -0.3% -0.3% V = 5.0V IN -0.4% -0.4% -0.5% -0.5% 0.0 0.4 0.8 1.2 1.6 2.0 0.0 0.4 0.8 1.2 1.6 2.0 Output Current (A) Output Current (A) © 2010 Semtech Corp. www.semtech.com 5 Load Regulation Loss (mW) Efficiency (%) Load Regulation Efficiency (%) Loss (mW) SC183C Typical Characteristics Circuit Conditions: C = 10mF/6.3V, C = 22mF/6.3V. Unless otherwise noted, L= 2.2mH (TOKO: 1127AS-2R2M). IN OUT RDSON (P & N) Variation Over Temperature R R V Daria SON tion v (P & N) V sa . I rinput ation ov V eoltage r Line R Variation vs. Temperature DS(ON) DS(ON) 20% 30% V = 5.0V IN 15% 25% I = ±100mA LX P-Channel 10% 20% 5% 15% N-Channel 0% 10% -5% 5% -10% 0% I = ±100mA LX N-Channel P-Channel -15% -5% T = 25°C A -20% -10% -40 -15 10 35 60 85 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (°C) Input Voltage (V) Switching Frequency vs. Temperature Switching F Switchin rg equenc Frequenc y v y Vs ar . I ianput tion ove V roltage Line Switching Frequency Variation 5% 1.0% 4% 0.8% V = 3.3V OUT 3% 0.6% 2% 0.4% 1% 0.2% 0% 0.0% -1% -0.2% -2% V = 1.5V -0.4% OUT -3% -0.6% I = 0A OUT V = 5.0V IN T = 25°C -4% A -0.8% I = 0A OUT -5% -1.0% 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40 -15 10 35 60 85 Input Voltage (V) Ambient Temperature (°C) Line R Line Reg egula ulationtion ove Line Line Regulation vs. Temperature Line Regulation over Temperature 1.0% 1.0% 0.8% 0.8% 0.6% 0.6% V = 1.5V 0.4% OUT 0.4% 0.2% 0.2% 0.0% 0.0% -0.2% -0.2% -0.4% -0.4% V = 3.3V OUT -0.6% -0.6% I = 0A V = 1.5V OUT OUT -0.8% -0.8% T = 25°C A I = 0A OUT -1.0% -1.0% 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40 -15 10 35 60 85 Input Voltage (V) Ambient Temperature (°C) © 2010 Semtech Corp. www.semtech.com 6 Regulation Variation Variation Regulation Variation Variation SC183C Typical Characteristics Circuit Conditions: C = 10mF/6.3V, C = 22mF/6.3V. Unless otherwise noted, L= 2.2mH (TOKO: 1127AS-2R2M). IN OUT UVLO Rising Threshold Variation UVLO H UVLy O st Hy er stesis eresisV V aria ariatition on UVLO Rising Threshold Variation 5% 1.0% 4% 0.8% 3% 0.6% 2% 0.4% 1% 0.2% 0% 0.0% -1% -0.2% -2% -0.4% -3% -0.6% -4% -0.8% I = 0A I = 0A OUT OUT -1.0% -5% -40 -15 10 35 60 85 -40 -15 10 35 60 85 Ambient Temperature (°C) Ambient Temperature (°C) Dropout Voltage in 100% Duty Cycle Operation 500 T = 25°C A 450 400 L= 1071AS-2R2M (DCR= 60m_max) 350 300 250 200 150 L= 1127AS-2R2M 100 (DCR=48m_max) 50 0 0.0 0.4 0.8 1.2 1.6 2.0 Output Current (A) © 2010 Semtech Corp. www.semtech.com 7 Dropout Voltage (mV) Variation Variation SC183C Typical Waveforms Circuit Conditions: C = 10mF/6.3V, C = 22mF/6.3V, L= 2.2mH (TOKO: 1127AS-2R2M). IN OUT Output Voltage Ripple (V =1.5V) Output Voltage Ripple (V =1.5V) OUT OUT Output Voltage Ripple (V =1.5V) Output Voltage Ripple (V =1.5V) OUT OUT V V OUT OUT 10mV/div 10mV/div I I LX LX 1A/div 1A/div V V LX LX 2V/div 2V/div V =3.3V V =5.0V IN IN 500ns/div 500ns/div I =2A I =2A OUT OUT Output Voltage Ripple (V =3.3V) Output Voltage Ripple (V =3.3V) OUT OUT Output Voltage Ripple (V =3.3V) Output Voltage Ripple (V =3.3V) OUT OUT V OUT 10mV/div V OUT 10mV/div I LX 0.5A/div I LX 1A/div V V LX LX 2V/div 2V/div V =5.0V V =5.0V IN IN 500ns/div 500ns/div I =0A I =2A OUT OUT Transient Response (V =1.5V) Transient Response (V =3.3V) OUT OUT Transient Response (V =1.5V; 0A to 1A) Transient Response (V =3.3V; 0A to 1A) OUT OUT V V OUT OUT 100mV/div 100mV/div I I OUT OUT 1A/div 500mA/div V =5.0V V =5.0V IN IN 50µs/div 50µs/div I =0A to 1A I =0A to 1A OUT OUT © 2010 Semtech Corp. www.semtech.com 8 SC183C Typical Waveforms Circuit Conditions: C = 10mF/6.3V, C = 22mF/6.3V, L= 2.2mH (TOKO: 1127AS-2R2M). IN OUT Start Up (V =1.5V) Start Up (V =1.5V) OUT OUT Start Up (Enable)(V =1.5V) Start Up (Enable)(V =1.5V) OUT OUT V V IN IN 2V/div 2V/div V V EN EN 2V/div 2V/div V V OUT OUT 0.5V/div 0.5V/div V =5.0V V =5.0V IN IN 50µs/div 200µs/div R =1k R =0.75 (2A) OUT OUT Start Up (V =1.5V), EN=VIN Start Up (V =1.5V), EN=VIN OUT OUT Start Up (Power up V ) (V =1.5V) Start Up (Power up V ) (V =1.5V) IN OUT IN OUT V V IN IN 2V/div 2V/div V V OUT OUT 0.5V/div 0.5V/div V =5.0V V =5.0V IN IN 200µs/div 200µs/div R =1k R =0.75 (2A) OUT OUT Start Up (V =3.3V) Start Up (V =3.3V) OUT OUT Start Up (Enable)(V =3.3V) Start Up (Enable)(V =3.3V) OUT OUT V V IN IN 2V/div 2V/div V V EN EN 2V/div 2V/div V V OUT OUT 1V/div 1V/div V =5.0V V =5.0V IN IN 100µs/div 200µs/div R =1k R =1.65 (2A) OUT OUT © 2010 Semtech Corp. www.semtech.com 9 SC183C Typical Waveforms Circuit Conditions: C = 10mF/6.3V, C = 22mF/6.3V, L= 2.2mH (TOKO: 1127AS-2R2M). IN OUT Start Up (V =3.3V), EN=VIN Start Up (V =3.3V), EN=VIN OUT OUT Start Up (Power up V ) (V =3.3V) Start Up (Power up V ) (V =3.3V) IN OUT IN OUT V V IN IN 2V/div 2V/div V V OUT OUT 1.5V/div 1.5V/div V =5.0V V =5.0V IN IN 200µs/div 200µs/div R =1k R =1.65 (2A) OUT OUT Shutdown-Disable (1.5V) Shutdown-Disable (3.3V) Shutdown (Disable)(V =1.5V) Shutdown (Disable)(V =3.3V) OUT OUT V V IN IN 2V/div 2V/div V V EN EN 2V/div 2V/div V V OUT OUT 1V/div 1.5V/div V =5.0V V =5.0V IN IN 200µs/div 200µs/div R =1.5 R =3.3 OUT OUT © 2010 Semtech Corp. www.semtech.com 10 SC183C Pin Descriptions Pin # Pin Name Pin Function 1,2 PVIN Input supply voltage for the converter power stage. 3 AGND Ground connection for the internal circuitry. AGND needs to be connected to PGND directly. 4 AVIN Power supply for the internal circuitry. Connect a 10W resistor to PVIN and a 1mF capacitor to AGND. Control bit 0 - see Table 1 for decoding. This pin has a 1 MΩ internal pulldown resistor. This resistor is switched 5 CTL0 in circuit whenever the EN pin is below the enable input high threshold, or when the part is in undervoltage lockout. Control bit 1 - see Table 1 for decoding. This pin has a 1 MΩ internal pulldown resistor. This resistor is switched 6 CTL1 in circuit whenever the EN pin is below the enable input high threshold, or when the part is in undervoltage lockout. Control bit 2 - see Table 1 for decoding. This pin has a 1 MΩ internal pulldown resistor. This resistor is switched 7 CTL2 in circuit whenever the EN pin is below the enable input high threshold, or when the part is in undervoltage lockout. Control bit 3 - see Table 1 for decoding. This pin has a 1 MΩ internal pulldown resistor. This resistor is switched 8 CTL3 in circuit whenever the EN pin is below the enable input high threshold, or when the part is in undervoltage lockout. 9 NC No connection. 10 VOUT Output voltage sense pin. 11,12,13 PGND Ground connection for converter power stage. 14,15,16 LX Switching node - connect an inductor between this pin and the output capacitor. © 2010 Semtech Corp. www.semtech.com 11 SC183C Block Diagram Current Amp PVIN AVIN P Plliim miitt A Cm om pp Oscillator & Slope Generator Control LX Logic VOUT CTL0 Voltage PWM Comp CTL1 Select Error Amp CTL2 500mV Ref CTL3 PGND AGND © 2010 Semtech Corp. www.semtech.com 12 SC183C Applications Information Detailed Description an external resistor divider. There will be a typical 2µA The SC183C is a synchronous step-down converter utiliz- current flowing into the VOUT pin. The typical sche- ing a 2.5MHz fixed frequency voltage mode architecture. matic for an adjustable output voltage option from The switching frequency is chosen to minimize the size of the standard 1.0V with CTLx=[0010], is shown in Figure the external inductor and capacitors while maintaining 1. RFB1 and RFB2 are used to adjust the desired out- high efficiency. put voltage. If the RFB2 current is such that the 2µA VOUT pin current can be ignored, then RFB1 can be Operation found by Equation 1. RFB2 needs to be low enough in During normal operation, the PMOS MOSFET is activated value for the current through the resistor chain to be on each rising edge of the internal oscillator. The voltage at least 20µA in order to ignore the VOUT pin current. feedback loop uses an internal feedback resistor divider. The period is set by the internal oscillator. The device has an V −V OUT OSTD R = ⋅R (1) FB1 FB2 internal synchronous NMOS rectifier and does not require a V OSTD Schottky diode on the LX pin. The device operates as a buck converter in PWM mode with a fixed frequency of 2.5MHz. where V is the pre-determined output voltage via the OSTD CTL pins. Programmable Output Voltage The SC183C has fifteen pre-determined output voltage C is needed to maintain good transient response perfor- FF values which can be individually selected by program- mance. The correct value of C can be found using FF ming the CTL input pins (see Table 1 — Output Voltage Equation 2. Settings). Each CTL pin has an active 1 MΩ internal pull- 2 (V −0.5) V down resistor. The 1MΩ resistor is switched in circuit OUT OSTD C [nF]=2.5× ×( ) (2) FF R [kΩ]⋅(V −V ) V −0.5 whenever the CTL input voltage is below the input FB1 OUT OSTD OSTD threshold, or when the part is in undervoltage lockout. It is recommended to tie all high CTL pins together and use To simplify the design, it is recommended to program the an external pull-up resistor to AVIN if there is no enable desired output voltage from a standard 1.0V as shown in signal or if the enable input is an open drain/collector Figure 1 with a proper C calculated from Equation 2. For FF signal. The CTL pins may be driven by a microprocessor to programming the output voltage from other standard allow dynamic voltage adjustment for systems that reduce voltages, R , R and C need to be adjusted to meet FB1 FB2 FF the supply voltage when entering sleep states. Avoid all Equation 1and 2. zeros being present on the CTL pins when changing pro- grammable output voltages as this would disable the Protection Features device. The SC183C provides the following protection features: SC183C is also capable of regulating a different (higher) • Current Limit output voltage, which is not shown in the Table 1, via • Over-Voltage Protection L • Soft-Start Operation V LX V PVIN OUT IN R AVIN C 10 SC183C IN C OUT • Thermal Shutdown 10µF AVIN C R C AVIN FB1 FF 1µF VOUT R FB2 R = (V −1)×R FB1 OUT FB2 CTL0 10k Enable CTL1 for CTLx= 0010 (1.0V) CTL2 PGND Current Limit CTL3 AGND The internal PMOS power device in the switching stage is protected by a current limit feature. If the inductor current is above the PMOS current limit for 16 consecutive cycles, Figure 1 — Typical Schematic for Adjusting the Output Voltage Up from an Output Voltage of 1.0V the part enters foldback current limit mode and the (CTLx=[0010]) output current is limited to the current limit holding © 2010 Semtech Corp. www.semtech.com 13 SC183C Applications Information (continued) current (I ) of a few hundred milliampere. Under this maintained for 200μs following an internal reference CL_HOLD condition, the output voltage will be the product of I start up of 50μs giving a total nominal startup period of CL_HOLD and the load resistance. The current limit holding current 850μs. During startup, the chip operates by controlling (I ) will decrease when the output voltage increases. the inductor current swings between 0A and current CL_HOLD The load presented must fall below the current limit limit. If at any time V reaches 86% of the target or at OUT holding current for the part to exit foldback current limit the end of the soft-start period, the SC183C will switch mode. Figure 2 shows how the typical current limit to PWM mode operation. Figure 3 shows the typical holding current varies with output voltage. The SC183C is diagram of soft start operation. capable of sustaining an indefinite short circuit without The SC183C is capable of starting up into a pre-biased damage and will resume normal operation when the fault output. When the output is precharged by another is removed. The foldback current limit mode is disabled supply rail, the SC183C will not discharge the output during soft-start. The current limit functionality is shown in Figure 4. during the soft start interval. Shut Down Current Limit Holding Current over Vout When all CTL pins are low, the SC183C will run in shut- 300 down mode, drawing less than 1μA from the input power T = 25°C A supply. The internal switches and bandgap voltage will 250 V = 3.6V IN V = 5.0V IN be immediately turned off. 200 Thermal Shutdown 150 The device has a thermal shutdown feature to protect the 100 SC183C if the junction temperature exceeds 160°C. V = 3.3V IN During thermal shutdown, the on-chip power devices are 50 disabled, tri-stating the LX output. When the temperature 0 drops by 10°C, it will initiate a soft start cycle to resume 1.0 1.5 2.0 2.5 3.0 3.5 Output Voltage (V) normal operation. Figure 2 — Typical Current Limit Holding Current Inductor Selection The SC183C converter has internal loop compensation. The compensation is designed to work with a output filter corner frequency of less than 40kHz for a V of 5V IN and 50kHz for a V of 3.3V over any operating condition. Over-Voltage Protection IN The corner frequency of the output filter can be defined In the event of a 15% over-voltage on the output, the by Equation 3. PWM drive is disabled with LX pin floating. 1 (3) f = C 2π L⋅C OUT Soft-Start Values outside this range may lead to instability, malfunc- The soft-start mode is activated after AVIN reaches its tion, or out-of-specification performance. UVLO and one or more CTL pins are set high to enable the part. A thermal shutdown event will also activate the soft In general, the inductance is chosen by making the induc- start sequence. Soft-start mode controls the maximum tor ripple current to be less than 30% of maximum load current during startup thus limiting in-rush current. The current. When choosing an inductor, it is important to PMOS current limit is stepped through four soft start levels consider the change in inductance with DC bias current. of approximately 20%, 25%, 40%, & 100%. Each step is © 2010 Semtech Corp. www.semtech.com 14 Current Limit Holding Current (mA) SC183C Applications Information (continued) The inductor saturation current is specified as the current options. The saturation characteristics and DC current at which the inductance drops a specific percentage from ratings are also shown. the nominal value. This is approximately 30%. Except for short-circuit or other fault conditions, the peak current L at Dimen- DCR Rated Manufacturer L Rated sions must always be less than the saturation current specified Max Current (μH) Current LxWxH Part Number (Ω) (A) by the manufacturer. The peak current is the maximum (μH) (mm) load current plus one half of the inductor ripple current at TOKO 2.20±20% 0.060 1.80 1.54 2.8x3.0x1.5 the maximum input voltage. Load and/or line transients 1071AS-2R2M can cause the peak current to exceed this level for short TOKO 1.00±30% 0.040 2.70 0.70 2.8x3.0x1.5 1071AS-1R0N durations. Maintaining the peak current below the induc- TOKO tor saturation specification keeps the inductor ripple 2.20±20% 0.048 2.50 1.54 3.5x3.7x1.8 1127AS-2R2M current and the output voltage ripple at acceptable levels. Panasonic Manufacturers often provide graphs of actual inductance 1.00±23% 0.062 2.20 0.70 3.2x3.2x1.5 ELLVGG1R0N and saturation characteristics versus applied inductor current. The saturation characteristics of the inductor can Table 2 – Recommended Inductors vary significantly with core temperature. Core and ambient C Selection OUT temperatures should be considered when examining the The internal voltage loop compensation in the SC183C core saturation characteristics. limits the minimum output capacitor value to 22µF if using an inductor value of 2.2µH or 44mF if using an induc- When the inductance has been determined, the DC resis- tor of 1µH. This is due to its influence on the the loop tance (DCR) must be examined. The efficiency that can be crossover frequency, phase margin, and gain margin. achieved is dependent upon the DCR of the inductor. Increasing the output capacitor above this minimum value Lower values give higher efficiency. The RMS DC current will reduce the crossover frequency and provide greater rating of the inductor is associated with losses in the phase margin. The total output capacitance should not copper windings and the resulting temperature rise of the exceed 50mF to avoid any start-up problems. For most inductor. This is usually specified as the current which typical applications it is recommended to use an output produces a 40˚C temperature rise. Most copper windings capacitance of 22mF to 44mF. When choosing the output are rated to accommodate this temperature rise above capacitor’s capacitance, verify the voltage derating effect maximum ambient. from the capacitor vendors data sheet. Magnetic fields associated with the output inductor can Capacitors with X7R or X5R ceramic dielectric are recom- interfere with nearby circuitry. This can be minimized by mended for their low ESR and superior temperature and the use of low noise shielded inductors which use the voltage characteristics. Y5V capacitors should not be used minimum gap possible to limit the distance that magnetic as their temperature coefficients make them unsuitable fields can radiate from the inductor. However shielded for this application. inductors typically have a higher DCR and are thus less efficient than a similar sized non-shielded inductor. The output voltage droop due to a load transient is deter- mined by the capacitance of the ceramic output capacitor. Final inductor selection depends upon various design The ceramic capacitor supplies the load current initially considerations such as efficiency, EMI, size, and cost. Table until the loop responds. Within a few switching cycles the 2 lists the manufacturers of recommended inductor loop will respond and the inductor current will increase to match the required load. The output voltage droop during the period prior to the loop responding can be related to the choice of output capacitor by the relationship from Equation 4. © 2010 Semtech Corp. www.semtech.com 15 SC183C Applications Information (continued) tor should be placed as closely as possible to the PVIN and 3⋅∆I LOAD C = (4) OUT PGND pins of the SC183C. V ⋅ f DROOP OSC Value Rated Dimensions Manufacturer Value at The output capacitor RMS current ripple may be calcu- Type Voltage LxWxH (μF) 3.3V Part Nunber (VDC) (mm) lated from Equation 5. (μF) V ⋅(V −V ) 1   Murata 2.0x1.25x1.25 OUT IN(MAX ) OUT   (5) 10±10% X5R 6.3 4.74 I = COUT(RMS) (EIA:0805)   GRM21BR60J106K 2 3 L⋅ f ⋅V  OSC IN  Murata 2.0x1.25x0.85 10±10% X5R 6.3 4.05 GRM219R60J106K (EIA:0805) Table 3 lists the manufacturers of recommended output Murata 2.0x1.25x1.25 22±20% X5R 6.3 6.57 (EIA:0805) capacitor options. GRM21BR60J226M Murata 3.2x1.6x1.6 47±20% X5R 6.3 20.3 GRM31CR60J476M (EIA:1206) C Selection IN The SC183C source input current is a DC supply current Table 3 – Recommended Capacitors with a triangular ripple imposed on it. To prevent large input voltage ripple, a low ESR ceramic capacitor is required. A minimum value of 4.7μF should be used. It is important to consider the DC voltage coefficient charac- teristics when determining the actual required value. It should be noted that a 10mF, 6.3V, X5R ceramic capacitor with 5V DC applied may exhibit a capacitance as low as 4.5mF. To estimate the required input capacitor, determine the acceptable input ripple voltage and calculate the minimum value required for C from Equation 6. IN   V V OUT OUT 1−    V V IN  IN  C = (6) IN   ∆V  −ESR⋅ f OSC   I OUT   The input capacitor RMS ripple current varies with the input and output voltage. The maximum input capacitor RMS current is found from Equation 7. V  V  OUT OUT   (7) I = 1− CIN(RMS)   V V IN  IN  The input voltage ripple and RMS current ripple are at a maximum when the input voltage is twice the output voltage or 50% duty cycle. The input capacitor provides a low impedance loop for the edges of pulsed current drawn by the PMOS switch. Low ESR/ESL X5R ceramic capacitors are recommended for this function. To minimise stray inductance, the capaci- © 2010 Semtech Corp. www.semtech.com 16 SC183C Applications Information (continued) SC4633 Soft Start B Stage Stage A C 1 2 Stage 0 G F Stage H 3 D Stage 5 Stage 4 E I Stage 6 Figure 3 — Typical Diagram of Soft Start Operation SC183C/SC283/SC4633 Over Current Protection K J Stage Stage 7 8 Stage 6 M L Figure 4 — Typical Diagram of Current Limit Protection © 2010 Semtech Corp. www.semtech.com 17 SC183C Applications Information (continued) PCB Layout Considerations The layout diagrams in Figure 5 and Figure 6 show a rec- ommended PCB layout for a standard V option and an L OUT VOUT adjustable V option, respectively. Fundamental layout OUT VIN rules must be followed since the layout is critical for achieving the performance specified in the Electrical Characteristics table. Poor layout can degrade the perfor- U1 C OUT GND mance of the DC-DC converter and can contribute to EMI GND problems, ground bounce, and resistive voltage losses. CTLx Poor regulation and instability can result. (a) Top layer for standard volatge option The following guidelines are recommended when devel- oping a PCB layout: GND VOUT 1. The input capacitor, C , provides a low impedance IN VIN loop for the pulsed currents present at the buck converter’s inputs. C should therefore be placed as IN close to the PVIN and PGND pins as possible, and no GND more than 3mm away from the PVIN pin. Place the C IN and SC183C on the same component side to eliminate (b) Bottom layer for standard voltage option the use of vias between C and the device pins. Use IN short wide traces or a copper plane to connect as Figure 5 — Recommended PCB Top & Bottom Layer closely to the IC as possible. Use multiple vias for the Layout for Standard V Option OUT ground connection to the ground plane to reduce the parasitic inductance. These measures will minimize EMI and input voltage ripple by localizing the high frequency current pulses. VOUT L 2. Keep the LX pin traces as short as possible to minimize pickup of high frequency switching edges to other VIN parts of the circuit. C and L should be connected as OUT close as possible between the LX and GND pins, with U1 C C OUT IN a direct return to the GND pin from C . GND GND OUT 3. Route the output voltage feedback/sense path away CTLx from the inductor and LX node to minimize noise and (a) Top layer for adjustable voltage option magnetic interference. 4. Use a ground plane referenced to the SC183C PGND pin. Use several vias to connect to the component GND side ground to further reduce noise and interference VOUT on sensitive circuit nodes. VIN 5. If possible, minimize the resistance from the VOUT and AGND pins to the load. This will reduce the R FB1 voltage drop on the ground plane and improve the C FF R GND FB2 load regulation. And it will also improve the overall efficiency by reducing the copper losses on the output (b) Bottom layer for adjustable voltage option and ground planes. Figure 6 — Recommended PCB Top & Bottom Layer Layout for Adjustable V Option OUT © 2010 Semtech Corp. www.semtech.com 18 C IN SC183C Outline Drawing – 3x3 MLPQ-UT16 DIMENSIONS A D B INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX - - A .020 .024 0.50 0.60 - - A1 .000 .002 0.00 0.05 (.006) (0.152) A2 PIN 1 E b .007 .009 .012 0.18 0.23 0.30 INDICATOR D .114 .118 .122 2.90 3.00 3.10 (LASER MARK) D1 .061 .067 .071 1.55 1.70 1.80 E .114 .118 .122 2.90 3.00 3.10 E1 .061 .067 .071 1.55 1.70 1.80 e .020 BSC 0.50 BSC L .012 .016 .020 0.30 0.40 0.50 A2 N 16 16 aaa .003 0.08 A bbb .004 0.10 SEATING PLANE aaa C C A1 D1 e/2 LxN E/2 E1 2 1 N e bxN D/2 bbb C A B NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 3. DAP IS 1.90 x 1.90mm. Land Pattern – 3x3 MLPQ-UT16 H R DIMENSIONS DIM INCHES MILLIMETERS (.114) (2.90) C G .083 2.10 (C) Z K G H .067 1.70 K .067 1.70 .020 0.50 P R .006 0.15 Y X .012 0.30 Y .031 0.80 X Z .146 3.70 P NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. © 2010 Semtech Corp. www.semtech.com 19 SC183C © Semtech 2010 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. 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