SEMTECH SC1189

SC1189 Programmable Synchronous DC/DC Converter, Dual LDO Controller POWER MANAGEMENT Features Description The SC1189 combines a synchronous voltage mode ‹ ·Synchronous design, enables no heatsink solution controller with two low-dropout linear regulators ‹ 95% efficiency (switching section) providing most of the circuitry necessary to implement ‹ 5 bit DAC for output programmability three DC/DC converters for powering advanced ® ‹ Designed for Intel Pentium III requirements ® microprocessors such as Pentium III. ‹ 1.25V, 2.5V short circuit protected linear controllers ‹ Linear controllers adjustable to 1.8V chipset. The SC1189 switching section features an integrated 5 ‹ VRM 8.5 Compliant bit D/A converter, latched drive output for enhanced noise ‹ VRM 8.4 Compliant (1.3V to 1.8V) immunity, pulse by pulse current limiting and logic ‹ 1.0% accuracy (1.6V to 1.8V) compatible shutdown. The SC1189 switching section ‹ On Chip Power Good Signal operates at a fixed frequency of 200kHz, providing an op- timum compromise between size, efficiency and cost in ‹ Available in Lead free package, fully WEEE and RoHS compliant. the intended application areas. The integrated D/A con- verter provides programmability of output voltage from 1.05V to 1.825V in 25mV increments with no external Applications components. ® ‹ Pentium III microprocessor supplies ‹ 1.050V to 1.825V microprocessor supplies The SC1189 linear sections are low dropout regulators ‹ Programmable triple power supplies with short circuit protection, supplying 1.25V for Vtt and 2.5V for non-GTL I/O. They can be easily adjusted to sup- ply higher voltages e.g. 1.8V chipset. Simplified Application Circuit 12V + 5V 47uF 0.1uF + 10 1500uF U6 x4 5 9 VCC CS+ 0.1uF 7 8 0.1uF LDOEN CS- 0.1uF VID25MV 22 17 1.00k OPEN VID25MV VOSENSE 2R2 VID0 21 15 VID0 BSTH 2.5mOhm VCC_CORE VID1 20 11 VID1 DH 1.2uH VID2 19 14 VID2 BSTL 2R2 VID3 18 13 VID3 DL + EN 16 10 0.1uF EN PGNDH 1 12 1500uF AGND PGNDL x6 23 6 1k LDOV PWRGD 24 2 5V GATE2 GATE1 4 3 LDOS2 LDOS1 SC1189CS 10k 3.3V PWRGD + 1.8V 2.5V 330uF 442 + + 1.0k 330uF 330uF 1 Revision: November 1, 2007 www.semtech.com SC1189 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Sm ymbo Ms aximu Unit VV CC to AGND -V 0.3 to +7 IN PGNDH, PGNDL to AGND ±V 1 BSTH to PGNDH, BSTL to PGNDL -V 0.3 to +15 DH to PGNDH, DL to PGNDL (Note2) -V 1 to +15 OT perating Temperature Range 0C to +70 ° A JT unction Temperature Range 0C to +125 ° J ST torage Temperature Range -C 65 to +150 ° STG LT ead Temperature (Soldering) 10 Sec. 3C 00 ° LEAD Thermal Resistance Junction to Ambient 8W 0 °C/ θ JA Thermal Impedance Junction to Case θ 2W 5 °C/ JC Electrical Characteristics Unless specified: V = 4.75V to 5.25V; GND = P = 0V; V = V ; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; T = 0 to 70°C CC GND OSENSE O A Ps arameter Cn ondition Mp i Tx y Ms a Unit Switching Section OI utput Voltage = 2A in Application Circuit See Output Voltage Table O SC upply VoltageV5 C 47 . V SV upply CurrentV8 CC = 5.0 1A5 m LI oad Regulation=1 0.8A to 24A % O Line Regulation +50% . Current Limit Voltage 50 5 758V m Oscillator Frequency 10 70 20 0 2z 3 kH Oscillator Max Duty Cycle 95 09% Peak DH Sink/Source Current 2 A BV STH - DH = 4.5V, DH - PGNDH = 3.3 1 A DH - PGNDH = 1.5V 100 mA Peak DL Sink/Source Current 2 A BV STL - DL = 4.5V, DL - PGNDL = 3.3 1 A DL - PGNDL = 1.5V 100 mA Gain (A)V VOSENSE to 3B 5 d OL O Vx ID Source Current VID ≤21 .4V 1A0 u VV ID Leakage VIDx = 3.3 ±10 µA VIDx = 0V 100 µA Power good threshold voltage 82 8 1% 1 Dead Time 40 01s 0 n www.semtech.com  2007 Semtech Corp. 2 SC1189 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: V = 4.75V to 5.25V; GND = P = 0V; V = V ; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; T = 0 to 70°C CC GND OSENSE O A Ps arameter Cn ondition Mp i Tx y Ms a Unit Linear Sections QV uiescent Current L5 DOV = 12 mA Output Voltage LDO1 25 .48723 .52 2V .56 Output Voltage LDO2 10 .23119 .25 1V .26 Gain (A))L0 DOS (1,2) to GATE (1,2 9B d OL LI oad Regulation =3 0 to 8A 0% . O Line Regulation 0% .3 OV utput Impedance V1 GATE = 6.5 1k .5 Ω LDOV Undervoltage Lockout 60 .5 80 . 1V LDOEN Threshold 19 .3 1V . LV DOEN Sink Current LDOEN = 3.3 0.01 1.0 µA LDOEN = 0V -200 -300 µA Ot vercurrent Trip Voltage %0 of Vo set poin 20406% Power-up Output Short Circuit Immunity 15 6s 0 m Output Short Circuit Glitch Immunity 04 .5 3s 0 m G; ate Pulldown Impedance GATE (1,2) -AGND 80 0 30 0 7k 5 Ω VCC+BST=0V VOSENSE Impedance 1k 0 Ω Notes: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required. (2) See Gate Resistor Selection recommendations.  2007 Semtech Corp. 3 www.semtech.com SC1189 POWER MANAGEMENT Pin Configuration Ordering Information (1) DevicePr ackage Linea Temp TOP VIEW Voltage Range (T ) J AGND 1 24 GATE2 GATE1 2 23 LDOV SC1189SWTR LDOS1 3 22 VID25MV SV O-241C .25V/2.5 0° to 125° (2) LDOS2 4 21 VID0 SC1189SWTRT VCC 5 20 VID1 PWRGD 6 19 VID2 Notes: LDOEN 7 18 VID3 (1) Only available in tape and reel packaging. A reel CS- 8 17 VOSENSE CS+ 9 16 EN contains 1000 devices. PGNDH 10 15 BSTH (2) Lead free product. This product is fully WEEE and DH 11 14 BSTL RoHS compliant. PGNDL 12 13 DL (24 Pin SOIC) Pin Descriptions Pe in #Pn in Nam Pin Functio 1DAd GN Small Signal Analog and Digital Groun 21G1 ATE Gate Drive Output LDO 31L1 DOS Sense Input for LDO 42L2 DOS Sense Input for LDO 5CVe C Input Voltag 6D PWRG Power Good Output, pulls low if VCC_CORE is outside valid range 7NL. DOE LDO Supply Monitor 8-C) S Current Sense Input (negative 9+C) S Current Sense Input (positive 1H 0Ph GND Power Ground for High Side Switc 1H 1Dt High Side Driver Outpu 1L 2Ph GND Power Ground for Low Side Switc 1L 3Dt Low Side Driver Outpu 1L 4Br ST Supply for Low Side Drive 1H 5Br ST Supply for High Side Drive (1) 1N 6 E Logic low shuts down the converter, High or open for normal operation 1E 7V. OSENS Top end of internal feedback chain (1) 13 8 VID Programming Input (MSB) (1) 12 9 VID Programming Input (1) 21 0 VID Programming Input (1) 20 1 VID Programming Input (1) 2V 2 VID25M Programming Input (LSB) 2V 3Ln DO +12V for LDO sectio 22 4G2 ATE Gate Drive Output LDO Note: (1) All logic level inputs and outputs are open collector TTL compatible. www.semtech.com  2007 Semtech Corp. 4 SC1189 POWER MANAGEMENT Block Diagram VCC CS- CS+ EN CURRENT LIMIT REF BSTH + 70mV - VID3 ERROR AMP VID2 LEVEL SHIFT AND DH HIGH SIDE DRIVE D/A + VID1 - - VID0 + VID25MV PGNDH VOSENSE R SHOOT-THRU CONTROL + Q OSCILLATOR - S OPEN PWRGD COLLECTORS + BSTL - AGND SYNCHRONOUS LDOEN DL MOSFET DRIVE LDOS1 2.5V FET 1.25V FET REF CONTROLLER CONTROLLER PGNDL GATE1 LDOV GATE2 LDOS2 AGND  2007 Semtech Corp. 5 www.semtech.com SC1189 POWER MANAGEMENT Applications Information - Output Voltage Table Unless specified: 4.75V < VCC < 5.25V; GND = PGND = 0V; VOSENSE = V ; 0mV < (CS+-CS-) < 60mV; = 0°C < T < 85°C O j VID Ps arameter Condition Mp inTx yMs a Unit 20 5MV 321 (1) Output Voltage I=0 2A in Application circuit 04 10010 .0316 .051V .06 O 1009 1015 .0511 .07 1.09 0104 0110 .0817 .10 1.11 1108 0115 .1012 .12 1.14 0003 0110 .1317 .15 1.16 1007 0115 .1513 .17 1.19 0102 0010 .1818 .20 1.21 1107 0015 .2013 .22 1.24 0001 0010 .2319 .25 1.26 1006 0015 .2514 .27 1.29 0111 1110 .2810 .30 1.32 1115 1115 .3015 .32 1.34 0010 1110 .3310 .35 1.37 1014 1115 .3516 .37 1.39 0119 1010 .3711 .40 1.42 1114 1015 .4016 .42 1.44 0018 1010 .4212 .45 1.47 1013 1015 .4517 .47 1.49 0118 0110 .4713 .50 1.52 1112 0115 .5018 .52 1.54 0017 0110 .5213 .55 1.57 1011 0115 .5519 .57 1.59 0114 0010 .5816 .60 1.61 1119 0015 .6011 .62 1.64 0014 0010 .6317 .65 1.66 1018 0015 .6512 .67 1.69 0103 1110 .6817 .70 1.71 1108 1115 .7012 .72 1.74 0003 1110 .7318 .75 1.76 1007 1115 .7513 .77 1.79 0102 1010 .7818 .80 1.81 1108 1015 .7912 .82 1.85 Note 1: VID[3:0] correspond to legacy VRM8.4 voltage levels for 1.3V to 1.8V www.semtech.com  2007 Semtech Corp. 6 SC1189 POWER MANAGEMENT Layout Guidelines Careful attention to layout requirements are necessary for transition switching. Connections should be as wide and successful implementation of the SC1189 PWM control- as short as possible to minimize loop inductance. Mini- ler. High currents switching at 200kHz are present in the mizing this loop area will a) reduce EMI, b) lower ground application and their effect on ground plane voltage differ- injection currents, resulting in electrically “cleaner” grounds entials must be understood and minimized. for the rest of the system and c) minimize source ringing, 1). The high power parts of the circuit should be laid out resulting in more reliable gate switching signals. first. A ground plane should be used, the number and 3). The connection between the junction of Q1, Q2 and position of ground plane interruptions should be such as the output inductor should be a wide trace or copper re- to not unnecessarily compromise ground plane integrity. gion. It should be as short as practical. Since this connec- Isolated or semi-isolated areas of the ground plane may tion has fast voltage transitions, keeping this connection be deliberately introduced to constrain ground currents to short will minimize EMI. The connection between the out- particular areas, for example the input capacitor and bot- put inductor and the sense resistor should be a wide trace tom FET ground. or copper area, there are no fast voltage or current transi- 2). The loop formed by the Input Capacitor(s) (Cin), the Top tions in this connection and length is not so important, FET (Q1) and the Bottom FET (Q2) must be kept as small however adding unnecessary impedance will reduce effi- as possible. This loop contains all the high current, fast ciency. 12V IN 5V 10 1 24 AGND GATE2 2 23 GATE1 LDOV 2.32k 3 22 LDOS1 VID0 Cin + 4 21 Q1 1.00k LDOS2 VID1 0.1uF 5 20 5mOhm VCC VID2 Vout 6 19 PWRGD VID3 L + 7 18 Q2 LDOEN VID25MV Cout 8 17 CS- VOSENSE 9 16 CS+ EN 0.1uF 10 15 PGNDH BSTH 11 14 DH BSTL 12 13 PGNDL DL SC1189 Heavy lines indicate 3.3V Vo Lin1 high current paths. Q3 + + Cout Lin1 Cin Lin Layout Diagram SC1189 Vo Lin2 Q4 + Cout Lin2  2007 Semtech Corp. 7 www.semtech.com SC1189 POWER MANAGEMENT Layout Guidelines (Cont.) 4) The Output Capacitor(s) (Cout) should be located as Cin, Q1, Q2 loop. close to the load as possible, fast transient load currents 6) Vcc for the SC1189 should be supplied from the 5V are supplied by Cout only, and connections between Cout supply through a 10Ω resistor, the Vcc pin should be and the load must be short, wide copper areas to mini- decoupled directly to AGND by a 0.1µF ceramic capacitor, mize inductance and resistance. trace lengths should be as short as possible. 5) The SC1189 is best placed over a quiet ground plane 7) The Current Sense resistor and the divider across it area, avoid pulse currents in the Cin, Q1, Q2 loop flowing should form as small a loop as possible, the traces run- in this area. PGNDH and PGNDL should be returned to ning back to CS+ and CS- on the SC1189 should run par- the ground plane close to the package. The AGND pin allel and close to each other. The 0.1µF capacitor should should be connected to the ground side of (one of) the be mounted as close to the CS+ and CS- pins as possible. output capacitor(s). If this is not possible, the AGND pin 8) Ideally, the grounds for the two LDO sections should be may be connected to the ground path between the Output returned to the ground side of (one of) the output Capacitor(s) and the Cin, Q1, Q2 loop. Under no circum- capacitor(s). stances should AGND be returned to a ground inside the 5V Currents in Power Section + Vout + www.semtech.com  2007 Semtech Corp. 8 SC1189 POWER MANAGEMENT Component Selection S S S S SWIT WIT WIT WIT WITCHING SECTION CHING SECTION CHING SECTION CHING SECTION CHING SECTION OUTPUT CAP OUTPUT CAP OUTPUT CAP OUTPUT CAP OUTPUT CAPA A A A ACIT CIT CIT CIT CITORS ORS ORS ORS ORS - Selection begins with the most and 0% duty cycle capability, so some allowance must be critical component. Because of fast transient load current made. Choosing an inductor value of 50 to 75% of the requirements in modern microprocessor core supplies, the calculated maximum will guarantee that the inductor cur- output capacitors must supply all transient load current rent will ramp fast enough to reduce the voltage dropped requirements until the current in the output inductor ramps across the ESR at a faster rate than the capacitor sags, up to the new level. Output capacitor ESR is therefore one hence ensuring a good recovery from transient with no of the most important criteria. The maximum ESR can be additional excursions. simply calculated from: We must also be concerned with ripple current in the out- put inductor and a general rule of thumb has been to V t allow 10% of maximum output current as ripple current. R ≤ ESR I t Note that most of the output voltage ripple is produced by Where the inductor ripple current flowing in the output capacitor ESR. Ripple current can be calculated from: V = Maximum transient voltage excursion t I = Transient current step V t IN I = L RIPPLE ⋅ ⋅ 4 L f OSC For example, to meet a 100mV transient limit with a 10A Ripple current allowance will define the minimum permit- load step, the output capacitor ESR must be less than ted inductor value. 10mΩ. To meet this kind of ESR level, there are three available capacitor technologies. PO PO PO PO POWER FETS WER FETS WER FETS - The FET WER FETS WER FETS s are chosen based on several criteria, with probably the most important being power Each Cap. Total dissipation and power handling capability. Qty. Technology C ESR C ESR T T T T TOP FET OP FET OP FET - The po OP FET OP FET wer dissipation in the top FET is a combi- Rqd. (µF) (mΩ) (µF) (mΩ) nation of conduction losses, switching losses and bottom FET body diode recovery losses. L0 ow ESR Tantalum 30 3 6620 000 1 a) Conduction losses are simply calculated as: O0 S-CON 35 3 2393 90 8. 2 P = I ⋅R ⋅ δ COND O DS(on) L0 ow ESR Aluminum14 50 4573 500 8. where V O The choice of which to use is simply a cost/performance δ = duty cycle ≈ V IN issue, with Low ESR Aluminum being the cheapest, but taking up the most space. b) Switching losses can be estimated by assuming a switch- ing time, if we assume 100ns then: INDUCTOR INDUCTOR INDUCTOR INDUCTOR - Having decided on a suitable type and value INDUCTOR −2 of output capacitor, the maximum allowable value of in- P = I ⋅ V ⋅10 SW O IN ductor can be calculated. Too large an inductor will pro- or more generally, duce a slow current ramp rate and will cause the output I ⋅ V ⋅(t + t ) ⋅ f O IN r f OSC capacitor to supply more of the transient load current P = SW 4 for longer - leading to an output voltage sag below the c) Body diode recovery losses are more difficult to esti- ESR excursion calculated above. mate, but to a first approximation, it is reasonable to as- The maximum inductor value may be calculated from: sume that the stored charge on the bottom FET body di- R C ESR ode will be moved through the top FET as it starts to turn L ≤ ⋅ V A I t on. The resulting power dissipation in the top FET will be: where V is the lesser of V or () V − V A O IN O P = Q ⋅ V ⋅ f RR RR IN OSC The calculated maximum inductor value assumes 100% To a first order approximation, it is convenient to only con-  2007 Semtech Corp. 9 www.semtech.com SC1189 POWER MANAGEMENT Component Selection (Cont.) sider conduction losses to determine FET suitability. INPUT CAP INPUT CAP INPUT CAP INPUT CAP INPUT CAPA A A A ACIT CIT CIT CIT CITORS ORS ORS - since the RMS ripple current in the ORS ORS For a 5V in; 2.8V out at 14.2A requirement, typical FET input capacitors may be as high as 50% of the output losses would be: current, suitable capacitors must be chosen accordingly. Using 1.5X Room temp R to allow for temperature rise. Also, during fast load transients, there may be restrictions DS(ON) on input di/dt. These restrictions require useable energy storage within the converter circuitry, either as extra FR ET type (mΩ)P(e W) Packag DS(on) D output capacitance or, more usually, additional input ca- 2 I5 RL34025191D .6 Pak pacitors. Choosing low ESR input capacitors will help maxi- 2 mize ripple rating for a given size. I5 RL220319 0. 1D .1 Pak S0 i44102628 .2 S0- G G G G GA A A A ATE RESIS TE RESIS TE RESIS TE RESIS TE RESIST T T T TOR SELECTION OR SELECTION OR SELECTION OR SELECTION OR SELECTION - The gate resistors for the top and bottom switching FETs limit the peak gate current BO BO BO BO BOTT TT TT TT TTOM FET OM FET OM FET OM FET OM FET - Bottom FET losses are almost entirely due and hence control the transition time. It is important to to conduction. The body diode is forced into conduction at control the off time transition of the top FET, it should be the beginning and end of the bottom switch conduction fast to limit switching losses, but not so fast as to cause period, so when the FET turns on and off, there is very excessive phase node oscillation below ground as this can little voltage across it, resulting in low switching losses. lead to current injection in the IC substrate and erratic Conduction losses for the FET can be determined by: behaviour or latchup. The actual value should be deter- 2 mined in the application, with the final layout and FETs. P = I ⋅R ⋅(1− δ) COND O DS(on) For the example above: CURRENT SENSE, LIMIT CURRENT SENSE, LIMIT CURRENT SENSE, LIMIT CURRENT SENSE, LIMIT CURRENT SENSE, LIMIT, DR , DR , DR , DR , DROOP AND OFFSET OOP AND OFFSET OOP AND OFFSET OOP AND OFFSET OOP AND OFFSET The converter is protected and it’s loadline shaped by the FR ET type (mΩ)P(e W) Packag DS(on) D signals generated from the sense resistor and associated 2 I5 RL34025131D .3 Pak components. 2 I5 RL220313 0. 0D .9 Pak CURRENT LIMIT CIRCUIT V CS S0 i44102718 .7 S0- Io R RD F Vo Each of the package types has a characteristic thermalR S INDUCTOR impedance. For the surface mount packages on double + Ra Rb sided FR4, 2 oz printed circuit board material, thermal VOSENSE Rc o 2 o impedances of 40 C/W for the D PAK and 80 C/W for theRload DROOP AND SO-8 are readily achievable. The corresponding tempera- OFFSET CIRCUIT ture rise is detailed below: Current Limit, Droop and Offset circuit O Temperature Rise ( C) Current Limit is given by FT ET typeTT op FE Bottom FE I = V .(R +R )/(R .R ) OLIM CS D F S F I6 RL3402562 7. 53. At no load the output voltage is given by: I6 RL2203 42 7. 37. V =V *(1+(Ra.Rb)/(Rc*(Ra+Rb)) O O(nom) so the offset is: S8 i4410 16 80. 141. V =V *1000*(Ra.Rb)/(Rc*(Ra+Rb)) OS O(nom) and the droop is calculated as: It is apparent that single SO-8 Si4410 are not adequate V =Io*R *Rb/(Ra+Rb) D S for this application, but by using parallel pairs in each where R is in mΩ, V and V in mV S OS D position, power dissipation will be approximately halved For a full design procedure for droop and offset, see Appli- and temperature rise reduced by a factor of 4. cation Note AN97-9, “Using Droop and Vout Offset for im- proved transient response”. www.semtech.com  2007 Semtech Corp. 10 SC1189 POWER MANAGEMENT I OLIM FOLDBACK CURRENT LIMITING M = I OS The SC1189 implements a “Hard Current Limit” overcurrent protection for the switching supply output. In 3) Choose V and calculate R B B a short circuit condition, this will lead to higher than nor- M⋅ V ⋅R ⋅R B D F R = mal power dissipation in the bottom side FETs. If this is B (M −1)V (R + R ) CS D F problematic, foldback current limiting can be easily and 4) Calculate the ratio of the input divider inexpensively implemented to drastically reduce dissipa- tion during output short circuit R V + V + V C B CS F = (R + R ) V A C IN R R A B V To CS+ where V = Forward Voltage drop of diode (≈ 0.6V) IN F V CS R C Choose R 1, the value of R or I must be increased. S OLIM Then let R =1kW and calculate R . F D 2) Choose a short circuit current (I ) and calculate M, do OS not be too agressive with M, a value between 2 and 3 should be sufficient. Choosing too low a value for I will OS result in a high value for M and may cause startup prob- lems due to insufficient current.  2007 Semtech Corp. 11 www.semtech.com VOUT SC1189 POWER MANAGEMENT Theory of Operation (Linear OCP) The Linear controllers in the SC1189 have built in Gate Overcurrent Protection (OCP). An overcurrent is assumed to have occured when the external FET is turned fully on 1.4V/us and the output currrent is R limited, this is detected Vout DS(ON) by the gate voltage going very high while the output volt- 1V/ms age is below approximately 40% of it’s setpoint. To allow for capacitor charging and very short overcurrent dura- Vout/2 tions, the gate voltage is ramped very slowly upwards when- ever the output voltage is below the OCP threshold. To guarantee that the LDO output voltage is capable of reach- Time ing it’s setpoint, the gate drive is disabled until both LDOV Undervoltage Lockout (UVLO) and LDOEN Threshold val- Startup with no short circuit ues are exceeded, ensuring that there is sufficient gate If at some later time, a short circuit is applied to the out- drive capability and sufficient LDO input voltage capabil- put, the GATEx voltage will ramp up quickly as Vout falls to ity. A block diagram of one LDO controller is shown below. try and maintain regulation. Once Vout has fallen to the OCP threshold, switch S1 will open and the gate will con- tinue ramping at the 1V/ms rate. If the short is not re- 12V 3.3V moved before the GATEx output reaches approximately LDOV LDOEN LDOV - 0.7V, the GATEx pin will be latched low, disabling the LDO + - 10pF C Short RAMP LDOV LDOV-0.7V applied - 1V/ms gm - GATEx + + Gate VREF 1.3V R2 LDOSx Vout 1.26V SWITCH CLOSED R ON LOW Vout - S1 + + Vout/2 10nA R R1 Time 14uA AGND Short circuit after startup RESET BY S + LDOV LOW Q - If the LDO tries to start into a short, the gate ramps at the R LDOV-0.7V 1V/ms rate to LDOV - 0.7V, where the GATEx pin will be latched low. LDOV-0.7V During a normal start-up, once LDOV and LDOEN have Gate reached their thresholds, the GATEx pin is released and C is charged by 10nA causing the GATEx voltage to RAMP ramp at 10nA/10pF = 1V/ms. Once the GATEx output has 1V/ms ramped to the external FET threshold, Vout starts to ramp up, following GATEx. When Vout reaches the OCP thresh- old, approximately 40% of setpoint, switch S1 is closed and GATEx ramps up at a much faster rate, followed by Time Vout, until Vout reaches setpoint and the loop settles into Startup into short circuit steady state regulation. www.semtech.com  2007 Semtech Corp. 12 SC1189 POWER MANAGEMENT Typical Characteristics Typical Ripple, Vo=1.75V, Io=10A Typical Efficiency (Switching section) 100% PIN Descriptions 90% 1.75V 80% 1.50V Vo=1.25V 70% 0 5 10 15 20 25 30 Output Current (A) Transient Response Vo=1.75V, Io=0A to 28A 2.5V Linear Short circuit output response  2007 Semtech Corp. 13 www.semtech.com Efficiency SC1189 POWER MANAGEMENT Typical Application Circuit www.semtech.com  2007 Semtech Corp. 14 J2 1 3.3V 2 12V 3.3V 3 COM 4 5V 5 D2 + COM 6 C26 5V 1N4148 7 47uF R20 R21 COM 8 1k 18k D1 PWR_OK 9 5V 5VSB TABLE VALID FOR 2x5mOhm SENSE 10 RESISTOR 12V 11 + R1 1N4148 3.3V 12 C2 R22 DROOP OFFSET R11 R15 C1 C27 -12V 13 1500uF 10 + + 390 mV/A mV/V (Ohm) (Ohm) 0.1uF OPEN COM 14 C18 C19 0 0 0 EMPTY PS_ON 15 + 1500uF 1500uF 1 2 3.3 5.0 COM 16 C3 2 2 10 2.5 COM 5 2 EMPTY 2.0 17 1500uF COM 1 5 8.3 12.5 18 R3 -5V U1 2 525 6.3 19 C4 C5 5V 5 5 EMPTY 5 20 EMPTY 0.1uF 5 9 R4 1.00k R5 OPEN 5V VCC CS+ 1 10 16.7 25.0 0.1uF 2 10 50 12.5 ATX M/B MOLEX 39-29-9202 ON/OFF 7 8 LDOEN CS- 5 10 EMPTY 10.0 Q1 Q2 VID25MV 22 17 IRL3103S IRL3103S R19 5mOhm VID0 VOSENSE R6 2R2 R7 2R2 VID0 21 15 VID1 BSTH R8 5mOhm VID1 20 11 VCC_CORE VID2 DH Q3 Q4 L1 1.2uH VID2 19 14 IRL2203 IRL2203 VID3 BSTL J17 R9 2R2 R10 2R2 C6 + C7 + VID3 18 13 R15 R11 VID4 DL 1 See Table 2 See Table 2 + C9 + C10 2 EN 16 10 0.1uF EN PGNDH 3 C8 4 5VSTBY 1 12 AGND PGNDL S2 5V R12 23 6 1k 1500uF 1500uF CON4 LDOV PWRGD C29 C28 R2 10k 1500uF 1500uF 24 2 GATE2 GATE1 0.1uF 10uF 4 3 LDOS2 LDOS1 J15 J18 SCOPE TP VCC_CORE PWRGD SC1189CS C11 C12 Q5 IRLR024N + + Q6 C20 + C21 + 330uF 330uF IRLR024N 5VSTBY C22 + C23 + 1k R24 2.5V J14 Clock R23 442 1.8V J13 + CHIPSET 3.3V STBY C16 C17 330uF 330uF R25 U2 Q8 + 1500uF 1500uF C15 100k 1 15 IRFR120N 1500uF 1500uF + + 5VSTBY VTTIN C14 J24 R27 1.00k R26 330uF 330uF Q9 2 14 VID VID VOUT VID VID VOUT 100k PWRGD VTTGATE 25MV 3210 25MV 3210 IRFR120N 6 13 VTT J26 0 0100 1.050 0 1100 1.450 ADJGATE VTTSEN 1.25V/1.5V VTT 1 0100 1.075 1 1100 1.475 7 12 C31 C30 + 0 0011 1.100 0 1011 1.500 ADJSEN AGPGATE J27 1.8V STBY 1 0011 1.125 1 1011 1.525 CHIPSET 4 11 Q10 0.1uF C32 + 330uF 0 0010 1.150 0 1010 1.550 VTTSEL AGPSEN 3.3V STBY 1 0010 1.175 1 1010 1.575 R28 5 9 330uF J28 4.99k 0 0001 1.200 0 1001 1.600 AGPSEL CAP+ C35 C36 C37 C39 C40 C38 C41 C42 1 0001 1.225 1 1001 1.625 330uF 330uF 330uF 0.1uF 0.1uF 330uF 0.1uF 0.1uF 3 8 C33 IRFR120N AGP J29 0 0000 1.250 0 1000 1.650 DELAY CAP- 0.1uF 1.5V/3.3V AGP (2X/4X) 1 0000 1.275 1 1000 1.675 C34 R29 C43 16 10 + 0 1111 1.300 0 0111 1.700 GND FC 330uF 10k C45 + C44 1 1111 1.325 1 0111 1.725 22nF SC1112CS 0 1110 1.350 0 0110 1.750 + + + + C46 1 1110 1.375 1 0110 1.775 1uF 330uF J30 0.1uF J31 0 1101 1.400 0 0101 1.800 1 1101 1.425 1 0101 1.825 VTTSEL = 1, VTT = 1.5 V J32 J33 AGPSEL VTTSEL VTTSEL = 0, VTT = 1.25 V AGPSEL = 1, AGP=3.3V AGPSEL = 0, AGP=1.5V SC1189 POWER MANAGEMENT Evaluation Board Bill of Materials I. temQe tyRe eferenc Vs alu Note C1, C4, C5, C10, C28, C31, C33, C39, C40, C41, 12 1 0.1uF C42, C46 C2, C3, C6, C7, C8, C9, C18, C19, C20, C21, Low ESR Sanyo MV-GX or 22 1 1500uF C22, C23 equivalent C11, C12, C14, C15, C16, C17, C30, C32, C34, 34 1 330uF C35, C36, C37, C38, C44 41CF 26 47u 61CF 29 10u 71CF 43 22n 81CF 45 1u 92D8 1, D2 1N414 11 0JB 2 A2 TX M/ MOLEX 39-29-920 61LH 1 11 .2u Panasonic PCC-S 72QS 1, Q2 IRLR3103 82Q3 3, Q4 IRL220 92QN 5, Q6 IRLR024 23 5QN 8,Q9,Q10 IRFR120 11 0R0 1 1 12 1Rk 2, R29 10 22 9Rk 4, R27 1.00 14 3R2 6, R7, R9, R10 2R 12 4Rm 8, R19 51 mOh IRC OAR 12 5Re 11, R15 See Tabl 13 2Rk 12, R20, R24 1 11 6Rk 21 18 11 7R0 22 39 31 6R2 23 44 32 7Rk 26, R25 100 31 8Rk 28 4.99 11 8US 1 SH C1189C SEMTEC 41 1US 2 SH C1112C SEMTEC  2007 Semtech Corp. 15 www.semtech.com SC1189 POWER MANAGEMENT Outline Drawing - SO-24 DIMENSIONS A D e INCHES MILLIMETERS N DIM MIN NOM MAX MIN NOM MAX A .093 - .104 2.35 - 2.65 - - A1 .004 .012 0.10 0.30 - - A2 .081 .100 2.05 2.55 2X E/2 b .012 - .020 0.31 - 0.51 c - - .008 .013 0.20 0.33 .602 .606 .610 15.30 15.40 15.50 D E1 .291 .295 .299 7.40 7.50 7.60 E1 E E .406 BSC 10.30 BSC R e .050 BSC 1.27 BSC h .010 - .030 0.25 - 0.75 - - J .020 .030 0.50 0.75 - - L .016 .041 0.40 1.04 L1 (.041) (1.04) N 24 24 13 2 ccc C - - R .024 .035 0.60 0.90 2X N/2 TIPS 01 0° - 8° 0° - 8° e/2 aaa .004 0.10 B bbb .010 0.25 D ccc 0.33 .013 h aaa C A2 A h SEATING H PLANE bxN A1 C bbb C A-B D c GAGE J PLANE 0.25 L 01 (L1) SEE DETAIL A SIDE VIEW DETAIL A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS AND TO BE DETERMINED AT DATUM PLANE -A- -B- -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-013, VARIATION AD. Land Pattern - SO-24 X DIMENSIONS DIM INCHES MILLIMETERS C (.362) (9.20) (C) G Z G .276 7.00 P .050 1.27 X .024 0.60 Y .087 2.20 Z .449 11.40 Y P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A, RLP NO. 307A. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012-8790 Phone: (805)498-2111 FAX (805)498-3804 www.semtech.com  2007 Semtech Corp. 16