SEMTECH SC1186

SC1186 Programmable Synchronous DC/DC Converter, Dual LDO Controller POWER MANAGEMENT Features Description The SC1186 combines a synchronous voltage mode ‹ Synchronous design, enables no heatsink solution controller with two low-dropout linear regulators ‹ 95% efficiency (switching section) providing most of the circuitry necessary to implement three ‹ 5 bit DAC for output programmability DC/DC converters for powering advanced microprocessors ® ‹ Designed for Intel Pentium ll & III requirements ® such as Pentium II & III. ‹ 1.5V, 2.5V short circuit protected linear controllers ‹ 1.265V ± 1.5% Reference available The SC1186 switching section features an integrated 5 bit D/A converter, latched drive output for enhanced noise Applications immunity, pulse by pulse current limiting and logic compatible shutdown. The SC1186 switching section ® ‹ Pentium ll & III microprocessor supplies operates at a fixed frequency of 140kHz, providing an op- ‹ Flexible motherboards timum compromise between size, efficiency and cost in ‹ 1.3V to 3.5V microprocessor supplies the intended application areas. The integrated D/A con- ‹ Programmable triple power supplies verter provides programmability of output voltage from 2.0V to 3.5V in 100mV increments and 1.30V to 2.05V in 50mV increments with no external components. The SC1186 linear sections are low dropout regulators with short circuit protection, supplying 1.5V for GTL bus and 2.5V for non-GTL I/O. The Reference voltage is made available for external linear regulators. Typical Application Circuit 12V + 0.1uF 47uF 5V + 1500uF 10 x4 5 9 VCC CS+ 0.1uF 7 8 LDOEN CS- 0.1uF 0.1uF VID0 22 17 IRLR3103N 1.00k 2.32k VID0 VOSENSE 2R2 VID1 21 15 VID1 BSTH 5mOhm VCC_CORE VID2 20 11 VID2 DH 1.9uH VID3 19 14 IRLR3103N VID3 BSTL 2R2 VID4 18 13 VID4 DL + EN 16 10 0.1uF EN PGNDH 1 12 1500uF AGND PGNDL x6 23 6 1k LDOV REF 24 2 12V 3.3V GATE2 GATE1 4 3 LDOS2 LDOS1 8 SC1186CS 3 + 3.3V 1 IRLR024N 2 - LM358 VLIN3 + 4 1.5V 2.5V 330uF IRLR024N + IRLR024N 330uF + + 330uF 330uF 1 Revision: December 2, 2004 www.semtech.com SC1186 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability. Pl arameter Sm ymbo Ms aximu Unit VV CC to AGND -V 0.3 to +7 IN PGNDH, PGNDL to AGND ±V 1 BSTH to PGNDH, BSTL to PGNDL -V 0.3 to +15 DH to PGNDH, DL to PGNDL (Note2) -V 1 to +15 OT perating Temperature Range 0C to +70 ° A JT unction Temperature Range 0C to +125 ° J ST torage Temperature Range -C 65 to +150 ° STG LT ead Temperature (Soldering) 10 Sec. 3C 00 ° LEAD Thermal Resistance Junction to Ambient 8W 0 °C/ θ JA Thermal Impedance Junction to Case 2W 5 °C/ θ JC Electrical Characteristics Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = V ; 0mV < (CS+-CS-) < 60mV; LDOV = BST = 11.4V to 12.6V; T = 0 to 70°C O A Ps arameter Cn ondition Mp i Tx y Ms a Unit Switching Section OI utput Voltage = 2A in Application Circuit See Output Voltage Table O SC upply VoltageV5 C 47 . V SV upply CurrentV8 CC = 5.0 1A5 m LI oad Regulation=1 0.8A to 15A % O Line Regulation ±% 0.5 Current Limit Voltage 60 0 758V m Oscillator Frequency 10 20 10 4 1z 6 kH Oscillator Max Duty Cycle 95 09% PV eak DH Sink/Source Current BSTH - DH = 4.5V, DH- PGNDH = 3.3 1 A DH- PGNDH = 1.5V 100 mA PV eak DL Sink/Source Current BSTL - DL = 4.5V, DL - PGNDL= 3.3 1 A DL- PGNDH = 1.5V 100 mA Gain (A)V VOSENSE to 3B 5 d OL O Vx ID Source Current V< ID21 .4V 1A0 u VV ID LeakageV0 IDx = 5 1A u Power good threshold voltage 82 8 1% 1 Dead Time 40 01s 0 n www.semtech.com  2004 Semtech Corp. 2 SC1186 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = V ; 0mV < (CS+-CS-) < 60mV; LDOV = BST = 11.4V to 12.6V; T = 0 to 70°C O A Ps arameter Cn ondition Mp i Tx y Ms a Unit Linear Sections QV uiescent Current L5 DOV = 12 mA Output Voltage LDO1 25 .49326 .52 2V .55 Output Voltage LDO2 15 .49614 .51 1V .53 RA eference Voltage I6 ref < 100u 15 .2414 .26 1V .28 Gain (A))L0 DOS (1,2) to GATE (1,2 9B d OL LI oad Regulation =3 0 to 8A 0% . O Line Regulation 0% .3 OV utput Impedance V1 GATE = 6.5 1k .5 Ω LDOV Undervoltage Lockout 60 .5 80 . 1V LDOEN Threshold 19 .3 1V . LV DOEN Sink Current LDOEN = 3.3 0.01 1.0 µA LDOEN = 0V -200 -300 µA Ot vercurrent Trip Voltage %0 of Vo set poin 20406% Power-up Output Short Circuit Immunity 15 6s 0 m Output Short Circuit Glitch Immunity 04 .5 2s 0 m G; ate Pulldown Impedance GATE (1,2) -AGND 80 0 30 0 7k 5 Ω VCC+BST=0V VOSENSE Impedance 1k 0 Ω Note: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required. (2) See Gate Resistor Selection recomendations.  2004 Semtech Corp. 3 www.semtech.com SC1186 POWER MANAGEMENT Pin Configuration Ordering Information (1) (1) Device Package Linear Temp TOP VIEW Voltage Range (T ) J AGND 1 24 GATE2 GATE1 2 23 LDOV SC1186CSW.TR LDOS1 3 22 VID0 SV O-241C .5V/2.5 0° to 125° (2) SC1186CSWTRT LDOS2 4 21 VID1 VCC 5 20 VID2 REF 6 19 VID3 Notes: LDOEN 7 18 VID4 (1) Only available in tape and reel packaging. A reel CS- 8 17 VOSENSE contains 1000 devices. CS+ 9 16 EN (2) Lead free product. This product is fully WEEE and PGNDH 10 15 BSTH RoHS compliant. DH 11 14 BSTL PGNDL 12 13 DL (24 Pin SOIC) Pin Descriptions Pe in #Pn in Nam Pin Functio 1DAd GN Small Signal Analog and Digital Groun 21G1 ATE Gate Drive Output LDO 31L1 DOS Sense Input for LDO 42L2 DOS Sense Input for LDO 5CVe C Input Voltag 6FRt E Buffered Reference Voltage outpu 7NL. DOE LDO Supply Monitor 8-C) S Current Sense Input (negative 9+C) S Current Sense Input (positive 1H 0Ph GND Power Ground for High Side Switc 1H 1Dt High Side Driver Outpu 1L 2Ph GND Power Ground for Low Side Switc 1L 3Dt Low Side Driver Outpu 1L 4Br ST Supply for Low Side Drive 1H 5Br ST Supply for High Side Drive (1) 1N 6 E Logic low shuts down the converter, High or open for normal operation 1E 7V. OSENS Top end of internal feedback chain (1) 14 8 VID Programming Input (MSB) (1) 13 9 VID Programming Input (1) 22 0 VID Programming Input (1) 21 1 VID Programming Input (1) 20 2 VID Programming Input (LSB) 2V 3Ln DO +12V for LDO sectio 22 4G2 ATE Gate Drive Output LDO Note: (1) All logic level inputs and outputs are open collector TTL compatible. www.semtech.com  2004 Semtech Corp. 4 SC1186 POWER MANAGEMENT Block Diagram VCC CS- CS+ EN CURRENT LIMIT BSTH REF + 70mV - VID4 LEVEL SHIFT AND DH HIGH SIDE DRIVE VID3 + - D/A VID2 - + ERROR VID1 AMP PGNDH VID0 VOSENSE R SHOOT-THRU CONTROL Q OSCILLATOR AGND S BSTL LDOEN LDOS1 2.5V FET 1.5V FET SYNCHRONOUS DL CONTROLLER CONTROLLER MOSFET DRIVE 1.275V GATE1 REF PGNDL LDOV REF GATE2 LDOS2  2004 Semtech Corp. 5 www.semtech.com SC1186 POWER MANAGEMENT Applications Information - Output Voltage Table Unless specified: 4.75V < VCC < 5.25V; GND = PGND = 0V; VOSENSE = V ; 0mV < (CS+-CS-) < 60mV; = 0°C < T < 85°C O j Ps arameter Cd ondition Vi Mp in Tx y Ms a Unit 43210 (1) Output Voltage I=1 2A in Application circuit (Figure 1) 07 11110 .2713 .30 1V .32 O 06 111010 .3214 .35 1.37 05 110110 .3715 .40 1.42 04 110010 .4216 .45 1.47 08 101110 .4713 .50 1.52 07 101010 .5213 .55 1.57 06 100110 .5714 .60 1.62 05 100010 .6215 .65 1.67 05 011110 .6716 .70 1.72 04 011010 .7216 .75 1.77 02 010110 .7818 .80 1.81 02 010010 .8319 .85 1.86 01 001110 .8819 .90 1.91 01 001010 .9310 .95 1.97 00 000110 .9820 .00 2.02 00 000020 .0321 .05 2.07 10 111110 .9720 .00 2.03 19 111020 .0622 .10 2.13 17 110120 .1623 .20 2.23 16 110020 .2625 .30 2.33 14 101120 .3626 .40 2.43 13 101020 .4628 .50 2.53 11 100120 .5629 .60 2.63 10 100020 .6621 .70 2.74 18 011120 .7522 .80 2.84 12 011020 .8428 .90 2.95 10 010120 .9430 .00 3.06 18 010030 .0332 .10 3.16 16 001130 .1334 .20 3.26 14 001030 .2336 .30 3.36 12 000130 .3338 .40 3.46 10 000030 .4330 .50 3.57 www.semtech.com  2004 Semtech Corp. 6 SC1186 POWER MANAGEMENT Layout Guidelines Careful attention to layout requirements are necessary for transition switching. Connections should be as wide and successful implementation of the SC1186 PWM control- as short as possible to minimize loop inductance. Mini- ler. High currents switching at 140kHz are present in the mizing this loop area will a) reduce EMI, b) lower ground application and their effect on ground plane voltage differ- injection currents, resulting in electrically “cleaner” grounds entials must be understood and minimized. for the rest of the system and c) minimize source ringing, 1). The high power parts of the circuit should be laid out resulting in more reliable gate switching signals. first. A ground plane should be used, the number and 3). The connection between the junction of Q1, Q2 and position of ground plane interruptions should be such as the output inductor should be a wide trace or copper re- to not unnecessarily compromise ground plane integrity. gion. It should be as short as practical. Since this connec- Isolated or semi-isolated areas of the ground plane may tion has fast voltage transitions, keeping this connection be deliberately introduced to constrain ground currents to short will minimize EMI. The connection between the out- particular areas, for example the input capacitor and bot- put inductor and the sense resistor should be a wide trace tom FET ground. or copper area, there are no fast voltage or current transi- 2). The loop formed by the Input Capacitor(s) (Cin), the Top tions in this connection and length is not so important, FET (Q1) and the Bottom FET (Q2) must be kept as small however adding unnecessary impedance will reduce effi- as possible. This loop contains all the high current, fast ciency. 12V IN 5V 10 1 24 AGND GATE2 2 23 GATE1 LDOV 2.32k 3 22 LDOS1 VID0 Cin + 4 21 Q1 1.00k LDOS2 VID1 0.1uF 5 20 5mOhm VCC VID2 Vout 6 19 REF VID3 L + 7 18 Q2 0.1uF LDOEN VID4 Cout 8 17 CS- VOSENSE 9 16 CS+ EN 10 15 PGNDH BSTH 11 14 DH BSTL 12 13 PGNDL DL SC1186 Heavy lines indicate 3.3V Vo Lin1 high current paths. Q3 + + Cout Lin1 Cin Lin Layout Diagram SC1186 Vo Lin2 Q4 + Cout Lin2  2004 Semtech Corp. 7 www.semtech.com SC1186 POWER MANAGEMENT Layout Guidelines (Cont.) 4) The Output Capacitor(s) (Cout) should be located as 6) Vcc for the SC1186 should be supplied from the 5V close to the load as possible, fast transient load currents supply through a 10Ω resistor, the Vcc pin should be are supplied by Cout only, and connections between Cout decoupled directly to AGND by a 0.1µF ceramic capacitor, and the load must be short, wide copper areas to mini- trace lengths should be as short as possible. mize inductance and resistance. 7) The Current Sense resistor and the divider across it 5) The SC1186 is best placed over a quiet ground plane should form as small a loop as possible, the traces run- area, avoid pulse currents in the Cin, Q1, Q2 loop flowing ning back to CS+ and CS- on the SC1186 should run par- in this area. PGNDH and PGNDL should be returned to allel and close to each other. The 0.1µF capacitor should the ground plane close to the package. The AGND pin be mounted as close to the CS+ and CS- pins as possible. should be connected to the ground side of (one of) the 8) Ideally, the grounds for the two LDO sections should be output capacitor(s). If this is not possible, the AGND pin returned to the ground side of (one of) the output may be connected to the ground path between the Output capacitor(s). Capacitor(s) and the Cin, Q1, Q2 loop. Under no circum- stances should AGND be returned to a ground inside the Cin, Q1, Q2 loop. 5V Currents in Power Section + Vout + www.semtech.com  2004 Semtech Corp. 8 SC1186 POWER MANAGEMENT Component Selection SWITCHING SECTION The calculated maximum inductor value assumes 100% OUTPUT CAPACITORS - Selection begins with the most and 0% duty cycle capability, so some allowance must be critical component. Because of fast transient load current made. Choosing an inductor value of 50 to 75% of the requirements in modern microprocessor core supplies, the calculated maximum will guarantee that the inductor cur- output capacitors must supply all transient load current rent will ramp fast enough to reduce the voltage dropped requirements until the current in the output inductor ramps across the ESR at a faster rate than the capacitor sags, up to the new level. Output capacitor ESR is therefore one hence ensuring a good recovery from transient with no of the most important criteria. The maximum ESR can be additional excursions. simply calculated from: We must also be concerned with ripple current in the out- put inductor and a general rule of thumb has been to V t allow 10% of maximum output current as ripple current. R ≤ ESR I t Note that most of the output voltage ripple is produced by Where the inductor ripple current flowing in the output capacitor ESR. Ripple current can be calculated from: V = Maximum transient voltage excursion t I = Transient current step V t IN I = L RIPPLE ⋅ ⋅ 4 L f OSC For example, to meet a 100mV transient limit with a 10A Ripple current allowance will define the minimum permit- load step, the output capacitor ESR must be less than ted inductor value. 10mΩ. To meet this kind of ESR level, there are three available capacitor technologies. POWER FETS - The FETs are chosen based on several criteria, with probably the most important being power Each Cap. Total dissipation and power handling capability. Qty. Technology C ESR C ESR TOP FET - The power dissipation in the top FET is a com- Rqd. (µF) (mΩ) (µF) (mΩ) bination of conduction losses, switching losses and bot- tom FET body diode recovery losses. L0 ow ESR Tantalum 30 3 6620 000 1 a) Conduction losses are simply calculated as: O0 S-CON 35 3 2393 90 8. 2 P = I ⋅R ⋅ δ COND O DS(on) L0 ow ESR Aluminum14 50 4573 500 8. where V O The choice of which to use is simply a cost/performance δ = duty cycle ≈ V IN issue, with Low ESR Aluminum being the cheapest, but taking up the most space. b) Switching losses can be estimated by assuming a switch- ing time, if we assume 100ns then: INDUCTOR - Having decided on a suitable type and value −2 of output capacitor, the maximum allowable value of in- P = I ⋅ V ⋅10 SW O IN ductor can be calculated. Too large an inductor will pro- or more generally, duce a slow current ramp rate and will cause the output I ⋅ V ⋅(t + t ) ⋅ f O IN r f OSC capacitor to supply more of the transient load current for P = SW 4 longer - leading to an output voltage sag below the ESR c) Body diode recovery losses are more difficult to esti- excursion calculated above. mate, but to a first approximation, it is reasonable to as- The maximum inductor value may be calculated from: sume that the stored charge on the bottom FET body di- R C ESR ode will be moved through the top FET as it starts to turn L ≤ ⋅ V A I t on. The resulting power dissipation in the top FET will be: where V is the lesser of V or () V − V A O IN O P = Q ⋅ V ⋅ f RR RR IN OSC  2004 Semtech Corp. 9 www.semtech.com SC1186 POWER MANAGEMENT Component Selection (Cont.) To a first order approximation, it is convenient to only INPUT CAPACITORS - since the RMS ripple current in the consider conduction losses to determine FET suitability. input capacitors may be as high as 50% of the output For a 5V in; 2.8V out at 14.2A requirement, typical FET current, suitable capacitors must be chosen accordingly. losses would be: Also, during fast load transients, there may be restric- Using 1.5X Room temp R to allow for temperature rise. tions on input di/dt. These restrictions require useable DS(ON) energy storage within the converter circuitry, either as extra output capacitance or, more usually, additional in- FR ET type (mΩ)P(e W) Packag DS(on) D put capacitors. Choosing low ESR input capacitors will 2 I5 RL34025191D .6 Pak help maximize ripple rating for a given size. 2 I5 RL220319 0. 1D .1 Pak GATE RESISTOR SELECTION - The gate resistors for the S0 i44102628 .2 S0- top and bottom switching FETs limit the peak gate current and hence control the transition time. It is important to BOTTOM FET - Bottom FET losses are almost entirely control the off time transition of the top FET, it should be due to conduction. The body diode is forced into conduc- fast to limit switching losses, but not so fast as to cause tion at the beginning and end of the bottom switch con- excessive phase node oscillation below ground as this can duction period, so when the FET turns on and off, there lead to current injection in the IC substrate and erratic is very little voltage across it, resulting in low switching behaviour or latchup. The actual value should be deter- losses. Conduction losses for the FET can be determined mined in the application, with the final layout and FETs. by: 2 P = I ⋅R ⋅(1− δ) SHORT CIRCUIT PROTECTION - LINEARS COND O DS(on) The Short circuit feature on the linear controllers is imple- For the example above: mented by using the Rds(on) of the FETs. As output cur- rent increases, the regulation loop maintains the output FR ET type (mΩ)P(e W) Packag DS(on) D voltage by turning the FET on more and more. Eventually, 2 I5 RL34025131D .3 Pak as the Rds(on) limit is reached, the FET will be unably to turn on more fully, and output voltage will start to fall. 2 I5 RL220313 0. 0D .9 Pak When the output voltage falls to approximately 40% of nominal, the LDO controller is latched off, setting output S0 i44102718 .7 S0- voltage to 0. Power must be cycled to reset the latch. Each of the package types has a characteristic thermal To prevent false latching due to capacitor inrush currents impedance. For the surface mount packages on double or low supply rails, the current limit latch is initially dis- sided FR4, 2 oz printed circuit board material, thermal abled. It is enabled at a preset time (nominally 2ms) after o 2 o impedances of 40 C/W for the D PAK and 80 C/W for the both the LDOV and LDOEN pins rise above their lockout SO-8 are readily achievable. The corresponding tempera- points. ture rise is detailed below: To be most effective, the linear FET Rds(on) should not be selected artificially low, the FET should be chosen so that, O at maximum required current, it is almost fully turned on. Temperature Rise ( C) If, for example, a linear supply of 1.5V at 4A is required FT ET typeTT op FE Bottom FE from a 3.3V ± 5% rail, max allowable Rds(on) would be. Rds(on)max = (0.95*3.3-1.5)/4 » 400mΩ I6 RL3402562 7. 53. To allow for temperature effects 200mΩ would be a suit- I6 RL2203 42 7. 37. able room temperature maximum, allowing a peak short circuit current of approximately 15A for a short time be- S8 i4410 16 80. 141. fore shutdown. It is apparent that single SO-8 Si4410 are not adequate for this application, but by using parallel pairs in each position, power dissipation will be approximately halved and temperature rise reduced by a factor of 4. www.semtech.com  2004 Semtech Corp. 10 SC1186 POWER MANAGEMENT Theory of Operation (Linear OCP) The Linear controllers in the SC1186 have built in Gate Overcurrent Protection (OCP). An overcurrent is assumed to have occured when the external FET is turned fully on 1.4V/us and the output currrent is R limited, this is detected Vout DS(ON) by the gate voltage going very high while the output volt- 1V/ms age is below approximately 40% of it’s setpoint. To allow for capacitor charging and very short overcurrent dura- Vout/2 tions, the gate voltage is ramped very slowly upwards when- ever the output voltage is below the OCP threshold. To guarantee that the LDO output voltage is capable of reach- Time ing it’s setpoint, the gate drive is disabled until both LDOV Undervoltage Lockout (UVLO) and LDOEN Threshold val- Startup with no short circuit ues are exceeded, ensuring that there is sufficient gate If at some later time, a short circuit is applied to the out- drive capability and sufficient LDO input voltage capabil- put, the GATEx voltage will ramp up quickly as Vout falls to ity. A block diagram of one LDO controller is shown below. try and maintain regulation. Once Vout has fallen to the OCP threshold, switch S1 will open and the gate will con- tinue ramping at the 1V/ms rate. If the short is not re- 12V 3.3V moved before the GATEx output reaches approximately LDOV LDOEN LDOV - 0.7V, the GATEx pin will be latched low, disabling the LDO + - 10pF C RAMP Short LDOV LDOV-0.7V applied - 1V/ms - gm GATEx + + Gate VREF 1.3V R2 LDOSx Vout 1.26V SWITCH CLOSED R ON LOW Vout - S1 + + Vout/2 10nA R R1 Time 14uA AGND Short circuit after startup RESET BY S + LDOV LOW Q - If the LDO tries to start into a short, the gate ramps at the R LDOV-0.7V 1V/ms rate to LDOV - 0.7V, where the GATEx pin will be latched low. LDOV-0.7V During a normal start-up, once LDOV and LDOEN have Gate reached their thresholds, the GATEx pin is released and C is charged by 10nA causing the GATEx voltage to RAMP ramp at 10nA/10pF = 1V/ms. Once the GATEx output has 1V/ms ramped to the external FET threshold, Vout starts to ramp up, following GATEx. When Vout reaches the OCP thresh- old, approximately 40% of setpoint, switch S1 is closed and GATEx ramps up at a much faster rate, followed by Time Vout, until Vout reaches setpoint and the loop settles into Startup into short circuit steady state regulation.  2004 Semtech Corp. 11 www.semtech.com SC1186 POWER MANAGEMENT Typical Characteristics Typical Ripple, Vo=2.0V, Io=10A Typical Efficiency (Switching section) 96% PIN Descriptions 92% 88% 84% Vo=2.8V 80% Vo=2.0V Vo=2.5V 76% 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 Io (Amps) Transient Response Vo=2.4V, Io=300mA to 15A 2.5V Linear Short circuit output response www.semtech.com  2004 Semtech Corp. 12 Efficiency (%) SC1186 POWER MANAGEMENT Evaluation Board Schematic  2004 Semtech Corp. 13 www.semtech.com J1 12V TABLE VALID FOR 1x5mOhm SENSE RESISTOR + DROOP OFFSET R11 R15 C27 C28 VID VOUT VID VOUT 47uF mV/A mV/V (Ohm) (Ohm) 0.1uF 43210 43210 0 0 0 EMPTY J21 01111 1.30 11111 NO CPU 1 2 2.5 10 01110 1.35 11110 2.10 2 2 3.3 5 5V 01101 1.40 11101 2.20 J16 5 2 EMPTY 2 01100 1.45 11100 2.30 1 5 6.3 25 R1 01011 1.50 11011 2.40 1 2 5 8.3 12.5 C1 01010 1.55 11010 2.50 2 5 5 EMPTY 5 10 + + + + 01001 1.60 11001 2.60 0.1uF 3 C2 C3 C18 C19 1 10 12.5 50 01000 1.65 11000 2.70 4 2 10 16.7 25 1500uF 1500uF 1500uF 1500uF 00111 1.70 10111 2.80 5 10 EMPTY 10 00110 1.75 10110 2.90 00101 1.80 10101 3.00 R3 00100 1.85 10100 3.10 U1 C4 C5 00011 1.90 10011 3.20 EMPTY 0.1uF 5 9 00010 1.95 10010 3.30 VCC CS+ 00001 2.00 10001 3.40 0.1uF 7 8 00000 2.05 10000 3.50 LDOEN CS- Q1 Q2 VID0 22 17 IRLR3103 IRLR3103N R4 1.00k R5 2.32k VID0 VOSENSE R6 2R2 R7 2R2 VID1 21 15 VID1 BSTH R8 5mOhm VID2 20 11 L2R VCC_CORE VID2 DH Q3 L1 1.9uH VID3 19 14 IRLR3103N VID3 BSTL J17 R9 2R2 R10 2R2 C6 + C7 + VID4 18 13 R15 R11 VID4 DL 1 Q4 See Table See Table C9 + + C10 2 EN 16 10 IRLR3103N 0.1uF EN PGNDH 3 C8 4 1 12 12V 6 5 4 3 2 1 AGND PGNDL S1 R12 23 6 1k 1500uF 1500uF LDOV REF 1500uF 1500uF 24 2 GATE2 GATE1 8 4 3 3 U2A LDOS2 LDOS1 + 1 J18 2 SCOPE TP SC1186CS - J12 LM358 3.3V 3.3V R16 4 0 Q6 Q7 C20 C21 + + IRLR024N + C11 R17 J19 C22 + C23 + 330uF J13 J14 VLIN3 Q5 VLIN2 VLIN1 IRLR024N IRLR024N 1.5V 2.5V See Table + C13 C12 R18 + + 0.1uF 330uF + + + + See Table C24 C25 C14 C15 C16 C17 330uF 330uF 1500uF 1500uF 330uF 330uF 330uF 330uF J20 1500uF 1500uF J22 J23 J24 VLIN3 R17 R18 J25 J15 1.5V 18.7 100 1.8V 42.2 100 2.5V 97.6 100 SC1186 POWER MANAGEMENT Evaluation Board Bill of Materials I. temQe tyRe eferenc Vs alu Note 16CF 1, C4, C5, C10, C13, C28 0.1u C2, C3, C6, C7, C8, C9, C18, C19, C20, C21, Low ESR Sanyo MV-GX or 22 1 1500uF C22, C23 equivalent 38CF 11, C12, C14, C15, C16, C17, C24, C25 330u 41CF 27 47u 51LH 1 1.9u 63QN 1, Q2, Q3, Q4 IRLR3103 73QN 5, Q6, Q7 IRLR024 81R0 1 1 91RY 3 EMPT 11 0Rk 4 1% .00 1 11 1Rk 5 2% .32 1 14 2R2 6, R7, R9, R10 2R 11 3Rm 8 51 mOh IRC OAR 12 4R2 15, R11 See Table 11 5Rk 12 1 11 6R0 16 12 7Re 17, R18 See Tabl 11 8US 1 SH C1186C SEMTEC 11 9U8 2 LM35 www.semtech.com  2004 Semtech Corp. 14 SC1186 POWER MANAGEMENT Outline Drawing - SO-24 DIMENSIONS A D INCHES MILLIMETERS e DIM N MIN NOM MAX MIN NOM MAX - - A .093 .104 2.35 2.65 A1 .004 - .012 0.10 - 0.30 A2 .081 - .100 2.05 - 2.55 2X E/2 - - b .012 .020 0.31 0.51 c .008 - .013 0.20 - 0.33 D .602 .606 .610 15.30 15.40 15.50 E1 .291 .295 .299 7.40 7.50 7.60 E1 E E .406 BSC 10.30 BSC R e .050 BSC 1.27 BSC - - h .010 .030 0.25 0.75 - - J .020 .030 0.50 0.75 L .016 - .041 0.40 - 1.04 (.041) (1.04) L1 N 24 24 13 2 ccc C R .024 - .035 0.60 - 0.90 - - 2X N/2 TIPS 01 0° 8° 0° 8° e/2 aaa .004 0.10 B bbb .010 0.25 ccc D .013 0.33 h aaa C A2 A h SEATING H PLANE bxN A1 C bbb C A-B D c GAGE J PLANE 0.25 L 01 (L1) SEE DETAIL A DETAIL A SIDE VIEW NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS AND TO BE DETERMINED AT DATUM PLANE -A- -B- -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-013, VARIATION AD. Outline Drawing - SO-24 X DIMENSIONS DIM INCHES MILLIMETERS C (.362) (9.20) (C) G Z G .276 7.00 P .050 1.27 X .024 0.60 Y .087 2.20 Z .449 11.40 Y P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A, RLP NO. 307A. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Rd., Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2004 Semtech Corp. 15 www.semtech.com