SC1185 & SC1185A Programmable Synchronous DC/DC Converter, Dual LDO Controller POWER MANAGEMENT Features Description The SC1185 combines a synchronous voltage mode con- � Synchronous design, enables no heatsink solution troller with two low-dropout linear regulators providing � 95% efficiency (switching section) most of the circuitry necessary to implement three DC/ � 5 bit DAC for output programmability DC converters for powering advanced microprocessors � On chip power good function ® such as Pentium II . ® � Designed for Intel Pentium ll requirements � 1.5V, 2.5V @ 1.25% for linear section The SC1185 switching section features an integrated 5 � 1.265V ± 1.5% Reference available bit D/A converter, pulse by pulse current limiting, inte- � 24-lead SO package. Lead free option available. grated power good signaling, and logic compatible shut- Lead free product is fully WEEE and RoHS down. The SC1185 switching section operates at a fixed compliant. frequency of 140kHz, providing an optimum compromise between size, efficiency and cost in the intended appli- cation areas. The integrated D/A converter provides pro- Applications grammability of output voltage from 2.0V to 3.5V in 100mV increments and 1.30V to 2.05V in 50mV incre- ® � Pentium ll microprocessor supplies ments with no external components. � Flexible motherboards � 1.3V to 3.5V microprocessor supplies The SC1185 linear sections are low dropout regulators � Programmable triple power supplies supplying 1.5V for GTL bus and 2.5V for non-GTL I/O. The Reference voltage is made available for external lin- ear regulators. Typical Application Circuit 12V 5V + 4.7uF 10 + 0.1uF 1500uF x4 0.1uF 5 9 VCC CS+ 0.1uF PWRGOOD 7 8 PWRGOOD CS- VID0 22 17 IRLR3103N 1.00k 2.32k VOSENSE VID0 VID1 21 15 VID1 BSTH 5mOhm 2R2 VCC_CORE VID2 20 11 VID2 DH 1.9uH 19 14 IRLR3103N VID3 VID3 BSTL 18 13 VID4 VID4 DL + 2R2 16 10 EN 0.1uF EN PGNDH 1 12 AGND PGNDL 1k 23 6 1500uF LDOV REF 12V 3.3V x6 24 2 GATE2 GATE1 4 3 LDOS2 LDOS1 SC1185CS 8 3.3V 3 + 1 IRLR024N 2 - LM358 VLIN3 + 4 1.5V 2.5V 330uF IRLR024N + IRLR024N 330uF + + 330uF 330uF 1 www.semtech.com Revision: July 28, 2005 SC1185 & SC1185A POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability. Pl arameter Sm ymbo Ms aximu Unit VV CC to GND -V 0.3 to +7 IN PGND to GND +1 V BST to GND -V 0.3 to +15 OT perating Temperature Range 0C to +70 ° A JT unction Temperature Range 0C to +125 ° J ST torage Temperature Range -C 65 to +150 ° STG LT ead Temperature (Soldering) 10 Sec. 3C 00 ° L Thermal Impedance Junction to Ambient θ 8W 0 °C/ JA Thermal Impedance Junction to Case 2W 5 °C/ θ JC Electrical Characteristics Unless specified: V = 4.75V to 5.25V; GND = P = 0V; V = V ; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; T = 0 to 70°C CC GND OSENSE O A Ps arameter Cn ondition Mp i Tx y Ms a Unit Switching Section OI utput Voltage=e 2A in Application Circuit See Output Voltage Tabl O SC upply VoltageV5 C 47 . V SV upply CurrentV8 CC = 5.0 1A5 m LI oad Regulation=1 0.8A to 15A % O Line Regulation +50% .1 Current Limit Voltage 60 0 758V m Oscillator Frequency 10 25 10 4 1z 6 kH Oscillator Max Duty Cycle 95 09% P, eak DH Sink/Source CurrentBV STH - DH = 4.5V DH - PGNDH = 3.1 1 A DH - PGNDH = 1.5v 100 mA P, eak DL Sink/Source CurrentBV STL - DL = 4.5V DL - PGNDL = 3.1 1 A DL - PGNDL = 1.5V 100 mA Gain (A)V to V 3B 5 d OL OSENSE O Vx ID Source Current V< ID21 .4V 1A0 µ Vx ID Leakage V< ID20 .4V 1A µ Power good threshold voltage 80 8 12 0 1% 1 Dead time 40 01s 0 n www.semtech.com  2005 Semtech Corp. 2 SC1185 & SC1185A POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: V = 4.75V to 5.25V; GND = P = 0V; V = V ; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; T = 0 to 70°C CC GND OSENSE O A Ps arameter Cn ondition Mp i Tx y Ms a Unit Linear Sections QV uiescent currentL5 DOV = 12 mA Output Voltage LDO1 20 .46921 .50 2V .53 Output Voltage LDO2 10 .48119 .50 1V .51 Rf eference Voltage I< re16 00µA 15 .2414 .26 1V .28 Gain (A))L0 DOS (1, 2) to GATE (1, 2 9B d OL LI oad Regulation=3 0 to 8A 0% . O Line Regulation 0% .3 OV utput ImpedanceV1 GATE = 6.5 1.5 Ω GV ate Pulldown ImpedanceG0 ATE (1,2)-AGND; VCC=LDOV=O 8030 0 7k 5 Ω VOSENSE Impedance 1k 0 Ω NOTE: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required.  2005 Semtech Corp. 3 www.semtech.com SC1185 & SC1185A POWER MANAGEMENT Pin Configuration Ordering Information TOP VIEW (1) Pe art Number Packag Linear Temp Voltage Range (T ) J AGND 1 24 GATE2 GATE1 2 23 LDOV SC1185CSW.TR LDOS1 3 22 VID0 SV O-241C .5V2.5 0° to 125° (3) LDOS2 4 21 VID1 SC1185CSW.TRT VCC 5 20 VID2 SC1185ACSW.TR REF 6 19 VID3 SV O-241C .5V2.5 0° to 125° PWRGOOD 7 18 VID4 (3) SC1185ACSW.TRT CS- 8 17 VOSENSE CS+ 9 16 EN Notes: PGNDH 10 15 BSTH (1) Only available in tape and reel packaging. A reel contains DH 11 14 BSTL 1000 devices. PGNDL 12 13 DL (2) SC1185A provides improved output tolerance. See Output Voltage Table. (24 Pin SOIC) (3). Lead free product. This product is fully WEEE and RoHS compliant. Pin Descriptions Pe in #Pn in Nam Pin Functio 1DAd GN Small Signal Analog and Digital Groun 21G1 ATE Gate Drive Output LDO 31L1 DOS Sense Input for LDO 42L2 SOS Sense Input for LDO 5CVe C Input Voltag 6FRt E Buffered Reference Voltge outpu (1) 7D PWRGOO Open collector logic output, high if V within 10% of setpoint O 8-C) S Current Sense Input (negative 9+C) S Current Sense Input (positive 1H 0Ph GND Power Ground for High Side Switc 1H 1Dt High Side Driver Outpu 1L 2Ph GND Power Ground for Low Side Swtc 1L 3Dt Low side Driver Outpu 1L 4Br ST Supply for Low Side Drive 1H 5Br ST Supply for High Side Drive (1) 1N 6 E Logic low shuts down the converter. High or open for normal operation. 1E 7Vn OSENS Top end of internal feedback chai (1) 14 8 VID Programming Input (MSB) (1) 13 9 VID Programming Input (1) 22 0 VID Programming Input (1) 21 1 VID Programming Input (1) 20 2 VID Programming Input (LSB) 2V 3Ln DO +12V for LDO sectio 22 4G2 ATE Gate Drive Output LDO Note: (1) All logic level inputs and outputs are open collector TTL compatible. www.semtech.com  2005 Semtech Corp. 4 SC1185 & SC1185A POWER MANAGEMENT Block Diagram CS- CS+ VCC EN CURRENT LIMIT BSTH REF - 70mV + LEVEL SHIFT AND HIGH SIDE VID4 DH MOSFET DRIVE VID3 D/A VID2 R VID1 Q PGNDH OSCILLATOR S VID0 SHOOT-THRU CONTROL VOSENSE - OPEN + COLLECTORS BSTL + + - PWRGOOD - ERROR SYNCHRONOUS AMP MOSFET DRIVE DL + - AGND PGNDL LDOS1 2.5V FET 1.5V FET 1.265V CONTROLLER CONTROLLER GATE1 REF AGND LDOV REF GATE2 LDOS2 AGND  2005 Semtech Corp. 5 www.semtech.com SC1185 & SC1185A POWER MANAGEMENT Output Voltage Table Unless specified: 4.75V < VCC < 5.25V; GND = PGND = 0V; VOSENSE = V ; 0mV < (CS+-CS-) < 60mV; = 0°C < T < 85°C O j Pd arameter Sn tandar "A" Versio Vid Mp in Tx y Mn a Mp i Tx y Ms a Unit 43210 O1 utput Voltage07 11110 .27 13 .30 17 .32 10 .28 13 .30 1V .31 06 111010 .32 14 .35 17 .37 10 .33 14 .35 1.36 05 110110 .37 15 .40 16 .42 10 .38 14 .40 1.41 04 110010 .42 16 .45 16 .47 10 .43 15 .45 1.46 08 101110 .47 13 .50 15 .52 10 .48 15 .50 1.51 07 101010 .52 13 .55 15 .57 10 .53 16 .55 1.56 06 100110 .57 14 .60 14 .62 10 .58 16 .60 1.61 05 100010 .62 15 .65 14 .67 10 .63 17 .65 1.66 05 011110 .67 16 .70 13 .72 10 .68 17 .70 1.71 04 011010 .72 18 .75 13 .81 10 .73 18 .75 1.76 02 010110 .78 19 .80 12 .86 10 .78 18 .80 1.81 02 010010 .83 19 .85 12 .91 10 .83 19 .85 1.86 01 001110 .8810 .90 11 .97 10 .8819 .90 1.91 01 001010 .9310 .9521 .02 10 .9310 .95 1.97 00 000110 .98 20 .00 20 .02 10 .98 20 .00 2.02 00 000020 .03 21 .05 20 .0720 .03 21 .05 2.07 10 111110 .97 20 .00 20 .03 10 .97 20 .00 2.03 19 111020 .06 22 .10 29 .13 20 .06 22 .10 2.13 17 110120 .16 23 .20 27 .23 20 .16 23 .20 2.23 16 110020 .26 25 .30 26 .33 20 .26 25 .30 2.33 14 101120 .36 26 .40 24 .43 20 .36 26 .40 2.43 13 101020 .46 28 .50 23 .53 20 .46 28 .50 2.53 11 100120 .5629 .60 21 .63 20 .5629 .60 2.63 10 100020 .66 21 .70 20 .7420 .66 21 .70 2.74 18 011120 .75 22 .80 28 .84 20 .75 22 .80 2.84 12 011020 .84 28 .90 5220 .84 28 .90 2.95 10 010120 .94 30 .00 30 .06 20 .94 30 .00 3.06 18 010030 .03 32 .10 38 .16 30 .03 32 .10 3.16 16 001130 .13 34 .20 36 .26 30 .13 34 .20 3.26 14 001030 .23 36 .30 34 .36 30 .23 36 .30 3.36 12 000130 .33 38 .40 32 .46 30 .33 38 .40 3.46 10 000030 .43 30 .50 30 .57 30 .43 30 .50 3.57 www.semtech.com  2005 Semtech Corp. 6 SC1185 & SC1185A POWER MANAGEMENT Layout Guidelines Careful attention to layout requirements are necessary for transition switching. Connections should be as wide and successful implementation of the SC1185 PWM control- as short as possible to minimize loop inductance. Mini- ler. High currents switching at 140kHz are present in the mizing this loop area will a) reduce EMI, b) lower ground application and their effect on ground plane voltage differ- injection currents, resulting in electrically “cleaner” grounds entials must be understood and minimized. for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 1). The high power parts of the circuit should be laid out first. A ground plane should be used, the number and 3). The connection between the junction of Q1, Q2 and position of ground plane interruptions should be such as the output inductor should be a wide trace or copper re- to not unnecessarily compromise ground plane integrity. gion. It should be as short as practical. Since this connec- Isolated or semi-isolated areas of the ground plane may tion has fast voltage transitions, keeping this connection be deliberately introduced to constrain ground currents to short will minimize EMI. The connection between the out- particular areas, for example the input capacitor and bot- put inductor and the sense resistor should be a wide trace tom FET ground. or copper area, there are no fast voltage or current transi- tions in this connection and length is not so important, 2). The loop formed by the Input Capacitor(s) (Cin), the Top however adding unnecessary impedance will reduce effi- FET (Q1) and the Bottom FET (Q2) must be kept as small ciency. as possible. This loop contains all the high current, fast 12V IN 5V 10 1 24 AGND GATE2 2 23 GATE1 LDOV 3 22 2.32k LDOS1 VID0 Cin + 4 21 Q1 1.00k LDOS2 VID1 0.1uF 5 20 5mOhm VCC VID2 Vout 6 19 REF VID3 L + 7 18 Q2 0.1uF PWRGOOD VID4 Cout 8 17 CS- VOSENSE 9 16 CS+ EN 10 15 PGNDH BSTH 11 14 DH BSTL 12 13 PGNDL DL SC1185 Heavy lines indicate 3.3V Vo Lin1 high current paths. Q3 + + Cout Lin1 Cin Lin Layout Diagram SC1185(A) Vo Lin2 Q4 + Cout Lin2  2005 Semtech Corp. 7 www.semtech.com SC1185 & SC1185A POWER MANAGEMENT Layout Guidelines 4) The Output Capacitor(s) (Cout) should be located as supply through a 10Ω resistor, the Vcc pin should be close to the load as possible, fast transient load cur- decoupled directly to AGND by a 0.1µF ceramic capacitor, rents are supplied by Cout only, and connections between trace lengths should be as short as possible. Cout and the load must be short, wide copper areas to minimize inductance and resistance. 7) The Current Sense resistor and the divider across it should form as small a loop as possible, the traces run- 5) The SC1185 is best placed over a quiet ground plane ning back to CS+ and CS- on the SC1185 should run area, avoid pulse currents in the Cin, Q1, Q2 loop flowing parallel and close to each other. The 0.1µF capacitor should in this area. PGNDH and PGNDL should be returned to be mounted as close to the CS+ and CS- pins as possible. the ground plane close to the package. The AGND pin should be connected to the ground side of (one of) the 8) Ideally, the grounds for the two LDO sections should be output capacitor(s). If this is not possible, the AGND pin returned to the ground side of (one of) the output may be connected to the ground path between the Output capacitor(s). Capacitor(s) and the Cin, Q1, Q2 loop. Under no circum- stances should AGND be returned to a ground inside the Cin, Q1, Q2 loop. 6) Vcc for the SC1185 should be supplied from the 5V 5V + Vout + Currents in various parts of the power section www.semtech.com  2005 Semtech Corp. 8 SC1185 & SC1185A POWER MANAGEMENT Layout Guidelines COMPONENT SELECTION COMPONENT SELECTION COMPONENT SELECTION COMPONENT SELECTION COMPONENT SELECTION The calculated maximum inductor value assumes 100% S S SWIT WIT WITCHING SECTION CHING SECTION CHING SECTION and 0% duty cycle, so some allowance must be made. S SWIT WITCHING SECTION CHING SECTION OUTPUT CAP OUTPUT CAP OUTPUT CAP OUTPUT CAP OUTPUT CAPA A A A ACIT CIT CIT CIT CITORS ORS ORS ORS ORS - Selection begins with the most Choosing an inductor value of 50 to 75% of the calculated critical component. Because of fast transient load current maximum will guarantee that the inductor current will ramp requirements in modern microprocessor core supplies, the fast enough to reduce the voltage dropped across the ESR output capacitors must supply all transient load current at a faster rate than the capacitor sags, hence ensuring a requirements until the current in the output inductor ramps good recovery from transient with no additional excursions. up to the new level. Output capacitor ESR is therefore one of the most important criteria. The maximum ESR can be We must also be concerned with ripple current in the out- simply calculated from: put inductor and a general rule of thumb has been to allow 10% of maximum output current as ripple current. V t Note that most of the output voltage ripple is produced by R ≤ ESR I t the inductor ripple current flowing in the output capacitor Where ESR. Ripple current can be calculated from: V = Maximum transient voltage excursion t V IN I = L RIPPLE I = Transient current step t 4 ⋅L ⋅ f OSC Ripple current allowance will define the minimum permit- For example, to meet a 100mV transient limit with a 10A ted inductor value. load step, the output capacitor ESR must be less than 10mΩ. To meet this kind of ESR level, there are three PO PO PO PO POWER FETS WER FETS WER FETS - The FET WER FETS WER FETS s are chosen based on several available capacitor technologies. criteria with probably the most important being power dis- sipation and power handling capability. Each Cap. Total Qty. Technology T TOP FET OP FET C ESR C ESR T T TOP FET OP FET - The po OP FET wer dissipation in the top FET is a combi- Rqd. (µF) (mΩ) (µF) (mΩ) nation of conduction losses, switching losses and bottom FET body diode recovery losses. L0 ow ESR Tantalum 30 3 6620 000 1 a) Conduction losses are simply calculated as: O0 S-CON 35 3 2393 90 8. 2 L0 ow ESR Aluminum14 50 4573 500 8. P = I ⋅R ⋅ δ COND O DS(on) where The choice of which to use is simply a cost/performance V O δ = duty cycle ≈ issue, with Low ESR Aluminum being the cheapest, but V IN taking up the most space. b) Switching losses can be estimated by assuming a switch- ing time, if we assume 100ns then: INDUCT INDUCT INDUCT INDUCT INDUCTOR OR OR OR OR - Having decided on a suitable type and value of output capacitor, the maximum allowable value of in- −2 P = I ⋅ V ⋅10 SW O IN ductor can be calculated. Too large an inductor will pro- or more generally, duce a slow current ramp rate and will cause the output I ⋅ V ⋅(t + t ) ⋅ f capacitor to supply more of the transient load current for O IN r f OSC P = SW 4 longer - leading to an output voltage sag below the ESR c) Body diode recovery losses are more difficult to esti- excursion calculated above. mate, but to a first approximation, it is reasonable to as- sume that the stored charge on the bottom FET body di- The maximum inductor value may be calculated from: ode will be moved through the top FET as it starts to turn R C ESR on. The resulting power dissipation in the top FET will be: L ≤ ⋅ V A I t P = Q ⋅ V ⋅ f RR RR IN OSC where V is the lesser of V or () V − V A O IN O To a first order approximation, it is convenient to only con-  2005 Semtech Corp. 9 www.semtech.com SC1185 & SC1185A POWER MANAGEMENT Layout Guidelines sider conduction losses to determine FET suitability. position, power dissipation will be approximately halved For a 5V in; 2.8V out at 14.2A requirement, typical FET and temperature rise reduced by a factor of 4. losses would be: Using 1.5X Room temp R to allow for DS(ON) temperature rise. INPUT CAP INPUT CAP INPUT CAP INPUT CAP INPUT CAPA A A A ACIT CIT CIT CIT CITORS ORS ORS - since the RMS ripple current in the ORS ORS input capacitors may be as high as 50% of the output current, suitable capacitors must be chosen accordingly. FR ET type (mΩ)P(e W) Packag DS(on) D Also, during fast load transients, there may be restrictions 2 I5 RL34025 191D .6 Pak on input di/dt. These restrictions require useable energy 2 storage within the converter circuitry, either as extra out- I5 RL2203 19 0. 1D .1 Pak put capacitance or, more usually, additional input capaci- S0 i4410 2628 .2 S0- tors. Choosing low ESR input capacitors will help maximize ripple rating for a given size. BO BO BO BO BOTT TT TT TT TTOM FET OM FET OM FET - Bo OM FET OM FET ttom FET losses are almost entirely due to conduction. The body diode is forced into conduction at the beginning and end of the bottom switch conduction period, so when the FET turns on and off, there is very little voltage across it, resulting in low switching losses. Conduction losses for the FET can be determined by: 2 P = I ⋅R ⋅(1− δ) COND O DS(on) For the example above: FR ET type (mΩ)P(e W) Packag DS(on) D 2 I5 RL34025 131D .3 Pak 2 I5 RL2203 13 0. 0D .9 Pak S0 i4410 2718 .7 S0- Each of the package types has a characteristic thermal impedance, for the TO-220 package, thermal impedance is mostly determined by the heatsink used. For the sur- face mount packages on double sided FR4, 2 oz printed o circuit board material, thermal impedances of 40 C/W for 2 o the D PAK and 80 C/W for the SO-8 are readily achiev- able. The corresponding temperature rise is detailed be- low: o Temperature rise ( C) FT ET typeTT op FE Bottom FE I6 RL34025 62 7. 53. I6 RL2203 42 7. 37. S8 i4410 16 80. 141. It is apparent that single SO-8 Si4410 are not adequate for this application, but by using parallel pairs in each www.semtech.com  2005 Semtech Corp. 10 SC1185 & SC1185A POWER MANAGEMENT Typical Characteristics Typical Efficiency at Vo=3.5V Typical Efficiency at Vo=2.8V 95% 95% 90% 90% 85% 85% 80% 80% 3.5V Std 2.8V Std 3.5V Sync 2.8V Sync 3.5V Sync Lo Rds 75% 2.8V Sync Lo Rds 75% 70% 70% 0 2 4 6 8 10 12 14 16 02 46 8 10 12 14 16 Io (Amps) Io (Amps) Typical Efficiency at Vo=2.5V Typical Efficiency at Vo=2.0V 95% 95% 90% 90% 85% 85% 80% 80% 2.0V Std 2.5V Std 2.0V Sync 2.5V Sync 2.0V Sync Lo Rds 2.5V Sync Lo Rds 75% 75% 70% 70% 02 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 Io (Amps) Io (Amps) Typical Ripple, Vo=2.8V, Io=10A Transient Response Vo=2.8V, Io=300mA to 10A  2005 Semtech Corp. 11 www.semtech.com Efficiency Efficiency Efficiency Efficiency SC1185 & SC1185A POWER MANAGEMENT Typical Application Circuit www.semtech.com  2005 Semtech Corp. 12 J1 12V TABLE VALID FOR 1x5mOhm SENSE RESISTOR + C26 DROOP OFFSET R11 R15 4.7uF mV/A mV/V (Ohm) (Ohm) VID VOUT VID VOUT J21 0 0 0 EMPTY 43210 43210 1 2 2.5 10 01111 1.30 11111 NO CPU 5V 2 2 3.3 5 J16 01110 1.35 11110 2.10 5 2 EMPTY 2 01101 1.40 11101 2.20 R1 1 5 6.3 25 1 01100 1.45 11100 2.30 C1 2 5 8.3 12.5 2 01011 1.50 11011 2.40 + + 10 + + 0.1uF 5 5 EMPTY 5 3 01010 1.55 11010 2.50 C2 C3 C18 C19 1 10 12.5 50 4 01001 1.60 11001 2.60 1500uF 1500uF 1500uF 1500uF 2 10 16.7 25 01000 1.65 11000 2.70 5 10 EMPTY 10 00111 1.70 10111 2.80 CON4 00110 1.75 10110 2.90 R3 U3 00101 1.80 10101 3.00 C4 C5 EMPTY 0.1uF 5 9 00100 1.85 10100 3.10 VCC CS+ 00011 1.90 10011 3.20 0.1uF 00010 1.95 10010 3.30 7 8 PWRGOOD CS- 00001 2.00 10001 3.40 Q1 Q2 VID0 22 17 IRLR3103 IRLR3103N R4 1.00k R5 2.32k 00000 2.05 10000 3.50 VID0 VOSENSE R6 2R2 R7 2R2 VID1 21 15 VID1 BSTH R8 5mOhm VID2 20 11 VCC_CORE VID2 DH Q3 L1 1.9uH VID3 19 14 IRLR3103N VID3 BSTL J17 R9 2R2 R10 2R2 C6 C7 + + VID4 18 13 R15 R11 VID4 DL 1 Q4 See Table 2 See Table 2 + C9 + C10 2 EN 16 10 IRLR3103N 0.1uF EN PGNDH 3 C8 4 6 5 4 3 2 1 1 12 12V AGND PGNDL S1 R12 23 6 1k 1500uF 1500uF CON4 LDOV REF 1500uF 1500uF 24 2 GATE2 GATE1 8 4 3 3 U2A LDOS2 LDOS1 + 1 J18 2 SCOPE TP SC1185CS - J12 LM358 3.3V 3.3V R16 4 0 Q6 Q7 C20 + C21 + + IRLR024N C11 J13 R17 J19 C22 C23 J14 + + 330uF VLIN3 1.5V 2.5V Q5 IRLR024N + IRLR024N See Table C13 C12 R18 + + 0.1uF 330uF See Table C24 C25 + + + + C14 C15 C16 C17 330uF 330uF 1500uF 1500uF 330uF 330uF 330uF 330uF J20 1500uF 1500uF VLIN3 R17 R18 1.5V 18.7 100 J22 J23 J24 1.8V 42.2 100 J25 J15 2.5V 97.6 100 SC1185 & SC1185A POWER MANAGEMENT Materials List I. temQe tyRe eferenc Vs alu Note 15Cc 1, C4, C5, C10, C13 0.1uF Cerami C2, C3, C6, C7, C8, C9, C18, C19, C20, 22 1 1R 500uF Sanyo MV-GX or equiv. Low ES C21, C22, C23 38CF 11, C12, C14, C15, C16, C17, C24, C25 330u 41CF 26 4.7u 6 Turns 16AWG on MICROMETALS 51LH 1 1.9u T50-52D core 64QN 1, Q2, Q3, Q4 IRLR3103 73QN 5, Q6, Q7 IRLR024 81R0 1 1 91RY 3 EMPT 11 0Rk 4 1.00 11 1Rk 5 2.32 14 2R2 6, R7, R9, R10 2R 11 3Rm 8 5s mOh IRC OAR-1 Serie 12 4Re 15, R11 See Tabl 11 5Rk 12 1 11 6R0 16 12 7Re 17, R18 See Tabl 11 8U8 2 LM35 11 9US 3 SH C1185C SEMTEC  2005 Semtech Corp. 13 www.semtech.com SC1185 & SC1185A POWER MANAGEMENT Outline Drawing - SO - 24 DIMENSIONS A D INCHES MILLIMETERS e N DIM MIN NOM MAX MIN NOM MAX A .093 - .104 2.35 - 2.65 - - A1 .004 .012 0.10 0.30 - - A2 .081 .100 2.05 2.55 2X E/2 b .012 - .020 0.31 - 0.51 c .008 - .013 0.20 - 0.33 D .602 .606 .610 15.30 15.40 15.50 E1 .291 .295 .299 7.40 7.50 7.60 E1 E E .406 BSC 10.30 BSC R e .050 BSC 1.27 BSC .010 - .030 0.25 - 0.75 h J .020 - .030 0.50 - 0.75 - - L .016 .041 0.40 1.04 (.041) (1.04) L1 N 24 24 13 2 ccc C - - R .024 .035 0.60 0.90 2X N/2 TIPS - - 01 0° 8° 0° 8° e/2 aaa .004 0.10 B bbb .010 0.25 ccc D .013 0.33 h aaa C A2 A h SEATING H PLANE bxN A1 C bbb C A-B D c GAGE J PLANE 0.25 L 01 (L1) SEE DETAIL A SIDE VIEW DETAIL A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS AND TO BE DETERMINED AT DATUM PLANE -A- -B- -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-013, VARIATION AD. Land Pattern - SO - 24 X DIMENSIONS DIM INCHES MILLIMETERS (.362) (9.20) C (C) G Z G .276 7.00 P .050 1.27 X .024 0.60 Y .087 2.20 Z .449 11.40 Y P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A, RLP NO. 307A. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012-8790 Phone: (805)498-2111 FAX (805)498-3804 www.semtech.com  2005 Semtech Corp. 14