SEMTECH SC1112

SC1112 Triple Low Dropout Regulator Controllers POWER MANAGEMENT Description Features The SC1112 was designed for the latest high speed ‹‹‹‹‹ Triple linear controllers motherboards. It includes three low dropout regulator con- ‹‹‹‹‹ Selectable and adjustable output voltages trollers. The controllers provide the power for the system ‹‹ ‹‹‹ LDOs track input voltage within 200mV (Function of AGTL bus Termination Voltage, Chipset, and clock circuitry. the MOSFETs used) until regulation ‹‹‹‹‹ Integrated charge pump An adjustable controller with a 1.2V reference is available, ‹‹ ‹‹‹ Programmable power good delay signal while two selectable outputs are provided for the VTT ‹‹‹‹‹ Latched over current protection (VTT) (1.25 V or 1.5V, SC1112) or (1.2V or 1.5V, SC1112A) ‹‹‹ Pb-free package available, fully WEEE and RoHS ‹‹ and the AGP (1.5V or 3.3V). The SC1112 low dropout compliant regulators are designed to track the 3.3V power supply as the VTTIN supply is cycled On and Off. A latched short Applications circuit protection is also available for the VTT output. ® ‹‹‹‹‹ Pentium III Motherboards Other features include an integrated charge pump that ‹‹‹ Triple power supplies ‹‹ provides adequate gate drives for the external MOSFETs, and a capacitive programable delay for the power good signal. Typical Application Circuit +3.3V VTT +5V STBY 1K C1 10u R1 C3 SC1112/A POWER GOOD 0.1u C6 5VSTBY GND 330u Q2 Q3 C14 330u ADJGATE AGPGATE AGP ADJSEN AGPSEN ADJ 0.1u C11 C2 C18 CAP- VTTGATE Q1 330u C16 C17 330u 0.1u CAP+ VTTSEN RA 1u C10 FC AGPSEL VTT DELAY VTTSEL 22n C5 C19 C8 C9 RB PWRGD VTTIN C13 C12 330u 330u 0.1u 0.1u 330u VTT SELECT Signal AGP SELECT Signal 1 Revision: August 30, 2006 www.semtech.com SC1112 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Sm ymbo Ms aximu Unit 5VSTBY to GND -V 0.3 to +7 VTTSEN to GND -V 0.3 to 5 AGPSEN to GND -V 0.3 to 5 ADJSEN to GND -V 0.3 to 5 OT perating Temperature Range 0C to +70 ° A JT unction Temperature Range 0C to +125 ° J ST torage Temperature Range -C 65 to +150 ° STG LT ead Temperature (Soldering) 10 Sec. 3C 00 ° L Thermal Resistance Junction to Ambient SOIC 130 °C/W θ JA TSSOP 115 Thermal Impedance Junction to Case SOIC θ 30 °C/W JC TSSOP 38 ED SD Rating (Human Body Model) E2 S kV Electrical Characteristics Unless specified: 5VSTBY=4.75V to 5.25V; VTTIN=3.3V; T = 25°C A Pl arameter Ss ymboCn onditionMp i Tx y Ms a Unit Supply (5VSTBY) Supply Voltage 45 .75 5V .25 5VSTBY Supply Current 5V VSTBY=6 5 8 1A2 m I 5VSTBY VTT Short Circuit Protection (4) VTT Short Circuit Delay Timer Threshold 1V .5 SC Th (4) VTT Short Circuit Delay Time (Cdelay*SC )/I S SC TH SC td (4) VTT Short Circuit Delay Source Current 12 6 282A µ I SC (4) VTT Short Circuit Threshold 60 50 70 0 7V 5 m VTTSC Th VTT Power Good (5) PWRGD Delay Timer Threshold 10 .450 10 .50 1V .55 PG Delay_TH (5) PWRGD Threashold 15 .060 10 .08 1V .11 PG TH_1.2 (5) PWRGD Threashold 10 .330 10 .35 1V .39 PG TH_1.5 (5) PWRGD Delay Time (Cdelay*PG )/I S PG TH_1.2 PG td_1.2 (5) PWRGD Delay Time (Cdelay*PG )/I S PG TH_1.5 PG td_1.5 (5) PWRGD Source Current 12 6 282A µ I PG Linear Sections VTT Input Supply Threshold 12 .45 15 .5 1V .5 VTTIN TH (1)(3) Tracking Difference V = 3.30V, 2V 00 m IN Delta TRACK I = 0A O www.semtech.com  2006 Semtech Corp. 2 SC1112 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: 5VSTBY=4.75V to 5.25V; VTTIN=3.3V; T = 25°C A Pl arameter Ss ymbo Cn ondition Mp i Tx y Ms a Unit Linear Sections (Cont.) O) utput Voltage VTT (SC1112A I=6 0 to 2A, VTTSEL = LOW10 .17 14 .20 1V .22 O VTT 1.2 (SC1112) I=5 0 to 2A, VTTSEL = LOW10 .22 15 .25 1.27 O VTT 1.25 VTT I=0 0 to 2A, VTTSEL = HIGH10 .47 10 .50 1V .53 1.5 O OP utput Voltage AGP AG I=0 0 to 2A, AGPSEL = LOW10 .47 10 .50 1V .53 1.5 O AGP I=4 0 to 2A, AGPSEL = HIGH30 .233V .30 3.3 O OJ utput Voltage ADJ AI D =% 0 to 2A -) 21% .2*(1+RA/RB+V 2 O VTTSEN Bias Current Ibias 90 0 10 2 1A 4 µ VTTSEN (SC1112) VTTSEN Bias Current Ibias 15 µA VTTSEN (SC1112A) As GPSEN Bias Current Ibia 10 10 10 5 1A 7 µ AGPSEN As DJSEN Bias Current Ibia 15 µA ADJSEN Ve TT Gate Current Isourc50 VSTBY = 4.75V, Vgate = 3.0V 5A 0 µ VTTgate Isink 5A 00 µ VTTgate Ae GP Gate Current Isourc50 VSTBY = 4.75V, Vgate = 3.0V 5A 0 µ AGPgate Isink 5A 00 µ AGPgate Ae DJ Gate Current Isourc50 VSTBY = 4.75V, Vgate = 3.0V 5A 0 µ ADJgate Isink 5A 00 µ ADJgate LD oad Regulation LOA VTTIN = 3.30V, I=3 0 to 2A 0% . REG O LE ine Regulation LIN VTTIN = 3.13V to 3.47V, 0% .3 REG Io = 2A (2) Gain (AOL) GAINL0 DOS Output to GATE 5B d LDO Notes: (1) All electrical characteristics are for the application circuit on page 19. (2) Guaranteed by design (3) Tracking Difference is defined as the delta between 3.3V Vin and the VTT, AGP, ADJ output voltages during the linear ramp up until regulation is achieved. The Tracking Voltage difference might vary depending on MOSFETs Rdson, and Load Conditions. (4) During power up, an internal short circuit glitch timer will start once the VTT Input Voltage exceeds the VTTIN (1.5V). During the glitch TH timer immunity time, determined by the Delay capacitor (Delay time is approximately equal to (Cdelay*SCTH)/ISC), the short circuit protection is disabled to allow VTT output to rise above the trip threshold (0.7V). If the VTT output has not risen above the trip threshold after the immunity time has elapsed, the VTT output is latched off and will only be enabled again if either the VTT input voltage or the 5VSTBY is cycled. (5) PWRGD pin is kept low during the power up, until the VTT output has reached its PG or PG level. At that time the PWRGD td1.2 td1.5 source current I (20uA) is enabled and will start charging the external PWRGD delay capacitor connected to the DELAY pin. Once the PG capacitor is charged above the PG (1.5V), the PWRGD pin is released from ground. Delay_TH  2006 Semtech Corp. 3 www.semtech.com SC1112 POWER MANAGEMENT Timing Diagrams NORMAL STARTUP CONDITION VTTIN VTTIN=1.5V VTT The delay capacitor does not begin charging until VTTIN has reached 1.5V and VTT is above the powergood threshold of 1.08V. Once DELAY reaches 1.5V, the PWRGD signal goes high. DELAY DELAY=1.5V VTTGATE initially turns on hard, until VTT reaches regulation. Then VTTGATE drops to its normal regulating level. PWRGD VTTGATE SHORT-CIRCUIT STARTUP VTTIN VTTIN=1.5V VTT The delay capacitor does not begin charging until VTTIN has reached 1.5V and VTT is below the short circuit threshold of 0.7V. VTTGATE initially turns on hard and is latched off when DELAY DELAY reaches 1.5V and VTT is below DELAY=1.5V 0.7V PWRGD VTTGATE www.semtech.com  2006 Semtech Corp. 4 SC1112 POWER MANAGEMENT Timing Diagrams (Cont.) SHORT-CIRCUIT DURING NORMAL OPERATION VTTIN VTT Once VTT drops out of VTT=0.7V VTT=1.08V regulation, VTTGATE turns on harder to try and raise VTT. When VTT drops below 1.08V, the delay capacitor is discharged and PWRGD goes low. When VTT drops below DELAY 0.7V, the delay capacitor DELAY=1.5V begins charging. If VTT is still below 0.7V when DELAY reaches 1.5V, VTTGATE is latched off. PWRGD VTTGATE SHORT-CIRCUIT AND RECOVERY DURING NORMAL OPERATION VTTIN Once VTT drops out of VTT regulation, VTTGATE turns on harder to try and raise VTT. When VTT drops below 1.08V, VTT=1.08V VTT=0.7V VTT=1.08V the delay capacitor is discharged and PWRGD goes low. When VTT drops below 0.7V, the delay capacitor begins charging. If VTT recovers above 0.7V DELAY before DELAY reaches 1.5V, DELAY=1.5V DELAY is again discharged. If VTT reaches 1.08V the delay capacitor begins charging and normal operation continues. PWRGD VTTGATE  2006 Semtech Corp. 5 www.semtech.com SC1112 POWER MANAGEMENT Pin Configuration Ordering Information Temp (1)(2) Top View Part Number Package Range (T ) J SC1112STR 1 16 5VSTBY GND (3) 2 15 SC1112STRTSC O-16 0° to 125° PWRGD VTTIN 3 14 DELAY VTTGATE SC1112ASTR 4 13 VTTSEL VTTSEN SC1112TSTR 5 12 AGPGATE AGPSEL (3) SC1112TSTRTTC SSOP-16 0° to 125° 6 11 ADJGATE AGPSEN SC1112ATSTR 7 10 ADJSEN FC 8 9 CAP+ CAP- Sd C1112EVB Evaluation Boar Notes: (16-Pin SOIC or TSSOP) (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Part Number (SO-16): SC1112STR and SC1112STRT = 1.25V and SC1112ASTR = 1.2V. Part Number (TSSOP-16): SC1112TSTR = 1.25V and SC1112ATSTR = 1.2V. (3) Pb-free product. This product is fully WEEE and RoHS compliant. www.semtech.com  2006 Semtech Corp. 6 SC1112 POWER MANAGEMENT Pin Descriptions Pe in #Pn in Nam Pin Functio 1Y 5VSTB 5V Standby input, supplies power for Ref, Charge Pump, Oscillator and FET controllers. 2DP. WRG Open collector Power Good Flag for VTT output 3Y DELA A capacitor from this pin to GND will program the delay for the Power Good Flag of VTT output and the glitch immunity time. 4L VTTSE TTL signal that programs the VTT output voltage: VTTSEL = LOW, VTT = 1.2XV VTTSEL = HIGH, VTT = 1.5V 5L AGPSE TTL signal that programs the AGP output voltage: AGPSEL = LOW, AGP = 1.5V AGPSEL = HIGH, AGP = 3.3V 6EA. DJGAT Gate drive output for AGP 7NA. DJSE Sense input for ADJ 8-C. AP Negative connection to boost capacitor 9+C. AP Positive connection to boost capacitor 1C 0 F Filter capacitor for the internal charge pump should be connected from this pin to GND. 1N 1A. GPSE Sense input for AGP 1E 2A. GPGAT Gate drive output for AGP 1N 3V. TTSE Sense input for VTT 1E 4V. TTGAT Gate drive output for VTT 1N 5V. TTI Short circuit sense line connected to the 3.3Vin 1D 6 G. N Ground NOTE: (1) All logic level inputs and outputs are open collector TTL compatible.  2006 Semtech Corp. 7 www.semtech.com SC1112 POWER MANAGEMENT Block Diagram 5VSTBY VTTSEL FC 1.5V 1.5V + Bandgap VTTGATE 1.35V _ Reference Disable1.5 1.2V + _ + VTTSEN - 1.08V Vref 1.2V + 0.7V _ Disable1.2 + _ S Q VTTIN R DELAY FC 1.5V _ 1.5V + AGPGATE + _ Disable1.5 + _ AGPSEN Vref + _ Disable3.3 0.7V Oscillator + _ VTTSEN FC ChargePump PWRGD + _ Pwrgd Threshold 1.2V + ADJGATE _ ADJSEN GND AGPSEL CAP+ CAP- www.semtech.com  2006 Semtech Corp. 8 SC1112 POWER MANAGEMENT Typical Characteristics VTT(1.5V) Output Voltage @ Io = 0A vs Ta VTT(1.5V) Output Voltage @ Io = 2A vs Ta 1.5035 1.5055 1.5050 1.5030 1.5045 1.5025 1.5040 1.5020 1.5035 1.5015 1.5030 1.5010 1.5025 1.5005 5V Stby = 5.25V 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 5.00V 5V Stby = 4.75V 5V Stby = 4.75V 1.5020 1.5000 1.5015 1.4995 0 10 20304050 6070 0 10 20304050 6070 Ta (°C.) Ta (°C.) VTT(1.25V) Output Voltage @ Io = 0A vs Ta VTT(1.5V) Output Voltage @ Io = 2A vs Ta 1.2465 1.2485 1.2460 1.2480 1.2455 1.2475 1.2450 1.2470 1.2445 1.2465 1.2440 1.2460 1.2435 1.2455 5V Stby = 5.25V 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 5.00V 5V Stby = 4.75V 5V Stby = 4.75V 1.2430 1.2450 1.2425 1.2445 0 1020 3040 506070 0 10 20304050 6070 Ta (°C.) Ta (°C.) VTT Input Supply Threshold vs Ta VTT Sense Bias current vs Ta 1.498 116 5V Stby = 5.25V 5V Stby = 5.00V 1.497 5V Stby = 4.75V 114 1.496 112 1.495 110 1.494 108 1.493 5V Stby = 4.75V 5V Stby = 5.00V 5V Stby = 5.25V 106 1.492 1.491 104 0 102030 40 506070 0 10203040 506070 Ta (°C.) Ta (°C.)  2006 Semtech Corp. 9 www.semtech.com VTT (V) VTT (V) 1.5 1.2 VTTIN (V) TH VTT (V) 1.5 VTT (V) 1.2 Ibias (uA) VTTSEN SC1112 POWER MANAGEMENT Typical Characteristics (Cont.) VTT Gate Current @ Vgate = 3V, 5V Stby = 4.75V vs Ta VTT Short circuit Delay source current vs Ta 800 23.60 5V Stby = 5.25V Source current 5V Stby = 5.00V 5V Stby = 4.75V Sink current 23.40 750 23.20 700 23.00 650 22.80 600 22.60 22.40 550 22.20 500 22.00 450 21.80 400 21.60 0 102030 40 50 6070 0 102030 40 506070 Ta (°C.) Ta (°C.) VTT Short circuit Delay Time (Cdelay = 0.1uF) vs Ta 8.40 8.30 8.20 8.10 8.00 7.90 5V Stby = 4.75V 5V Stby = 5.00V 5V Stby = 5.25V 7.80 7.70 0 1020 30 405060 70 Ta (°C.) VTT Short circuit Delay Timer Threshold vs Ta 1.515 1.510 1.505 1.500 1.495 1.490 1.485 1.480 1.475 5V Stby = 4.75V 5V Stby = 5.00V 5V Stby = 5.25V 1.470 1.465 0 102030 40 506070 Ta (°C.) www.semtech.com  2006 Semtech Corp. 10 I (uA) VTT_Gate I (uA) SC (V) SC th SC (mS) td SC1112 POWER MANAGEMENT Typical Characteristics (Cont.) VTT (1.25V) Power Good Threshold vs Ta VTT (1.25V) Power Good Delay Time vs Ta 1.098 8.40 1.096 8.30 1.094 8.20 1.092 8.10 1.090 1.088 8.00 1.086 7.90 5V Stby = 4.75V 1.084 5V Stby = 5.00V 5V Stby = 5.25V 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V 7.80 1.082 1.080 7.70 0 10 2030 4050 6070 0 102030 40506070 Ta (°C.) Ta (°C.) VTT (1.5V) Power Good Threshold vs Ta VTT (1.5V) Power Good Delay Time vs Ta 8.40 1.361 1.360 8.30 1.359 1.358 8.20 1.357 8.10 1.356 1.355 8.00 1.354 7.90 1.353 5V Stby = 4.75V 5V Stby = 5.00V 1.352 5V Stby = 5.25V 5V Stby = 5.25V 7.80 5V Stby = 5.00V 5V Stby = 4.75V 1.351 1.350 7.70 0 102030 405060 70 0 102030 405060 70 Ta (°C.) Ta (°C.) VTT Power Good Source current vs Ta 23.60 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V 23.40 23.20 23.00 22.80 22.60 22.40 22.20 22.00 21.80 21.60 21.40 0 10203040506070 Ta (°C.)  2006 Semtech Corp. 11 www.semtech.com PGTH_1.25(V) PG (V) TH_1.5 PGtd_1.25(mS) IPG(uA) PG (mS) td_1.5 SC1112 POWER MANAGEMENT Typical Characteristics (Cont.) AGP (1.5V) Output Voltage @ Io = 0A vs Ta AGP (1.5V) Output Voltage @ Io = 2A vs Ta 1.5055 1.5035 1.5050 1.5030 1.5045 1.5025 1.5040 1.5020 1.5035 1.5015 1.5030 1.5010 1.5025 1.5005 1.5020 1.5000 1.5015 1.4995 5V Stby = 5.25V 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 5.00V 5V Stby = 4.75V 5V Stby = 4.75V 1.5010 1.4990 1.5005 1.4985 0 10203040 506070 0 10203040506070 Ta (°C.) Ta (°C.) AGP (3.3V) Output Voltage @ Io = 0A vs Ta AGP (3.3V) Output Voltage @ Io = 2A vs Ta 3.2900 3.2900 3.2890 3.2890 3.2880 3.2880 3.2870 3.2870 3.2860 3.2860 3.2850 3.2850 3.2840 3.2840 5V Stby = 5.25V 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 5.00V 5V Stby = 4.75V 5V Stby = 4.75V 3.2830 3.2830 3.2820 3.2820 0 10203040506070 0 10203040 506070 Ta (°C.) Ta (°C.) AGP Sense Bias current vs Ta AGP Gate Current @ Vgate = 3V, 5V Stby = 4.75 vs Ta 142 900 5V Stby = 5.25V Sink current 5V Stby = 5.00V 5V Stby = 4.75V Source current 140 850 138 800 136 750 134 700 132 650 130 128 600 0 102030405060 70 0 1020 30405060 70 Ta (°C.) Ta (°C.) www.semtech.com  2006 Semtech Corp. 12 AGP (V) AGP (V) 1.5 3.3 IbiasAGPSEN (uA) AGP (V) 1.5 AGP (V) 3.3 I (uA) AGP_Gate SC1112 POWER MANAGEMENT Typical Characteristics (Cont.) ADJ (1.2V) Output Voltage @ Io = 0A vs Ta ADJ (1.2V) Output Voltage @ Io = 2A vs Ta 1.2020 1.1955 1.1950 1.2010 1.1945 1.2000 1.1940 1.1990 1.1935 1.1980 1.1930 1.1970 5V Stby = 5.25V 1.1925 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 5.00V 5V Stby = 4.75V 1.1960 5V Stby = 4.75V 1.1920 1.1950 1.1915 0 1020 3040 5060 70 0 1020 3040 5060 70 Ta (°C.) Ta (°C.) ADJ Sense Bias current vs Ta ADJ Gate Current @ Vgate = 3V, 5V Stby = 4.75V vs Ta 350 900 5V Stby = 4.75V Sink current 5V Stby = 5.00V 5V Stby = 5.25V 330 Source current 850 310 290 800 270 250 750 230 700 210 190 650 170 150 600 0 1020 3040 506070 0 102030 40506070 Ta (°C.) Ta (°C.)  2006 Semtech Corp. 13 www.semtech.com ADJ (V) 1.2 Ibias (uA) ADJSEN ADJ (V) 1.2 I (uA) ADJ_Gate SC1112 POWER MANAGEMENT Typical Characteristics (Cont.) I 5V Stby vs Ta Output Select Threshold vs Ta 7.50 1.60 VTTSEL AGPSEL 7.30 1.55 7.10 1.50 6.90 1.45 6.70 6.50 1.40 6.30 1.35 6.10 1.30 5.90 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V 1.25 5.70 5.50 1.20 0 1020 30 40 506070 0 1020 30 40 506070 Ta (°C.) Ta (°C.) Line Regulation VTTIN = 3.13V to 3.47V Io = 2A vs Ta Load Regulation VTTIN = 3.3V Io = 0 to 2A vs Ta 180.0E-3 160.0E-3 170.0E-3 140.0E-3 160.0E-3 120.0E-3 150.0E-3 100.0E-3 140.0E-3 80.0E-3 130.0E-3 60.0E-3 120.0E-3 40.0E-3 VTT 1.25V VTT 1.25V AGP 1.25V AGP 1.25V 110.0E-3 20.0E-3 100.0E-3 000.0E+0 0 10 2030 40506070 0 10203040 50 6070 Ta (°C.) Ta (°C.) Charge Pump Output Voltage vs Ta Charge Pump Frequency vs Ta 9.32 375 V Charge Pump Charge Pump Frequency 9.31 370 9.30 9.29 365 9.28 9.27 360 9.26 9.25 355 9.24 9.23 350 9.22 345 9.21 0 10203040 5060 70 0 1020 3040 5060 70 Ta (°C.) Ta (°C.) www.semtech.com  2006 Semtech Corp. 14 I5vstby (mA) V Charge Pump(V) Line Regulation(%) Output Select Threshold (V) Charge Pump Frequency (kHz) Load Regulation(%) SC1112 POWER MANAGEMENT Typical Gain & Phase Margin SC1112 Gain / Phase VTT = 1.25V @ 2A SC1112 Gain / Phase VTT = 1.5V @ 2A 60 200 60 200 Gain Gain Phase (deg) Phase (deg) 180 50 180 50 Gain 160 160 Gain 40 40 140 140 30 30 120 120 Phase 20 20 Phase 100 100 10 10 80 80 0 0 60 60 -10 -10 40 40 -20 -20 20 20 -30 0 -30 0 10 100 1000 10000 100000 1000000 10 100 1000 10000 100000 1000000 Freq (Hz) Freq (Hz) SC1112 Gain / Phase AGP = 1.5V @ 2A SC1112 Gain / Phase ADJ = 1.2V @ 2A 50 200 50 200 Gain Gain Phase (deg) Phase (deg) 180 180 40 40 Gain Gain 160 160 30 140 30 140 20 120 120 20 Phase Phase 10 100 100 10 80 80 0 60 60 0 -10 40 40 -10 -20 20 20 -30 0 -20 0 10 100 1000 10000 100000 1000000 10 100 1000 10000 100000 1000000 Freq (Hz) Freq (Hz)  2006 Semtech Corp. 15 www.semtech.com Gain (dB) Gain (dB) Phase (deg) Phase (deg) Gain (dB) Gain (dB) Phase (deg) Phase (deg) SC1112 POWER MANAGEMENT Applications Infomation Theory Of Operation Also included is an overcurrent protection circuit that The SC1112 was designed for the latest high speed mother monitors the VTT voltage. If the output voltage drops boards requiring a controlled power up sequencing of below 700mV, as would occur during an overcurrent or the Outputs, and a programmable delay for the Power short condition, the device will pull the drive pin low and good signal. latch off the output. Three Linear controllers have been incorporated into the Fixed Output Voltage Options (VTT, AGP) SC1112. The VTT output can be programmed to either a 1.250V or a 1.500V by applying a LOW or a HIGH control Please refer to the Application Circuit on Page 1. The VTT signal to the VTTSEL pin. AGP output can also be pro- and the AGP fixed output voltage can be programed from grammed via AGPSEL pin to a 1.50V or a 3.30V. The a Control logic signal. Table below shows the possible SC1112 also provides an Adjustable output which utilizes voltages: a resistive voltage divider. VL TTSELAT GPSEVP T AG The +5VSTBY supply will power the internal Reference, Charge Pump, Oscillator, and the Fet controllers. After 00 1V .25V 1.50 the +5VSTBY has been established, LDO outputs will track 01 1V .25V 3.30 the VTTIN (3.30V) supply as it is applied. 10 1V .50V 1.50 11 1V .50V 3.30 An external capacitor connected to the Delay pin will pro- gram the VTT short circuit delay time (SC ), and the PWRGD td Once the VTTSEL or the AGPSEL signal is established, an delay time (PG ). td internal resistive divider is used to compare the bandgap reference voltage with the feedback output voltage. The During power up, an internal short circuit glitch timer will drive pin voltage is then adjusted to start once the VTT Input Voltage exceeds the VTTIN (1.5V). TH maintain the output voltage set by the internal resistor During the glitch timer immunity time, determined by the divider. Referring to the block diagram on page 8. Delay capacitor (Delay time is approximately equal to (Cdelay*SCTH)/ISC), the short circuit protection is disabled It is possible to adjust the output voltage of the VTT or to allow VTT output to rise above the trip threshold (0.7V). AGP, by applying an external resistor divider to the sense pin (please refer to Figure 1 on Page 17). Since the sense If the VTT output has not risen above the trip threshold pin sinks a nominal 100µA, the resistor after the immunity time has elapsed, the VTT output is values should be selected to allow 10mA to flow through latched off and will only be enabled again if either the VTT the divider. This will ensure that variations in this current input voltage or the 5VSTBY is cycled. do not adversely affect output voltage regulation. Thus a target value for R2 (maximum) can be calculated: PWRGD pin is kept low during the power up, until the VTT output has reached its PG or PG level. At that time td1.25 td1.5 V the PWRGD source current I (20uA) is enabled and will OUT (FIXED ) PG R2 ≤ Ω 10mA start charging the external PWRGD delay capacitor The output voltage can only be adjusted upwards from connected to the DELAY pin. Once the capacitor is charged the fixed output voltage, and can be calculated using the above the PG (1.5V), the PWRGD pin is released from Delay_TH following equation: ground. A detailed timing diagram is shown on pages 4 to 5.  R1  V = V • 1+  + R1• 100 µA Volts OUT ( ADJUSTED ) OUT (FIXED ) R2   www.semtech.com  2006 Semtech Corp. 16 SC1112 POWER MANAGEMENT Applications Infomation (Cont.) +3.3V +5V STBY C1 10u C3 SC1112 0.1u 5VSTBY GND Q3 C14 330u ADJGATE AGPGATE AGP ADJSEN AGPSEN C2 C18 CAP- VTTGATE Q1 330u C16 C17 330u 0.1u CAP+ VTTSEN FC AGPSEL VTT DELAY VTTSEL C19 C8 C9 PWRGD VTTIN 330u 330u 0.1u R1 VTT SELECT Signal AGP SELECT Signal R2 Figure 1: Adjusting The Output Voltage of VTT or AGP Adjustable Output Voltage Option The adjustable output voltage option does not have an internal resistor divider. The adjust pin connects directly to the inverting input of the error amplifier, and the output voltage is set using external resistors (please refer to Figure 2). In this case, the adjust pin sources a nominal 0.5µA, so the resistor values should be selected to allow 50µA to flow through the divider. Again, a target VTT value for RB (maximum) can be 1K calculated: R1 SC11 POWER GOOD C6 1.200 V 5VSTBY 330u Q2 RB ≤ Ω 50µA ADJGATE ADJSEN 0.1u C11 CAP- The output voltage can be calculated as follows: CAP+ RA 1u C10 RA   FC V = 1.200 • 1+ − 0.5µA • RA   OUT DELAY RB   22n C5 RB PWRGD C13 C12 0.1u 330u The maximum output voltage that can be obtained from the adjustable option is determined by the input supply voltage and the R and gate threshold voltage of the DS(ON) external MOSFET. Assuming that the MOSFET gate Figure 2 threshold voltage is sufficiently low for the output voltage chosen and a worst-case drive voltage of 9V, V OUT(MAX) is given by: V = VTTIN −I •R OUT(MAX) (MIN) OUT(MAX) DS(ON)(MAX)  2006 Semtech Corp. 17 www.semtech.com SC1112 POWER MANAGEMENT Applications Infomation (Cont.) Layout Guidelines Short Circuit Protection The VTT short circuit protection feature of the SC1112 One of the advantages of using the SC1112 to drive an external MOSFET is that the bandgap reference and is implemented by using the R of the MOSFET. As DS(ON) control circuitry do not need to be located right next to the the output current increases, the regulation loop main- power device, thus a very accurate output voltage can be tains the output voltage by turning the FET on more and obtained since heating effects will be minimal. more. Eventually, as the R limit is reached, the MOS- DS(ON) FET will be unable to turn on any further, and the output The 0.1µF bypass capacitor should be located close to the voltage will start to fall. When the VTT output voltage falls +5VSTBY supply pin, and connected directly to the ground to approximately 700mV, the LDO controller is latched off, plane. The ground pin of the device should also be con- setting output voltage to 0V. Power must be cycled to re- nected directly to the ground plane. The sense or adjust set the latch. pin does not need to be close to the output voltage plane, To prevent false latching due to capacitor inrush currents but should be routed to avoid noisy traces if at all pos- or low supply rails, the current limit latch is initially sible. disabled. It is enabled once the short circuit delay time has elapsed. Timing diagram on pages 4 to 5 will show a Power dissipation within the device is practically detailed operation of the Short Circuit protection circuitry. negligible, requiring no special consideration during To be most effective, the MOSFET R should not be layout. DS(ON) selected artificially low. The MOSFET should be chosen so that at maximum required current, it is almost fully turned on. If, for example, a supply of 1.5V at 4A is required from a 3.3V ± 5% rail, the maximum allowable R would be: DS(ON) () 0.95 • 3.3 − 1.5 • 1.025 R = ≈ 400 m Ω DS (ON )(MAX ) 4 To allow for temperature effects 200mΩ would be a suitable room temperature maximum, allowing a peak short circuit current of approximately 15A for a short time before shutdown. Capacitor Selection Output Capacitors: Low ESR aluminum electrolytic or tan- talum capacitors are recommended for bulk capacitance, with ceramic bypass capacitors for decoupling high frequency transients. Input Capacitors: Placement of low ESR aluminum electrolytic or tantalum capacitors at the input to the MOSFET (VTTIN) will help to hold up the power supply during fast load changes, thus improving overall transient response. The +5VSTBY supply should be bypassed with a 10µF ceramic capacitor. www.semtech.com  2006 Semtech Corp. 18 SC1112 POWER MANAGEMENT Evaluation Board Gerbers Board Layout Assembly Bottom Board Layout Assembly Top Board Layout Top Board Layout Bottom  2006 Semtech Corp. 19 www.semtech.com SC1112 POWER MANAGEMENT Evaluation Board Schematic www.semtech.com  2006 Semtech Corp. 20 +5VSTBY J1 +5VSTBY C1 10uF J2 GND +3.3V +3.3V J3 C3 +3.3V J4 0.1uF C4 + C2 + C18 VTT 0.1uF 330uF 330uF J5 GND POWER GOOD R1 J7 GND J6 1k U1 SC1112CS 1 16 5VSTBY GND 2 15 Q1 PWRGD VTTIN IRFR120N C5 22nF 3 14 DELAY VTTGATE C6 C7 + 100k R2 VTT 330uF 0.1uF 4 13 VTT VTTSEL VTTSEN J8 100k R3 5 12 J9 VTT AGPSEL AGPGATE Q2 C9 + C8 + C19 IRFR120N 6 11 0.1uF 330uF 330uF J10 ADJGATE AGPSEN GND ADJ 7 10 ADJ J12 J11 GND ADJSEN FC C10 8 9 ADJ J13 CAP- CAP+ ** 1uF RA VTT SELECT Signal J14 C12 C13 + ** ADJ = 1.2*(1+RA/RB) 330uF 0.1uF AGP SELECT Signal C11 0.1uF C15 C14 + 0.1uF 330uF J15 ** Q3 RB IRFR120N J16 GND * * 1 1 JP1 JP2 AGP J17 AGP GND J18 J19 AGP * JP1 = OPEN, VTT = 1.5 V C17 C16 + 2 2 0.1uF 330uF J20 GND * JP1 = SHORT, VTT = 1.25 V J21 GND * JP2 = OPEN, AGP = 3.3 V * JP2 = SHORT, AGP = 1.5 V SC1112 POWER MANAGEMENT Evaluation Board Bill of Materials I. temQe tyRt eferenc Pt ar Foot Prin 11CF 1 16 0u 120 28CF 2,C6,C8,C12,C14,C16,C18,C1931 30u CPCYL/D.2.75/LS.100/.03 38CF 3,C4,C7,C9,C11,C13,C15,C17 05 .1u 080 41CF 5 25 2n 080 51CF 10 15 u 080 62J2 P1,JP2 TP P VIA/2 71JY 1 +2 5VSTB ED505 89JD 2,J5,J7,J10,J12,J16,J17,J20,J21G2 N ED505 92JV 3,J4 +2 3.3 ED505 11 0Jd 6 P2 ower Goo ED505 12 1JT 8,J9 V2 T ED505 12 2JJ 11,J12 A2 D ED505 11 3Jl 14 V2 TT SELECT Signa ED505 11 4Jl 15 A2 GP SELECT Signa ED505 12 5JP 18,J19 A2 G ED505 13 6QN 1,Q2,Q3 IT RFR120 DPAKFE 13 7Rk 1,RA,RB 15 080 12 8Rk 2,R3 15 00 080 11 9UT 1 S6 C1112STR SO-1  2006 Semtech Corp. 21 www.semtech.com SC1112 POWER MANAGEMENT Outline Drawing - TSSOP-16 DIMENSIONS A INCHES MILLIMETERS DIM D MIN NOM MAX MIN NOM MAX e - - - - A .047 1.20 N - - A1 .002 .006 0.05 0.15 - - A2 .031 .042 0.80 1.05 2X E/2 - - b .007 .012 0.19 0.30 c - .003 - .007 0.09 0.20 E1 D .192 .196 .201 4.90 5.00 5.10 E E1 .169 .173 4.30 .177 4.40 4.50 PIN 1 E .252 BSC 6.40 BSC INDICATOR e .026 BSC 0.65 BSC L .018 .024 .030 0.45 0.60 0.75 (.039) (1.0) ccc C 1 2 3 L1 e/2 N 16 16 2X N/2 TIPS - - 01 0° 8° 0° 8° B aaa .004 0.10 bbb .004 0.10 ccc .008 0.20 D aaa C A2 A SEATING PLANE H C A1 bxN c bbb C A-B D GAGE PLANE 0.25 L 01 (L1) DETAIL A SEE DETAIL A SIDE VIEW NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS AND TO BE DETERMINED AT DATUM PLANE -A- -B- -H- DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS 3. OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AB. Land Pattern - TSSOP-16 X DIMENSIONS DIM INCHES MILLIMETERS C (.222) (5.65) (C) G .161 4.10 G Z P .026 0.65 X .016 0.40 .061 1.55 Y Y Z .283 7.20 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. www.semtech.com  2006 Semtech Corp. 22 SC1112 POWER MANAGEMENT Outline Drawing - SO-16 DIMENSIONS INCHES MILLIMETERS A DIM MIN NOM MAX MIN NOM MAX D e - - A .053 .069 1.35 1.75 N - - A1 .004 .010 0.10 0.25 - - A2 .049 .065 1.25 1.65 - - 2X E/2 b .012 .020 0.31 0.51 - - c .007 .010 0.17 0.25 E1 E D .386 .390 .394 9.80 9.90 10.00 .150 .154 .157 3.80 3.90 4.00 E1 E .236 BSC 6.00 BSC e .050 BSC 1.27 BSC - - h .010 .020 0.25 0.50 12 3 ccc C L .016 .028 .041 0.40 0.72 1.04 (.041) (1.04) 2X N/2 TIPS e/2 L1 N 16 16 - - B 01 0° 8° 0° 8° aaa .004 0.10 bbb .010 0.25 D ccc .008 0.20 aaa C A2 A h SEATING PLANE C A1 h bxN H bbb C A-B D c GAGE PLANE 0.25 L 01 (L1) A SEE DETAIL SIDE VIEW DETAIL A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS AND TO BE DETERMINED AT DATUM PLANE -A- -B- -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-012, VARIATION AC. Minimum Land Pattern - SO-16 X DIMENSIONS DIM INCHES MILLIMETERS (.205) (5.20) C (C) G .118 3.00 G Z P .050 1.27 X .024 0.60 Y .087 2.20 Y Z .291 7.40 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A, RLP NO. 304A. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2006 Semtech Corp. 23 www.semtech.com