SEMTECH SC1109

SC1109 Synchronous PWM Controller with Dual Low Dropout Regulator Controllers POWER MANAGEMENT Description Features The SC1109 was designed for the latest high speed ‹ Dual linear controllers motherboards. It combines a synchronous voltage mode ‹ LDOs track input voltage within 200mV (function of controller (switching section) with two low-dropout linear the MOSFETs used) until regulation regulator controllers. The voltage mode controller pro- ‹ Integrated drivers vides the power supply for the system AGTL bus. The Dual ‹ Power good signal (SC1109A, SC1109B) linear controllers power the chip set and clock circuitry. ‹ Soft start ‹ Lossless current sense The SC1109A switching section features lossless current ‹ Programmable over current limit (SC1109C) sensing, while SC1109C provides programmable over cur- ‹ 200kHz (SC1109A, SC1109C), and 500kHz (SC1109B) rent limit. SC1109 also utilizes latched driver outputs for fixed frequency. enhanced noise immunity. SC1109A and SC1109C oper- ate at a fixed frequency of 200kHz, and the SC1109B is available at a fixed frequency of 500kHz. The VTT output Applications voltage is internally fixed at 1.2V ® ‹‹‹‹‹ Pentium III Motherboards The SC1109 linear sections are low dropout regulators ‹‹ ‹‹‹ Triple power supplies designed to track the 3.3V power supply when it turns on or off. The voltage for the linear controllers LDO1, and LDO2 are 1.8V/1.5V. Typical Application Circuit 12V IN 5V STBY C1 0.1uF 5V IN C2 C3 SC1109ACSTR or SC1109BCSTR C4 2x1500uF + 0.1uF 0.1uF 11 3 VCC STBY C5 0.1uF 4 10 BCAP+ BST Q1 R1 2.2 C6 9 MOSFET N DH 0.1uF L1 4uH 5 7 1.2V 6A BCAP- PHASE VTT 14 C7 C8 SS/EN Q2 3x1500uF + 0.1uF R2 2.2 12 8 MOSFET N POWER GOOD PWRGD DL 13 6 VOSENSE GND C9 0.1uF 15 2 GATE2 GATE1 16 1 LDOS2 LDOS1 U1 3.3V IN Q3 Q4 C10 MOSFET N MOSFET N + 330uF LDO1 = 1.8V LDO2 = 1.5V + C11 + C12 330uF 330uF 12V IN 5V STBY C1 0.1uF 5V IN C2 C3 U1 C4 2x1500uF + 0.1uF 0.1uF 11 3 VCC STBY C13 1nF R3 C5 TBD 0.1uF 4 10 BCAP+ BST Q1 R1 2.2 C6 9 MOSFET N DH 0.1uF L1 4uH 1.2V 6A 5 7 BCAP- PHASE VTT 14 C7 C8 SS/EN Q2 3x1500uF 0.1uF + R2 2.2 12 8 MOSFET N OCSET OCSET DL 13 6 VOSENSE GND C9 0.1uF 15 2 GATE2 GATE1 16 1 LDOS2 LDOS1 SC1109CCSTR 3.3V IN Q3 Q4 MOSFET N MOSFET N + C10 330uF LDO1 = 1.8V LDO2 = 1.5V C11 C12 + + 330uF 330uF 1 Revision: May 13, 2004 www.semtech.com SC1109 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pl arameter Sm ymbo Ms aximu Unit VD CC to GN -V 0.3 to +7 STBY to GND -V 0.3 to +7 BST to GND -V 0.3 to +20 PHASE to GND -V 1 to +15 LDOSx -V 0.3 to 5 OT perating Temperature Range 0C to +70 ° A JT unction Temperature Range 0C to +125 ° J ST torage Temperature Range -C 65 to +150 ° STG LT ead Temperature (Soldering) 10 Seconds 3C 00 ° L Thermal Resistance Junction to Ambient 1W 30 °C/ θ JA Thermal Impedance Junction to Case 3W 0 °C/ θ JC Electrical Characteristics Unless specified: VOSENSE = V ; Vcc=4.75V to 5.25V; STBY=4.75V to 5.25V; BST = 11.4V to 12.6V; T = 0 to 70°C O A Pl arameter Ss ymbo CN ondition MP I TX YMS A UNIT Supply (V ) CC SV upply Voltage 45 .4 5V .25 CC SI upply Quiescent Current V=8 5V, SS/EN = 0V 1A2 m CCQ CC (1) Supply Operating Current I V=0 5V, SS/EN > 1V 2A m CC CC Switching Section (1) Output Voltage V I=8 2A 10 .1812 .201V .21 TT O (1) Load Regulation( LOAD I=1 0A to 6A % REG O (1) Line Regulation LINEV5 in = 4.75V to 5.25V ±% 0.1 REG S5 C1109A 10 7 25 0 2z 2 kH Of scillator Frequency S0 C1109B 40 5 50 0 5z 5 kH OSC S5 C1109C 10 7 25 0 2z 2 kH OD scillator Max Duty Cycle 9509% S0 C1109A 10 8 20 0 2V 2 m Vtrip Ilimit Current Limit trip (Vin-V ) S0 C1109B 10 8 20 0 2V 2 m PHASE Itrip S2 C1109C 10 1 18 6 2A 0 u Ilimit (3) OscillatorGain (A ) GAIN VOSENSE to V 3B 5 d OL VTT O Under Voltage Lock Out TC hreshold VC 31 .9 44 . 4V . HIGH HC ysteresis VC 2V 00 m HYST Power Good PG ower Good Threshold Voltage P 82 8 1% 1 th Soft Start / Enable (2) SS/EN Source current Isource V=5 1.5V 120 1A µ SS/EN SS/EN (2) SS/EN Sink current Isink V=1 1.5V 23 µA SS/EN SS/EN SV hutdown Voltage 60 00 6V 5 m SS/EN www.semtech.com  2004 Semtech Corp. 2 SC1109 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: VOSENSE = V ; Vcc=4.75V to 5.25V; STBY=4.75V to 5.25V; BST = 11.4V to 12.6V; T = 0 to 70°C O A Pl arameter Ss ymbo CN ondition MP I TX Y MS A UNIT Internal Drivers Pe eak DH Source Current IsourcB0 ST-DH = 4.5V5A 0 m DH D0 H-PHASE = 3.1V5A 0 m Pk eak DH Sink Current Isin DH D0 H-PHASE = 1.5V1A 0 m Pe eak DL Source Current IsourcV0 CC-DL = 4.5V5A 0 m DL D0 L-GND = 3.1V5A 0 m Pk eak DL Sink Current Isin DL D0 L-GND = 1.5V1A 0 m DT ead time 40 01s 0 n DEAD Linear Sections SV tandby Voltage 45 .4 5V .25 STBY SI tandby Quiescent currentV9 STBY = 5V, SS/EN = 0V mA STDBYQ (1)(4) Tracking Difference Delta 2V 00 m TRACK OV utput Voltage LDO1 I=2 0 to 4A, Vin = 3.3V 18 .7814 .81 1V .85 LDO1 O OV utput Voltage LDO2 I=0 0 to 4A, Vin = 3.3V 10 .4710 .50 1V .53 LDO2 O LD oad Regulation LOA I=3 0 to 4A, Vin = 3.3V 0% . REG O LE ine Regulation LINI3 o = 2A, Vin = 3.13V to 3.47V 0% . REG (3) LDOS(1,2) Input Impedance Z 1k 0 Ω IN (3) Gain (AOL) GAINL0 DOS (1,2) to GATE (1,2) 5B d LDO Notes: (1) All electrical characteristics are for the application circuit on page 16. (2) Soft start function is performed after Vcc is above the UVLO and SS/EN is above 600mV. The Soft start capacitor is then charged at a 10uA constant current until SS/EN is charged to above 1V. (3) Guaranteed by design (4) Tracking Difference is defined as the delta between 3.3V Vin and the LDO1, LDO2 output voltages during the linear ramp up until regulation is achieved. The tracking voltage difference might vary depending on MOSFETs RdS , and load conditions. ON (5) This device is ESD sensitive. Use of standard ESD handling precautions is required.  2004 Semtech Corp. 3 www.semtech.com SC1109 POWER MANAGEMENT Pin Configuration Top View Top View 1 16 LDOS1 LDOS2 1 16 LDOS1 LDOS2 2 15 GATE1 GATE2 GATE1 2 15 GATE2 3 14 STBY SS/EN 3 14 STBY SS/EN 4 13 BCAP+ VOSENSE 4 13 VOSENSE BCAP+ 5 12 BCAP- PWRGD 12 5 OCSET BCAP- 6 11 GND VCC 6 11 GND VCC 7 10 PHASE BST 7 10 PHASE BST 8 9 DL DH 8 9 DL DH (SC1109A/B) (SC1109C) Ordering Information Linear PWM Over Temp (1) Part Number Package Voltage Frequency Current set Range (T ) J S6 C1109ACSTRSV O-11z .8V/1.52l 00kHIC nterna 0° to 125° S6 C1109BSTRSV O-11z .8V/1.55l 00kHIC nterna 0° to 125° Note: S6 C1109CSTRSV O-11z .8V/1.52l 00kHEC xterna 0° to 125° (1) Only available in tape and reel Sd C1109EVB Evaluation Boar packaging. A reel contains 2500 devices. Pin Descriptions Pe in #Pn in Nam Pin Functio 11L. DOS Sense Input for LDO1 21G. ATE Gate Drive Output LDO1 (1.8V) 3Y STB 5V Standby Input, supplies power for Ref, Charge Pump, Oscillator and FET controllers. Should be present prior to other voltages and switched off last. 4+B. CAP Positive Connection to Boost Capacitor 5-B. CAP Negative Connection to Boost Capacitor 6DG. N Ground 7EP. HAS Phase Node 8LD. Low Side Driver Output 9HD. High Side Driver Output 1T 0 B. S Boost Input 1C 1V. C Power Supply Input 1D 2 PWRG Open Colector Power Good Flag for 1.2V Outpu t(SC1109A, and SC1109B). OCSET Over current set pin for the PWM (SC1109C). A resistor to the Mosfe'ts supply will program the over current level. 1E 3V. OSENS Output Sense Input for 1.2V Output 1N 4S. S/E Soft Start/Enable 12 5G. ATE Gate Drive output LDO2 (1.5V) 12 6L. DOS Sense Input for LDO2 www.semtech.com  2004 Semtech Corp. 4 SC1109 POWER MANAGEMENT Block Diagram VCC VBG 200mV UVLO 1.2V + OVER + Bandgap CURRENT - - -10% BST +10% HIGH SIDE DRIVE DH - PWRGD + OSCILLATOR PHASE SHOOT - THRU CONTROL + PWM VCC - ERROR AMP R - VOSENSE + Q + VBG VCC LOW S DL SET DOMINATES SIDE DRIVE S 10uA Q 0.8V + GND SC1109A/B R SS/EN - HICCUP LATCH FAULT LOW SIDE OFF SS/EN + 0.6V - 5VSTBY 2uA 5VSTBY VBG + GATE2 - 5VSTBY LDOS2 5VSTBY CHARGE PUMP STBY OSCILLATOR VBG + GATE1 - BCAP+ LDOS1 BCAP- VCC 160uA VBG UVLO 1.2V + OVER + OCSET Bandgap CURRENT - - BST HIGH SIDE DRIVE DH OSCILLATOR PHASE SHOOT THRU CONTROL PWM VCC - R ERROR AMP - VOSENSE + Q + VBG VCC LOW SET DOMINATES S DL SIDE DRIVE S 10uA Q 0.8V SC1109C + GND R SS/EN - HICCUP LATCH FAULT LOW SIDE OFF SS/EN + 0.6V - 5VSTBY 2uA 5VSTBY VBG + GATE2 - 5VSTBY LDOS2 CHARGE 5VSTBY PUMP STBY OSCILLATOR VBG + GATE1 - BCAP+ LDOS1 BCAP- Marking Information SC1109ACS SC1109BS SC1109CS yyww SC1109A yyww SC1109B yyww SC1109C xxxxx xxxxx xxxxx yyww = Datecode (Example: 9912) xxxxx = Semtech Lot # (Example: 90101)  2004 Semtech Corp. 5 www.semtech.com SC1109 POWER MANAGEMENT Application Information THEORY OF OPERATION The gate drive status stays the same until the capacitors voltage reaches 1V, when the error amplifier output starts The SC1109 has integrated a synchronous buck control- to cross the oscillator triangular ramp of 1V to 2V. ler and two Low drop out regulator controllers into a 16 Pin SOIC package. The switching regulator provides a 1.2V As the SS/EN pin continues to rise, the error amplifier (VTT) bus termination voltage for use in AGTL (Assisted output also rises at the same rate and the duty cycle Gunning Transceiver Logic), while the dual LDO regulators increases. provide 1.5V, and 1.8V to power up the Chip set and the ® Clock circuitry used in Pentium III Motherboards. Once the VTT output has reached regulation and is within 1.2V ± 12% , an open collector power good flag is acti- SUPPLIES vated, and the error amplifier output will no longer be clamped to the SS/EN voltage and will stay between 1V Two supplies, VSTBY, and VCC are used to power the to 2V and maintain regulation of ± 1%. The SS/EN volt- SC1109 . VSTBY supply provides the bias for the Internal age continues to rise up to 2.5V and will stay at that Reference, Oscillator, and the LDO FET controllers. This voltage level during normal operation. supply should always be brought up first and turned off last in accordance with PC power configuration require- ments. The VCC supply provides the bias for the Power Vcc Good circuitry, and the high side FET Rdson sensing/ over current circuitry, VCC also is used to drive the low side MOSFET gate. An external 12V supply or a classical boot strapping technique can provide the gate drive for PowerGood the upper Mosfet. PWM CONTROLLER Softstart SC1109 is a voltage mode buck controller that utilizes an internally compensated high bandwidth error amplifier to sense the VTT output voltage. External compensation com- PhaseNode ponents are not needed and a stable closed loop re- sponse is insured due to the internal compensation. If an over current condition occurs, the SS/EN pin will START UP SEQUENCE discharge by a 2µA current source, from 2.5V to 800mV. Initially during the power up, the SC1109 is in under volt- During this time both DH, and DL will be turned off. Once age lockout condition. The latch (SET dominant) in the the SS/EN reaches 800mV, the low side gate will be hiccup section is set , and the SS/EN pin is pulled low by turned on, and the SS/EN pin will again start to be charged the 2µA soft start current source. by the 10µA current source, and the same soft start se- quence mentioned above will be repeated. Mean while, the high side and low side gate drivers DH, and DL are kept low. Once the VCC exceeds the UVLO OVER CURRENT threshold of 4.2V, the latch is reset and the external soft start capacitor starts to be charged by a 10µA current SC1109A/B monitor the Upper MOSFETs Rdson voltage source. drop due to an over current condition. This method of cur- rent sensing minimizes any unnecessary losses due to ex- The gate drives are still kept off until the soft start ca- ternal sense resistance. pacitors voltage rises above 600mV, when the low side gate is turned on, and the high side gate is kept off. www.semtech.com  2004 Semtech Corp. 6 SC1109 POWER MANAGEMENT Application Information (Cont.) An internal comparator with a 200mV reference moni- GATE DRIVERS tors the Drop across the upper FET, Once the Vdson of the MOSFET exceeds the 200mV limit, the low side gate The Low side gate driver is supplied from VCC and provide is turned on and the upper FET is turned off. Also an a peak source/sink current of and 500mA. internal latch is set and the soft start capacitor is dis- The high side gate drive is also capable of sourcing and charged. Once the lower threshold of the soft start cir- sinking peak currents of 500mA. The high side MOSFET cuit is crossed, the same softstart sequence mentioned gate drive can be provided by an external 12V supply that previously is repeated. This sequence is repeated until is connected from BST to GND. The actual gate to source the over condition is removed. voltage of the upper MOSFET will approximately equal 7V (12V-VCC). If the external 12V supply is not available, a classical boot strap technique can be implemented Upper Gate from the VCC supply. A boot strap capacitor is connected from BST to Phase while VCC is connected through a diode (Schottky or other fast low VF diode) to the BST. Lower Gate This will provide a gate to source voltage approximately to VCC-Vdiode drop. PhaseNode Lo w er Gat e Lo w er Gat e PhaseNode Vtt Sho rted Shoot through control circuitry provides a 100ns dead time to ensure both upper and lower MOSFET will not turn on Upper Gate simultaneously and cause a shoot through condition. Lo w er Gate DUAL LDO CONTROLLERS SC1109 also provides two low drop out linear regulator controllers that can be used to generate a 1.8V and a 1.5V output. The LDO output voltage is achieved by con- trolling the voltage drop across an external MOSFET from a 3.3V supply voltage. The SC1109C utilizes an internal current source and an external resistor connected from the OCSET pin to the The output voltage is sensed at the LDOS pin of the SC1109 Mosfet’s supply to program a current limit level. This limit and compared to an internal reference. The gate drive to is programmable by choosing the resistor according to the external MOSFET is then adjusted until regulation is the level required. To reduce any noise pick up a 1nF achieved. In order to have sufficient voltage to the gate capacitor should be placed across the programing resis- drives of the external MOSFET, an internal charge pump is tor. The device operation is similar to the SC1109A/B utilized to boost the gate drive voltage to about two times during the over current condition as mentioned above. the VSTBY.  2004 Semtech Corp. 7 www.semtech.com SC1109 POWER MANAGEMENT Application Information (Cont.) LAYOUT GUIDELINES The internal charge pump charges an external Bucket Careful attention to layout requirements are necessary capacitor to VSTBY and then connects it in series with for successful implementation of the SC1109 PWM con- VSTBY to the LDOs supply at a frequency of about troller. High currents switching are present in the appli- 200kHz. This ensures sufficient gate drive voltage for cation and their effect on ground plane voltage differen- the LDOs independent of the VCC or the 12V external tials must be understood and minimized. supply being available due to start up timing sequence 1). The high power parts of the circuit should be laid out from the silver box. first. A ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. 3.3V Vin Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, for example the input capacitor and bottom FET ground. 1.8V Vout 2). The loop formed by the Input Capacitor(s) (Cin), the Top FET (Q1) and the Bottom FET (Q2) must be kept as 1.5V Vout small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically “cleaner” grounds for the rest of the system and c) minimize source The LDO1, and LDO2 output voltages are forced to track ringing, resulting in more reliable gate switching signals. the 3.3V input supply. This feature ensures that during 3). The connection between the junction of Q1, Q2 and the output inductor should be a wide trace or copper the start up application of the 3.3V, the LDO1, and LDO2 region. It should be as short as practical. Since this con- outputs track the 3.3V within 200mV typical until regula- nection has fast voltage transitions, keeping this con- tion is achieved. However, the VSTBY should be established at least 500us, to allow the charge pump to reach its nection short will minimize EMI. Also keep the Phase con- maximum voltage, before the linear section will track within nection to the IC short, top FET gate charge currents flow in this trace. 200mV. This tracking will sequence the correct start up timing for the external Chipset and Clock circuitry. 12V IN 5V STBY 5V IN U4 SC1109A VCC STBY + BCAP+ BST DH BCAP- PHASE VTT SS/EN PWRGD DL + VOSENSE GND GATE2 GATE1 LDOS2 LDOS1 3.3V IN Heavy Lines indicate high current paths. 1.5V 1.8V C10 + + + 330uF www.semtech.com  2004 Semtech Corp. 8 SC1109 POWER MANAGEMENT Application Information (Cont.) 6) BST for the SC1109 should be supplied from the 12V 4) The Output Capacitor(s) (Cout) should be located as supply, the BST pin should be decoupled directly to GND close to the load as possible, fast transient load cur- rents sre supplied by Cout only, and connections between by a 0.1mF ceramic capacitor, trace lengths should be as short as possible. If a 12V supply is not available, a classi- Cout and the load must be short, wide copper areas to cal boot strap method could be implemented to achieve minimize inductance and resistance. the upper MOSFETs gate drive. 5) The SC1109 is best placed over a quiet ground plane 7) The Phase connection should be short . area, avoid pulse currents in the Cin, Q1, Q2 loop flowing in this area. GND should be returned to the ground plane 8) Ideally, the grounds for the two LDO sections should be returned to the ground side of (one of) the output close to the package and close to the ground side of capacitor(s). (one of) the output capacitor(s). If this is not possible, the GND pin may be connected to the ground path be- tween the Output Capacitor(s) and the Cin, Q1, Q2 loop. Under no circumstances should GND be returned to a ground inside the Cin, Q1, Q2 loop. 5V + Vout +  2004 Semtech Corp. 9 www.semtech.com SC1109 POWER MANAGEMENT Application Information (Cont.) COMPONENT SELECTION The maximum inductor value may be calculated from: SWITCHING SECTION R C ESR L ≤ () V − V OUTPUT CAPACITORS - Selection begins with the most IN O I t critical component. Because of fast transient load cur- The calculated maximum inductor value assumes 100% rent requirements in modern microprocessor core sup- duty cycle, so some allowance must be made. Choosing plies, the output capacitors must supply all transient load an inductor value of 50 to 75% of the calculated maxi- current requirements until the current in the output in- mum will guarantee that the inductor current will ramp ductor ramps up to the new level. Output capacitor ESR fast enough to reduce the voltage dropped across the is therefore one of the most important criteria. The maxi- ESR at a faster rate than the capacitor sags, hence en- mum ESR can be simply calculated from: suring a good recovery from transient with no additional V excursions. We must also be concerned with ripple cur- t R ≤ ESR rent in the output inductor and a general rule of thumb I t has been to allow 10% of maximum output current as Where ripple current. Note that most of the output voltage ripple V = Maximum transient voltage excursion is produced by the inductor ripple current flowing in the t output capacitor ESR. Ripple current can be calculated I = Transient current step t from: V IN I = For example, to meet a 100mV transient limit with a 10A L RIPPLE 4 ⋅ L ⋅ f OSC load step, the output capacitor ESR must be less than Ripple current allowance will define the minimum permit- 10mΩ. To meet this kind of ESR level, there are three ted inductor value. available capacitor technologies. POWER FETS - The FETs are chosen based on several Each Total criteria with probably the most important being power Capacitor Qty dissipation and power handling capability. Technology Rqd. C ESR C ESR (uF) (mΩ) (uF) (mΩ) TOP FET - The power dissipation in the top FET is a com- bination of conduction losses, switching losses and bot- L0 ow ESR Tantalum30 3 6620 000 1 tom FET body diode recovery losses. O0 S-CON 35 3 23 93 90 8. a) Conduction losses are simply calculated as: L0 ow ESR Aluminum14 50 4578 500 8. 2 P = I ⋅ R ⋅ δ COND O DS ( on ) The choice of which to use is simply a cost/performance issue, with Low ESR Aluminum being the cheapest, but where taking up the most space. V O δ = duty cycle ≈ V IN INDUCTOR - Having decided on a suitable type and value of output capacitor, the maximum allowable value of in- b) Switching losses can be estimated by assuming a ductor can be calculated. Too large an inductor will pro- switching time, if we assume 100ns then: duce a slow current ramp rate and will cause the output − 3 P = I ⋅ V ⋅ 10 SW O IN capacitor to supply more of the transient load current for longer - leading to an output voltage sag below the ESR excursion calculated above. www.semtech.com  2004 Semtech Corp. 10 SC1109 POWER MANAGEMENT Application Information (Cont.) or more generally, FR ET Type (mΩ)P(e W) Packag DS(on) D I ⋅ V ⋅ (t + t ) ⋅ f O IN r f OSC P = SW 2 4 I5 RL3402S131D .3 PAK c) Body diode recovery losses are more difficult to esti- 2 I5 RL220313 0. 0D .9 PAK mate, but to a first approximation, it is reasonable to assume that the stored charge on the bottom FET body S0 i44102718 .7 SO- diode will be moved through the top FET as it starts to turn on. The resulting power dissipation in the top FET will be: Each of the package types has a characteristic thermal impedance, for the TO-220 package, thermal impedance P = Q ⋅ V ⋅ f RR RR IN OSC is mostly determined by the heatsink used. For the sur- face mount packages on double sided FR4, 2 oz printed To a first order approximation, it is convenient to only o circuit board material, thermal impedances of 40 C/W consider conduction losses to determine FET suitability. 2 o for the D PAK and 80 C/W for the SO-8 are readily achiev- For a 5V in; 2.8V out at 14.2A requirement, typical FET able. The corresponding temperature rise is detailed be- losses would be: low: Using 1.5X Room temp R to allow for temperature DS(ON) 0 rise. Temperature rise ( C) FT ET TypeTT op FE Bottom FE FR ET Type (mΩ))Pe D(W Packag DS(on) I6 RL3402S62 7. 53. 2 I5 RL3402S191D .6 PAK I6 RL2203 42 7. 37. 2 I5 RL220319 0. 1D .1 PAK S8 i4410 16 80. 141. S0 i44102628 .2 SO- It is apparent that single SO-8 Si4410 are not adequate BOTTOM FET - Bottom FET losses are almost entirely for this application, but by using parallel pairs in each due to conduction. The body diode is forced into conduc- position, power dissipation will be approximately halved tion at the beginning and end of the bottom switch con- and temperature rise reduced by a factor of 4. duction period, so when the FET turns on and off, there is very little voltage across it, resulting in low switching INPUT CAPACITORS - since the RMS ripple current in the losses. Conduction losses for the FET can be determined input capacitors may be as high as 50% of the output by: current, suitable capacitors must be chosen accordingly. Also, during fast load transients, there may be restric- 2 P = I ⋅ R ⋅ (1 − δ ) COND O DS ( on ) tions on input di/dt. These restrictions require useable energy storage within the converter circuitry, either as For the example above: extra output capacitance or, more usually, additional in- put capacitors. Choosing low ESR input capacitors will help maximize ripple rating for a given size.  2004 Semtech Corp. 11 www.semtech.com Phase Margin (Deg.) SC1109 POWER MANAGEMENT SC1109 Gain & Phase Margin SC1109A Gain & Phase Margin 50 200 180 40 160 30 Gain 140 20 120 100 Phase Margin 10 80 0 60 -10 40 -20 20 10 100 1,000 10,000 100,000 frequency(Hz) Typical VTT Gain/Phase plot at Vin = 5V, Iout = 3A www.semtech.com  2004 Semtech Corp. 12 Gain (dB) SC1109 POWER MANAGEMENT Typical Characteristics SC1109 Quiescent Current (Linear) vs Ta SC1109 Quiescent Current vs Ta 7.90 4.45 Vcc = 5.25 7.85 4.40 Vcc = 4.75 7.80 4.35 7.75 4.30 7.70 4.25 7.65 4.20 4.15 7.60 4.10 7.55 4.05 7.50 Vcc = 5.25 4.00 7.45 Vcc = 4.75 3.95 7.40 0 10203040506070 0 10 20304050 6070 Ta (°C.) Ta (°C.) Typical ISTBYQ (Linear section) Typical Icc (Switching section) SC1109 Soft start Source Current vs Ta SC1109 Soft start Source Current vs Ta 9.32 8.10 Vcc = 5.25V , Vss = 0V Vcc = 4.75V , Vss = 1.5V 9.30 8.08 Vcc = 4.75V , Vss = 0V Vcc = 5.25V , Vss = 1.5V 9.28 8.06 9.26 8.04 9.24 8.02 9.22 8.00 9.20 7.98 9.18 7.96 9.16 9.14 7.94 0 102030 40506070 0 102030 40506070 Ta (°C.) Ta (°C) Typical Soft start source Current Vss = 1.5V Typical Soft start source Current Vss = 0V SC1109 Soft start Sink Current vs Ta SC1109 Soft start Sink Current vs Ta 1.80 9.30 Vcc = 5.25V , Vss = 0V Vcc = 4.75V , Vss = 1.5V 9.28 1.79 9.26 Vcc = 4.75V , Vss = 0V Vcc = 5.25V , Vss = 1.5V 9.24 1.79 9.22 9.20 1.78 9.18 9.16 1.78 9.14 9.12 1.77 9.10 1.77 9.08 0 102030 40506070 0 102030 40506070 Ta (°C.) Ta (°C.) Typical Soft start sink Current Vss = 1.5V Typical Soft start sink Current Vss = 0V  2004 Semtech Corp. 13 www.semtech.com Iss (uA) Iss (uA) Icc (mA) Iss (uA) Iss (uA) ISTBYQ (mA) SC1109 POWER MANAGEMENT Typical Characteristics SC1109 Tracking Difference (Io LDO1,2 = 2A) vs Ta 280.0 260.0 240.0 220.0 200.0 LDO2 Vcc = 4.75 LDO2 Vcc = 5.25 180.0 LDO1 Vcc = 4.75 LDO1 Vcc = 5.25 160.0 0 1020 30 4050 6070 Ta (°C.) Typical Tracking difference (BetweenVin3.3 & LDO) www.semtech.com  2004 Semtech Corp. 14 Delta (mV) SC1109 POWER MANAGEMENT Typical Characteristics SC1109 (VTT) Line Reg. vs Vin (Iout = 6.0A) SC1109 (VTT) Eff. vs Iout (Vin = 5.0V) 90.0% 0.350% 80.0% 0.300% 70.0% 0.250% 60.0% 0.200% 50.0% 0.150% 40.0% 30.0% 0.100% IRL3103R(V1.8,V2.5 No load) 20.0% 0.050% IRL3103R(V1.8,V2.5 No load) 10.0% 0.000% 0.0% 4.000 4.500 5.000 5.500 6.000 6.500 7.000 0.00 2.00 4.00 6.00 8.00 Vin (V) Iout_Vtt (Amps) Typical VTT Efficiency at Vin=5V Typical VTT Line Regulation at Iout = 6 Amps SC1109 (VTT) Line Reg. vs Vin (Iout = 3.0A) SC1109 (VTT) Load Reg. vs Iout (Vin = 5.0V) 0.000% 0.120% IRL3103R(V1.8,V2.5 No load) -0.100% 0.100% 0.080% -0.200% 0.060% -0.300% 0.040% -0.400% 0.020% IRL3103R(V1.8,V2.5 No load) -0.500% 0.000% -0.600% 4.700 4.800 4.900 5.000 5.100 5.200 5.300 0.00 2.00 4.00 6.00 8.00 Vin (V) Iout_Vtt (Amps) Typical VTT Line Regulation at Iout = 3 Amps Typical VTT Load Regulation at Vin=5V  2004 Semtech Corp. 15 www.semtech.com Load Reg.(%) Efficiency(%) Line Reg.(%) Line Reg.(%) SC1109 POWER MANAGEMENT Evaluation Board Schematic 12V IN J1 GND J2 5V STBY J3 GND J4 C1 0.1uF 5V IN J5 R5 5V IN J6 C2 C3 0 C4 0.1uF U1 SC1109A/B 0.1uF + 11 3 VCC STBY R1 1500uF 10k C5 C6 + 0.1uF 4 10 Q1 BCAP+ BST 1500uF IRLR3103 VTT R2 0 C7 9 J7 DH 0.1uF L1 4uH R4 2.2 GND J8 1.2V 6A 5 7 BCAP- PHASE J9 J10 GND 14 D1 C11 VTT SS/EN Q2 C8 + C9 + C10 + 0.1uF R3 0 12 8 IRLR3103 POWER GOOD J11 PWRGD DL D1N4148 1500uF 1500uF 1500uF 13 6 GND VOSENSE GND C16 C12 J12 0.1uF 0.1uF 15 2 GATE2 GATE1 J13 16 1 LDOS2 LDOS1 GND 3.3V IN J14 Q3 Q4 IRLR3103 IRLR3103 + C13 1.5V 330uF 1.8V J15 J16 C14 C15 + + GND 330uF 330uF GND GND J17 J18 J19 J1 12V IN J2 GND 5V STBY J3 GND J4 C1 0.1uF 5V IN J5 R5 5V IN J6 C2 C3 0 C4 + 0.1uF U1 SC1109C 0.1uF C16 11 3 VCC STBY 1nF R1 1500uF TBD C5 + C6 0.1uF 4 10 Q1 BCAP+ BST 1500uF IRLR3103 VTT R2 0 C7 9 J7 DH 0.1uF L1 4uH R4 2.2 GND J8 5 7 1.2V 6A J9 BCAP- PHASE J10 GND 14 D1 C11 VTT SS/EN Q2 C8 C9 C10 0.1uF + + + R3 0 12 8 IRLR3103 OCSET J11 OCSET DL D1N4148 1500uF 1500uF 1500uF 13 6 GND VOSENSE GND C12 J12 0.1uF 15 2 GATE2 GATE1 J13 16 1 LDOS2 LDOS1 GND 3.3V IN J14 Q3 Q4 C13 IRLR3103 IRLR3103 + 1.5V 330uF 1.8V J15 J16 C14 C15 + + 330uF 330uF GND GND GND J17 J19 J18 www.semtech.com  2004 Semtech Corp. 16 SC1109 POWER MANAGEMENT Evaluation Board Bill of Materials I. temQe ty Referenc Part 18CF 1,C3,C4,C6,C7,C11,C12,C13 0.1µ 25CF 2,C5,C8,C9,C10 1500µ 33CF 13,C14,C15 330µ 41 C16 0.1uF(SC1109A/B), 1nF(SC1109C) 51D8 1 D1N414 61JN 1 12V I 79JD 2,J4,J8,J10,J12,J13,J17,J18,J19 GN 81JY 3 5V STB 92JN 5,J6 5V I 12 0JT 7,J9 VT 11 1 J11 POWER GOOD / OCSET 11 2JN 14 3.3V I 11 3JV 15 2.5 11 4JV 16 1.8 11 5LH 1 4µ 14 6Q3 1,Q2,Q3,Q4 IRLR310 11 7 R1 10k (SC1109A/B), TBD(SC1109C) 13 8R0 2,R3,R5 11 9R2 4 2. 21 0UC 1 SC1109A/B/  2004 Semtech Corp. 17 www.semtech.com SC1109 POWER MANAGEMENT Evaluation Board Gerber Plots Board Layout Assembly Top Board Layout Bottom Board Layout Top www.semtech.com  2004 Semtech Corp. 18 SC1109 POWER MANAGEMENT Outline Drawing - SO-16 Land Pattern - SO-16 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2004 Semtech Corp. 19 www.semtech.com