Model 71660 4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - XMC General Information generator, and a PCIe interface complete the ® Model 71660 is a member of the Cobalt factory-installed functions and enable the 71660 to operate as a complete turnkey family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multi- solution without the need to develop any channel, high-speed data converter, it is FPGA IP. suitable for connection to HF or IF ports of a Extendable IP Design communications or radar system. Its built- For applications that require specialized in data capture features offer an ideal function, users can install their own custom turnkey solution as well as a platform for developing and deploying custom FPGA IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory- processing IP. installed modules as documented source It includes four A/Ds and four banks of memory. In addition to supporting PCI Ex- code. Developers can integrate their own IP with the Pentek factory-installed functions press Gen. 2 as a native interface, the Model or use the GateFlow kit to completely replace 71660 includes general purpose and gigabit serial connectors for application-specific I/O . the Pentek IP with their own. The Cobalt Architecture Xilinx Virtex-6 FPGA The Pentek Cobalt Architecture features The Virtex-6 FPGA can be populated with a variety of different FPGAs to match a Virtex-6 FPGA. All of the board’s data and the specific requirements of the processing control paths are accessible by the FPGA, enabling factory-installed functions including task. Supported FPGAs include: LX130T LX240T, LX365T, SX315T, or SX475T. The data multiplexing, channel selection, data SXT parts feature up to 2016 DSP48E slices packing, gating, triggering and memory control. The Cobalt Architecture organizes and are ideal for modulation/demodulation, encoding/decoding, encryption/decryption, the FPGA as a container for data processing and channelization of the signals between applications where each function exists as an intellectual property (IP) module. transmission and reception. For applications not requiring large DSP resources, one of Each member of the Cobalt family is the lower-cost LXT FPGAs can be installed. delivered with factory-installed applications ideally matched to the board’s analog Option -104 installs the P14 PMC connec- tor with 20 pairs of LVDS connections to interfaces. The 71660 factory-installed the FPGA for custom I/O. functions include four A/D acquisition IP modules. Option -105 installs the P16 XMC connec- Features tor with one 8X or two 4X gigabit links to IP modules for either DDR3 or QDRII+ ■ Complete radar and software the FPGA to support serial protocols. memories, a controller for all data clocking ➤ radio interface solution and synchronization functions, a test signal ■ Supports Xilinx Virtex-6 LXT and SXT FPGAs RF In RF In RF In RF In ■ Four 200 MHz 16-bit A/Ds ■ Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM RF RF RF RF XFORMR XFORMR XFORMR XFORMR Sample Clk / ■ Sample clock synchronization to Reference Clk In an external system reference Gate / Trigger / TIMING BUS A/D Clock/Sync Bus Sync / PPS GENERATOR 200 MHz 200 MHz 200 MHz 200 MHz ■ LVPECL clock/sync bus for 16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT A/D TTL Gate / Trig Clock / Sync / multimodule synchronization Gate / PPS TTL Sync / PPS ■ PCI Express (Gen. 1 & 2) Sample Clk 16 16 16 16 Reset interface up to x8 Gate A Gate B ■ VITA 42.0 XMC compatible Sync / PPS A VIRTEX-6 FPGA Sync / PPS B with switched fabric interfaces VCXO LX130T, LX240T, LX365T, SX315T or SX475T Timing Bus ■ User-configurable gigabit GTX GTX GTX LVDS serial interface 16 16 16 16 16 16 16 16 16 ■ LVDS connections to the 40 8X 4X 4X Virtex-6 FPGA for custom I/O QDRII+ QDRII+ QDRII+ QDRII+ Config SRAM SRAM SRAM SRAM FLASH 8MB 8MB 8MB 8MB 64 MB QDRII+ option 150 QDRII+ option 160 x8 PCIe Gigabit FPGA Serial I/O DDR3 option 155 DDR3 option 165 GPIO (option 105) (option 104) DDR3 DDR3 DDR3 DDR3 SDRAM SDRAM SDRAM SDRAM P15 P16 P14 512 MB 512 MB 512 MB 512 MB XMC XMC PMC Memory Banks1&2 Memory Banks3&4 One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ New! New! New! New! New! Model 71660 4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - XMC ➤ ➤ A/D Converter Stage ➤ ➤ ➤ LVPECL bus can drive the timing signals The front end accepts four full-scale for synchronizing multiple modules. analog HF or IF inputs on front panel SSMC Multiple 71660’s can be driven from the connectors at +8 dBm into 50 ohms with LVPECL bus master, supporting synchro- transformer coupling into four Texas nous sampling and sync functions across Instruments ADS5485 200 MHz, 16-bit all connected modules. A/D converters. Memory Resources The digital outputs are delivered into the Virtex-6 FPGA for signal processing, The 71660 architecture supports up to data capture or for routing to other module four independent memory banks which resources. can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two Clocking and Synchronization banks of each type of memory. An internal timing bus provides all Each QDRII+ SRAM bank can be up to timing and synchronization required by 8 MB deep and is an integral part of the the A/D converters. It includes a clock, two module’s DMA capabilities, providing sync and two gate or trigger signals. An on- FIFO memory space for creating DMA board clock generator receives an external packets. For applications requiring deeper sample clock from the front panel SSMC memory resources, DDR3 SDRAM banks connector. This clock can be used directly can each be up to 512 MB deep. Built-in by the A/D or divided by a built-in clock memory functions include multichannel synthesizer circuit. In an alternate mode, A/D data capture, tagging and streaming. the sample clock can be sourced from an In addition to the factory-installed on-board programmable voltage-controlled functions, custom user-installed IP within A/D Acquisition IP Modules crystal oscillator. In this mode, the front the FPGA can take advantage of the memo- The 71660 features four A/D panel SSMC connector can be used to ries for many other purposes. Acquisition IP Modules for eas- provide a 10 MHz reference clock for synchro- XMC Interface ily capturing and moving data. nizing the internal oscillator. Each IP module can receive data A front panel 26-pin LVPECL Clock/Sync The Model 71660 complies with the from any of the four A/Ds or a connector allows multiple modules to be VITA 42.0 XMC specification. Two connec- test signal generator synchronized. In the slave mode, it accepts tors each provide dual 4X links or a single Each IP module has an asso- LVPECL inputs that drive the clock, sync 8X link with up to a 6 GHz bit clock. With ciated memory bank for buffering and gate signals. In the master mode, the dual XMC connectors, the 71660 ➤ data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily from from from from moving A/D data through the A/D Ch 1 A/D Ch 2 A/D Ch 3 A/D Ch 4 PCIe interface. These powerful linked-list DMA engines are TEST capable of a unique Acquisition SIGNAL INPUT MULTIPLEXER GENERATOR Gate Driven mode. In this mode, the length of a transfer performed DATA DATA DATA DATA by a link definition need not be PACKING PACKING PACKING PACKING & FLOW & FLOW & FLOW & FLOW known prior to data acquisition; CONTROL CONTROL CONTROL CONTROL rather, it is governed by the length MEMORY MEMORY MEMORY MEMORY MUX MUX MUX MUX of the acquisition gate. This is CONTROL CONTROL CONTROL CONTROL extremely useful in applications to to METADATA METADATA to METADATA to METADATA Mem GENERATOR Mem GENERATOR Mem GENERATOR Mem GENERATOR where an external gate drives Bank 1 Bank 2 Bank 3 Bank 4 acquisition and the exact length LINKED-LIST LINKED-LIST LINKED-LIST LINKED-LIST DMA ENGINE DMA ENGINE DMA ENGINE DMA ENGINE of that gate is not known or is A/D A/D A/D likely to vary. A/D ACQUISITION ACQUISITION ACQUISITION ACQUISITION IP MODULE 1 For each transfer, the DMA IP MODULE 2 IP MODULE 3 IP MODULE 4 engine can automatically construct metadata packets containing A/D channel ID, a sample-accu- PCIe INTERFACE rate time stamp and data length VIRTEX-6 VIRTEX-6 FPGA FPGA D DA AT TAFLOW AFLOW D DET ETAIL AIL (supports user installed IP) information. These actions sim- plify the host processor’s job of identifying and executing on the 8X 4X 4X 40 Memory Memory Memory Memory Gigabit FPGA PCIe data. Bank 1 Bank 2 Bank 3 Bank 4 Serial I/O GPIO One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 71660 4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - XMC supports x8 PCIe on the first XMC con- External Clock ➤ nector leaving the second connector free to Type: Front panel female SSMC connec- support user-installed transfer protocols tor, sine wave, 0 to +10 dBm, AC-coupled, specific to the target application. 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference PCI Express Interface Timing Bus: 26-pin front panel connector; The Model 71660 includes an industry- LVPECL bus includes, clock/sync/gate/ standard interface fully compliant with PCI PPS inputs and outputs; TTL signal for Express Gen. 1 & 2 bus specifications. gate/trigger and sync/PPS inputs Supporting PCIe links up to x8, the inter- External Trigger Input face includes multiple DMA controllers Type: Front panel female SSMC connec- for efficient transfers to and from the tor, LVTTL module. Function: Programmable functions in- clude: trigger, gate, sync and PPS Specifications Field Programmable Gate Array Front Panel Analog Signal Inputs Standard: Xilinx Virtex-6 XC6VLX130T Input Type: Transformer-coupled, front Optional: Xilinx Virtex-6 XC6VLX240T, panel female SSMC connectors XC6VLX365T, XC6VSX315T, or Transformer Type: Coil Craft XC6VSX475T WBC4-6TLB Custom I/O Full Scale Input: +8 dBm into 50 ohms Option -104: Installs the PMC P14 con- 3 dB Passband: 300 kHz to 700 MHz nector with 20 LVDS pairs to the FPGA A/D Converters Option -105: Installs the XMC P16 con- Type: Texas Instruments ADS5485 nector configurable as one 8X or two 4X Sampling Rate: 10 MHz to 200 MHz gigabit serial links to the FPGA Resolution: 16 bits Memory Sample Clock Sources: On-board clock Option 150 or 160: Two 8 MB QDRII+ synthesizer SRAM memory banks, 400 MHz DDR Clock Synthesizer Option 155 or 165: Two 512 MB DDR3 Clock Source: Selectable from on-board SDRAM memory banks, 400 MHz DDR programmable VCXO (10 to 810 MHz), PCI-Express Interface front panel external clock or LVPECL PCI Express Bus: Gen. 1: x4 or x8; timing bus Gen. 2: x4 Ordering Information Synchronization: VCXO can be locked Environmental Model Description to an external 4 to 180 MHz PLL system Operating Temp: 0° to 50° C 71660 4-Channel 200 MHz A/D reference, typically 10 MHz Storage Temp: –20° to 90° C with Virtex-6 FPGA - XMC Clock Dividers: External clock or VCXO Relative Humidity: 0 to 95%, non-cond. Options: can be divided by 1, 2, 4, 8, or 16 for the Size: Standard XMC module, 2.91 in. x 5.87 in. -062 XC6VLX240T FPGA A/D clock -063 XC6VLX365T FPGA -064 XC6VSX315T FPGA -065 XC6VSX475T FPGA -104 LVDS FPGA I/O through P14 connector -105 Gigabit serial FPGA I/O through P16 connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -160 Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Contact Pentek for availability of rugged and conduction-cooled versions One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @ Model 71660 4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - XMC A/D Performance Spurious Free Dynamic Range Spurious Pick-up f = 70 MHz, f = 200 MHz, Internal Clock f = 200 MHz, Internal Clock in s s Two-Tone SFDR Two-Tone SFDR f = 30 MHz, f = 70 MHz, f = 200 MHz f = 69 MHz, f = 71 MHz, f = 200 MHz 1 2 s 1 2 s Adjacent Channel Crosstalk Crosstalk Input Frequency Response f = 200 MHz, Internal Clock f = 70 MHz, f = 200 MHz, Ch 1 shown s in Ch2 s One Park Way ◆ Upper Saddle River ◆ New Jersey 07458 Pentek, Inc. www.pentek.com . . . . Tel: 201 818 5900 ◆ Fax: 201 818 5904 ◆ Email: info pentek.com @