ON Semiconductor� BC817-16LT1 General Purpose Transistors BC817-25LT1 NPN Silicon BC817-40LT1 MAXIMUM RATINGS Rating Symbol Value Unit Collector–Emitter Voltage V 45 V CEO Collector–Base Voltage V 50 V CBO 3 Emitter–Base Voltage V 5.0 V EBO 1 Collector Current — Continuous I 500 mAdc C 2 THERMAL CHARACTERISTICS Characteristic Symbol Max Unit CASE 318–08, STYLE 6 SOT–23 (TO–236AB) Total Device Dissipation FR–5 Board, (1) P D T = 25°C 225 mW A Derate above 25°C 1.8 mW/°C Thermal Resistance, Junction to Ambient R 556 °C/W �JA Total Device Dissipation P COLLECTOR D Alumina Substrate, (2) T = 25°C 300 mW 3 A Derate above 25°C 2.4 mW/°C Thermal Resistance, Junction to Ambient R 417 °C/W 1 �JA BASE Junction and Storage Temperature T , T –55 to +150 °C J stg DEVICE MARKING 2 BC817–16LT1 = 6A; BC817–25LT1 = 6B; BC817–40LT1 = 6C EMITTER ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) A Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Collector–Emitter Breakdown Voltage V 45 — — V (BR)CEO (I = –10 mA) C Collector–Emitter Breakdown Voltage V 50 — — V (BR)CES (V = 0, I = –10 μA) EB C Emitter–Base Breakdown Voltage V 5.0 — — V (BR)EBO (I = –1.0 �A) E Collector Cutoff Current I CBO (V = 20 V) — — 100 nA CB (V = 20 V, T = 150°C) — — 5.0 μA CB A 1. FR–5 = 1.0 x 0.75 x 0.062 in. 2. Alumina = 0.4 x 0.3 x 0.024 in. 99.5% alumina.  Semiconductor Components Industries, LLC, 2001 1 Publication Order Number: November, 2001 – Rev. 4 BC817–16LT1/D BC817–16LT1 BC817–25LT1 BC817–40LT1 ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (Continued) A Characteristic Symbol Min Typ Max Unit ON CHARACTERISTICS DC Current Gain h — FE (I = 100 mA, V = 1.0 V) BC817–16 100 — 250 C CE BC817–25 160 — 400 BC817–40 250 — 600 (I = 500 mA, V = 1.0 V) 40 — — C CE Collector–Emitter Saturation Voltage V — — 0.7 V CE(sat) (I = 500 mA, I = 50 mA) C B Base–Emitter On Voltage V — — 1.2 V BE(on) (I = 500 mA, V = 1.0 V) C CE SMALL–SIGNAL CHARACTERISTICS Current–Gain — Bandwidth Product f 100 — — MHz T (I = 10 mA, V = 5.0 Vdc, f = 100 MHz) C CE Output Capacitance C — 10 — pF obo (V = 10 V, f = 1.0 MHz) CB 1000 V = 1 V CE T = 25 °C J 100 10 0.1 1.0 10 100 1000 I , COLLECTOR CURRENT (AMP) C Figure 1. DC Current Gain http://onsemi.com 2 h , DC CURRENT GAIN FE BC817–16LT1 BC817–25LT1 BC817–40LT1 1.0 1.0 T = 25 °C T = 25 °C J A V @ I /I = 10 BE(sat) C B 0.8 0.8 V @ V = 1 V BE(on) CE 0.6 0.6 I = 10 mA 100 mA 300 mA 500 mA C 0.4 0.4 0.2 0.2 V @ I /I = 10 CE(sat) C B 0 0 0.01 0.1 1 10 100 1 10 100 1000 I , BASE CURRENT (mA) I , COLLECTOR CURRENT (mA) B C Figure 2. Saturation Region Figure 3. “On” Voltages 100 +1 θ for V VC CE(sat) 0 C ib 10 -1 C ob θ for V VB BE -2 1 1 10 100 1000 0.1 1 10 100 I , COLLECTOR CURRENT (mA) V , REVERSE VOLTAGE (VOLTS) C R Figure 4. Temperature Coefficients Figure 5. Capacitances http://onsemi.com 3 θ , TEMPERATURE COEFFICIENTS (mV/ C) ° V , COLLECTOR-EMITTER VOLTAGE (VOLTS ) V CE C, CAPACITANCE (pF) V, VOLTAGE (VOLTS) BC817–16LT1 BC817–25LT1 BC817–40LT1 INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the interface between the board and the package. With the total design. The footprint for the semiconductor packages correct pad geometry, the packages will self align when must be the correct size to insure proper solder connection subjected to a solder reflow process. 0.037 0.95 0.037 0.95 0.079 2.0 0.035 0.9 0.031 inches 0.8 mm SOT–23 SOT–23 POWER DISSIPATION SOLDERING PRECAUTIONS The power dissipation of the SOT–23 is a function of the pad size. This can vary from the minimum pad size for The melting temperature of solder is higher than the soldering to a pad size given for maximum power dissipa- rated temperature of the device. When the entire device is tion. Power dissipation for a surface mount device is deter- heated to a high temperature, failure to complete soldering mined by T , the maximum rated junction temperature within a short time could result in device failure. There- J(max) of the die, R , the thermal resistance from the device fore, the following items should always be observed in θJA junction to ambient, and the operating temperature, T . order to minimize the thermal stress to which the devices A Using the values provided on the data sheet for the SOT–23 are subjected. package, P can be calculated as follows: • Always preheat the device. D • The delta temperature between the preheat and T – T J(max) A P = D soldering should be 100°C or less.* R θJA • When preheating and soldering, the temperature of the The values for the equation are found in the maximum leads and the case must not exceed the maximum ratings table on the data sheet. Substituting these values temperature ratings as shown on the data sheet. When into the equation for an ambient temperature T of 25°C, A using infrared heating with the reflow soldering one can calculate the power dissipation of the device which method, the difference shall be a maximum of 10°C. in this case is 225 milliwatts. • The soldering temperature and time shall not exceed 150°C – 25°C 260°C for more than 10 seconds. P = = 225 milliwatts D 556°C/W • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. The 556°C/W for the SOT–23 package assumes the use • After soldering has been completed, the device should of the recommended footprint on a glass epoxy printed be allowed to cool naturally for at least three minutes. circuit board to achieve a power dissipation of 225 milli- Gradual cooling should be used as the use of forced watts. There are other alternatives to achieving higher cooling will increase the temperature gradient and power dissipation from the SOT–23 package. Another result in latent failure due to mechanical stress. alternative would be to use a ceramic substrate or an • Mechanical stress or shock should not be applied aluminum core board such as Thermal Clad. Using a during cooling. board material such as Thermal Clad, an aluminum core * Soldering a device without preheating can cause exces- board, the power dissipation can be doubled using the same sive thermal shock and stress which can result in damage footprint. to the device. http://onsemi.com 4 BC817–16LT1 BC817–25LT1 BC817–40LT1 PACKAGE DIMENSIONS SOT–23 (TO–236) CASE 318–08 ISSUE AF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. A 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS L IS THE MINIMUM THICKNESS OF BASE MATERIAL. 3 INCHES MILLIMETERS S B DIM MIN MAX MIN MAX 1 2 A 0.1102 0.1197 2.80 3.04 B 0.0472 0.0551 1.20 1.40 C 0.0350 0.0440 0.89 1.11 V G D 0.0150 0.0200 0.37 0.50 G 0.0701 0.0807 1.78 2.04 H 0.0005 0.0040 0.013 0.100 J 0.0034 0.0070 0.085 0.177 C K 0.0140 0.0285 0.35 0.69 L 0.0350 0.0401 0.89 1.02 S 0.0830 0.1039 2.10 2.64 H J D K V 0.0177 0.0236 0.45 0.60 STYLE 6: PIN 1. BASE 2. EMITTER 3. COLLECTOR http://onsemi.com 5 BC817–16LT1 BC817–25LT1 BC817–40LT1 Notes http://onsemi.com 6 BC817–16LT1 BC817–25LT1 BC817–40LT1 Notes http://onsemi.com 7 BC817–16LT1 BC817–25LT1 BC817–40LT1 Thermal Clad is a trademark of the Bergquist Company. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: JAPAN: ON Semiconductor, Japan Customer Focus Center Literature Distribution Center for ON Semiconductor 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 P.O. Box 5163, Denver, Colorado 80217 USA Phone: 81–3–5740–2700 Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Email: r14525@onsemi.com Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Email: ONlit@hibbertco.com For additional information, please contact your local N. American Technical Support: 800–282–9855 Toll Free USA/Canada Sales Representative. BC817–16LT1/D http://onsemi.com 8