NORITAKE MN12818A

Graphic Dot Matrix Chip In Glass VFD MN12818A q 128 x 18 Graphic Dot Matrix This VF glass includes twin 96 bit serial shift register, latched drivers q Chip in Glass Driver IC which connect to the anode and grid electrodes. An external host is q High Brightness Blue Green Display required to provide a multiplexing data stream to refresh the display. q Synchronous Serial Interface The signal inputs can be connected to the ports of a CMOS q Low Pinout Count microprocessor. The a.c. filament supply (F1, F2) can be derived from a q Wide Operating Temperature source of 10KHz to 200KHz. Consult our application notes for further information. G1 G2 G3 a b c d e f g h a b Row 1 Row 2 G31 G32 PIN OUT Row 1 Pin Sig 25.0 1 F1 13.69 2 F1 3 F1 Row 18 6.5 4 SIN 5 VDD1 6 SOUT 6.56 83.05 13.48 7 LAT 2.0 110.0 8 BLK 9 CLK 10 VSS 11 VSS 6.6 3 4 12 17 6.0 12 VDD2 6.0 15 F2 78.0 2.0 16 F2 100.0 Dimensions in mm 17 F2 See full spec for tolerances ELECTRICAL SPECIFICATION INTERFACE EXAMPLE Parameter Sym Min Typ Max Unit Condition Logic Voltage V DD1 4.5 5.0 5.5 V VSS=0V MISO SOUT KEY Logic Current I DD1 - 3.0 6.0 mA VDD1=5V SCAN M Filament Voltage E f 3.6 4.0 4.4 Vac VDD2=0V MPU 47R N TXD SCK CLK 1 Filament Current I f 135 150 165 mAac VDD2=0V RXD VDD2 0.10µF 100V MOSI SIN 2 Display Voltage V DD2 30.0 40.0 42.0 V VSS=0V 10K 8 PA0 LAT PSU Display Current I DD2 - 15.0 25.0 mA VDD2=40V 1 F2 PA1 BLK 8 Filament Bias E K 4.5 5.0 5.5 V VSS=0V A Ef F1 Logic High Input VIH +2.4 - V DD1 V VSS=0V Logic Low Input VIL 0 - +0.7 V VSS=0V Ek VDD1 VSS Logic High Input IIH - - 0.3 VDD1=5V mA 5V 0V Logic Low Input IIL -250 -70 -35 mA VDD1=5V ENVIRONMENTAL and OPTICAL SPECIFICATION MULTIPLEX TIMING Parameter Value 100ms <10ms Display Area (XxY mm) 83.05 x 13.69 G1 Dot Size/Pitch (XxY mm) 0.5 x 0.6/0.65 x 0.77 2 G2 Luminance 700 cd/m Typ. G32 Colour of Illumination Blue-Green (Filter for colours) Operating Temperature -40°C to +85°C cdfe abhg cdfe abhg cdfe abhg cdfe abhg Anode Storage Temperature -50°C to +85°C Operating Humidity (non condensing) 5 to 95% @ 25°C 94 95 96 1 2 Shift Reg Bit 95 96 1 2 3 1. The power on rise time should be less than 50ms. SIN 2. The 47R resistor at the VDD2 input is required to prevent current surge during CLK switching. 3. If scanning of the display stops with VDD2 applied, the BLK input must be set high LATCH to prevent damage to the display. BLK POWER SEQUENCE CONTACT SHIFT REGISTER ASSIGNMENT INTERFACE TIMING Noritake Sales Office Tel Nos Electrode Bit Numbers Parameter Time Nagoya Japan: +81 (0 )52-561-9867 Grid G1-G16 81-96 CLK Cycle 500ns min 40V VDD2 Canada: +1-416-291-2946 Grid G32-G17 177-192 CLK High 200ns min Chicago USA: +1-847-439-9020 Row 18‘abcd’,’hgfe’ 1-4, 97-100 CLK Low 200ns min Munchen (D): +49 (0)89-3214-290 Itron UK: +44 (0)1493 601144 Row 17‘abcd’,’hgfe’ 5-8, 101-104 SIN Setup 40ns min VDD1 5V Rest Europe: +49 (0)61-0520-9220 : : SIN Hold 30ns min www.noritake-itron.com Row 2‘abcd’,’hgfe’ 65-68, 161-164 LAT High 300ns min Subject to change without notice. ON OFF Row 1‘abcd’,’ hgfe’ 69-72, 165-168 CLK then LAT 250ns min Doc Ref:00791 Iss:4 22NOV99 Not Connected 73-80,169-176 BLK Hold 10ms min NORITAKE ITRON VFD 128 x 18 Dot Graphic