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NJR/JRC CORPORATION NJU6355ED

Description

IC SERIAL REAL TIME CLOCK 8DIP

Part Number

NJU6355ED

Price

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Manufacturer

NJR/JRC CORPORATION

Lead Time

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Category

PRODUCTS - N

Datasheet

pdf file

9598092_1.pdf

62 KiB

Extracted Text

NJU6355 SERIAL I/O REAL TIME CLOCK GENERAL DESCRIPTION PACKAGE OUTLINE The NJU6355 series is a serial I/O real time clock suitable for 4 bits microprocessor. It contains quartz crystal oscillator, counter, shift register, voltage regulator, voltage detector and interface controller. The NJU6355 series required only 4-port of microprocessor for data transfer, and the microprocessor can receive the data at any time when the microprocessor requires. The operating voltage is as wide as 2.0V to 5.5V, NJU6355ED NJU6355EM consequently, the NJU6355 series can count accurate time data even if the back up period. Furthermore, the long time back up is available as the operating current during the back up period is less than 3uA(TYP). FEATURES PIN CONFIGURATION Low Operating Voltage 2.0 to 3.6V Low Operating Current 3.0uA (TYP) @2.0V I/O V DD 3.0uA (TYP) @3.0V XT DATA 4.0uA (TYP) @5.0V XT CLKBCD Counts of Seconds, Minutes, Hours, Days of Week Day, Month and Year CE V SS Required only 4-port DATA, CLK, CE and I/O Low Battery Detector Low Voltage Alarm Signal Output Automatic Leap Year Compensation Up to AD 2099 Package Outline DIP8 / DMP8 C-MOS Technology LINE-UP TABLE Type No. Output Data Oscillation Capacitor NJU6355 E Seconds, Minutes, Hours, Days of Week, Day, Month, Year Cd=21pF / Cg=21pF on Chip BLOCK DIAGRAM Timer Counter XT Oscillator Days of XT Divider Sec. Min. Hr. Day Month Year Week Days of DATA Sec. Min. Hr. Day Month Year Week Shift Register I/O VSS Controller V DD CLK & Clock Counter Voltage Detector CE -1 - NJU6355 TREMINAL DESCRIPTION No. SYMBOL FUNCTION I/O Input/Output Select Terminal for DATA Terminal 1 "H" : Input, "L" : Output During the CE terminal is "L", the DATA terminal is high impedance. 2 XT Quartz Crystal Connecting Terminal (f=32.768kHz) Refer to the line-up table for internal Cg, Cd value. XT 3 Chip Enable Input Terminal (with Pull-down Resistance) "H" : DATA input/output is available. 5 CE "L" : DATA terminal is high impedance. When the CE signal is which rising edge or falling edge, the CLK signal should be fixed to "L". Clock Input Terminal 6 CLK The DATA input/output is synchronized this clock. When the CE terminal is "L" the DATA terminal is high impedance. Serial Timer Data Input/Output Terminal I/O CE DATA H H Input 7 DATA L H Output H L High Impedance L L High Impedance 8 V Power Supply DD 4 V GND SS FUNCTIONAL DESCRIPTION 1. Timer Data Structure The NJU6355 using BCD code which consisting of 4 bits per 1 digit. The calender function including the last date of each month and the leap year calculation is executed automatically. The unused bit for the timer data is “0”. Timer Data Bit Map MSB LSB Range Second 0 S6 S5 S4 S3 S2 S1 S0 0 to 59 Minute 0 m6 m5 m4 m3 m2 m1 m0 0 to 59 Hour 0 0 H5 H4 H3 H2 H1 H0 0 to 23 Days of Week 0 W2 W1 W0 1 to 7 Day 0 0 D5 D4 D3 D2 D1 D0 1 to 31 Month 0 0 0 M4 M3 M2 M1 M0 1 to 12 Year Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 0 to 99 - 2 - NJU6355 2. Timer Data Reading When the I/O termianl is "L" and the CE tarminal is "H", timer data can read out. The output is LSB first and the output data strings is shown below. The timer data is transferred from timer counter to shift register at rising edge of the chip enable on the CE terminal, and output the LSB of the timer data from the DATA terminal. Afterward the timer data in the shift register shift by synchronized at the falling edge of clock signal on the CLK terminal and output from the DATA terminal. If the timer data is updated in the data output, there are one second difference between timer data and output data. Type E Days of Year Month Day Hour Minute Second Week The data is read out from LSB of Year, and first 52-bit is effective. If the low voltage detector detect the low battery, (EE) is written into each digit of timer data and read out. The H code of (EE) is a warning for the broken. H < Read Out Timing > CLK CE I/O Data 0 1 2 3 4 5 6 7 3 4 5 6 7 Output Year Second Shift 0 1 2 3 4 5 6 7 3 4 5 6 7 Register The timer data is transferred to the shift register at rising edge of the CE (1) (1) (2) and LSB of the timer data is output to the DATA terminal. Afterward the timer data in the shift register shift by synchronized at falling edge of the CLK(2) then output to the DATA terminal time-to-time. Note) When the CE signal is which rising edge or falling edge, the CLK signal should be fixed to “L”. And so, before the CE signal is raised, the I/O signal should be fixed to “L”. -3 - NJU6355 3. Timer Data Writing When both of the I/O terminal and the CE terminal are "H", update is stopped, the oscillator divider is cleared, and the timer data can be written to the NJU6355. The timer data is written into the shift register from the DATA terminal by synchronized with rising edge of the clock signal input from the CLK terminal, and the data is transferred from the shift register to the timer counter by synchronized with falling edge of the CE signal. In this time the second-counter is cleared to "0", and the oscillator divider start the operation. The input data strings are LSB first of each digit as shown below. Type E Days of Year Month Day Hour Minute Second Week The data is read out from LSB of Year, and last 44-bit is effective. < Write Down Timing > CLK CE I/O Data 0 1 2 3 4 5 6 7 3 4 5 6 7 Input Year Minute Shift 0 1 2 3 4 5 6 7 3 4 5 6 7 Register The data is input into the shift The data in the shift register is register at rising edge of the transferred to the timer counter at this CLK. falling edge of the CE, then the oscillator divider start the operation. Note) When the CE signal is which rising edge or falling edge, the CLK signal should be fixed to "L". And so, before the CE signal is raised, the I/O signal should be fixed to "H". 4. Low Voltage Detector The NJU6355 series incorporate the low battery detector. If the supply voltage reduce to the detection level, (EE) is written into each digit of the shift register as warning code for the CPU. H 5. Data Access The NJU6355 series can operate from 2.0V to 5.5V. However, it is not allow the data access out of the range of 5V±10%. It may be broken the data unless 5V±10%. Thus, when the data access, the CE terminal should be "H" after the power supply rise to 5V±10%, then start the operation. - 4 - NJU6355 ABSOLUTE MAXIMUM RATINGS (Ta=25°C) PARAMETER SYMBOL RATING UNIT Supply Voltage V -0.3 to +6.0 V DD Input Voltage V V -0.3 to V+0.3 V IN SS DD Power Dissipation P 250(DIP8) 200(DMP8) mW D Operating Temperature Range Topr -30 to +80 °C Storage Temperature Range Tstg -55 to +150 °C ELECTRICAL CHARACTERISTICS DC Characteristics (V =2.0V, Ta=25°C) DD PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Operating Current I XT=32.768kHz, CE=0V 3.0 4.0 uA DD Low Battery Detect Voltage V 1.1 1.7 V DET (V =5.0V±10%, Ta=25°C) DD PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Operating Voltage V 4.5 5.5 V DD Operating Current I XT=32.768kHz, CE=0V 4 15 uA DD 3-st. Leakage Current I DATA (CE=0V) -2.0 2.0 uA TSL Input Leakage Current I I/O, CLK -1.0 1.0 uA IL Input Current I CE (CE=V) 20 uA CE DD V I/O, CE, CLK, DATA 0.8V V IH DD DD Input Voltage V V I/O, CE, CLK, DATA V 0.2V IL SS DD V DATA (I=-0.4mA) 4.1 OH OH Output Voltage V V DATA (I=1.0mA) 0.4 OL OL AC Characteristics (V =5.0V±10%, Ta=25°C, C =50pF) DD L PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT CLK Pulse "H" Period t 0.47 5000 us CWH CLK Pulse "L” Period t 0.47 5000 us CWL CE Set-up Time Before t 470 ns CS CLK Rising CE Hold Time After CLK Falling t 20 ns CH I/O Set-up Time t 60 ns DS Before CLK Rising I/O Hold Time After CLK Falling t 20 ns DH Write Down Data Set-Up Time t 100 ns WDS Write Down Data Hold Time t 20 ns WDH Data Delay Time t 200 ns RDD After CLK Falling Rise/Fall Time t 50 ns RF -5 - NJU6355 CLK CLK t t t t CS CH CS CH CE CE t t I/O t t DS DH I/O DS DH (in) (out) t WDS t t CWL CWH tr tf 80% CL K 50% 50% 50% CL K 20% 20% Vss t RDD t WDH 80% 80% 80% Output Data Input Data 20% 20% 20% Vss APPLICATION CIRCUIT Main Power V DD Supply NJU6355 V DD DATA I/O CPU CLK CE V SS XT XT [CAUTION] The specifications on this data book are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this data book are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 6 -

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