NJU3716 16-BIT SERIAL TO PARALLEL CONVERTER � GENERAL DESCRIPTION � PACKAGE OUTLINE The NJU3716 is a 16-bit serial to parallel converter especially applying to MPU outport expander. The effective outport assignment of MPU is available as the connection between NJU3716 and MPU using only 4 lines. The serial data synchronizing with 5MHz or more clock can be input to the serial data input terminal and the data are output from parallel output buffer through serial in parallel out shift register and parallel data NJU3716M NJU3716L latches. Furthermore, the NJU3716 outputs the serial data from SO terminal through the shift register. Therefore, it connects with other SIPO ICs like as NJU3711 in cascade for expanding the parallel conversion outputs. The hysteresis input circuit realizes wide noise margin and the high drive-ability output buffer (25mA) can drive LED directly. � PIN CONFIGURATION � FEATURES � 16-Bit Serial In Parallel Out V 1 24 DD P7 P8 23 P6 � Hysteresis Input 0.5V typ 2 3 22 P5 P9 � Operating Voltage 5V±10% P10 4 21 P4 � Maximum Operating Frequency 5MHz and more P3 P11 5 20 V 6 19 P2 SS � Output Current 25mA P12 7 18 V SS � C-MOS Technology P1 17 P13 8 P14 9 16 CLR � Package Outline SDIP24/DMP24 STB 10 15 P15 CLK P16 11 14 DATA SO 12 13 NJU3716L/M � BLOCK DIAGRAM P1 DATA P2 CLK P3 P15 P16 SO STB Controller Circuit CLR Ver.2003-11-18 - 1 - Shift Register Latch Circuit NJU3716 � TERMINAL DESCRIPTION No. SYMBOL I/O FUNCTION 1 P7 O 2 P8 O Parallel Conversion Data Output Terminals 3 P9 O 4 P10 O 5 P11 O 6 V - GND SS 7 P12 O 8 P13 O 9 P14 O Parallel Conversion Data Output Terminals 10 P15 O 11 P16 O 12 SO O Serial Data Output Terminal 13 DATA I Serial Data Input Terminal 14 CLK I Clock Signal Input Terminal 15 STB I Strobe Signal Input Terminal CLR 16 I Clear Signal Input Terminal 17 P1 O Parallel Conversion Data Output Terminal 18 V - GND SS 19 P2 O 20 P3 O 21 P4 O Parallel Conversion Data Output Terminals 22 P5 O 23 P6 O 24 V - Power Supply Terminal (4.5 to 5.5V) DD Ver.2003-11-18 - 2 - NJU3555 NJU3555 NJU3716 � FUNCTIONAL DESCRIPTION (1) Reset When the "L" level is input to the CLR terminal, all latches are reset and all of parallel conversion output are "L" level. Normally, the CLR terminal should be "H" level. (2) Data Transmission In the STB terminal is "H" level and the clock signals are inputted to the CLK terminal, the serial data into the DATA terminal are shifted in the shift register synchronizing at a rising edge of the clock signal. When the STB terminal is changed to "L" level, the data in the shift register are transferred to the latches. Even if the STB terminal is "L" level, the input clock signal shifts the data in the shift register, therefore, the clock signal should be controlled for data order. (3) Cascade Connection The serial data input from DATA terminal is output from the SO terminal through internal shift register unrelated with the CLR and STB status. Furthermore, the 4 input circuits provide a hysteresis characteristics using the schmitt trigger structure to protect the noise. STB CLR CLK OPERATION All of latches are reset (the data in the shift register is no change). X X L All of parallel conversion outputs are "L". The serial data into the DATA terminal are inputted to the shift register. H H In this stage, the data in the latch is not changed. L The data in the shift register is transferred to the latch. And the data in the H latch is output from the parallel conversion output terminals. L H When the clock signal is inputted into the CLK terminal in state of the STB="L" and CLR="H", the data is shifted in the shift register and latched data is also changed in accordance with the shift register. Note 1) X: Don’t care Ver.2003-11-18 - 3 - NJU3716 � TIMING CHART CLK CLR STB DATA P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 SO Ver.2003-11-18 - 4 - NJU3555 NJU3555 NJU3716 � ABSOLUTE MAXIMUM RATINGS (Ta=25°C) PARAMETER SYMBOL RATINGS UNIT Supply Voltage Range V -0.5 ~ +7.0 V DD Input Voltage Range V V -0.5 ~ V+0.5 V I SS DD Output Voltage Range V V -0.5 ~ V+0.5 V O SS DD Output Current I ±25 mA O Output Short Current V =7V, V=0V 10 (max) O I (SO Terminal) I mA OS V =0V, V=7V -10 (max) (Note 5) O I Output Short Current V =7V, V=0V 20 (max) O I I mA (P1~P16 Terminals) OSD V =0V, V=7V -20 (max) (Note 5) O I 700 (SDIP) Power Dissipation P mW D 500 (DMP) Operating Temperature Range Topr -25 ~ +85 °C Storage Temperature Range Tstg -65 ~+150 °C Note 2) All voltage are relative to V =0V reference. SS Note 3) Do not exceed the absolute maximum ratings, otherwise the stress may cause a permanent damage to the IC. It is also recommended that the IC be used in the range specified in the DC electrical characteristics, or the electrical stress may cause malfunctions and impact on the reliability. Note 4) To stabilize the IC operation, place decoupling capacitor between V and V . DD SS Note 5) V =7V, V =0V, less than 1 second per pin. DD SS � DC ELECTRICAL CHARACTERISTICS (V =4.5~5.5V, V =0V, Ta=25°C, unless otherwise noted) DD SS PARAMETER SYMBOL CONDITION MIN TYP MAX UNIT Operating Voltage V 4.5 - 5.5 V DD Operating Current I V =V , V =V - - 0.1 mA DDS IH DD IL SS High-level Output Voltage V I=-0.4mA 4.0 - V V OH OH DD SO Terminal Low-level Output Voltage V I =+3.2mA V - 0.4 V OL OL SS High-level Input Voltage V 0.7V - V V IH DD DD Low-level Input Voltage V V - 0.3V V IL SS DD Input Leakage Current I V =0~V -10 - 10 µA LI I DD IOH=-25mA V-1.5 - V DD DD P1~P16 High-level Output Voltage V I =-15mA V OH V-1.0 - V OHD DD DD (Note 6) Terminals I =-10mA V-0.5 - V OH DD DD I =+25mA V - 1.5 OL SS P1~P16 Low-level Output Voltage V I =+15mA V OL V - 0.8 OLD SS (Note 6) Terminals I =+10mA V - 0.4 OL SS Note 6) Specified value represent output current per pin. When use, total current consideration and less than power dissipation in rating operation should be required. Ver.2003-11-18 - 5 - NJU3716 � SWITCHING CHARACTERISTICS (V =4.5~5.5V, V =0V, Ta=25°C, unless otherwise noted) DD SS PARAMETER SYMBOL CONDITION MIN TYP MAX UNIT Set-Up Time t DATA-CLK 20 - - ns SD Hold Time t CLK-DATA 20 - - ns HD STB-CLK Set-Up Time t 30 - - ns SSTB Hold Time t CLK-STB 30 - - ns HSTB t CLK-SO - - 70 ns pd O t CLK-P1~P16 - - 100 ns pd PCK Output Delay Time STB-P1~P16 t - - 80 ns pd PSTB t CLR-P1~P16 - - 80 ns pd PCLR Maximum Operating Frequency f 5 - - MHz MAX Note 7) C =50pF OUT Ver.2003-11-18 - 6 - NJU3555 NJU3555 NJU3716 � SWITCHING CHARACTERISTICS TEST WAVEFORM f MAX CLK t SD DATA t HD STB t t HSTB SSTB CLK t pd O SO CLK t pd PCK L STB P1~P16 CLK H STB t pd PSTB P1~P16 CLR DATA t pd PCLR H P1~P16 Ver.2003-11-18 - 7 - NJU3716 � APPLICATION CIRCUIT (1) P1 P3 P5 P7 P9 P11 P13 P15 MPU P2 P4 P6 P8 P10 P12 P14 P16 DATA CLK NJU3716 STB CLR SO � APPLICATION CIRCUIT (2) (Combined with NJU3711) P1 P3 P5 P7 P9 P11 P13 P15 MPU P2 P4 P6 P8 P10 P12 P14 P16 DATA CLK NJU3716 STB CLR SO P1 DATA P2 P3 CLK MOTOR P4 NJU3711 M P5 DRIVER STB P6 P7 CLR P8 [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver.2003-11-18 - 8 -