DS90C2501 DS90C2501 Transmitter with Built-In Scaler for LVDS Display Interface (LDI) Literature Number: SNLS136G DS90C2501 Transmitter with Built-In Scaler for LVDS Display Interface (LDI) OBSOLETE September 22, 2011 DS90C2501 Transmitter with Built-In Scaler for LVDS Display Interface (LDI) General Description Features The DS90C2501 is a highly integrated scaling IC with LVDS Complies with Open LDI and GMCH DVO specification for ■ transmitter with a scaled resolution up to SXGA+ for single digital display interfaces pixel input. The DS90C2501 is a video controller hub de- 25 to 65 MHz clock in single pixel in to single pixel out ■ signed to be compatible with Graphic Memory Controller Hub operation. (GMCH). The input interface can be single or dual DVO port 50 to 130 MHz clock in single pixel in to dual pixel out ■ (12 pin per port). The high quality cubic zoom engine scales operation. the input graphics into the desired/optimal output resolution Support 24bit/48bit color TFT LCD with Conventional and ■ up to 1400x1050 resolution. A two-wire serial interface is used Non-Conventional Color Mappings. to communicate with the host system. The dual high speed Support 18bit/36bit color TFT LCD. ■ LVDS channels supports single pixel in-single pixel out, single Single pixel transmitter inputs support single pixel GUI ■ pixel in-dual pixel out, and dual pixel in-dual pixel out trans- interface. mission modes. The DS90C2501 complies to Open LDI stan- Up scaling/panel fitting supports VGA to SXGA+ output in dard, and can be paired up with DS90CF388 receiver or ■ single pixel input mode at 640x480@60Hz, FPD8531x/FPD8731x series integrated timing controller or 800x600@60Hz, 1024x768@60Hz, 1280x1024@60Hz, FPDLink LVDS receivers such as DS90CF364/ 1400x1050@60Hz. DS90CF384A/DS90CF384/DS90CF384A. The LVDS output is similar to DS90C387 and DS90C387R. Thus, this trans- Independent horizontal and vertical scaling. ■ mitter can be paired up with DS90CF388, receiver of 112MHz Support dithering, 8-bit color in, 6-bit color out. ■ LDI chipset or FPD-Link Receivers in non-DC Balance mode Allow 2% at 200kHz spread spectrum clocking, rejects ■ operation which provides GUI/LCD panel/mother board ven- cycle-to-cycle jitter (+/− 20% of input data bit time). dors a wide choice of inter-operation with LVDS based TFT Programmable LCD panel power sequencing. ■ panels. Support low voltage swing signal level (1V to 1.8V), 2.5V ■ This chip is an ideal solution to solve EMI and cable size and 3.3V LVTTL level on CLKINP, CLKINM, D0 to D23, problems for high-resolution flat panel applications. It pro- DE, HSYNC and VSYNC pins vides a reliable industry standard interface based on LVDS Support 2.5V/3.3V LVTTL level on configuration pins ■ technology that delivers the bandwidth needed for high-res- olution panels while maximizing bit times, and keeping clock Support 3.3V LVTTL level on GPIO pins ■ rates low to reduce EMI and shielding requirements. For more Available in 10mm x 10mm x 1mm 128pin thermally ■ details, please refer to the “Applications Information” section enhanced CSP package. of this datasheet. Two-wire serial communication interface is active during ■ normal as well as power down mode and support data rates up to 400kHz. TIA/EIA-644, Open LDI, DVO compliance. ■ DVO is a registered trademark of Intel Corporation. AGP or 4x AGP is a registered trademark of Intel Corporation. © 2011 National Semiconductor Corporation 200045 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 Block Diagram 20004552 www.national.com 2 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 128 CSP Package: Absolute Maximum Ratings (Note 1) DS90C2501 1.8W If Military/Aerospace specified devices are required, Maximum Package Temperature: 97°C (measured at please contact the National Semiconductor Sales Office/ top center of package) Distributors for availability and specifications. ESD Rating: Supply Voltage (V ) −0.3V to +2.8V CC DS90C2501 Supply Voltage (V ) −0.3V to +3.6V CC3V (HBM, 1.5kΩ, 100pF) > 2 kV CMOS/TTL Input Voltage −0.3V to V CC3V (EIAJ, 0Ω, 200pF) > 250 V CMOS/TTL Output −0.3V to (V + 0.3V) Voltage CC Recommended Operating LVDS Driver Output −0.3V to (V + 0.3V) Voltage Conditions CC LVDS Output Short Circuit Min Nom Max Units Duration Continuous All Supply Voltage except 2.250 2.5 2.750 V Junction Temperature +150°C (V ) CC3V Storage Temperature −65°C to +150°C V Supply Voltage 3.0 3.3 3.6 V CC3V Lead Temperature Operating Free Air (Soldering, 4 sec.) +235°C (not for Pb-free Temperature (T ) 0 +25 +70 °C A reflow temp.) Supply Noise Voltage (V ) 100 mV CC P-P Typical Package Power Dissipation Capacity @ 70°C up to 33Mhz and Max V CC DC Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units LVCMOS/LVTTL DC SPECIFICATIONS (All input pins when operate in LVTTL level except DUAL pin. Note: On ID0, ID1 pins have typical 30K ohm internal pull-down, and ID2 and ID3 pins have typical 3K ohm internal pull-down.) V High Level Input Voltage V = V 2.0 V V IH REF CC3V CC3V V Low Level Input Voltage V = V -0.3 0.8 V IL REF CC3V V Input Clamp Voltage I = 18 mA -0.9 -1.5 V CL CL I Input Current V = 0.4V, or V +1.8 +15 µA IN IN CC V = GND −15 0 µA IN LVCMOS/LVTTL DC SPECIFICATIONS for DUAL pin, pin35 V DUAL High Level Input Voltage (for PD = V 2.0 V V IH CC3V CC dual pixel in to dual pixel out). V DUAL High Level Input Voltage (for PD = V ½V −0.1 ½V ½V +0.1 V IM CC3V CC CC CC single pixel in to dual pixel out). V DUAL High Level Input Voltage (for PD = V 0 0.4 V IL CC3V single pixel in to single pixel out). V Input Clamp Voltage I = 18 mA -0.9 -1.5 V CL CL I Input Current V = 0.4V, V 1.8 15 µA IN IN CC V = Gnd -15 0 µA IN LVCMOS/LVTTL DC SPECIFICATIONS for MSEN, pin 98 V Low level Open Drain Output I = 2 mA 0.1 0.3 V OL OL Voltage LVCMOS/LVTTL DC SPECIFICATIONS (Pin 62 to pin 69 when operate in 3.3V LVTTL level) V High Level Input Voltage I = 2 mA 2.2 2.95 V OH OL V Low Level Input Voltage 0.055 0.4 V OL I Output Short Circuit Current V = 0V -50 −120 mA OS OUT 3 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 Symbol Parameter Conditions Min Typ Max Units Low Voltage Level DC SPECIFICATIONS (pins D0 to D23, CLKINP, CLKINM, DE, HSYNC,VSYNC) V Low Swing Voltage from GMCH 1 +1.8 V DDQ V Low Swing High Level Input V + V V ILSH REF DDQ Voltage 100mV V Low Swing Low Level Input 0 V - V ILSL REF Voltage 100mV V Differential Input Reference 0.475 ½V 0.945 V REF DDQ Voltage LVDS DRIVER DC SPECIFICATIONS (Output pins AnP, AnM, CLKnP and CLKnM) V Differential Output Voltage 250 345 450 mV R = 100Ω OD L Change in V between 3 35 mV ΔV OD OD Complimentary Output States V Offset Voltage 1.125 1.32 1.475 V OS Change in V between 1.5 35 mV ΔV OS OS Complimentary Output States I Output Short Circuit Current V = 0V 0 −8.5 -15 mA OS OUT I Output TRI-STATE Current PD = 0V, V = 0V or V ±0.1 ±10 µA OZ OUT CC SUPPLY CURRENT I 1 Transmitter Supply Current f = 65MHz, scaler 70 120 mA R = 100Ω, C = 5 CC L L when data input and clock input off, 2.75V supply pF, DUAL pin = are at Low Swing level. GND, BAL = GND, f = 65 MHz, scaler 38 90 mA one 12bit input, off, 3.6V supply Pattern Figure 1 I 2 Transmitter Supply Current f = 108MHz, scaler 85 130 mA R = 100Ω, C = 5 CC L L when data input and clock input off, 2.75V supply pF, DUAL pin = ½ are at Low Swing level. VCC, BAL = GND, f = 108 MHz, scaler 75 130 mA one 12bit input, off, 3.6V supply. Pattern Figure 1 I 3 Transmitter Supply Current f = 65 MHz, scaler 330 415 mA R = 100Ω, C = 5 CC L L when data input and clock input on, 2.75V supply pF, DUAL pin = are at Low Swing level. GND, BAL = GND, one 12bit input I 4 Transmitter Supply Current f = 108 MHz, scaler 483 610 mA R = 100Ω, C = 5 CC L L when data input and clock input on, 2.75V supply pF, DUAL pin = are at Low Swing level. ½V , BAL = CC GND, one 12bit input ICCTZ Transmitter Supply Current PD = GND. TST1, TST2, TST3, ID0, 75 µA Power Down ID1, ID2, ID3, A0, A1, A2, RES1, RES2, RES3, RES4 = GND, BAL = GND. www.national.com 4 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 Two-Wire Serial Communication Interface Unless otherwise noted, below specifications apply for V 3V pin = 3.0V to 3.6V. CC Symbol Parameter Conditions Min Typ Max Units V (1) Logical “ 1 ” input voltage 2.1 V IN V (0) Logical “ 0 ” input voltage 0.8 V IN V Serial Bus Low level output voltage I = 3mA 0.1 0.4 V OL OL I = 6mA 0.15 0.6 V OL Recommended DVO Port Input Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Min Typ Max Units TCIT TxCLK IN Transition Time (Figure 4) DUAL = Gnd 0.8 1.2 2.4 ns TCIP TxCLK IN Period (Figure 5) DUAL = Gnd 5.9 T 40 ns TCIH TxCLK in High Time (Figure 5) 0.35T 0.5T 0.65T ns TCIL TxCLK in Low Time (Figure 5) 0.35T 0.5T 0.65T ns TXIT D0 to D23 Transition Time 1 ns VDDQ Low Swing Voltage Amplitude from GMCH 1.0 1.8 V 5 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 AC Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Min Typ Max Units LLHT LVDS Low-to-High Transition Time (Figure 3). (Note 7) 0.14 0.8 ns LHLT LVDS High-to-Low Transition Time (Figure 3). (Note 7) 0.11 0.8 ns TBIT Transmitter Output Bit Width DUAL pin = V or Gnd 1/7 TCIP ns CC DUAL pin = ½V 2/7 TCIP ns CC TCCS TxOUT Channel to Channel Skew 100 ps TPPOS0 Transmitter Output Pulse Position for Bit 0 f = 65 MHz, DUAL pin = −0.49 0 +0.49 ns (previous cycle) from CLK1P rising edge. (Note V CC 7) TPPOS1 Transmitter Output Pulse Position for Bit1 f = 65 MHz, DUAL pin = (1/7)TCIP (1/7)TCIP (1/7)TCIP ns (previous cycle) from CLK1P rising edge. (Note V −0.49 +0.49 CC 7) TPPOS2 Transmitter Output Pulse Position for Bit2 from f = 65 MHz, DUAL pin = (2/7)TCIP (2/7)TCIP (2/7)TCIP ns CLK1P rising edge. (Note 7) V −0.49 +0.49 CC TPPOS3 Transmitter Output Pulse Position for Bit3 from f = 65 MHz, DUAL pin = (3/7)TCIP (3/7)TCIP (3/7)TCIP ns CLK1P rising edge. (Note 7) V −0.49 +0.49 CC TPPOS4 Transmitter Output Pulse Position for Bit4 from f = 65 MHz, DUAL pin = (4/7)TCIP (4/7)TCIP (4/7)TCIP ns CLK1P rising edge. (Note 7) V −0.49 +0.49 CC TPPOS5 Transmitter Output Pulse Position for Bit5 from f = 65 MHz, DUAL pin = (5/7)TCIP (5/7)TCIP (5/7)TCIP ns CLK1P rising edge. (Note 7) V −0.49 +0.49 CC TPPOS6 Transmitter Output Pulse Position for Bit6 from f = 65 MHz, DUAL pin = (6/7)TCIP (6/7)TCIP (6/7)TCIP ns CLK1P rising edge. (Note 7) V −0.49 +0.49 CC TSTC DxIN Setup to CLKINP (Figure 6) (Note 7) 0.8 ns THTC DxIN Hold to CLKINP (Figure 6) (Note 7) 0.8 ns TJCC Transmitter Jitter Cycle-to-cycle (Note 4) f = 85 MHz, DUAL pin = 114 ps Gnd f = 54 MHz, DUAL pin = 114 ps V CC TPLLS Transmitter Phase Lock Loop Set (Figure 7) (Note 7) 10 ms TPDD Transmitter Powerdown Delay (Figure 8) (Note 7) 100 ns Transmitter Input to Output Latency for single f = 170 MHz (Note 6) 1.5 TCIP ns in-to-dual out mode. Figure 9 +4.1 www.national.com 6 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 Two-Wire Serial Communication Interface Switching Characteristics Unless otherwise noted, below specifications apply for V 3V pin = +3.3V, load capacitance on output lines = 80 pF. CC Load capacitance on output lines can be up to 400pF provided that external pull-up is on board. The following parameters are the timing relationship between SCL and SDA signals related to the DS90C2501. Symbol Parameter Min Typ Max Units 2000 t SCL (Clock) Period 2.5 μs 1 (Note 7) t Data in Set-Up Time to SCL High 100 ns 2 t Data Out Stable after SCL Low 0 ns 3 t SDA Low Set-Up Time to SCL Low (Start Condition) 100 ns 4 t SDA High Hold Time after SCL High (Stop Condition) 100 ns 5 Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “DC Characteristics” and “AC Switching Characteristics” specify conditions for device operation. Note 2: Typical values are given for V = 2.5V and V = 3.3V at T = +25°C. CC CC3V A Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except V and ΔV ). OD OD Note 4: The limits are based on bench characterization of the device's jitter response over the power supply voltage range. Output clock jitter is measured with a cycle-to-cycle jitter of ± 20% data input bit time applied to the input clock signal while data inputs are switching (see figures 11 and 12). This parameter is used when calculating system margin as described in AN-1059. Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPOS). This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable) and clock jitter. RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle). Note 6: From V = 1.25V of CLKINP to V = 0V of CLK1P when EDGE pin = Gnd, DUAL pin = Gnd or V or ½V , BAL pin= Gnd. DIFF CC CC Note 7: Guaranteed by Design AC Timing Diagrams 20004532 FIGURE 1. “Alternate High/Low” Test Pattern in 12-bit Input Mode (Note 8) 7 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 20004551 FIGURE 2. “16 Grayscale” Test Pattern in 12-bit Input Mode(Note 9) Note 8: The “Alternate High/Low” test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 9: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. www.national.com 8 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 20004512 FIGURE 3. DS90C2501 (Transmitter) LVDS Output Load and Transition Times 20004514 FIGURE 4. DS90C2501 (Transmitter) Input Clock Transition Time 20004555 FIGURE 5. DS90C2501 (Transmitter) Input Clock High/Low Times 20004554 FIGURE 6. Setup/Hold Times, V = 0.900V, EDGE = Gnd, DUAL = V , BAL = Gnd REF CC 9 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 20004519 FIGURE 7. DS90C2501 (Transmitter) Phase Lock Loop Set Time 20004521 FIGURE 8. Transmitter Power Down Delay 20004553 FIGURE 9. Transmitter Input to Output Lantency www.national.com 10 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 20004525 C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos—Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference) (Note ISI is dependent on interconnect length; may be zero ) Cable Skew—typically 10 ps–40 ps per foot, media dependent Note 10: ISI is dependent on interconnect length; may be zero FIGURE 10. Receiver Skew Margin 20004508 FIGURE 11. Resistor Network for “DUAL” pin input - recommend using R1=R2=10kΩ ±1% for single to dual mode 11 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 Pin Descriptions Pin Name Pin No. I/O Type Description DVO INTERFACE D0–D23 17, 16, 15, I-LVTTL/ Low DVO Port RGB input data 14, 13, 12, Swing (See When DUAL pin = GND inputs D0–D11 correspond to LVDS ports A0–A3. 9, 8, 7, 6, 5, V signal When DUAL pin = ½V , 1st pixel from D0–D11 corresponds to LVDS ports A0–A3, 2nd REF CC 4, 32, 31, description for pixel from D0–D11 corresponds to LVDS ports A4–A7. 30, 29, 28, more When DUAL pin = V , 1st pixel from D0–D11 corresponds to LVDS ports A0–A3, 2nd CC 27, 26, 25, information on pixel from D12–D23 corresponds to LVDS ports A4–A7. 24, 23, 22, Low Swing) Note: Ports refer to the corresponding differential LVDS pin pairs. The port A nomenclature should not be confused with the serial interface slave address pins AO-A2. 21 DE 3 I-LVTTL/ Low Display Data Enable. When High, input pixel data is valid to DS90C2501 when R_FDE Swing bit = High (default). See RFDE register field for more information . HSYNC 2 I-LVTTL/ Low Display Horizontal Sync input control signal. Swing VSYNC 1 I-LVTTL/ Low Display Vertical Sync input control signal. Swing CLKINP 10 I-LVTTL/ Low “Positive” differential pixel clock input. A differential clock is recommended for Swing applications 65 MHz or higher. Differential CLKINM 11 I-LVTTL/ Low “Minus” differential pixel clock input. A differential clock is recommended for applications Swing 65 MHz or higher. Differential HOST INTERFACE RESETN 61 I-LVTTL 2.5 Active low RESET signal. Asserting RESETN will reset all internal logic and clear the Host Interface registers. S2CCLK 72 I-LVTTL3V This is the clock line for the two-wire serial communication interface. Normally a pull-up resistor is required in the system. S2CDAT 71 I/O-LVTTL3V This is the data line for two-wire serial communication interface. A Pull-up resistor is normally required in the system. MSEN 98 O-LVTTL 2.5 Interrupt signal. This is an open drain output, a pull-up resistor is required. Please refer to MDI, RSEN, TSEL and MSEL register fields in Register Field Definitions for more information. This signal requires support from host software. PD 99 I-LVTTL 2.5 Power Down Signal. A logic “0” will place the device in power down mode per Table 1 below. When maximum power savings is desired, the PD pin or soft power down bit (Reg 08h bit 0) should be used to power down the DS90C2501. LVDS outputs of the device will be in TRI-STATE. Scaling engine will be powered down, and retain all register values. PLL will be powered down. All data input pads will be powered down. V circuit is powered down. The two-wire REF serial communication interface remains active and all register contents will be retained. All GPIO pins will be disabled (tri-state if programmed as an output). ENAVDD, ENABKL, PWM, VSTALL and HIRQ pins remain active and can be accessed through the two-wire serial communication interface. CLOCK REFCLK1 18 I-LVTTL3V Reference clock,—A 3V, 14.318 MHz clock is required for internal control and timing. This clock must be stable when the DS90C2501 is powered-up. OPTION SELECTION BAL 97 I-LVTTL 2.5 Tie this pin to GND. www.national.com 12 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 Pin Name Pin No. I/O Type Description DUAL 35 I-LVTTL 2.5 LVTTL level input. Input = GND for single pixel in-to-single pixel out mode. LVDS output channels A0 to A3 are enabled, A4 to A7 are CLK2 are disable. Input = V for dual pixel in-to-dual pixel out mode. LVDS output channel A0 to A7, CLK1 CC and CLK2 are enable. Use a 10K typ. pull-up resistor. Input = ½V for single pixel in-to-dual pixel out mode. LVDS output channel A0 to A7, CC CLK1 and CLK2 are enabled. See register CFG1 (08h) BPASS field for more information. See Figure 11 for example interface circuit. COLOR 34 I-LVTTL 2.5 LVTTL level input to select RGB to LVDS color mapping. Tie to GND for 18-bit/36-bit LCD. Tie to GND to select conventional color mapping for 24-bit/48-bit LCD. Tie to Logic “1” to select non-conventional color mapping for 24-bit/48-bit LCD. A0, A1, A2 115, 116, I-LVTTL 2.5 These are input pins to select the 2-wire Serial Communication Slave Device Address 117 Lower Bits. EDGE 36 I-LVTTL 2.5 Selects primary clock edge E1. Tie to Logic “1” to select Rising edge for E1. Tie to ground to select Falling edge for E1. PANEL INTERFACE A0P, A1P, A2P, 55, 53, 51, O-LVDS Positive LVDS differential data output. A3P 47 When DUAL pin = GND, input to D0–D11 will be coming out of A0P to A3P. For 6-bit color application, no connect for channel A3P. When DUAL pin = ½V , the first pixel going in D0–D11 will be coming out of A0P to CC A3P, and the second pixel going in D0–D11 will come out of A4P to A7P. For 6-bit color application, no connect for channels A3P and A7P. When DUAL pin = V , the first pixel going in D0–D11 will be coming out of A0P to A3P, CC the second pixel going in D12–D23 will be coming out of A4P to A7P. For 6-bit color application, no connect for channels A3P and A7P. A0M, A1M, 56, 54, 52, O-LVDS Negative LVDS differential data output. A2M, A3M 48 When DUAL pin = GND, input to D0–D11 will be coming out of A0M to A3M. For 6-bit color application, no connect for channel A3M. When DUAL pin = ½V , the first pixel going in D0–D11 will be coming out of A0M to CC A3M, and the second pixel going in D0–D11 will come out of A4M to A7M. For 6-bit color application, no connect for channels A3M and A7M. When DUAL pin = V , the first pixel going in D0–D11 will be coming out of A0M to A3M, CC the second pixel going in D12–D23 will be coming out of A4M to A7M. For 6-bit color application, no connect for channels A3M and A7M. A4P, A5P, A6P, 45, 43, 41, O-LVDS Positive LVDS differential data output for second pixel. A7P 39 When DUAL pin = GND, input to D0–D11 will be coming out of A0P to A3P. For 6-bit color application, no connect for channel A3P. When DUAL pin = ½V , the first pixel going in D0–D11 will be coming out of A0P to CC A3P, and the second pixel going in D0–D11 will come out of A4P to A7P. For 6-bit color application, no connect for channels A3P and A7P. When DUAL pin = V , the first pixel going in D0–D11 will be coming out of A0P to A3P, CC the second pixel going in D12–D23 will be coming out of A4P to A7P. For 6-bit color application, no connect for channels A3P and A7P. A4M, A5M, 46, 44, 42, O-LVDS Negative LVDS differential data output for second pixel. A6M, A7M 40 When DUAL pin = GND, input to D0–D11 will be coming out of A0M to A3M. For 6-bit color application, no connect for channel A3M. When DUAL pin = ½V , the first pixel going in D0–D11 will be coming out of A0M to CC A3M, and the second pixel going in D0–D11 will come out of A4M to A7M. For 6-bit color application, no connect for channels A3M and A7M. When DUAL pin = V , the first pixel going in D0–D11 will be coming out of A0M to A3M, CC the second pixel going in D12–D23 will be coming out of A4M to A7M. For 6-bit color application, no connect for channels A3M and A7M. 13 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 Pin Name Pin No. I/O Type Description CLK1P 49 O-LVDS Positive LVDS differential clock output. CLK1M 50 O-LVDS Negative LVDS differential clock output. CLK2P 37 O-LVDS Additional positive LVDS differential clock output pin. Identical to CLK1P. No connect if not used. CLK2M 38 O-LVDS Additional negative LVDS differential clock output pin. Identical to CLK1M. No connect if not used. ID0, ID1, ID2, 57, 58, 59, I-LVTTL 2.5 These four pins are used to select one out of 16 pre-determined LCD display timing ID3 60 information. The values are from 0 to 15. This function requires support from VBIOS or display driver. Tie these pins to GND when not in use. Tie these four pins [ID3, ID2, ID1, ID0] to High or Low for selecting LCD panel. ID0 is the LSB, and ID3 is the MSB. For example: 1000 will select the 9th LCD panel. A 4-bit register field [3:0] will be used to store the selected value for the host to read. See PANEL field for more information. ENAVDD 69 O-LVTTL 2.5 Output to control LCD panel power under software control. Typically, this output is used with a power switch such as a FET circuit to control LCD panel V (Note 11). CC ENABKL 68 O-LVTTL 2.5 Output to control LCD panel back light power under software control. Typically, this output is used to control the enable on a backlight inverter (Note 11). MISCELLANEOUS/TEST GPIO1, GPIO2, 64, 63, 62 I/O-LVTTL 3V General purpose inputs or outputs referenced to GND. GPIO3 When the device is powered up, this pin defaults to an input. When the scaler is in the power down state these signals are tri-state if programmed as outputs (Note 11). CLK_INV 114 I-LVTTL 2.5 This pin is used to invert the polarity of the incoming pixel CLK (CLKINP/CLKINM). A logic 0 = Normal, Logic 1 = Invert. RES2 70 I-LVTTL 2.5 This pin is used in production testing and should be tied to GND in normal operation. RES3 113 I-LVTTL 2.5 This pin is used in production testing and should be tied to GND in normal operation. RES4 100 I-LVTTL 2.5 This pin is used in production testing and should be tied to GND in normal operation. PWM 67 O-LVTTL 3V This signal was provided for legacy support and is no longer required. This pin should be left open in normal operation. VSTALL 66 O-LVTTL 3V This signal was provided for legacy support and is no longer required. This pin should be left open in normal operation. HIRQ 65 O-LVTTL 3V This signal was provided for legacy support and is no longer required. This pin should be left open in normal operation. V 83 I-ANALOG This pin is never to be left floating and never tie to GND. REF For LVTTL level data input, tie V to V 3V. When V > 1.8V, input data is set to REF CC REF LVTTL level. For low voltage swing level data input, tie V to ½V (V provided by host REF DDQ DDQ interface) V is from the host. When V <=1.0V, indicates input data is in low voltage DDQ REF swing mode. Input data = logic High = V +100 mV in low voltage swing level. REF Input data = logic Low = V −100 mV in low voltage swing level. REF TST1, TST2, 19, 20, 85 I-LVTTL 2.5 These pins are used in production testing and should be tied to GND in normal operation. TST3 POWER (See Application Information for power supply decoupling requirements) V /DV 81, 82, 75, PWR Power supply pins (pin 75, 77, 81, 82, 96, 119, 123, and 125) for 2.5V LVTTL inputs and CC CC 77, 96, digital circuitry. 119, 123, 125 GND/DGND 33, 73, 74, PWR GND or DGND reference for 2.5V TTL inputs and digital circuitry. 76, 78, 79, 80, 84, 118, 122, 124 www.national.com 14 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 Pin Name Pin No. I/O Type Description V 3V 121, 127 PWR The V 3V is required for internal logic and certain 3V I/O. CC CC During power up stage, voltage readings on these pins must be higher than 2.5V pins. GND3V 120, 126, PWR Ground return pins for V 3V powered logic. CC 128 SPLLV 87, 89 PWR 2.5V power supply pins for scaler PLL circuitry. It is not recommended to share this power CC with PLLV . CC SPLLGND 86, 88, 90 PWR Ground returns for scaler PLL circuitry. PLLV 92, 94 PWR 2.5V power supply pins for Tx PLL circuitry. It is not recommended to share this power CC with SPLLV . CC PLLGND 91, 93, 95 PWR Ground returns for Tx PLL circuitry. LVDSV 105, 109 PWR Power supply pins for LVDS output drivers. CC LVDSGND 104, 108 PWR Ground return pins for LVDS output drivers. LVDSV 3V 101, 103, PWR 3V power supply pins for LVDS output drivers. CC 107, 111 During power up stage, voltage readings on these pins must be higher than 2.5V pins. LVDSGND3V 102, 106, PWR Ground return pins for 3V LVDS outputs. 110, 112 Note 11: When device power is applied, it is possible for these outputs to switch to a logic “1” momentarily as the 3.3V is rising and before 2.5V reaches at least 0.8V. During this brief period, the pad control logic could be non-deterministic, RESETN will have no effect. It is recommended these outputs are gated externally if the system design requires them to remain in the inactive logic “0” state during power-on. 15 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 TABLE 1. Scaler Is Powered Down Under These Conditions scaler is On scaler is OFF /PD pin H L DUAL pin provided L or ½V L or ½V or VCC CC CC that PD bit is 1 and BYPASS bit is 0 No input clock is NO YES detected PD bit issued by 1 0 host BYPASS bit issued 0 1 by host. The DS90C2501 latches the state of the address select pins Two-Wire Serial Communication during the first read or write on the Serial Bus. Changing the state of the address select pins after the first read or write to Interface Description any device on the Serial Bus will not change the slave address There are two register sets on DS90C2501. One set is for of the DS90C2501. controlling the input and output blocks as shown below, and one set is for controlling the scaler which is not shown on this COMMUNICATING WITH THE DS90C2501 CONTROL datasheet. Both register sets are accessible by the host sys- REGISTERS tem through the Two-Wire Serial Communication Interface. All registers are predefined as read only, or read and write. The DS90C2501 operates as a slave on the Serial Bus, so The Serial Interface will always attempt to detect if a LCD the SCL line is an input (no clock is generated by the panel/monitor is connected. DS90C2501) and the SDA line is bi-directional. DS90C2501 A Write to the DS90C2501 will always include the slave ad- has a 7-bit slave address. The address bits are controlled by dress byte, data register address byte, a data byte. the state of the address select pins A2, A1 and A0, and are A Read from the DS90C2501 can take place either of two set by connecting these pins to ground for a LOW, (0) , to ways: V 3V pin for a HIGH, (1). CC 1. If the location latched in the data register addresses is Therefore, the complete slave address is: correct , then the read can simply consist of a slave A6 A5 A4 A3 A2 A1 A0 address byte, followed by retrieving the data byte. MSB LSB 2. If the data register address needs to be set, then a slave address byte, data register address will be sent first, then and is selected as follows: the master will repeat start, send the slave address byte and receive data byte to accomplish a read. Address Select Pin DS90C2501 Serial The data byte has the most significant bit first. At the end of State Bus Slave Address a read, the DS90C2501 can accept either Acknowledge or No (A6:A3 are hardwired to Acknowledge from the Master (No Acknowledge is typically "0111") used as a signal for the slave that the Master has read its last A2 A1 A0 A6:A0 binary byte). 0 0 0 0111000 Serial Bus Protocol 0 0 1 0111001 The DS90C2501 slave state machine does not require an in- 0 1 0 0111010 ternal clock, and supports only byte read and write. Page 0 1 1 0111011 mode is not supported. The 7-bit binary address is 1 0 0 0111100 “0111A A A ”, where A A A are pin programmable and 2 1 0 2 1 0 1 0 1 0111101 A6:A3 are hardwired internally to "0111" 1 1 0 0111110 1 1 1 0111111 www.national.com 16 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 20004530 FIGURE 12. Byte Read The master must generate a “ Start ”, and send the 7-bit slave acknowledge from the master. When the master acknowl- address plus a 0 first, and wait for acknowledge from edges (the 4th ACK), and generates a “ Stop ”, this completes DS90C2501. When DS90C2501 acknowledges (the 1st ACK) the “ READ ”. that the master is calling, the master then sends the data reg- If the 4th ACK is received from the master and no “ Stop ” ister address byte, and waits for acknowledge from the slave. follows it, the slave will keep sending the data of next register When the slave acknowledges(the 2nd ACK), the master re- until “ Stop ” is received from the master. If the 4th ACK is not peats the “ Start ” by sending the 7-bit slave address plus a 1 received from the master, the slave will terminate the Serial (indicating that READ operation is in progress), and waits for Bus communication, and giving the bus control back to the acknowledge from DS90C2501. After the slave responds (the master. 3rd ACK), the slave sends the data to the bus, and waits for 20004531 FIGURE 13. Byte Write The master must generate a “ Start ”, and send the 7-bit slave slave. If the slave acknowledges, the master can send data address plus a 0 and wait for acknowledge from DS90C2501. to the next register address (Register Address + 2). If the When DS90C2501 acknowledges (the 1st ACK), that the slave doesn't acknowledges, the master will have the control master is calling, the master then sends the data register ad- of the bus and can generate a “ Stop ” to end the “ WRITE”op- dress byte, and waits for acknowledge from the slave. When eration. During the process, if the master attempts to send the slave acknowledges (the 2nd ACK), the master sends the data to “ Read Only ” registers, the slave will not acknowledge data byte and wait for acknowledge from the slave. When the and return the bus control back to the master. slave acknowledges (the 3rd ACK), the master generates a “ A complete programming guide is available for the Stop ”. This completes the “ WRITE ”. DS90C2501 to OEM customers. This can be obtained by If the master doesn't generate the “ Stop ”, the master can contacting your local National Semiconductor sales repre- keep sending data to location of the next register address sentative. (Register Address + 1), and waits for acknowledge from the 17 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 Host Control Register Descriptions Register Name: VND_IDL Address Offset: 00h Default Value: 05h Access Method: Read Only Bit Description 7:0 Vendor ID Low Byte Register Name: VND_IDH Address Offset: 01h Default Value: 13h Access Method: Read Only Bit Description 7:0 Vendor ID High Byte Register Name: DEV_IDL Address Offset: 02h Default Value: 26h Access Method: Read Only Bit Description 7:0 Device ID Low Byte Register Name: DEV_IDH Address Offset: 03h Default Value: 67h Access Method: R/W Bit Description 7:0 Device ID High Byte Register Name: DEVICE REVISION Address Offset: 04h Default Value: 01h Access Method: R/W Bit Description 7:0 Device Revision Value Register Name: RESERVED Address Offset: 05h Default Value: A5h Access Method: Read Only Bit Description 7:0 Reserved www.national.com 18 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 Register Name: FRQ_LOW Address Offset: 06h Default Value: 19h Access Method: Read Only Bit Description 7:0 Minimum LVDS Output Frequency (25 MHz) Register Name: FRQ_HIGH Address Offset: 07h Default Value: See Description Access Method: Read Only Bit Description 7:0 Maximum LVDS Output Frequency If DUAL = GND or V value is A2h (162 MHz) CC If DUAL = ½V value is 55h (85 MHz) CC Register Name: CFG1 Address Offset: 08h Default Value: 39h Access Method: R/W Bit Description 0 Soft Power Down; 0 = Power Down, 1 = Normal Operation 1 Reserved 2 BPASS (1 = bypass, 0 = non-bypass) This field is valid only when DUAL pin is 0V or ½V . Note: When image scaling is not required power savings can CC be achieved in bypass mode. 3 DSEL 0= Input clock is differential (recommended for clocks above 65 MHz), 1= input clock is single-ended 4 HEN (HSYNC enable) 0= HSYNC is transmitted as a fixed low, 1= HSYNC is same as input 5 VEN (VSYNC enable) 0= VSYNC is transmitted as a fixed low, 1= VSYNC is same as input 7:6 Reserved 19 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 Register Name: CFG2 Address Offset: 09h Default Value: 95h Access Method: R/W Bit Description 0 MDI (read only) 1 Reserved 2 RSEN (read only)—Receiver Sense 0= LVDS receiver connected to transmitter output, 1= No receiver connected Note: this function is valid only with DC coupled systems 3 TSEL —Interrupt generation 0= Interrupt bit (MDI) is generated by monitoring RSEN, fixed valve 4:6 MSEL (R/W)—Selects source for MSEL output pin 000= MSEN disabled 001= Output the MDI bit - interrupt 010= Output the RSEN bit - receiver detect 011–111= Reserved 7 VLOW (read only) 1= V set for low swing, REF 0= V set for LVTTL REF Register Name: CFG3 Address Offset: 0Ah Default Value: 81H Access Method: R/W Bit Description 0 R_FDE- Input DE strobe Polarity Select 0 = DE active Low, 1 = DE active High 3:1 Reserved 7:4 Reserved Register Name: CFG Address Offset: 0Bh Default Value: See Description Access Method: Read Only Bit Description 7:0 Contains state of input data bits 23:16 Register Name: PANEL Address Offset: 0Ch Default Value: See Description Access Method: R/W Bit Description 0:3 System defined Panel ID values set on ID0:3 pins (Read Only) 4:7 System defined Panel ID field which can be written/ read from host www.national.com 20 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 Register Name: DEBUG_A Address Offset: 0Dh Default Value: See Description—Depends on pin state Access Method: Mixed Bit Description 1:0 DUAL (1:0), State of DUAL pin (Read Only) 00= SISO 01= SIDO 11= DIDO 2 PLLOCK (Read Only) 3 Reserved (Read Only) 7:4 Reserved (R/W) Register Name: RESERVED Address Offset: 0Eh–0Fh Default Value: 00h Access Method: R/W Bit Description 7:0 Reserved LVDS Interface TABLE 2. LVDS data bit naming convention X Y Z Description X=R Red X=G Green X=B Blue Y=1 Odd (First) Pixel Y=2 Even (Second) Pixel Z=0-7 LVDS bit number (not VGA controller LSB to MSB) 21 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 TABLE 3. Conventional Data mapping for one 12-bit (two data per clock )single pixel in-to-single pixel out application (DUAL = Gnd, only Port1 A0-A3 are active, BAL = Gnd) VGA - TFT Data Signals Color Transmitter input pin names Receiver output pin names TFT Panel Data Bits Signals 24-bit 18-bit DS90C2501 DS90CF388 18-bit 24-bit LSB R0 E2-D4 R16 R0 R1 E2-D5 R17 R1 R2 R0 E2-D6 R10 R0 R2 R3 R1 E2-D7 R11 R1 R3 R4 R2 E2-D8 R12 R2 R4 R5 R3 E2-D9 R13 R3 R5 R6 R4 E2-D10 R14 R4 R6 MSB R7 R5 E2-D11 R15 R5 R7 LSB G0 E1-D8 G16 G0 G1 E1-D9 G17 G1 G2 G0 E1-D10 G10 G0 G2 G3 G1 E1-D11 G11 G1 G3 G4 G2 E2-D0 G12 G2 G4 G5 G3 E2-D1 G13 G3 G5 G6 G4 E2-D2 G14 G4 G6 MSB G7 G5 E2-D3 G15 G5 G7 LSB B0 E1-D0 B16 B0 B1 E1-D1 B17 B1 B2 B0 E1-D2 B10 B0 B2 B3 B1 E1-D3 B11 B1 B3 B4 B2 E1-D4 B12 B2 B4 B5 B3 E1-D5 B13 B3 B5 B6 B4 E1-D6 B14 B4 B6 MSB B7 B5 E1-D7 B15 B5 B7 www.national.com 22 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 TABLE 4. Conventional Data mapping for one 12-bit (two data per clock )single pixel in-to-dual pixel out application (DUAL = 1/2V , Port1 A0-A3 and Port2 A4-A7 are active, BAL = Gnd) CC VGA - TFT Data Transmitter input pin names Receiver output pin names TFT Panel Data Signals Color Bits Signals 24-bit DS90C2501 DS90CF388 18-bit 24-bit Port 1-Primary (the first active RGB pixel) LSB R0 E2-D4 R16 RO0 R1 E2-D5 R17 RO1 R2 E2-D6 R10 RO0 RO2 R3 E2-D7 R11 RO1 RO3 R4 E2-D8 R12 RO2 RO4 R5 E2-D9 R13 RO3 RO5 R6 E2-D10 R14 RO4 RO6 MSB R7 E2-D11 R15 RO5 RO7 LSB G0 E1-D8 G16 GO0 G1 E1-D9 G17 GO1 G2 E1-D10 G10 GO0 GO2 G3 E1-D11 G11 GO1 GO3 G4 E2-D0 G12 GO2 GO4 G5 E2-D1 G13 GO3 GO5 G6 E2-D2 G14 GO4 GO6 MSB G7 E2-D3 G15 GO5 GO7 LSB B0 E1-D0 B16 BO0 B1 E1-D1 B17 BO1 B2 E1-D2 B10 BO0 BO2 B3 E1-D3 B11 BO1 BO3 B4 E1-D4 B12 BO2 BO4 B5 E1-D5 B13 BO3 BO5 B6 E1-D6 B14 BO4 BO6 MSB B7 E1-D7 B15 BO5 BO7 Port 2-Secondary (the second active RGB pixel) LSB R0 E4-D4 R26 RE0 R1 E4-D5 R27 RE1 R2 E4-D6 R20 RE0 RE2 R3 E4-D7 R21 RE1 RE3 R4 E4-D8 R22 RE2 RE4 R5 E4-D9 R23 RE3 RE5 R6 E4-D10 R24 RE4 RE6 MSB R7 E4-D11 R25 RE5 RE7 LSB G0 E3-D8 G26 GE0 G1 E3-D9 G27 GE1 G2 E3-D10 G20 GE0 GE2 G3 E3-D11 G21 GE1 GE3 G4 E4-D0 G22 GE2 GE4 G5 E4-D1 G23 GE3 GE5 G6 E4-D2 G24 GE4 GE6 MSB G7 E4-D3 G25 GE5 GE7 LSB B0 E3-D0 B26 BE0 B1 E3-D1 B27 BE1 B2 E3-D2 B20 BE0 BE2 B3 E3-D3 B21 BE1 BE3 23 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 VGA - TFT Data Transmitter input pin names Receiver output pin names TFT Panel Data Signals Color Bits Signals B4 E3-D4 B22 BE2 BE4 B5 E3-D5 B23 BE3 BE5 B6 E3-D6 B24 BE4 BE6 MSB B7 E3-D7 B25 BE5 BE7 www.national.com 24 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 TABLE 5. Conventional Data Mapping for two 12-bit (two data per clock)dual pixel in-to-dual pixel out application(DUAL = V , Port1 A0-A3 and Port2 A4-A7 are active, BAL = Gnd. ) CC VGA - TFT Data Transmitter input pin names Receiver output pin names TFT Panel Data Signals Color Bits Signals 24-bit DS90C2501 DS90CF388 18-bit 24-bit Port 1-Primary ( the first active RGB pixel) LSB R0 E2-D4 R16 R0 R1 E2-D5 R17 R1 R2 E2-D6 R10 R0 R2 R3 E2-D7 R11 R1 R3 R4 E2-D8 R12 R2 R4 R5 E2-D9 R13 R3 R5 R6 E2-D10 R14 R4 R6 MSB R7 E2-D11 R15 R5 R7 LSB G0 E1-D8 G16 G0 G1 E1-D9 G17 G1 G2 E1-D10 G10 G0 G2 G3 E1-D11 G11 G1 G3 G4 E2-D0 G12 G2 G4 G5 E2-D1 G13 G3 G5 G6 E2-D2 G14 G4 G6 MSB G7 E2-D3 G15 G5 G7 LSB B0 E1-D0 B16 B0 B1 E1-D1 B17 B1 B2 E1-D2 B10 B0 B2 B3 E1-D3 B11 B1 B3 B4 E1-D4 B12 B2 B4 B5 E1-D5 B13 B3 B5 B6 E1-D6 B14 B4 B6 MSB B7 E1-D7 B15 B5 B7 Port 2-Secondary ( the second active RGB pixel) LSB R0 E2-D16 R26 R0 R1 E2-D17 R27 R1 R2 E2-D18 R20 R0 R2 R3 E2-D19 R21 R1 R3 R4 E2-D20 R22 R2 R4 R5 E2-D21 R23 R3 R5 R6 E2-D22 R24 R4 R6 MSB R7 E2-D23 R25 R5 R7 LSB G0 E1-D20 G26 G0 G1 E1-D21 G27 G1 G2 E1-D22 G20 G0 G2 G3 E1-D23 G21 G1 G3 G4 E2-D12 G22 G2 G4 G5 E2-D13 G23 G3 G5 G6 E2-D14 G24 G4 G6 MSB G7 E2-D15 G25 G5 G7 LSB B0 E1-D12 B26 B0 B1 E1-D13 B27 B1 B2 E1-D14 B20 B0 B2 B3 E1-D15 B21 B1 B3 25 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 VGA - TFT Data Transmitter input pin names Receiver output pin names TFT Panel Data Signals Color Bits Signals B4 E1-D16 B22 B2 B4 B5 E1-D17 B23 B3 B5 B6 E1-D18 B24 B4 B6 MSB B7 E1-D19 B25 B5 B7 www.national.com 26 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 TABLE 6. Non-Conventional Data mapping for one 12-bit (two data per clock )single pixel in-to-single pixel out application (DUAL = Gnd, only Port1 A0-A3 are active, BAL= Gnd) VGA - TFT Data Signals Color Transmitter input pin names Receiver output pin names TFT Panel Data Bits Signals 24-bit 18-bit DS90C2501 DS90CF388 18-bit 24-bit LSB R0 E2-D4 R16 R0 R1 E2-D5 R17 R1 R2 R0 E2-D6 R10 R0 R2 R3 R1 E2-D7 R11 R1 R3 R4 R2 E2-D8 R12 R2 R4 R5 R3 E2-D9 R13 R3 R5 R6 R4 E2-D10 R14 R4 R6 MSB R7 R5 E2-D11 R15 R5 R7 LSB G0 E1-D8 G16 G0 G1 E1-D9 G17 G1 G2 G0 E1-D10 G10 G0 G2 G3 G1 E1-D11 G11 G1 G3 G4 G2 E2-D0 G12 G2 G4 G5 G3 E2-D1 G13 G3 G5 G6 G4 E2-D2 G14 G4 G6 MSB G7 G5 E2-D3 G15 G5 G7 LSB B0 E1-D0 B16 B0 B1 E1-D1 B17 B1 B2 B0 E1-D2 B10 B0 B2 B3 B1 E1-D3 B11 B1 B3 B4 B2 E1-D4 B12 B2 B4 B5 B3 E1-D5 B13 B3 B5 B6 B4 E1-D6 B14 B4 B6 MSB B7 B5 E1-D7 B15 B5 B7 27 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 TABLE 7. Non-Conventional Data mapping for one 12-bit (two data per clock )single pixel in-to-dual pixel out application (DUAL = 1/2V , Port1 A0-A3 and Port2 A4-A7 are active, BAL = Gnd) CC VGA - TFT Data Transmitter input pin names Receiver output pin names TFT Panel Data Signals Color Bits Signals 24-bit DS90C2501 DS90CF388 18-bit 24-bit Port 1-Primary ( the first active RGB pixel) LSB R0 E2-D4 R16 RO0 R1 E2-D5 R17 RO1 R2 E2-D6 R10 RO0 RO2 R3 E2-D7 R11 RO1 RO3 R4 E2-D8 R12 RO2 RO4 R5 E2-D9 R13 RO3 RO5 R6 E2-D10 R14 RO4 RO6 MSB R7 E2-D11 R15 RO5 RO7 LSB G0 E1-D8 G16 GO0 G1 E1-D9 G17 GO1 G2 E1-D10 G10 GO0 GO2 G3 E1-D11 G11 GO1 GO3 G4 E2-D0 G12 GO2 GO4 G5 E2-D1 G13 GO3 GO5 G6 E2-D2 G14 GO4 GO6 MSB G7 E2-D3 G15 GO5 GO7 LSB B0 E1-D0 B16 BO0 B1 E1-D1 B17 BO1 B2 E1-D2 B10 BO0 BO2 B3 E1-D3 B11 BO1 BO3 B4 E1-D4 B12 BO2 BO4 B5 E1-D5 B13 BO3 BO5 B6 E1-D6 B14 BO4 BO6 MSB B7 E1-D7 B15 BO5 BO7 Port 2-Secondary ( the second active RGB pixel) LSB R0 E4-D4 R26 RE0 R1 E4-D5 R27 RE1 R2 E4-D6 R20 RE0 RE2 R3 E4-D7 R21 RE1 RE3 R4 E4-D8 R22 RE2 RE4 R5 E4-D9 R23 RE3 RE5 R6 E4-D10 R24 RE4 RE6 MSB R7 E4-D11 R25 RE5 RE7 LSB G0 E3-D8 G26 GE0 G1 E3-D9 G27 GE1 G2 E3-D10 G20 GE0 GE2 G3 E3-D11 G21 GE1 GE3 G4 E4-D0 G22 GE2 GE4 G5 E4-D1 G23 GE3 GE5 G6 E4-D2 G24 GE4 GE6 MSB G7 E4-D3 G25 GE5 GE7 LSB B0 E3-D0 B26 BE0 B1 E3-D1 B27 BE1 B2 E3-D2 B20 BE0 BE2 B3 E3-D3 B21 BE1 BE3 www.national.com 28 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 VGA - TFT Data Transmitter input pin names Receiver output pin names TFT Panel Data Signals Color Bits Signals B4 E3-D4 B22 BE2 BE4 B5 E3-D5 B23 BE3 BE5 B6 E3-D6 B24 BE4 BE6 MSB B7 E3-D7 B25 BE5 BE7 29 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 TABLE 8. Non-Conventional Data Mapping for two 12-bit (two data per clock)dual pixel in-to-dual pixel out application (DUAL= V , Port1 A0-A3 and Port2 A4-A7 are active, BAL= Gnd. ) CC VGA - TFT Data Transmitter input pin names Receiver output pin names TFT Panel Data Signals Color Bits Signals 24-bit DS90C2501 DS90CF388 18-bit 24-bit Port 1-Primary (the first active RGB pixel) LSB R0 E2-D4 R16 R0 R1 E2-D5 R17 R1 R2 E2-D6 R10 R0 R2 R3 E2-D7 R11 R1 R3 R4 E2-D8 R12 R2 R4 R5 E2-D9 R13 R3 R5 R6 E2-D10 R14 R4 R6 MSB R7 E2-D11 R15 R5 R7 LSB G0 E1-D8 G16 G0 G1 E1-D9 G17 G1 G2 E1-D10 G10 G0 G2 G3 E1-D11 G11 G1 G3 G4 E2-D0 G12 G2 G4 G5 E2-D1 G13 G3 G5 G6 E2-D2 G14 G4 G6 MSB G7 E2-D3 G15 G5 G7 LSB B0 E1-D0 B16 B0 B1 E1-D1 B17 B1 B2 E1-D2 B10 B0 B2 B3 E1-D3 B11 B1 B3 B4 E1-D4 B12 B2 B4 B5 E1-D5 B13 B3 B5 B6 E1-D6 B14 B4 B6 MSB B7 E1-D7 B15 B5 B7 Port 2-Secondary ( the second active RGB pixel) LSB R0 E2-D16 R26 R0 R1 E2-D17 R27 R1 R2 E2-D18 R20 R0 R2 R3 E2-D19 R21 R1 R3 R4 E2-D20 R22 R2 R4 R5 E2-D21 R23 R3 R5 R6 E2-D22 R24 R4 R6 MSB R7 E2-D23 R25 R5 R7 LSB G0 E1-D20 G26 G0 G1 E1-D21 G27 G1 G2 E1-D22 G20 G0 G2 G3 E1-D23 G21 G1 G3 G4 E2-D12 G22 G2 G4 G5 E2-D13 G23 G3 G5 G6 E2-D14 G24 G4 G6 MSB G7 E2-D15 G25 G5 G7 LSB B0 E1-D12 B26 B0 B1 E1-D13 B27 B1 B2 E1-D14 B20 B0 B2 B3 E1-D15 B21 B1 B3 www.national.com 30 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 VGA - TFT Data Transmitter input pin names Receiver output pin names TFT Panel Data Signals Color Bits Signals B4 E1-D16 B22 B2 B4 B5 E1-D17 B23 B3 B5 B6 E1-D18 B24 B4 B6 MSB B7 E1-D19 B25 B5 B7 31 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 20004533 FIGURE 14. How Data is Latched in the DS90C2501 Note 12: The lower half of the pixel is latched by the primary clock edge E1. Note 13: E3 and E4 only apply when DUAL pin = 1/2 V . CC Note 14: Above figure only valid when R_FDE bit = V , DE signal from GUI is set to be active HIGH. CC Note 15: D0 to D11 are clocked at the crossing point of CLKOUT+ and CLKOUT− when differential clock input is applied. This applies to D12 to D23 when DUAL pin = V . CC Note 16: Single-ended clock is not recommended for operation above 65MHz by GMCH vendor. TABLE 9. 12-bit (two data per clock) input application data mapping with GMCH. P0 P1 P2 P0L P0H P1L P1H P2L P2H Pin Name Low High Low High Low High D11 G0[3] R0[7] G1[3] R1[7] G2[3] R2[7] D10 G0[2] R0[6] G1[2] R1[6] G2[2] R2[6] D9 G0[1] R0[5] G1[1] R1[5] G2[1] R2[5] D8 G0[0] R0[4] G1[0] R1[4] G2[0] R2[4] D7 B0[7] R0[3] B1[7] R1[3] B2[7] R2[3] D6 B0[6] R0[2] B1[6] R1[2] B2[6] R2[2] D5 B0[5] R0[1] B1[5] R1[1] B2[5] R2[1] D4 B0[4] R0[0] B1[4] R1[0] B2[4] R2[0] D3 B0[3] G0[7] B1[3] G1[7] B2[3] G2[7] D2 B0[2] G0[6] B1[2] G1[6] B2[2] G2[6] D1 B0[1] G0[5] B1[1] G1[5] B2[1] G2[5] D0 B0[0] G0[4] B1[0] G1[4] B2[0] G2[4] Note 17: Color notation: R = RED, G = GREEN, B = BLUE. Note 18: Bit significance within a color: [7:0] = [MSB:LSB]. www.national.com 32 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 20004535 FIGURE 15. 24bit/48bit Conventional Data Inputs Mapped to LVDS Outputs (BAL = Gnd, DUAL = Gnd for A0 to A3-first pixel, DUAL = V for A0 to A7-first pixel and second pixel) CC 33 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 20004538 FIGURE 16. 24bit/48bit Conventional Data Inputs Mapped to LVDS Outputs ( BAL = Gnd, DUAL = 1/2V for A0 to A7-first pixel and second pixel) CC www.national.com 34 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 20004558 FIGURE 17. 24bit/48bit Non-Conventional Data Inputs Mapped to LVDS Outputs (BAL = Gnd, DUAL = Gnd for A0 to A3-first pixel, DUAL = V for A0 to A7-first pixel and second pixel) CC 35 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 20004560 FIGURE 18. 24bit/48bit Non-Conventional Data Inputs Mapped to LVDS Outputs (BAL = Gnd, DUAL = 1/2V for A0 to A7-first pixel and second pixel) CC www.national.com 36 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 In free-run mode, the display timing is decided by the values Scaler Information programmed into the various timing registers. In line-lock mode, the display line rate is a function of the selected input DVO INPUT AND BYPASS MODE clock, forcing the output frame rate to be locked to input frame The input single port DVO data is translated into 18bit/24bit rate. Timing management is more complicated The frame- RGB data for scaling. Single port data over 108MHz or dual lock mode is used more often. The output pixel clock and port data will be bypassed and not scaled. The LVDS output Hsync are generated from the external 14.318MHz reference can be single or dual port. clock and the embedded PLL, but the Vsync is refreshed at the input frame rate. INPUT TIMING CONTROL The DS90C2501 input timing is fully programmable through Output Timing Control two-wire serial communication interface for different display mode requirements. Input timing information such as hori- The DS90C2501 output timing is fully programmable through zontal and vertical sync width, pixel-total and line-total count two-wire serial communication interface for different panel re- and the active video starting and ending positions can be pro- quirements. When 6-bit color LCD is used, dithering can be vided by the host through two-wire serial communication turned on via two-wire serial communication programming in- interface to help determine the input mode. terface. The least two LSB of each color are default to be logic low all the time. When 8-bit color LCD is used, dithering is not DISPLAY SYNCHRONIZATION needed, and can be turned off via two-wire serial communi- The DS90C2501 synchronizes the display timing with input cation programming interface. graphics timing so that no external frame buffer is needed. To invoke the scaling feature, the graphics processors must There are three operation modes: program DS90C2501 through two-wire serial communication Free-run mode: No synchronization. Output timing is gener- interface. ated from external 14.318MHz reference clock. Contact local National Semiconductor representative to ob- Line lock mode: the display Hsync is synchronized with the tain "DS90C2501 Programming Guide" for further information input line rate. on programming these features. Frame lock mode: the display Vsync is synchronized with the input frame rate. 37 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 20004566 1 Vertical Scaling Region Start 2 Vertical Scaling Region End 3 Horizontal Scaling Region Start 4 Horizontal Scaling Region End FIGURE 19. Input Timing of DS90C2501 scaler 1of 2 20004567 FIGURE 20. Input Timing of DS90C2501 scaler 2 of 2 www.national.com 38 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 20004568 1 Vsync start. 2 Vsync end. 3 Vertical action region start. 4 Vertical action region end. 5 Total vertical scan-lines in a frame. 6 Hsync start. 7 Hsync end. 8 Horizontal active region start. 9 Horizontal active region end. 10 Total horizontal pixels in a scan-line. FIGURE 21. Display Signal Timing of DS90C2501 scaler 1of 2 39 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 20004557 FIGURE 22. Display Signal Timing of DS90C2501 scaler 2 of 2 20004562 FIGURE 23. Sample LCD Power Up Sequence www.national.com 40 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 FEATURES DESCRIPTION Applications Information 2. Programmable Primary Edge E1 HOW TO CONFIGURE THE DS90C2501 WITH DS90C364 The transmitter is latching data on both the rising and falling OR DS90CF364A OR DS90CF366 FOR MOST COMMON edges of clock signal coming in on CLKINP pin. The EDGE APPLICATION pin can be used to program to select the rising edge of CLK- INP as the primary edge E1 or to have the falling edge of 1. To configure for single pixel in to single pixel out application CLKINP as the primary edge E1. However, the logic state of using the DS90C2501 with DS90CF364 or DS90CF364A or the EDGE pin must agree with the GUI to generate the correct DS90CF366, the “DUAL” pin must be set to Gnd (single). In display. this mode, outputs A0-to-A3 and CLK1 are enabled, and out- puts A4-to-A7 and CLK2 are disabled which reduces power dissipation. TABLE 10. Connection for SISO Operation From DS90C2501 To GMCH RGB data signal connection D0 DVOxDATA0 D1 DVOxDATA1 D2 DVOxDATA2 D3 DVOxDATA3 D4 DVOxDATA4 D5 DVOxDATA5 D6 DVOxDATA6 D7 DVOxDATA7 D8 DVOxDATA8 D9 DVOxDATA9 D10 DVOxDATA10 D11 DVOxDATA11 D12 to D23 GND CLKINP DVOxCLKOUT1 CLKINM DVOxCLKOUT0 DE DVOxBLANK HSYNC DVOxHSYNC VSYNC DVOxVYSNC connection for other pins DUAL GND EDGE GND BAL GND A0 Pull Up/Pull Down, Based on Device Address A1 Pull Up/Pull Down, Based on Device Address A2 Pull Up/Pull Down, Based on Device Address ID0 Pull Up/Pull Down, Based on Panel ID ID1 Pull Up/Pull Down, Based on Panel ID ID2 Pull Up/Pull Down, Based on Panel ID ID3 Pull Up/Pull Down, Based on Panel ID RES1 GND RES2 GND RES3 GND RES4 GND TST1 GND TST2 GND TST3 GND S2Cclk I2CCLK S2Cdat I2CDATA 41 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 REFCLK 3V 14.31818MHz COLOR GND PD DVCC or equivalent RSETN DVCC or equivalent VREF ½V of GMCH DDQ www.national.com 42 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 3. To configure for single pixel in to dual pixel out application Table 10. The “DUAL” pin must be set to Gnd. In this mode, using the DS90C2501 for Single-In-Single-Out operation, see outputs A0-to-A7, and CLK1, CLK2 are enabled. TABLE 11. Connection for SIDO Operation From DS90C2501 To GMCH RGB data signal connection D0 DVOxDATA0 D1 DVOxDATA1 D2 DVOxDATA2 D3 DVOxDATA3 D4 DVOxDATA4 D5 DVOxDATA5 D6 DVOxDATA6 D7 DVOxDATA7 D8 DVOxDATA8 D9 DVOxDATA9 D10 DVOxDATA10 D11 DVOxDATA11 D12 to D23 GND CLKINP DVOxCLKOUT1 CLKINM DVOxCLKOUT0 DE DVOxBLANK HSYNC DVOxHSYNC VSYNC DVOxVYSNC connection for other pins DUAL ½VCC EDGE GND BAL GND A0 Pull Up/Pull Down, Based on Device Address A1 Pull Up/Pull Down, Based on Device Address A2 Pull Up/Pull Down, Based on Device Address ID0 Pull Up/Pull Down, Based on Panel ID ID1 Pull Up/Pull Down, Based on Panel ID ID2 Pull Up/Pull Down, Based on Panel ID ID3 Pull Up/Pull Down, Based on Panel ID RES1 GND RES2 GND RES3 GND RES4 GND TST1 GND TST2 GND TST3 GND S2Cclk I2CCLK S2Cdat I2CDATA REFCLK1 3V 14.31818MHz COLOR GND PD DVCC or equivalent RSETN DVCC or equivalent VREF ½V of GMCH DDQ 43 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 4. To configure for dual pixel in to dual pixel out application The graph in Figure 24 shows the expected junction temper- using the DS90C2501 with DS90CF364 or DS90CF364A or ature for a given plane area under varying ambient tempera- DS90CF366, the “DUAL” pin must be set to V . In this mode, ture conditions. Figure 25 shows the recommended PCB CC outputs A0-to-A7, and CLK1, CLK2 are enabled. Do note that footprint for the DS90C2501. The following assumptions were scaler will be shut down in this configuration. used: • Board Thickness = 1.6mm BOARD LAYOUT AND THERMAL CONSIDERATIONS • Board Area = 7742 sq. mm FOR THE DS90C2501 • Copper Plane = 1 oz. Note: The thermal information listed in this document is based • Number of layers = 4 on preliminary simulation results and subject to change. • Signal Trace Length = 25.4mm The thermal enhancement features of the (CSP) chip scale • Maximum Junction Temperature = +150°C package require special considerations and guidelines to be • Package θ = 31.7°C/W (Natural Convection) observed to insure optimal thermal performance in applica- JA tions where the cooling method is free-air convention. • The example does not take heating effects from adjacent system components into consideration. The CSP128 package has a 5x5 matrix of thermal pads de- • Pd (max) = 1.8W* signed to efficiently conduct heat from the device to the plane of the printed circuit board. The package requires this thermal *(scaler on, SXGA to SXGA+ scaling, single in -dual output connection to increase the effective surface area of the pack- port mode, V 2.5 +10%, V 3.3 +10%, max. process vari- DD DD age to maintain safe operating die temperatures. The vias of ation) the thermal pads should be connected to the board's ground As a final design verification, DS90C2501 needs to be oper- 2 plane having a minimum effective area of 2000 mm . ated not to exceed " Operating Free Air Temperature " under For more complex system thermal design situations, it is high- Recommended Operating Conditions section. In the case of ly recommended that system level thermal analysis tools be temperature at the top-center of the package (T ) exceeds CASE utilized to insure the maximum junction temperature is not 97°C, thermal damage to the device will occur. Any external exceeded. It is well known that devices such as CPUs/Graph- thermal reduction method is highly recommended such as ics Controllers/Digital Video processors or similar devices can heat sink or forced air cooling. generate a lot of heat to the PCB boards. Extreme care should be taken to insure DS90C2501 is operated not to exceed " Operating Free Air Temperature " under Recommended Op- erating Conditions section. Junction Temperature vs. Plane Area 20004570 FIGURE 24. Junction Temperature vs. Ground Plane Area www.national.com 44 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 20004571 FIGURE 25. Recommended Land Pattern Component Side (1) and Wiring Side (2) of Board with Thermal Pads Connected to Ground Plane of PCB. 45 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 Pin Diagram 20004564 www.national.com 46 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 DS90C2501 DS90C2501 Physical Dimensions inches (millimeters) unless otherwise noted Dimensions show in millimeters Order Number DS90C2501SLB NS Package Number SLB128B Refer to Application Note AN1125 for more information 47 www.national.com 200045 Version 8 Revision 6 Print Date/Time: 2011/09/22 07:52:23 Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage References www.national.com/vref Design Made Easy www.national.com/easy PowerWise® Solutions www.national.com/powerwise Applications & Markets www.national.com/solutions Serial Digital Interface (SDI) www.national.com/sdi Mil/Aero www.national.com/milaero Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic PLL/VCO www.national.com/wireless PowerWise® Design www.national.com/training University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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