MX29F002/002N T/B 2M-BIT [256K x 8] CMOS FLASH MEMORY FEATURES • 262,144x 8 only - Data polling & Toggle bit for detection of program and • Fast access time: 55/70/90/120ns erase cycle completion. • Low power consumption • Sector protection - 30mA maximum active current(5MHz) - Hardware method to disable any combination of - 1uA typical standby current sectors from program or erase operations • Programming and erasing voltage 5V ± 10% - Sector protect/unprotect for 5V only system or 5V/12V • Command register architecture system - Byte Programming (7us typical) • 100,000 minimum erase/program cycles - Sector Erase (16K-Byte x1, 8K-Byte x 2, 32K-Byte • Latch-up protected to 100mA from -1 to VCC+1V x1, and 64K-Byte x 3) • Boot Code Sector Architecture • Auto Erase (chip & sector) and Auto Program - T = Top Boot Sector - Automatically erase any combination of sectors or the - B = Bottom Boot Sector whole chip with Erase Suspend capability. • Hardware RESET pin(only for 29F002T/B) - Automatically programs and verifies data at specified - Resets internal state machine to read mode address • Low VCC write inhibit is equal to or less than 3.2V • Erase Suspend/Erase Resume • Package type: - Suspends an erase operation to read data from, or - 32-pin PDIP program data to, a sector that is not being erased, then - 32-pin PLCC resumes the erase operation. - 32-pin TSOP (Type 1) • Status Reply • 20 years data retention GENERAL DESCRIPTION The MX29F002T/B is a 2-mega bit Flash memory organ- MXIC's Flash technology reliably stores memory contents ized as 256K bytes of 8 bits only. MXIC's Flash memories even after 100,000 erase and program cycles. The MXIC offer the most cost-effective and reliable read/write non- cell is designed to optimize the erase and programming volatile random access memory. The MX29F002T/B is mechanisms. In addition, the combination of advanced packaged in 32-pin PDIP,PLCC and 32-pin TSOP(I). It is tunnel oxide processing and low internal electric fields for designed to be reprogrammed and erased in-system or in- erase and programming operations produces reliable standard EPROM programmers. cycling. The MX29F002T/B uses a 5.0V ± 10% VCC supply to perform the High Reliability Erase and auto The standard MX29F002T/B offers access time as fast as Program/Erase algorithms. 55ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the The highest degree of latch-up protection is achieved with MX29F002T/B has separate chip enable (CE) and output MXIC's proprietary non-epi process. Latch-up protection is enable (OE) controls. proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F002T/B uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. REV. 1.5, MAR. 28, 2005 P/N: PM0547 1 MX29F002/002N T/B PIN CONFIGURATIONS 32 PDIP 32 TSOP (TYPE 1) NC on MX29F002NT/B RESET 32 VCC 1 A11 1 32 OE A16 2 31 WE A9 2 31 A10 A15 3 30 A17 A8 3 30 CE A13 4 29 Q7 A14 A12 4 29 A14 5 28 Q6 A7 28 A13 5 A17 6 27 Q5 WE 7 26 Q4 A6 6 27 A8 VCC 8 MX29F002T/B 25 Q3 A5 7 26 A9 (NC on MX29F002NT/B) RESET 9 24 GND A16 10 23 Q2 A11 A4 8 25 A15 11 22 Q1 A3 24 OE 9 A12 12 21 Q0 A7 13 20 A0 A2 10 23 A10 A6 14 19 A1 A1 11 22 CE A5 15 18 A2 Q7 A4 16 17 A3 A0 12 21 Q0 13 20 Q6 Q1 14 19 Q5 Q4 Q2 15 18 (NORMAL TYPE) GND 17 Q3 16 32 PLCC SECTOR STRUCTURE NC on MX29F002NT/B A17~A0 3FFFFH 16 K-BYTE (BOO T SECT OR) 3BFFFH 4 1 32 30 A7 5 29 A14 8 K-BYTE A6 A13 39FFFH 8 K-BYTE A5 A8 37FFFH A4 A9 32 K-BYTE 9 MX29F002T/B 25 A3 A11 2FFFFH 64 K-BYTE A2 OE 1FFFFH A1 A10 64 K-BYTE A0 CE 0FFFFH 13 Q0 21 Q7 64 K-BYTE 14 17 20 00000H MX29F002T Sector Architecture A17~A0 PIN DESCRIPTION 3FFFFH 64 K-BYTE SYMBOL PIN NAME 2FFFFH 64 K-BYTE A0~A17 Address Input 1FFFFH 64 K-BYTE Q0~Q7 Data Input/Output 0FFFFH 32 K-BYTE CE Chip Enable Input 07FFFH WE Write Enable Input 8 K-BYTE 05FFFH RESET Hardware Reset Pin/Sector Protect Unlock 8 K-BYTE 03FFFH OE Output Enable Input 16 K-BYTE (BOOT SECTOR) VCC Power Supply Pin (+5V) 00000H GND Ground Pin MX29F002B Sector Architecture REV. 1.5, MAR. 28, 2005 P/N: PM0547 2 A12 Q1 A15 Q2 A16 VSS Q3 RESET MX29F002T/B VCC Q4 WE Q5 Q6 A17 Y-DECODER X-DECODER MX29F002/002N T/B BLOCK DIAGRAM WRITE CONTROL PROGRAM/ERASE STATE WE INPUT OE HIGH VOLTAGE MACHINE LOGIC WP (WSM) RESET MX29F002 STATE REGISTER ADDRESS FLASH ARRAY LATCH ARRAY A0~A17 AND SOURCE HV BUFFER Y-PASS GATE COMMAND DATA DECODER PGM SENSE DATA AMPLIFIER HV COMMAND DATA LATCH PROGRAM DATA LATCH I/O BUFFER Q0-Q7 REV. 1.5, MAR. 28, 2005 P/N: PM0547 3 MX29F002/002N T/B AUTOMATIC PROGRAMMING cally pre-program and verify the entire array. Then the device automatically times the erase pulse width, verifies The MX29F002T/B is byte programmable using the the erase, and counts the number of sequences. A status Automatic Programming algorithm. The Automatic bit similar to DATA polling and status bit toggling between Programming algorithm does not require the system to consecutive read cycles provides feedback to the user as time out or verify the data programmed. The typical chip to the status of the programming operation. programming time of the MX29F002T/B at room temperature is less than 3.5 seconds. Commands are written to the command register using standard microprocessor write timings. Register contents serve as inputs to an internal state-machine which controls the erase and programming circuitry. During write cycles, AUTOMATIC CHIP ERASE the command register internally latches address and data needed for the programming and erase operations. During Typical erasure at room temperature is accomplished in a system write cycle, addresses are latched on the falling less than 3 seconds. The device is erased using the edge, and data are latched on the rising edge of WE . Automatic Erase algorithm. The Automatic Erase algorithm automatically programs the entire array prior to electrical MXIC's Flash technology combines years of EPROM erase. The timing and verification of electrical erase are experience to produce the highest levels of quality, relia- internally controlled by the device. bility, and cost effectiveness. The MX29F002T/B electri- cally erases all bits simultaneously using Fowler-Nord- heim tunneling. The bytes are programmed one byte at a AUTOMATIC SECTOR ERASE time using the EPROM programming mechanism of hot electron injection. The MX29F002T/B is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes allow During a program cycle, the state-machine will control the sectors of the array to be erased in one erase cycle. The program sequences and command register will not re- Automatic Sector Erase algorithm automatically programs spond to any command set. During a Sector Erase cycle, the specified sector(s) prior to electrical erase. The timing the command register will only respond to Erase Suspend and verification of electrical erase are internally controlled command. After Erase Suspend is completed, the device by the device. stays in read mode. After the state machine has com- pleted its task, it will allow the command register to respond to its full command set. AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm requires the user to only write a program set-up commands include 2 unlock write cycle and A0H and a program command (program data and address). The device automatically times the programming pulse width, verifies the program, and counts the number of sequences. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provides feedback to the user as to the status of the programming operation. AUTOMATIC ERASE ALGORITHM MXIC's Automatic Erase algorithm requires the user to write commands to the command register using standard microprocessor write timings. The device will automati- REV. 1.5, MAR. 28, 2005 P/N: PM0547 4 MX29F002/002N T/B TABLE 1. SOFTWARE COMMAND DEFINITIONS First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus Command Bus Cycle Cycle Cycle Cycle Cycle Cycle Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Reset 1 XXXH F0H Read 1 RA RD Read Silicon ID 4 555H AAH 2AAH 55H 555H 90H ADI DDI Sector Protect 4 555H AAH 2AAH 55H 555H 90H (SA) 00H Verification (X02H) 01H Program 4 555H AAH 2AAH 55H 555H A0H PA PD Chip Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H Sector Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H Sector Erase Suspend 1 XXXH B0H Sector Erase Resume 1 XXXH 30H Unlock for sector 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 20H protect/unprotect Note: 1. ADI = Address of Device identifier; A1=0,A0 =0 for manufacture code,A1=0, A0 =1 for device code (Refer to Table 3). DDI = Data of Device identifier : C2H for manufacture code, 00B0h/0034h for device code. X = X can be VIL or VIH RA=Address of memory location to be read. RD=Data to be read at location RA. 2. PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. SA = Address to the sector to be erased. 3.The system should generate the following address patterns: 555H or 2AAH to Address A0~A10. Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA). Write Sequence may be initiated with A11~A17 in either state. 4.For Sector Protect Verification Operation : If read out data is 01H, it means the sector has been protected. If read out data is 00H, it means the sector is still not being protected. COMMAND DEFINITIONS Device operations are selected by writing specific address Note that the Erase Suspend (B0H) and Erase Resume and data sequences into the command register. Writing (30H) commands are valid only while the Sector Erase incorrect address and data values or writing them in the operation is in progress. Either of the two reset command improper sequence will reset the device to the read mode. sequences will reset the device(when applicable). Table 1 defines the valid register command sequences. REV. 1.5, MAR. 28, 2005 P/N: PM0547 5 MX29F002/002N T/B TABLE 2. MX29F002T/B BUS OPERATION Pins CE OE WE A0 A1 A6 A9 Q0~Q7 Mode Read Silicon ID L L H L L X V (2) C2H ID Manufacturer Code(1) Read Silicon ID L L H H L X V (2) B0h/34h ID Device Code(1) Read L L H A0 A1 A6 A9 D OUT Standby H X X X X X X HIGH Z Output Disable L H H X X X X HIGH Z Write L H L A0 A1 A6 A9 D (3) IN Sector Protect with 12V L V (2) L X X L V (2) X ID ID system(6) Chip Unprotect with 12V L V (2) L X X H V (2) X ID ID system(6) Verify Sector Protect L L H X H X V (2) Code(5) ID with 12V system Sector Protect without 12V L H L X X L H X system (6) Chip Unprotect without 12V L H L X X H H X system (6) Verify Sector Protect/Unprotect L L H X H X H Code(5) without 12V system (7) Reset X X X X X X X HIGH Z NOTES: 1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1. 2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V. 3. Refer to Table 1 for valid Data-In during a write operation. 4. X can be VIL or VIH. 5. Code=00H means unprotected. Code=01H means protected. A17~A13=Sector address for sector protect. 6. Refer to sector protect/unprotect algorithm and waveform. Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system" command. 7. The "verify sector protect/unprotect without 12V system" is only following "Sector protect/unprotect without 12V system" com- mand. REV. 1.5, MAR. 28, 2005 P/N: PM0547 6 MX29F002/002N T/B READ/RESET COMMAND SET-UP AUTOMATIC CHIP/SECTOR ERASE COMMANDS The read or reset operation is initiated by writing the read/ reset command sequence into the command register. Chip erase is a six-bus cycle operation. There are two Microprocessor read cycles retrieve array data. The "unlock" write cycles. These are followed by writing the device remains enabled for reads until the command "set-up" command 80H. Two more "unlock" write cycles register contents are altered. are then followed by the chip erase command 10H. If program-fail or erase-fail happen, the write of F0H will The Automatic Chip Erase does not require the device to reset the device to abort the operation. A valid command be entirely pre-programmed prior to executing the Automatic must then be written to place the device in the desired Chip Erase. Upon executing the Automatic Chip Erase, state. the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self- SILICON-ID-READ COMMAND timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at Flash memories are intended for use in applications where which time the device returns to the Read mode. The the local CPU alters memory contents. As such, system is not required to provide any control or timing manufacturer and device codes must be accessible while during these operations. the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high When using the Automatic Chip Erase algorithm, note that voltage. However, multiplexing high voltage onto address the erase automatically terminates when adequate erase lines is not generally desired system design practice. margin has been achieved for the memory array(no erase verify command is required). The MX29F002T/B contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. If the Erase operation was unsuccessful, the data on Q5 The operation is initiated by writing the read silicon ID is "1" (see Table 4), indicating the erase operation exceed command sequence into the command register. Following internal timing limit. the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H. A read cycle with The automatic erase begins on the rising edge of the last A1=VIL, A0=VIH returns the device code of B0h for WE pulse in the command sequence and terminates when MX29F002T, 34h for MX29F002B. the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. TABLE 3. EXPANDED SILICON ID CODE Pins A0 A1 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex) Code Manufacture code VIL VIL 1100 0010 C2H Device code VIH VIL 1011 0000 B0h for MX29F002T Device code VIH VIL 0011 0100 34h for MX29F002B Sector Protection X VIH 0000 0001 01H (Protected) Verification X VIH 0000 0000 00H (Unprotected) REV. 1.5, MAR. 28, 2005 P/N: PM0547 7 MX29F002/002N T/B the Sector Erase time-out immediately terminates the SET-UP AUTOMATIC SECTOR ERASE time-out period and suspends the erase operation. After COMMANDS this command has been executed, the command register will initiate erase suspend mode. The state machine will The Automatic Sector Erase does not require the device return to read mode automatically after suspend is ready. to be entirely pre-programmed prior to executing the At this time, state machine only allows the command Automatic Set-up Sector Erase command and Automatic register to respond to the Read Memory Array, Erase Sector Erase command. Upon executing the Automatic Resume and Program commands. The system can Sector Erase command, the device will automatically determine the status of the program operation using the Q7 program and verify the sector(s) memory for an all-zero or Q6 status bits, just as in the standard program operation. data pattern. The system does not require to provide any After an erase-suspended program operation is complete, control or timing during these operations. the system can once again read array data within non- suspended sectors. When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verification begin. The erase and verification operations are complete when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. The system does not required to provide any control or timing during these operations. When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verify command is required). Sector erase is a six- bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command-80H. Two more "unlock" write cycles are then followed by the sector erase command-30H. The sector address is latched on the falling edge of WE, while the command(data) is latched on the rising edge of WE. Sector addresses selected are loaded into internal register on the sixth falling edge of WE. Each successive sector load cycle started by the falling edge of WE must begin within 30us from the rising edge of the preceding WE. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sector Erase (30H) or Erase Suspend (BOH) during the time-out period resets the device to read mode. ERASE SUSPEND This command is only valid while the state machine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. Writing the Erase Suspend command during REV. 1.5, MAR. 28, 2005 P/N: PM0547 8 MX29F002/002N T/B TABLE 4. WRITE OPERATION STATUS Status Q7 Q6 Q5 Q3 Q2 Note1 Note2 Byte Program in Auto Program Algorithm Q7 Toggle 0 N/A No Toggle Auto Erase Algorithm 0 Toggle 0 1 Toggle Erase Suspend Read 1 No 0 N/A Toggle In Progress (Erase Suspended Sector) Toggle Erase Suspended Mode Erase Suspend Read Data Data Data Data Data (Non-Erase Suspended Sector) Erase Suspend Program Q7 Toggle 0 N/A N/A Byte Program in Auto Program Algorithm Q7 Toggle 1 N/A No Toggle Exceeded Auto Erase Algorithm 0 Toggle 1 1 Toggle Time Limits Erase Suspend Program Q7 Toggle 1 N/A N/A Note: 1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits. See "Q5:Exceeded Timing Limits " for more information. REV. 1.5, MAR. 28, 2005 P/N: PM0547 9 MX29F002/002N T/B ERASE RESUME fourth WE pulse of the four write pulse sequences for automatic program. This command will cause the command register to clear While the Automatic Erase algorithm is in operation, Q7 will the suspend state and return back to Sector Erase mode read "0" until the erase operation is competed. Upon but only if an Erase Suspend command was previously completion of the erase operation, the data on Q7 will read issued. Erase Resume will not have any effect in all other "1". The Data Polling feature is valid after the rising edge conditions. Another Erase Suspend command can be of the sixth WE pulse of six write pulse sequences for written after the chip has resumed erasing. automatic chip/sector erase. The Data Polling feature is active during Automatic Program/ SET-UP AUTOMATIC PROGRAM COMMANDS Erase algorithm or sector erase time-out.(see section Q3 Sector Erase Timer) To initiate Automatic Program mode, a three-cycle command sequence is required. There are two "unlock" Q6:Toggle BIT I write cycles. These are followed by writing the Automatic Program command A0H. The MX29F002T/B features a "Toggle Bit" as a method to indicate to the host system that the Auto Program/Erase Once the Automatic Program command is initiated, the algorithms are either in progress or completed. next WE pulse causes a transition to an active programming operation. Addresses are latched on the falling edge, and During an Automatic Program or Erase algorithm operation, data are internally latched on the rising edge of the WE successive read cycles to any address cause Q6 to toggle. pulse. The rising edge of WE also begins the programming The system may use either OE or CE to control the read operation. The system does not require to provide further cycles. When the operation is complete, Q6 stops toggling. controls or timings. The device will automatically provide an adequate internally generated program pulse and verify After an erase command sequence is written, if all sectors margin. selected for erasing are protected, Q6 toggles and returns to reading array data. If not all selected sectors are If the program operation was unsuccessful, the data on Q5 protected, the Automatic Erase algorithm erases the is "1", indicating the program operation exceed internal unprotected sectors, and ignores the selected sectors that timing limit. The automatic programming operation is are protected. completed when the data read on Q6 stops toggling for two consecutive read cycles and the data on Q7 and Q6 are The system can use Q6 and Q2 together to determine equivalent to data written to these two bits, at which time whether a sector is actively erasing or is erase suspended. the device returns to the Read mode(no program verify When the device is actively erasing (that is, the Automatic command is required). Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which WRITE OPERATION STATUS sectors are erasing or erase-suspended. Alternatively, the system can use Q7(see the subsection on Q7:Data Polling). DATA POLLING-Q7 If a program address falls within a protected sector, Q6 The MX29F002T/B also features Data Polling as a method toggles for approximately 2 us after the program command to indicate to the host system that the Automatic Program sequence is written, then returns to reading array data. or Erase algorithms are either in progress or completed. Q6 also toggles during the erase-suspend-program mode, While the Automatic Programming algorithm is in operation, and stops toggling once the Automatic Program algorithm an attempt to read the device will produce the complement is complete. data of the data last written to Q7. Upon completion of the Automatic Program Algorithm an attempt to read the The Write Operation Status table shows the outputs for device will produce the true data last written to Q7. The Toggle Bit I on Q6. Refer to the toggle bit algorithm. Data Polling feature is valid after the rising edge of the REV. 1.5, MAR. 28, 2005 P/N: PM0547 10 MX29F002/002N T/B system must start at the beginning of the algorithm when Q2:Toggle Bit II it returns to determine the status of the operation (top of the The "Toggle Bit II" on Q2, when used with Q6, indicates toggle bit algorithm flow chart). whether a particular sector is actively erasing (that is, the Automatic Erase algorithm is in process), or whether that sector is erase-suspended. Toggle Bit I is valid after the Q5 rising edge of the final WE pulse in the command sequence. Exceeded Timing Limits Q2 toggles when the system reads at addresses within Q5 will indicate if the program or erase time has exceeded those sectors that have been selected for erasure. (The the specified limits(internal pulse count). Under these system may use either OE or CE to control the read conditions Q5 will produce a "1". This time-out condition cycles.) But Q2 cannot distinguish whether the sector is which indicates that the program or erase cycle was not actively erasing or is erase-suspended. Q6, by comparison, successfully completed. Data Polling and Toggle Bit are indicates whether the device is actively erasing, or is in the only operating functions of the device under this Erase Suspend, but cannot distinguish which sectors are condition. selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 4 to compare If this time-out condition occurs during sector erase outputs for Q2 and Q6. operation, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still functional and may be used for the program or erase Reading Toggle Bits Q6/ Q2 operation. The device must be reset to use other sectors. Refer to the toggle bit algorithm for the following discussion. Write the Reset command sequence to the device, and Whenever the system initially begins reading toggle bit then execute program or erase command sequence. This status, it must read Q7-Q0 at least twice in a row to allows the system to continue to use the other active determine whether a toggle bit is toggling. Typically, the sectors in the device. system would note and store the value of the toggle bit after the first read. After the second read, the system would If this time-out condition occurs during the chip erase compare the new value of the toggle bit with the first. If the operation, it specifies that the entire chip is bad or toggle bit is not toggling, the device has completed the combination of sectors are bad. program or erase operation. The system can read array data on Q7-Q0 on the following read cycle. If this time-out condition occurs during the byte programming operation, it specifies that the entire sector containing that However, if after the initial two read cycles, the system byte is bad and this sector maynot be reused, (other determines that the toggle bit is still toggling, the system sectors are still functional and can be reused). also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine The Q5 time-out condition may also appear if a user tries again whether the toggle bit is toggling, since the toggle bit to program a non blank location without erasing. In this may have stopped toggling just as Q5 went high. If the case the device locks out and never completes the toggle bit is no longer toggling, the device has successfully Automatic Algorithm operation. Hence, the system never completed the program or erase operation. If it is still reads a valid data on Q7 bit and Q6 never stops toggling. toggling, the device did not complete the operation Once the Device has exceeded timing limits, the Q5 bit will successfully, and the system must write the reset command indicate a "1". Please note that this is not a device failure to return to reading array data. condition since the device was incorrectly used. The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the REV. 1.5, MAR. 28, 2005 P/N: PM0547 11 MX29F002/002N T/B Q3 LOGICAL INHIBIT Sector Erase Timer Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must After the completion of the initial sector erase command be a logical zero while OE is a logical one. sequence the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. POWER SUPPLY DECOUPLING If Data Polling or the Toggle Bit indicates the device has In order to reduce power switching effect, each device been written with a valid erase command, Q3 may be used should have a 0.1uF ceramic capacitor connected between to determine if the sector erase timer window is still open. its VCC and GND. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed SECTOR PROTECTION WITH 12V SYSTEM as indicated by Data Polling or Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. The MX29F002T/B features hardware sector protection. To insure the command has been accepted, the system This feature will disable both program and erase operations software should check the status of Q3 prior to and for these sectors protected. To activate this mode, the following each subsequent sector erase command. If Q3 programming equipment must force VID on address pin A9 were high on the second status check, the command may and control pin OE, (suggest VID = 12V) A6 = VIL and CE not have been accepted. = VIL.(see Table 2) Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated on the rising edge. Please refer to sector DATA PROTECTION protect algorithm and waveform. The MX29F002T/B is designed to offer protection against To verify programming of the protection circuitry, the accidental erasure or programming caused by spurious programming equipment must force VID on address pin A9 system level signals that may exist during power transition. ( with CE and OE at VIL and WE at VIH. When A1=1, it will During power up the device automatically resets the state produce a logical "1" code at device output Q0 for a machine in the Read mode. In addition, with its control protected sector. Otherwise the device will produce 00H register architecture, alteration of the memory contents for the unprotected sector. In this mode, the addresses, only occurs after successful completion of specific except for A1, are in "don't care" state. Address locations command sequences. The device also incorporates with A1 = VIL are reserved to read manufacturer and device several features to prevent inadvertent write cycles resulting codes.(Read Silicon ID) from VCC power-up and power-down transition or system noise. It is also possible to determine if the sector is protected in the system by writing a Read Silicon ID command. Performing a read operation with A1=VIH, it will produce a logical "1" at Q0 for the protected sector. WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 5ns(typical) on CE or WE will not initiate a write cycle. REV. 1.5, MAR. 28, 2005 P/N: PM0547 12 MX29F002/002N T/B Temporary Sector Unprotect Operation (For 29F002T/B only) Start RESET = VID (Note 1) Perform Erase or Program Operation Operation Completed RESET = VIH Temporary Sector Unprotect Completed(Note 2) Note : 1. All protected sectors are temporary unprotected. VID=11.5V~12.5V 2. All previously protected sectors are protected again. REV. 1.5, MAR. 28, 2005 P/N: PM0547 13 MX29F002/002N T/B TEMPORARY SECTOR UNPROTECT Parameter Std. Description Test Setup All Speed Options Unit tVIDR VID Rise and Fall Time (See Note) Min 500 ns tRSP RESET Setup Time for Temporary Sector Unprotect Min 4 us Note: Not 100% tested Temporary Sector Unprotect Timing Diagram (For 29F002T/B only) 12V RESET 0 or 5V 0 or 5V Program or Erase Command Sequence tVIDR tVIDR CE WE tRSP REV. 1.5, MAR. 28, 2005 P/N: PM0547 14 MX29F002/002N T/B AC CHARACTERISTICS Parameter Std Description Test Setup All Speed Options Unit tREADY RESET PIN Low (Not During Automatic Algorithms) MAX 500 ns to Read or Write (See Note) tRP1 RESET Pulse Width (During Automatic Algorithms) MIN 10 us tRP2 RESET Pulse Width (NOT During Automatic Algorithms) MIN 500 ns tRH RESET High Time Before Read(See Note) MIN 0 ns Note: Not 100% tested RESET TIMING WAVEFORM (For 29F002T/B only) CE, OE tRH RESET tRP2 tReady Reset Timing NOT during Automatic Algorithms RESET tRP1 Reset Timing during Automatic Algorithms REV. 1.5, MAR. 28, 2005 P/N: PM0547 15 MX29F002/002N T/B CHIP UNPROTECT WITH 12V SYSTEM ABSOLUTE MAXIMUM RATINGS The MX29F002T/B also features the chip unprotect mode, RATING VALUE so that all sectors are unprotected after chip unprotect is o o Ambient Operating Temperature 0 C to 70 C completed to incorporate any changes in the code. It is o o Storage Temperature -65 C to 125 C recommended to protect all sectors before activating chip Applied Input Voltage -0.5V to 7.0V unprotect mode. Applied Output Voltage -0.5V to 7.0V To activate this mode, the programming equipment must VCC to Ground Potential -0.5V to 7.0V force VID on control pin OE and address pin A9. The CE A9 -0.5V to 13.5V pins must be set at VIL. Pins A6 must be set to VIH.(see Table 2) Refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. The unprotection NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM mechanism begins on the falling edge of the WE pulse and RATINGS may cause permanent damage to the device. This is a is terminated on the rising edge. stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for It is also possible to determine if the chip is unprotected in extended period may affect reliability. the system by writing the Read Silicon ID command. NOTICE: Performing a read operation with A1=VIH, it will produce Specifications contained within the following tables are subject to 00H at data outputs(Q0-Q7) for an unprotected sector. It is change. noted that all sectors are unprotected after the chip unprotect algorithm is completed. SECTOR PROTECTION WITHOUT 12V SYSTEM The MX29F002T/B also feature a hardware sector protection method in a system without 12V power supply. The programming equipment do not need to supply 12 volts to protect sectors. The details are shown in sector protect algorithm and waveform. CHIP UNPROTECT WITHOUT 12V SYSTEM The MX29F002T/B also feature a hardware chip unprotection method in a system without 12V power supply. The programming equipment do not need to supply 12 volts to unprotect all sectors. The details are shown in chip unprotect algorithm and waveform. POWER-UP SEQUENCE The MX29F002T/B powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of a two-step command sequence. Vpp and Vcc power up sequence is not required. REV. 1.5, MAR. 28, 2005 P/N: PM0547 16 MX29F002/002N T/B DC/AC Operating Conditions for Read/Programming/Erase Operation MX29F002/002N -55 -70 -90 -12 o o o o o o o o Operating Temperature Commercial 0 C to 70C0 C to 70C0 C to 70C0 C to 70 C o o o o o o Industrial -40 C to 85 C -40 C to 85 C -40 C to 85 C Vcc Power Supply 5V±5% 5V±10% 5V±10% 5V±10% o CAPACITANCE TA = 25 C, f = 1.0 MHz SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS CIN1 Input Capacitance 8 pF VIN = 0V CIN2 Control Pin Capacitance 12 pF VIN = 0V COUT Output Capacitance 12 pF VOUT = 0V READ OPERATION DC CHARACTERISTICS SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS ILI Input Leakage Current 1(Note 3) uA VIN = GND to VCC ILO Output Leakage Current 10 uA VOUT = GND to VCC ISB1 Standby VCC current 1 mA CE = VIH ISB2 1 5 uA CE = VCC + 0.3V ICC1 Operating VCC current 30(Note 4) mA IOUT = 0mA, f=5MHz ICC2 50 mA IOUT = 0mA, f=10MHz VIL Input Low Voltage -0.3(NOTE 1) 0.8 V VIH Input High Voltage 2.0 VCC + 0.3 V VOL Output Low Voltage 0.45 V IOL = 2.1mA VOH1 Output High Voltage(TTL) 2.4 V IOH = -2mA VOH2 Output High Voltage(CMOS) VCC-0.4 V IOH = -100uA, VCC=VCC MIN NOTES: 1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns. VIL min. = -2.0V for pulse width is equal to or less than 20 ns. 2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns. If VIH is over the specified maximum value, read operation cannot be guaranteed. 3. ILI=10uA for Industrial grade. 4. ICC1=45mA for Industrial grade. REV. 1.5, MAR. 28, 2005 P/N: PM0547 17 MX29F002/002N T/B AC CHARACTERISTICS 29F002T/B-55 29F002T/B-70 SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT CONDITION tACC Address to Output Delay 55 70 ns CE=OE=VIL tCE CE to Output Delay 55 70 ns OE=VIL tOE OE to Output Delay 25 30 ns CE=VIL tDF OE High to Output Float (Note1) 0 20 0 20 ns CE=VIL tOH Address to Output hold 0 0 ns CE=OE=VIL 29F002T/B-90 29F002T/B-12 SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT CONDITIONS tACC Address to Output Delay 90 120 ns CE=OE=VIL tCE CE to Output Delay 90 120 ns OE=VIL tOE OE to Output Delay 40 50 ns CE=VIL tDF OE High to Output Float (Note1) 0 30 0 30 ns CE=VIL tOH Address to Output hold 0 0 ns CE=OE=VIL TEST CONDITIONS: NOTE: 1. tDF is defined as the time at which the output achieves the • Input pulse levels: 0.45V/2.4V for 70ns max., 0V/3V for 55ns • Input rise and fall times: < 10ns for 70ns max. open circuit condition and data is no longer driven. < 5ns for 55ns • Output load: 1 TTL gate + 100pF (Including scope and jig) for 70ns max. 1 TTL gate + 50pF (Including scope and jig) for 55ns speed grade • Reference levels for measuring timing: 0.8V, 2.0V for 70ns max. : 1.5V for 55ns READ TIMING WAVEFORMS VIH A0~17 ADD Valid VIL tCE VIH CE VIL VIH WE VIL tOE tDF VIH OE tACC VIL tOH HIGH Z HIGH Z VOH DATA DATA Valid Q0~7 VOL REV. 1.5, MAR. 28, 2005 P/N: PM0547 18 MX29F002/002N T/B COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION DC CHARACTERISTICS SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS ICC1 (Read) Operating VCC Current 30(Note 5) mA IOUT=0mA, f=5MHz ICC2 50 mA IOUT=0mA, F=10MHz ICC3 (Program) 50 mA In Programming ICC4 (Erase) 50 mA In Erase ICCES VCC Erase Suspend Current 2 mA CE=VIH, Erase Suspended NOTES: 1. VIL min. = -0.6V for pulse width is equal to or less than 20ns. 2. If VIH is over the specified maximum value, programming operation cannot be guaranteed. 3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is the sum of ICCES and ICC1 or ICC2. 4. All current are in RMS unless otherwise noted. 5. ICC1(Read)=45mA for Industrial Grade. REV. 1.5, MAR. 28, 2005 P/N: PM0547 19 MX29F002/002N T/B AC CHARACTERISTICS 29F002T/B-55(NOTE 2) SYMBOL PARAMETER MIN. MAX. UNIT tOES OE setup time 0 ns tCWC Command programming cycle 70 ns tCEP WE programming pulse width 45 ns tCEPH1 WE programming pulse width High 20 ns tCEPH2 WE programming pulse width High 20 ns tAS Address setup time 0 ns tAH Address hold time 45 ns tDS Data setup time 20 ns tDH Data hold time 0 ns tCESC CE setup time before command write 0 ns tDF Output disable time (Note 1) 20 ns tAETC Total erase time in auto chip erase 3(TYP.) 24 s tAETB Total erase time in auto sector erase 1(TYP.) 8 s tAVT Total programming time in auto verify 7 210 us (Byte Program time) tBAL Sector address load time 100 us tCH CE Hold Time 0 ns tCS CE setup to WE going low 0 ns tVLHT Voltage Transition Time 4 us tOESP OE Setup Time to WE Active 4 us tWPP1 Write pulse width for sector protect 10 us tWPP2 Write pulse width for sector unprotect 12 ms NOTES: 1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2. The test conditin of MX29F002T/B-55 : VCC=5V ± 5%,CL=50pf,VIH/VIL=3.0V/0V VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=-2mA o o TA= 0 C TO 70 C REV. 1.5, MAR. 28, 2005 P/N: PM0547 20 MX29F002/002N T/B AC CHARACTERISTICS 29F002T/B-70 29F002T/B-90 29F002T/B-12 SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. UNIT tOES OE setup time 0 0 0 ns tCWC Command programming cycle 70 90 120 ns tCEP WE programming pulse width 45 45 50 ns tCEPH1 WE programming pulse width High 20 20 20 ns tCEPH2 WE programming pulse width High 20 20 20 ns tAS Address setup time 0 0 0 ns tAH Address hold time 45 45 50 ns tDS Data setup time 30 45 50 ns tDH Data hold time 0 0 0 ns tCESC CE setup time before command write 0 0 0 ns tDF Output disable time (Note 1) 30 40 40 ns tAETC Total erase time in auto chip erase 3(TYP.) 24 3(TYP.) 24 3(TYP.) 24 s tAETB Total erase time in auto sector erase 1(TYP.) 8 1(TYP.) 8 1(TYP.) 8 s tAVT Total programming time in auto verify 7 210 7 210 7 210 us (Byte Program time) tBAL Sector address load time 100 100 100 us tCH CE Hold Time 0 0 0 ns tCS CE setup to WE going low 0 0 0 ns tVLHT Voltage Transition Time 4 4 4 us tOESP OE Setup Time to WE Active 4 4 4 us tWPP1 Write pulse width for sector protect 10 10 10 us tWPP2 Write pulse width for sector unprotect 12 12 12 ms NOTES: 1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven. REV. 1.5, MAR. 28, 2005 P/N: PM0547 21 MX29F002/002N T/B SWITCHING TEST CIRCUITS DEVICE UNDER 1.6K ohm +5V TEST CL 1.2K ohm DIODES=IN3064 OR EQUIVALENT CL=100pF Including jig capacitance CL=50pF for MX29F002T/B-55 SWITCHING TEST WAVEFORMS(I) for speed grade 70ns max. 2.4V 2.0V 2.0V TEST POINTS 0.8V 0.8V 0.45V INPUT OUTPUT AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are equal to or less than 20ns. SWITCHING TEST WAVEFORMS(II) for speed grade 55ns(MX29F002T/B-55) 3.0V TEST POINTS 1.5V 1.5V 0V INPUT OUTPUT AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 5ns. REV. 1.5, MAR. 28, 2005 P/N: PM0547 22 MX29F002/002N T/B COMMAND WRITE TIMING WAVEFORM VCC 5V VIH ADD ADD Valid A0~17 VIL tAS tAH VIH WE VIL tOES tCEPH1 tCEP tCWC VIH CE VIL tCS tCH VIH OE VIL tDS tDH VIH DATA DIN VIL Q0-7 REV. 1.5, MAR. 28, 2005 P/N: PM0547 23 MX29F002/002N T/B AUTOMATIC PROGRAMMING TIMING WAVEFORM One byte data is programmed. Verify in fast algorithm and verified by DATA polling and toggle bit checking after additional programming by external control are not required automatic verification starts. Device outputs DATA during because these operations are executed automatically by programming and DATA after programming on Q7.(Q6 is internal control circuit. Programming completion can be for toggle bit; see toggle bit, DATA polling, timing waveform) AUTOMATIC PROGRAMMING TIMING WAVEFORM Vcc 5V A11~A17 ADD Valid 2AAH 555H A0~A10 555H ADD Valid tAS tCWC tAH WE tCEPH1 tCESC tAVT CE tCEP OE tDS tDH tDF Q0~Q1,Q2 Command In Command In Command In Data In DATA DATA polling ,Q4(Note 1) Command In Command In Command In Data In DATA DATA Q7 Command #A0H Command #AAH Command #55H tOE (Q0~Q7) Notes: (1). Q6:Toggle bit, Q5:Tin=Timing-limit bit, Q3: Time-out bit REV. 1.5, MAR. 28, 2005 P/N: PM0547 24 MX29F002/002N T/B AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address NO Toggle Bit Checking Q6 not Toggled YES NO Invalid Verify Byte Ok Command YES NO . Q5 = 1 Auto Program Completed YES Reset Auto Program Exceed Timing Limit REV. 1.5, MAR. 28, 2005 P/N: PM0547 25 MX29F002/002N T/B TOGGLE BIT ALGORITHM START Read Q7~Q0 Read Q7~Q0 (Note 1) NO Toggle Bit Q6 =Toggle? YES NO Q5=1? YES (Note 1,2) Read Q7~Q0 Twice Toggle Bit Q6 =Toggle? YES Program/Erase Operation Not Program/Erase Operation Complete Complete, Write Reset Command Note: 1. Read toggle bit Q6 twice to determine whether or not it is toggle. See test. 2. Recheck toggle bit Q6 because it may stop toggling as Q5 changes to "1". See test. REV. 1.5, MAR. 28, 2005 P/N: PM0547 26 MX29F002/002N T/B AUTOMATIC CHIPE RASETIMING WAVEFORM starts. Device outputs 0 during erasure and 1 after erasure All data in chip are erased. External erase verify is not on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, required because data is erased automatically by internal timing waveform) control circuit. Erasure completion can be verified by DATA polling and toggle bit checking after automatic erase AUTOMATIC CHIP ERASE TIMING WAVEFORM Vcc 5V A11~A17 555H 2AAH 555H 2AAH 555H A0~A10 555H tAS tCWC tAH WE tCEPH1 tAETC CE tCEP OE tDS tDH Q0,Q1, Command In Command In Command In Command In Command In Command In Q4(Note 1) DATA polling Command In Command In Command In Command In Command In Command In Q7 Command #80H Command #AAH Command #55H Command #10H Command #AAH Command #55H (Q0~Q7) Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit REV. 1.5, MAR. 28, 2005 P/N: PM0547 27 MX29F002/002N T/B AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H NO Toggle Bit Checking Q6 not Toggled YES NO Invalid DATA Polling Command Q7 = 1 YES NO . Q5 = 1 Auto Chip Erase Completed YES Reset Auto Chip Erase Exceed Timing Limit REV. 1.5, MAR. 28, 2005 P/N: PM0547 28 MX29F002/002N T/B AUTOMATIC SECTOR ERASE TIMING WAVEFORM after automatic erase starts. Device outputs 0 during Sector data indicated by A13 to A17 are erased. External erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see erase verification is not required because data are erased toggle bit, DATA polling, timing waveform) automatically by internal control circuit. Erasure comple- tion can be verified by DATA polling and toggle bit checking AUTOMATIC SECTOR ERASE TIMING WAVEFORM Vcc 5V Sector Sector Sector A13~A17 Addressn Address0 Address1 555H 2AAH 555H 555H 2AAH A0~A10 tAS tCWC tAH WE tCEPH1 tBAL tAETB CE tCEP OE tDS tDH Q0,Q1, Command Command Command Command Command Command Command Command In In In In In In In In Q4(Note 1) DATA polling Command Command Command Command Command Command Command Command Q7 In In In In In In In In Command #AAH Command #55H Command #80H Command #AAH Command #55H Command #30H Command #30H Command #30H (Q0~Q7) Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit REV. 1.5, MAR. 28, 2005 P/N: PM0547 29 MX29F002/002N T/B AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address NO Toggle Bit Checking Invalid Command Q6 Toggled ? YES Load Other Sector Addrss If Necessary (Load Other Sector Address) NO Last Sector to Erase YES NO Time-out Bit Checking Q3=1 ? YES NO Toggle Bit Checking Q6 not Toggled YES NO Q5 = 1 DATA Polling Q7 = 1 YES Reset Auto Sector Erase Completed Auto Sector Erase Exceed Timing Limit REV. 1.5, MAR. 28, 2005 P/N: PM0547 30 MX29F002/002N T/B ERASE SUSPEND/ERASE RESUME FLOWCHART START Write Data B0H NO Toggle Bit checking Q6 not toggled YES Read Array or Program Reading or NO Programming End YES Write Data 30H Continue Erase . . Another NO Erase Suspend ? YES REV. 1.5, MAR. 28, 2005 P/N: PM0547 31 MX29F002/002N T/B TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITH 12V A1 A6 12V 5V A9 tVLHT Verify 12V 5V OE tVLHT tVLHT tWPP 1 WE tOESP CE Data 01H F0H tOE A17-A13 Sector Address REV. 1.5, MAR. 28, 2005 P/N: PM0547 32 MX29F002/002N T/B TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V A1 12V 5V A9 tVLHT A6 Verify 12V 5V OE tVLHT tVLHT tWPP 2 WE tOESP CE Data 00H F0H tOE REV. 1.5, MAR. 28, 2005 P/N: PM0547 33 MX29F002/002N T/B SECTOR PROTECTION ALGORITHM FOR SYSTEM WITH 12V START Set Up Sector Addr (A17,A16,A15,A14,A13) PLSCNT=1 OE=VID,A9=VID,CE=VIL A6=VIL Activate WE Pulse Time Out 10us Set WE=VIH, CE=OE=VIL A9 should remain VID Read from Sector No Addr=SA, A1=1 No Data=01H? PLSCNT=32? . Yes Device Failed Yes Protect Another Sector? Remove VID from A9 Write Reset Command Sector Protection Complete REV. 1.5, MAR. 28, 2005 P/N: PM0547 34 MX29F002/002N T/B CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V START Protect All Sectors PLSCNT=1 Set OE=A9=VID CE=VIL,A6=1 Activate WE Pulse Time Out 12ms Increment PLSCNT Set OE=CE=VIL A9=VID,A1=1 Set Up First Sector Addr Read Data from Device No No Data=00H? PLSCNT=1000? Increment Sector Addr Yes Yes Device Failed No All sectors have been verified? Yes Remove VID from A9 Write Reset Command Chip Unprotect Complete * It is recommended before unprotect the whole chip, all sectors should be protected in advance. REV. 1.5, MAR. 28, 2005 P/N: PM0547 35 MX29F002/002N T/B TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITHOUT 12V A1 A6 Toggle bit polling Verify 5V OE tCEP WE * See the following Note! CE Don't care Data 01H F0H (Note 2) tOE A17-A13 Sector Address Note1: Must issue "unlock for sector protect/unprotect" command before sector protection for a system without 12V provided. Note2: Except F0H REV. 1.5, MAR. 28, 2005 P/N: PM0547 36 MX29F002/002N T/B TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V A1 A6 Toggle bit polling Verify 5V OE tCEP WE * See the following Note! CE Data Don't care 00H F0H (Note 2) tOE Note1: Must issue "unlock for sector protect/unprotect" command before sector unprotection for a system without 12V provided. Note2: Except F0H REV. 1.5, MAR. 28, 2005 P/N: PM0547 37 MX29F002/002N T/B SECTOR PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V START PLSCNT=1 Write "unlock for sector protect/unprotect" Command(Table1) Set Up Sector Addr (A17,A16,A15,A14,A13) OE=VIH,A9=VIH CE=VIL,A6=VIL Activate WE Pulse to start Data don't care Toggle bit checking No Q6 not Toggled Yes Increment PLSCNT Set CE=OE=VIL A9=VIH Read from Sector No Addr=SA, A1=1 No Data=01H? PLSCNT=32? Yes Yes . Device Failed Yes Protect Another Sector? No Write Reset Command Sector Protection Complete REV. 1.5, MAR. 28, 2005 P/N: PM0547 38 MX29F002/002N T/B CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V START Protect All Sectors PLSCNT=1 Write "unlock for sector protect/unprotect" Command (Table 1) Set OE=A9=VIH CE=VIL,A6=1 Activate WE Pulse to start Data don't care No Toggle bit checking Q6 not Toggled Increment PLSCNT Yes Set OE=CE=VIL A9=VIH,A1=1 Set Up First Sector Addr Read Data from Device No No Data=00H? Increment PLSCNT=1000? Sector Addr Yes Yes Device Failed No All sectors have been verified? Yes Write Reset Command Chip Unprotect Complete * It is recommended before unprotect the whole chip, all sectors should be protected in advance. REV. 1.5, MAR. 28, 2005 P/N: PM0547 39 MX29F002/002N T/B ID CODE READ TIMING WAVEFORM MODE VCC 5V VID ADD VIH A9 VIL ADD AD tACC tACC A1 VIH VIL ADD VIH A2-A8 A10-A17 VIL CE VIH VIL tCE VIH WE VIL VIH tOE OE VIL tDF tOH tOH VIH DATA DATA OUT DATA OUT VIL Q0-Q7 B0h/34h C2H REV. 1.5, MAR. 28, 2005 P/N: PM0547 40 MX29F002/002N T/B ORDERING INFORMATION PLASTIC PACKAGE PART NO. Access Time Operating Current Standby Current Temperature PACKAGE (ns) (mA) MAX.(uA) Range o o MX29F002TPC-55 55 30 5 0 C~70 C 32 Pin PDIP o o MX29F002TPC-70 70 30 5 0 C~70 C 32 Pin PDIP o o MX29F002TPC-90 90 30 5 0 C~70 C 32 Pin PDIP o o MX29F002TPC-12 120 30 5 0 C~70 C 32 Pin PDIP o o MX29F002TTC-55 55 30 5 0 C~70 C 32 Pin TSOP (Normal Type) o o MX29F002TTC-70 70 30 5 0 C~70 C 32 Pin TSOP (Normal Type) o o MX29F002TTC-90 90 30 5 0 C~70 C 32 Pin TSOP (Normal Type) o o MX29F002TTC-12 120 30 5 0 C~70 C 32 Pin TSOP (Normal Type) o o MX29F002TQC-55 55 30 5 0 C~70 C 32 Pin PLCC o o MX29F002TQC-70 70 30 5 0 C~70 C 32 Pin PLCC o o MX29F002TQC-90 90 30 5 0 C~70 C 32 Pin PLCC o o MX29F002TQC-12 120 30 5 0 C~70 C 32 Pin PLCC o o MX29F002BPC-55 55 30 5 0 C~70 C 32 Pin PDIP o o MX29F002BPC-70 70 30 5 0 C~70 C 32 Pin PDIP o o MX29F002BPC-90 90 30 5 0 C~70 C 32 Pin PDIP o o MX29F002BPC-12 120 30 5 0 C~70 C 32 Pin PDIP o o MX29F002BTC-55 55 30 5 0 C~70 C 32 Pin TSOP (Normal Type) o o MX29F002BTC-70 70 30 5 0 C~70 C 32 Pin TSOP (Normal Type) o o MX29F002BTC-90 90 30 5 0 C~70 C 32 Pin TSOP (Normal Type) o o MX29F002BTC-12 120 30 5 0 C~70 C 32 Pin TSOP (Normal Type) o o MX29F002BQC-55 55 30 5 0 C~70 C 32 Pin PLCC o o MX29F002BQC-70 70 30 5 0 C~70 C 32 Pin PLCC o o MX29F002BQC-90 90 30 5 0 C~70 C 32 Pin PLCC o o MX29F002BQC-12 120 30 5 0 C~70 C 32 Pin PLCC o o MX29F002NTPC-55 55 30 5 0 C~70 C 32 Pin PDIP o o MX29F002NTPC-70 70 30 5 0 C~70 C 32 Pin PDIP o o MX29F002NTPC-90 90 30 5 0 C~70 C 32 Pin PDIP o o MX29F002NTPC-12 120 30 5 0 C~70 C 32 Pin PDIP o o MX29F002NTTC-55 55 30 5 0 C~70 C 32 Pin TSOP (Normal Type) REV. 1.5, MAR. 28, 2005 P/N: PM0547 41 MX29F002/002N T/B PART NO. Access Time Operating Current Standby Current Temperature PACKAGE (ns) (mA) MAX.(uA) Range o o MX29F002NTTC-70 70 30 5 0 C~70 C 32 Pin TSOP (Normal Type) o o MX29F002NTTC-90 90 30 5 0 C~70 C 32 Pin TSOP (Normal Type) o o MX29F002NTTC-12 120 30 5 0 C~70 C 32 Pin TSOP (Normal Type) o o MX29F002NTQC-55 55 30 5 0 C~70 C 32 Pin PLCC o o MX29F002NTQC-70 70 30 5 0 C~70 C 32 Pin PLCC o o MX29F002NTQC-90 90 30 5 0 C~70 C 32 Pin PLCC o o MX29F002NTQC-12 120 30 5 0 C~70 C 32 Pin PLCC o o MX29F002NBPC-55 55 30 5 0 C~70 C 32 Pin PDIP o o MX29F002NBPC-70 70 30 5 0 C~70 C 32 Pin PDIP o o MX29F002NBPC-90 90 30 5 0 C~70 C 32 Pin PDIP o o MX29F002NBPC-12 120 30 5 0 C~70 C 32 Pin PDIP o o MX29F002NBTC-55 55 30 5 0 C~70 C 32 Pin TSOP (Normal Type) o o MX29F002NBTC-70 70 30 5 0 C~70 C 32 Pin TSOP (Normal Type) o o MX29F002NBTC-90 90 30 5 0 C~70 C 32 Pin TSOP (Normal Type) o o MX29F002NBTC-12 120 30 5 0 C~70 C 32 Pin TSOP (Normal Type) o o MX29F002NBQC-55 55 30 5 0 C~70 C 32 Pin PLCC o o MX29F002NBQC-70 70 30 5 0 C~70 C 32 Pin PLCC o o MX29F002NBQC-90 90 30 5 0 C~70 C 32 Pin PLCC o o MX29F002NBQC-12 120 30 5 0 C~70 C 32 Pin PLCC o o MX29F002TPI-70 70 45 5 -40 C~85 C 32 Pin PDIP o o MX29F002TPI-90 90 45 5 -40 C~85 C 32 Pin PDIP o o MX29F002TPI-12 120 45 5 -40 C~85 C 32 Pin PDIP o o MX29F002TTI-70 70 45 5 -40 C~85 C 32 Pin TSOP (Normal Type) o o MX29F002TTI-90 90 45 5 -40 C~85 C 32 Pin TSOP (Normal Type) o o MX29F002TTI-12 120 45 5 -40 C~85 C 32 Pin TSOP (Normal Type) o o IMX29F002TQI-70 70 45 5 -40 C~85 C 32 Pin PLCC o o MX29F002TQI-90 90 45 5 -40 C~85 C 32 Pin PLCC o o MX29F002TQI-12 120 45 5 -40 C~85 C 32 Pin PLCC o o IMX29F002BPI-70 70 45 5 -40 C~85 C 32 Pin PDIP o o MX29F002BPI-90 90 45 5 -40 C~85 C 32 Pin PDIP o o MX29F002BPI-12 120 45 5 -40 C~85 C 32 Pin PDIP REV. 1.5, MAR. 28, 2005 P/N: PM0547 42 MX29F002/002N T/B PART NO. Access Time Operating Current Standby Current Temperature PACKAGE (ns) (mA) MAX.(uA) Range o o IMX29F002BTI-70 70 45 5 -40 C~85 C 32 Pin TSOP (Normal Type) o o MX29F002BTI-90 90 45 5 -40 C~85 C 32 Pin TSOP (Normal Type) o o MX29F002BTI-12 120 45 5 -40 C~85 C 32 Pin TSOP (Normal Type) o o MX29F002BQI-70 70 45 5 -40 C~85 C 32 Pin PLCC o o MX29F002BQI-90 90 45 5 -40 C~85 C 32 Pin PLCC o o MX29F002BQI-12 120 45 5 -40 C~85 C 32 Pin PLCC o o MX29F002NTPI-70 70 45 5 -40 C~85 C 32 Pin PDIP o o MX29F002NTPI-90 90 45 5 -40 C~85 C 32 Pin PDIP o o MX29F002NTPI-12 120 45 5 -40 C~85 C 32 Pin PDIP o o MX29F002NTTI-70 70 45 5 -40 C~85 C 32 Pin TSOP (Normal Type) o o MX29F002NTTI-90 90 45 5 -40 C~85 C 32 Pin TSOP (Normal Type) o o MX29F002NTTI-12 120 45 5 -40 C~85 C 32 Pin TSOP (Normal Type) o o MX29F002NTQI-70 70 45 5 -40 C~85 C 32 Pin PLCC o o MX29F002NTQI-90 90 45 5 -40 C~85 C 32 Pin PLCC o o MX29F002NTQI-12 120 45 5 -40 C~85 C 32 Pin PLCC o o MX29F002NBPI-70 70 45 5 -40 C~85 C 32 Pin PDIP o o MX29F002NBPI-90 90 45 5 -40 C~85 C 32 Pin PDIP o o MX29F002NBPI-12 120 45 5 -40 C~85 C 32 Pin PDIP o o MX29F002NBTI-70 70 45 5 -40 C~85 C 32 Pin TSOP (Normal Type) o o MX29F002NBTI-90 90 45 5 -40 C~85 C 32 Pin TSOP (Normal Type) o o MX29F002NBTI-12 120 45 5 -40 C~85 C 32 Pin TSOP (Normal Type) o o MX29F002NBQI-70 70 45 5 -40 C~85 C 32 Pin PLCC o o MX29F002NBQI-90 90 45 5 -40 C~85 C 32 Pin PLCC o o MX29F002NBQI-12 120 45 5 -40 C~85 C 32 Pin PLCC REV. 1.5, MAR. 28, 2005 P/N: PM0547 43 MX29F002/002N T/B PART NO. Access Time Operating Current Standby Current Temperature PACKAGE (ns) (mA) MAX.(uA) Range o o MX29F002TTC-70G 70 30 5 0 C~70 C 32 Pin TSOP (Pb-free) o o MX29F002TTC-90G 90 30 5 0 C~70 C 32 Pin TSOP (Pb-free) o o MX29F002BTC-70G 70 30 5 0 C~70 C 32 Pin TSOP (Pb-free) o o MX29F002BTC-90G 90 30 5 0 C~70 C 32 Pin TSOP (Pb-free) o o MX29F002TQC-70G 70 30 5 0 C~70 C 32 Pin PLCC (Pb-free) o o MX29F002TQC-90G 90 30 5 0 C~70 C 32 Pin PLCC (Pb-free) o o MX29F002BQC-70G 70 30 5 0 C~70 C 32 Pin PLCC (Pb-free) o o MX29F002BQC-90G 90 30 5 0 C~70 C 32 Pin PLCC (Pb-free) o o MX29F002TPC-70G 70 30 5 0 C~70 C 32 Pin PDIP (Pb-free) o o MX29F002TPC-90G 90 30 5 0 C~70 C 32 Pin PDIP (Pb-free) o o MX29F002BPC-70G 70 30 5 0 C~70 C 32 Pin PDIP (Pb-free) o o MX29F002BPC-90G 90 30 5 0 C~70 C 32 Pin PDIP (Pb-free) o o MX29F002TPI-70G 70 45 5 -40 C~85 C 32 Pin PDIP (Pb-free) o o MX29F002TPI-90G 90 45 5 -40 C~85 C 32 Pin PDIP (Pb-free) o o MX29F002BPI-70G 70 45 5 -40 C~85 C 32 Pin PDIP (Pb-free) o o MX29F002BPI-90G 90 45 5 -40 C~85 C 32 Pin PDIP (Pb-free) REV. 1.5, MAR. 28, 2005 P/N: PM0547 44 MX29F002/002N T/B PART NO. Access Time Operating Current Standby Current Temperature PACKAGE (ns) (mA) MAX.(uA) Range o o MX29F002NTTC-70G 70 30 5 0 C~70 C 32 Pin TSOP (Pb-free) o o MX29F002NTTC-90G 90 30 5 0 C~70 C 32 Pin TSOP (Pb-free) o o MX29F002NBTC-70G 70 30 5 0 C~70 C 32 Pin TSOP (Pb-free) o o MX29F002NBTC-90G 90 30 5 0 C~70 C 32 Pin TSOP (Pb-free) o o MX29F002NTQC-70G 70 30 5 0 C~70 C 32 Pin PLCC (Pb-free) o o MX29F002NTQC-90G 90 30 5 0 C~70 C 32 Pin PLCC (Pb-free) o o MX29F002NBQC-70G 70 30 5 0 C~70 C 32 Pin PLCC (Pb-free) o o MX29F002NBQC-90G 90 30 5 0 C~70 C 32 Pin PLCC (Pb-free) o o MX29F002NTPC-70G 70 30 5 0 C~70 C 32 Pin PDIP (Pb-free) o o MX29F002NTPC-90G 90 30 5 0 C~70 C 32 Pin PDIP (Pb-free) o o MX29F002NBPC-70G 70 30 5 0 C~70 C 32 Pin PDIP (Pb-free) o o MX29F002NBPC-90G 90 30 5 0 C~70 C 32 Pin PDIP (Pb-free) REV. 1.5, MAR. 28, 2005 P/N: PM0547 45 MX29F002/002N T/B ERASE AND PROGRAMMING PERFORMANCE(1) LIMITS PARAMETER MIN. TYP.(2) MAX.(3) UNITS Sector Erase Time 1 8 s Chip Erase Time 3 24 s Byte Programming Time 7 210 us Chip Programming Time 3.5 10.5 sec Erase/Program Cycles 100,000 Cycles Note: 1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured at 25° C, 5V. 3.Maximum values measured at 25° C, 4.5V. LATCH-UP CHARACTERISTICS MIN. MAX. Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V Current -100mA +100mA Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. DATA RETENTION PARAMETER MIN. UNIT Data Retention Time 20 Years REV. 1.5, MAR. 28, 2005 P/N: PM0547 46 MX29F002/002N T/B PACKAGE INFORMATION REV. 1.5, MAR. 28, 2005 P/N: PM0547 47 MX29F002/002N T/B REV. 1.5, MAR. 28, 2005 P/N: PM0547 48 MX29F002/002N T/B REV. 1.5, MAR. 28, 2005 P/N: PM0547 49 MX29F002/002N T/B REVISION HISTORY Revision Description Page Date 1.0 1.Removed "Advanced Information" datasheet marking and P1 DEC/27/1999 contain information on products in full production 2.The modification summary of Revision 0.9.8 to Revision 1.0: 2-1.Program/erase cycle times:10K cycles-->100K cycles P1,46 2-2.To add data retention 20 years P1,46 2-3.To add industrial grade range from "Read Mode" to "Full Range" P17,19,21,41-43 2-4.To remove A9 from "timing waveform for sector protection for P36 system without 12V" To remove A9 from "timing waveform for chip unprotection for P37 system without 12V" 2-5.Multi-sector erase time-out:30ms-->30us, tBAL:80us-->100us P8,20,21 1.1 Modified "Package Information" P45~47 JUN/14/2001 1.2 1. Corrected typing error All JUN/11/2002 1.3 1. Changed part no. from MX29F002/002N to MX29F002/002NT/B All NOV/11/2002 1.4 1. Added Pb-free option for PDIP package P43 NOV/08/2004 1.5 1. Added Pb-free option for all commercial-grade package with 70ns & 90ns P44,45 MAR/28/2005 REV. 1.5, MAR. 28, 2005 P/N: PM0547 50 MX29F002/002N T/B MACRONIX INTERNATIONAL CO., LTD. Headquarters: TEL:+886-3-578-6688 FAX:+886-3-563-2888 Europe Office : TEL:+32-2-456-8020 FAX:+32-2-456-8021 Hong Kong Office : TEL:+86-755-834-335-79 FAX:+86-755-834-380-78 Japan Office : Kawasaki Office : TEL:+81-44-246-9100 FAX:+81-44-246-9105 Osaka Office : TEL:+81-6-4807-5460 FAX:+81-6-4807-5461 Singapore Office : TEL:+65-6346-5505 FAX:+65-6348-8096 Taipei Office : TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. TEL:+1-408-262-8887 FAX:+1-408-262-8810 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.