Manufacturers
MICROSEMI A3P600-PQG208
Description
Microsemi A3P600-PQG208 IC FPGA 154 I/O 208PQFP
Part Number
A3P600-PQG208
Price
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Manufacturer
MICROSEMI
Lead Time
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Category
PRODUCTS - A
Datasheet
Extracted Text
Revision 13
ProASIC3 Flash Family FPGAs
with Optional Soft ARM Support
Advanced I/O
Features and Benefits
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
High Capacity
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• 15 k to 1 M System Gates • Wide Range Power Supply Voltage Support per JESD8-B,
• Up to 144 kbits of True Dual-Port SRAM Allowing I/Os to Operate from 2.7 V to 3.6 V
• Up to 300 User I/Os • Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3V/
Reprogrammable Flash Technology
†
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
2.5 V / 5.0 V Input
Process
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
• Instant On Level 0 Support
M-LVDS (A3P250 and above)
• Single-Chip Solution
• I/O Registers on Input, Output, and Enable Paths
• Retains Programmed Design when Powered Off
‡
• Hot-Swappable and Cold Sparing I/Os
High Performance
†
• Programmable Output Slew Rate and Drive Strength
• 350 MHz System Performance
• Weak Pull-Up/-Down
†
• 3.3 V, 66 MHz 64-Bit PCI
• IEEE 1149.1 (JTAG) Boundary Scan Test
In-System Programming (ISP) and Security
• Pin-Compatible Packages across the ProASIC3 Family
†
• ISP Using On-Chip 128-Bit Advanced Encryption Standard
Clock Conditioning Circuit (CCC) and PLL
® ®
(AES) Decryption (except ARM -enabled ProASIC 3 devices)
• Six CCC Blocks, One with an Integrated PLL
†
via JTAG (IEEE 1532–compliant)
• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities
®
• FlashLock to Secure FPGA Contents
and External Feedback
Low Power
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
†
• Core Voltage for Low Power
Embedded Memory
• Support for 1.5 V-Only Systems
• 1 kbit of FlashROM User Nonvolatile Memory
• Low-Impedance Flash Switches
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
†
High-Performance Routing Hierarchy
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• Segmented, Hierarchical Routing and Clock Structure • True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
®
• M1 ProASIC3 Devices—ARM Cortex™-M1 Soft Processor
Available with or without Debug
1
ProASIC3 Devices A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000
2
Cortex-M1 Devices M1A3P250 M1A3P400 M1A3P600 M1A3P1000
System Gates 15,000 30,000 60,000 125,000 250,000 400,000 600,000 1,000,000
Typical Equivalent Macrocells 128 256 512 1,024 2,048 – – –
VersaTiles (D-flip-flops) 384 768 1,536 3,072 6,144 9,216 13,824 24,576
RAM Kbits (1,024 bits) – – 18 36 36 54 108 144
4,608-Bit Blocks –– 4 8 8 12 24 32
FlashROM Kbits 11 1 1 1 1 1 1
3
Secure (AES) ISP – – Yes Yes Yes Yes Yes Yes
Integrated PLL in CCCs –– 1 1 1 1 1 1
4
VersaNet Globals 6 6 18 18 18 18 18 18
I/O Banks 22 2 2 4 4 4 4
Maximum User I/Os 49 81 96 133 157 194 235 300
Package Pins
5
QFN QN68 QN48, QN68, QN132 QN132 QN132
QN132
CS CS121
VQFP VQ100 VQ100 VQ100 VQ100
TQFP TQ144 TQ144
PQFP PQ208 PQ208 PQ208 PQ208 PQ208
5
FBGA FG144 FG144 FG144/256 FG144/256/ FG144/256/ FG144/256/
484 484 484
Notes:
1. A3P015 is not recommended for new designs.
2. Refer to the Cortex-M1 product brief for more information.
3. AES is not available for Cortex-M1 ProASIC3 devices.
4. Six chip (main) and three quadrant global networks are available for A3P060 and above.
5. The M1A3P250 device does not support this package.
6. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs datasheet.
† A3P015 and A3P030 devices do not support this feature. ‡ Supported only by A3P015 and A3P030 devices.
January 2013 I
© 2013 Microsemi Corporation
ProASIC3 Flash Family FPGAs
1
I/Os Per Package
ProASIC3
2 3 3
Devices A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000
Cortex-M1
3,5 3
Devices M1A3P250 M1A3P400 M1A3P600 M1A3P1000
I/O Type
Package
QN48 – 34 – – – – ––– ––
QN68 49 49 – – – – – – – – –
5
QN132 – 818084 87 19 – – – – –
CS121 – – 96 – – – –––– ––
VQ100 – 77 71 71 68 13 – – – – –
TQ144 – – 91 100 – – –––– ––
PQ208 – – – 133 151 34 151 34 154 35 154 35
FG144 – – 96 97 97 24 972597259725
5,6
FG256 – – – – 157 38 178 38 177 43 177 44
6
FG484 – – – – – – 194 38 235 60 300 74
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 FPGA Fabric User’s Guide
to ensure complying with design and board migration requirements.
2. A3P015 is not recommended for new designs.
3. For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. Refer to
the ProASIC3 FPGA Fabric User’s Guide for position assignments of the 15 LVPECL pairs.
4. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
5. The M1A3P250 device does not support FG256 or QN132 packages.
6. FG256 and FG484 are footprint-compatible packages.
Table 1 • ProASIC3 FPGAs Package Sizes Dimensions
Package CS121 QN48 QN68 QN132 VQ100 TQ144 PQ208 FG144 FG256 FG484
Length × Width 6 × 6 6 × 6 8 × 8 8 × 8 14 × 14 20 × 20 28 × 28 13 × 13 17 × 17 23 × 23
(mm\mm)
Nominal Area 36 36 64 64 196 400 784 169 289 529
2
(mm )
Pitch (mm) 0.5 0.4 0.4 0.5 0.5 0.5 0.5 1.0 1.0 1.0
Height (mm) 0.99 0.90 0.90 0.75 1.00 1.40 3.40 1.45 1.60 2.23
II Revision 13
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O
4
Single-Ended I/O
Differential I/O Pairs
4
Single-Ended I/O
Differential I/O Pairs
4
Single-Ended I/O
Differential I/O Pairs
4
Single-Ended I/O
Differential I/O Pairs
ProASIC3 Flash Family FPGAs
ProASIC3 Ordering Information
.
_
A3P1000 1 FG G 144 Y I
Application (Temperature Range)
Blank = Commercial (0°C to +70°C Ambient Temperature)
I = Industrial (–40°C to +85°C Ambient Temperature)
PP= Pre-Production
ES= Engineering Sample (Room Temperature Only)
Security Feature
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Blank = Device Does Not Include License to Implement IP Based
on the Cryptography Research, Inc. (CRI) Patent Portfolio
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G= RoHS-Compliant (Green) Packaging (some packages also halogen-free)
Package Type
=
QN Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches)
=
VQ Very Thin Quad Flat Pack (0.5 mm pitch)
=
TQ Thin Quad Flat Pack (0.5 mm pitch)
=
PQ Plastic Quad Flat Pack (0.5 mm pitch)
=
FG Fine Pitch Ball Grid Array (1.0 mm pitch)
=
CS Chip Scale Package (0.5 mm pitch)
Speed Grade
Blank = Standard
1 = 15% Faster than Standard
2 = 25% Faster than Standard
Part Number
ProASIC3 Devices
A3P015 = 15,000 System Gates (A3P015 is not recommended for new designs.)
A3P030 = 30,000 System Gates
A3P060 = 60,000 System Gates
A3P125 = 125,000 System Gates
A3P250 = 250,000 System Gates
A3P400 = 400,000 System Gates
A3P600 = 600,000 System Gates
A3P1000 = 1,000,000 System Gates
ProASIC3 Devices with Cortex-M1
M1A3P250 = 250,000 System Gates
M1A3P400 = 400,000 System Gates
M1A3P600 = 600,000 System Gates
M1A3P1000 = 1,000,000 System Gates
ProASIC3 Device Status
ProASIC3 Devices Status Cortex-M1 Devices Status
A3P015
Not recommended for new designs.
A3P030
Production
A3P060
Production
A3P125
Production
A3P250
Production M1A3P250 Production
A3P400
Production M1A3P400 Production
A3P600
Production M1A3P600 Production
A3P1000
Production M1A3P1000 Production
Revision 13 III
ProASIC3 Flash Family FPGAs
Temperature Grade Offerings
*
Package A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000
Cortex-M1 Devices M1A3P250 M1A3P400 M1A3P600 M1A3P1000
QN48 – C, I – – – – – –
QN68 C, I C, I – – – – – –
QN132 – C, I C, I C, I C, I – – –
CS121 – – C, I – ––– –
VQ100 – C, IC, IC, I C, I – – –
TQ144 – – C, I C, I ––– –
PQ208 – – – C, I C, I C, I C, I C, I
FG144 – – C, I C, I C, I C, I C, I C, I
FG256 – – – – C, I C, I C, I C, I
FG484 – – – – – C, I C, I C, I
Note: *A3P015 is not recommended for new designs.
C = Commercial temperature range: 0°C to 70°C ambient temperature
I = Industrial temperature range: –40°C to 85°C ambient temperature
Speed Grade and Temperature Grade Matrix
Temperature Grade Std. –1 –2
1
C
2
I
Notes:
1. C = Commercial temperature range: 0°C to 70°C ambient temperature
2. I = Industrial temperature range: –40°C to 85°C ambient temperature
References made to ProASIC3 devices also apply to ARM-enabled ProASIC3 devices. The ARM-enabled part numbers start with
M1 (Cortex-M1).
Contact your local Microsemi representative for device availability: http://www.microsemi.com/soc/contact/default.aspx.
A3P015 and A3P030
The A3P015 and A3P030 are architecturally compatible; there are no RAM or PLL features.
Devices Not Recommended For New Designs
A3P015 is not recommended for new designs.
IV Revision 13
ProASIC3 Flash Family FPGAs
Table of Contents
ProASIC3 Device Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
ProASIC3 DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-84
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-91
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-107
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-108
Pin Descriptions
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Package Pin Assignments
QN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
QN68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
QN132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
CS121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
TQ144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
FG144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52
FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Revision 13 V
1 – ProASIC3 Device Family Overview
General Description
ProASIC3, the third-generation family of Microsemi flash FPGAs, offers performance, density, and
PLUS®
features beyond those of the ProASIC family. Nonvolatile flash technology gives ProASIC3 devices
the advantage of being a secure, low power, single-chip solution that is Instant On. ProASIC3 is
reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable
designers to create high-density systems using existing ASIC or FPGA design flows and tools.
ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as
clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P015 and A3P030
devices have no PLL or RAM support. ProASIC3 devices have up to 1 million system gates, supported
with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os.
ProASIC3 devices support the ARM Cortex-M1 processor. The ARM-enabled devices have Microsemi
ordering numbers that begin with M1A3P (Cortex-M1) and do not support AES decryption.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-
based FPGAs, flash-based ProASIC3 devices allow all functionality to be Instant On; no external boot
PROM is required. On-board security mechanisms prevent access to all the programming information
and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system
reprogramming to support future design iterations and field upgrades with confidence that valuable
intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using the
industry-standard AES algorithm. The ProASIC3 family device architecture mitigates the need for ASIC
migration at higher user volumes. This makes the ProASIC3 family a cost-effective ASIC replacement
solution, especially for applications in the consumer, networking/ communications, computing, and
avionics markets.
Security
The nonvolatile, flash-based ProASIC3 devices do not require a boot PROM, so there is no vulnerable
external bitstream that can be easily copied. ProASIC3 devices incorporate FlashLock, which provides a
unique combination of reprogrammability and design security without external overhead, advantages that
only an FPGA with nonvolatile flash programming can offer.
ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level
of protection in the FPGA industry for intellectual property and configuration data. In addition, all
FlashROM data in ProASIC3 devices can be encrypted prior to loading, using the industry-leading
AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was adopted by the National
Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3
devices have a built-in AES decryption engine and a flash-based AES key that make them the most
comprehensive programmable logic device security solution available today. ProASIC3 devices with
AES-based security provide a high level of protection for remote field updates over public networks such
as the Internet, and are designed to ensure that valuable IP remains out of the hands of system
overbuilders, system cloners, and IP thieves.
ARM-enabled ProASIC3 devices do not support user-controlled AES security mechanisms. Since the
ARM core must be protected at all times, AES encryption is always on for the core logic, so bitstreams
are always encrypted. There is no user access to encryption for the FlashROM programming data.
Security, built into the FPGA fabric, is an inherent component of the ProASIC3 family. The flash cells are
located beneath seven metal layers, and many device design and layout techniques have been used to
make invasive attacks extremely difficult. The ProASIC3 family, with FlashLock and AES security, is
unique in being highly resistant to both invasive and noninvasive attacks.
Revision 13 1-1
ProASIC3 Device Family Overview
Your valuable IP is protected with industry-standard security, making remote ISP possible. A ProASIC3
device provides the best available security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3 FPGAs
do not require system configuration components such as EEPROMs or microcontrollers to load device
configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system
reliability.
Instant On
Flash-based ProASIC3 devices support Level 0 of the Instant On classification standard. This feature
helps in system component initialization, execution of critical tasks before the processor wakes up, setup
and configuration of memory blocks, clock generation, and bus activity management. The Instant On
feature of flash-based ProASIC3 devices greatly simplifies total system design and reduces total system
cost, often eliminating the need for CPLDs and clock generation PLLs that are used for these purposes in
a system. In addition, glitches and brownouts in system power will not corrupt the ProASIC3 device's
flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when
system power is restored. This enables the reduction or complete removal of the configuration PROM,
expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-
based ProASIC3 devices simplify total system design and reduce cost and design risk while increasing
system reliability and improving system initialization time.
Firm Errors
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike
a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These
errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a
complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 flash-based
FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3 FPGAs cannot be
altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in
the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and
correction (EDAC) circuitry built into the FPGA fabric.
Low Power
Flash-based ProASIC3 devices exhibit power characteristics similar to an ASIC, making them an ideal
choice for power-sensitive applications. ProASIC3 devices have only a very limited power-on current
surge and no high-current transition period, both of which occur on many FPGAs.
ProASIC3 devices also have low dynamic power consumption to further maximize power savings.
1-2 Revision 13
Bank 0 Bank 0
ProASIC3 Flash Family FPGAs
Advanced Flash Technology
The ProASIC3 family offers many benefits, including nonvolatility and reprogrammability through an
advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design
techniques are used to implement logic and control functions. The combination of fine granularity,
enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization
without compromising device routability or performance. Logic functions within the device are
interconnected through a four-level routing hierarchy.
Advanced Architecture
The proprietary ProASIC3 architecture provides granularity comparable to standard-cell ASICs. The
ProASIC3 device consists of five distinct and programmable architectural features (Figure 1-1 and
Figure 1-2 on page 1-4):
• FPGA VersaTiles
• Dedicated FlashROM
†
• Dedicated SRAM/FIFO memory
†
• Extensive CCCs and PLLs
• Advanced I/O structure
Bank 0
CCC
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block*
I/Os
VersaTile
ISP AES User Nonvolatile
Charge Pumps
Decryption* FlashROM
Bank 1
Note: *Not supported by A3P015 and A3P030 devices
Figure 1-1 • ProASIC3 Device Architecture Overview with Two I/O Banks (A3P015, A3P030, A3P060, and
A3P125)
† The A3P015 and A3P030 do not support PLL or SRAM.
Revision 13 1-3
Bank 1 Bank 1
Bank 1 Bank 1
ProASIC3 Device Family Overview
Bank 0
CCC
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
I/Os
VersaTile
RAM Block
4,608-Bit Dual-Port
ISP AES User Nonvolatile
Charge Pumps
SRAM or FIFO Block
Decryption FlashROM
(A3P600 and A3P1000)
Bank 2
Figure 1-2 • ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P600, and A3P1000)
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic
function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch
interconnections. The versatility of the ProASIC3 core tile as either a three-input lookup table (LUT)
equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile
capability is unique to the Microsemi ProASIC family of third-generation architecture flash FPGAs.
VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed
throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core
utilization is possible for virtually any design.
VersaTiles
PLUS®
The ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASIC core
tiles. The ProASIC3 VersaTile supports the following:
• All 3-input logic functions—LUT-3 equivalent
• Latch with clear or set
• D-flip-flop with clear or set
• Enable D-flip-flop with clear or set
Refer to Figure 1-3 for VersaTile configurations.
Enable D-Flip-Flop with Clear or Set
LUT-3 Equivalent D-Flip-Flop with Clear or Set
Data Y
Data Y
X1
X2 LUT-3 CLK
Y D-FF
D-FF CLK
X3 CLR
Enable
CLR
Figure 1-3 • VersaTile Configurations
1-4 Revision 13
Bank 3 Bank 3
ProASIC3 Flash Family FPGAs
User Nonvolatile FlashROM
ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can
be used in diverse system applications:
• Internet protocol addressing (wireless or fixed)
• System calibration settings
• Device serialization and/or inventory control
• Subscription-based business models (for example, set-top boxes)
• Secure key storage for secure communications algorithms
• Asset management/tracking
• Date stamping
• Version management
The FlashROM is written using the standard ProASIC3 IEEE 1532 JTAG programming interface. The
core can be individually programmed (erased and written), and on-chip AES decryption can be used
selectively to securely load data over public networks (except in the A3P015 and A3P030 devices), as in
security keys stored in the FlashROM for a user design.
The FlashROM can be programmed via the JTAG programming interface, and its contents can be read
back either through the JTAG programming interface or via direct FPGA core addressing. Note that the
FlashROM can only be programmed from the JTAG interface and cannot be programmed from the
internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte
basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks
and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the
FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM
address define the byte.
®
The ProASIC3 development software solutions, Libero System-on-Chip (SoC) and Designer, have
extensive support for the FlashROM. One such feature is auto-generation of sequential programming
files for applications requiring a unique serial number in each part. Another feature allows the inclusion of
static data for system version control. Data for the FlashROM can be generated quickly and easily using
Libero SoC and Designer software tools. Comprehensive programming file support is also included to
allow for easy programming of large numbers of parts with differing FlashROM contents.
SRAM and FIFO
ProASIC3 devices (except the A3P015 and A3P030 devices) have embedded SRAM blocks along their
north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory
configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent
read and write ports that can be configured with different bit widths on each port. For example, data can
be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be
initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in A3P015
and A3P030 devices).
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM
block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width
and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and
Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control
unit contains the counters necessary for generation of the read and write address pointers. The
embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC
ProASIC3 devices provide designers with very flexible clock conditioning capabilities. Each member of
the ProASIC3 family contains six CCCs. One CCC (center west side) has a PLL. The A3P015 and
A3P030 devices do not have a PLL.
The six CCC blocks are located at the four corners and the centers of the east and west sides.
All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay
operations as well as clock spine access.
Revision 13 1-5
ProASIC3 Device Family Overview
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
• Wide input frequency range (f ) = 1.5 MHz to 350 MHz
IN_CCC
• Output frequency range (f ) = 0.75 MHz to 350 MHz
OUT_CCC
• Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns
• 2 programmable delay types for clock skew minimization
• Clock frequency synthesis (for PLL only)
Additional CCC specifications:
• Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider
configuration (for PLL only).
• Output duty cycle = 50% ± 1.5% or better (for PLL only)
• Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global
network used (for PLL only)
• Maximum acquisition time = 300 µs (for PLL only)
• Low power consumption of 5 mW
• Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns (for PLL only)
• Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz /
f ) (for PLL only)
OUT_CCC
Global Clocking
ProASIC3 devices have extensive support for multiple clocking domains. In addition to the CCC and PLL
support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid
distribution of high fanout nets.
1-6 Revision 13
ProASIC3 Flash Family FPGAs
I/Os with Advanced I/O Standards
The ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V,
1.8 V, 2.5 V, and 3.3 V). ProASIC3 FPGAs support many different I/O standards—single-ended and
differential.
The I/Os are organized into banks, with two or four banks per device. The configuration of these banks
determines the I/O standards supported (Table 1-1).
Table 1-1 • I/O Standards Supported
I/O Standards Supported
LVTTL/ LVPECL, LVDS,
I/O Bank Type Device and Bank Location LVCMOS PCI/PCI-X B-LVDS, M-LVDS
Advanced East and west Banks of A3P250 and
larger devices
Standard Plus North and south banks of A3P250 and Not supported
larger devices
All banks of A3P060 and A3P125
Standard All banks of A3P015 and A3P030 Not Not supported
supported
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
• Single-Data-Rate applications
• Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications
ProASIC3 banks for the A3P250 device and above support LVPECL, LVDS, B-LVDS and M-LVDS.
B-LVDS and M-LVDS can support up to 20 loads.
Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card
in a powered-up system.
Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed
when the system is powered up, while the component itself is powered down, or when power supplies
are floating.
Wide Range I/O Support
ProASIC3 devices support JEDEC-defined wide range I/O operation. ProASIC3 supports the JESD8-B
specification, covering both 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V.
Wider I/O range means designers can eliminate power supplies or power conditioning components from
the board or move to less costly components with greater tolerances. Wide range eases I/O bank
management and provides enhanced protection from system voltage spikes, while providing the flexibility
to easily run custom voltage applications.
Specifying I/O States During Programming
You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for
PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.
Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have
limited display of Pin Numbers only.
1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during
programming.
2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator
window appears.
3. Click the Specify I/O States During Programming button to display the Specify I/O States During
Programming dialog box.
Revision 13 1-7
ProASIC3 Device Family Overview
4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.
Select the I/Os you wish to modify (Figure 1-4 on page 1-8).
5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings
for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state
settings:
1 – I/O is set to drive out logic High
0 – I/O is set to drive out logic Low
Last Known State – I/O is set to the last value that was driven out prior to entering the
programming mode, and then held at that value during programming
Z -Tristate: I/O is tristated
Figure 1-4 • I/O States During Programming Window
6. Click OK to return to the FlashPoint – Programming File Generator window.
Note: I/O States During programming are saved to the ADB and resulting programming files after
completing programming file generation.
1-8 Revision 13
2 – ProASIC3 DC and Switching Characteristics
General Specifications
Operating Conditions
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any
other conditions beyond those listed under the Recommended Operating Conditions specified in
Table 2-2 on page 2-2 is not implied.
Table 2-1 • Absolute Maximum Ratings
Symbol Parameter Limits Units
VCC DC core supply voltage –0.3 to 1.65 V
VJTAG JTAG DC voltage –0.3 to 3.75 V
VPUMP Programming voltage –0.3 to 3.75 V
VCCPLL Analog power supply (PLL) –0.3 to 1.65 V
VCCI DC I/O output buffer supply voltage –0.3 to 3.75 V
VMV DC I/O input buffer supply voltage –0.3 to 3.75 V
VI I/O input voltage –0.3 V to 3.6 V V
(when I/O hot insertion mode is enabled)
–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower
(when I/O hot-insertion mode is disabled)
2
T Storage temperature –65 to +150 °C
STG
2
T Junction temperature +125 °C
J
Notes:
1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may
undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.
2. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on
page 3-1 for further information.
3. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating
limits, refer to Table 2-2 on page 2-2.
Revision 13 2-1
ProASIC3 DC and Switching Characteristics
1,2
Table 2-2 • Recommended Operating Conditions
1
Symbol Parameters Commercial Industrial Units
T Ambient temperature 0 to +70 -40 to +85 °C
A
T Junction temperature 0 to 85 -40 to 100 °C
J
3
VCC 1.5 V DC core supply voltage 1.425 to 1.575 1.425 to 1.575 V
VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V
4
3.15 to 3.45 3.15 to 3.45 V
VPUMP Programming voltage Programming Mode
5
Operation 0 to 3.6 0 to 3.6 V
VCCPLL Analog power supply (PLL) 1.425 to 1.575 1.425 to 1.575 V
6
VCCI and VMV 1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V
1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V
2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V
3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V
7
3.3 V wide range DC supply voltage 2.7 to 3.6 2.7 to 3.6 V
LVDS/B-LVDS/M-LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V
LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V
Notes:
1. All parameters representing voltages are measured with respect to GND unless otherwise specified.
2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi
recommends that the user follow best design practices using Microsemi’s timing and power simulation tools.
3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O
standard are given in Table 2-18 on page 2-18.
4. The programming temperature range supported is T = 0°C to 85°C.
ambient
5. VPUMP can be left floating during operation (not programming mode).
6. VMV and VCCI should be at the same voltage within a given I/O bank. VMV pins must be connected to the
corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information.
7. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.
1
Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature
Product Programming Program Retention Maximum Storage Maximum Operating
2 2
Grade Cycles (biased/unbiased) Temperature T (°C) Junction Temperature T (°C)
STG J
Commercial 500 20 years 110 100
Industrial 500 20 years 110 100
Notes:
1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.
2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating
conditions and absolute limits.
2-2 Revision 13
ProASIC3 Flash Family FPGAs
1
Table 2-4 • Overshoot and Undershoot Limits
Average VCCI–GND Overshoot or Undershoot Maximum Overshoot/
2 2
VCCI and VMV Duration as a Percentage of Clock Cycle Undershoot
2.7 V or less 10% 1.4 V
5% 1.49 V
3 V 10% 1.1 V
5% 1.19 V
3.3 V 10% 0.79 V
5% 0.88 V
3.6 V 10% 0.45 V
5% 0.54 V
Notes:
1. Based on reliability requirements at 85°C.
2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the
maximum overshoot/undershoot has to be reduced by 0.15 V.
3. This table does not provide PCI overshoot/undershoot limits.
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
®
Sophisticated power-up management circuitry is designed into every ProASIC 3 device. These circuits
ensure easy transition from the powered-off state to the powered-up state of the device. The many
different supplies can power up in any sequence with minimized current spikes or surges. In addition, the
I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1
on page 2-4.
There are five regions to consider during power-up.
ProASIC3 I/Os are activated only if ALL of the following three conditions are met:
1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4).
2. VCCI > VCC – 0.75 V (typical)
3. Chip is in the operating mode.
VCCI Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically
built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:
• During programming, I/Os become tristated and weakly pulled up to VCCI.
• JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
PLL Behavior at Brownout Condition
Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-
up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout
activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4
for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25
V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down
Behavior of Low Power Flash Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide for
information on clock and lock recovery.
Revision 13 2-3
ProASIC3 DC and Switching Characteristics
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
Output buffers, after 200 ns delay from input buffer activation
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC
VCC = 1.575 V
Region 5: I/O buffers are ON
Region 4: I/O
Region 1: I/O Buffers are OFF
and power supplies are within
buffers are ON.
specification.
I/Os are functional
I/Os meet the entire datasheet
(except differential
and timer specifications for
but slower because VCCI
speed, VIH / VIL, VOH / VOL,
is below specification. For the
etc.
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
VCC = 1.425 V
Region 2: I/O buffers are ON.
Region 3: I/O buffers are ON.
I/Os are functional (except differential inputs)
I/Os are functional; I/O DC
but slower because VCCI / VCC are below
specifications are met,
specification. For the same reason, input
but I/Os are slower because
buffers do not meet VIH / VIL levels, and the VCC is below specification.
output buffers do not meet VOH / VOL levels.
Activation trip point:
V = 0.85 V ± 0.25 V
a
Deactivation trip point:
Region 1: I/O buffers are OFF
V = 0.75 V ± 0.25 V
d
VCCI
Activation trip point: Min VCCI datasheet specification
V = 0.9 V ± 0.3 V voltage at a selected I/O
a
Deactivation trip point: standard; i.e., 1.425 V or 1.7 V
V = 0.8 V ± 0.3 V or 2.3 V or 3.0 V
d
Figure 2-1 • I/O State as a Function of VCCI and VCC Voltage Levels
Thermal Characteristics
Introduction
The temperature variable in the Microsemi Designer software refers to the junction temperature, not the
ambient temperature. This is an important distinction because dynamic and static power consumption
cause the chip junction to be higher than the ambient temperature.
EQ 1 can be used to calculate junction temperature.
T = Junction Temperature = T + T
J A
EQ 1
where:
T = Ambient Temperature
A
T = Temperature gradient between junction (silicon) and ambient T = * P
ja
= Junction-to-ambient of the package. numbers are located in Table 2-5.
ja ja
P = Power dissipation
2-4 Revision 13
ProASIC3 Flash Family FPGAs
Package Thermal Characteristics
The device junction-to-case thermal resistivity is and the junction-to-ambient air thermal resistivity is
jc
. The thermal characteristics for are shown for two air flow rates. The absolute maximum junction
ja ja
temperature is 100°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation
allowed for a 484-pin FBGA package at commercial temperature and in still air.
Max. junction temp. (C) – Max. ambient temp. (C) 100C7 – 0C ·
------------------------------------------------------------------------------------------------------------------------------------------ -------------------------------------
Maximum Power Allowed = = = 1.463 W
(C/W) 20.5C/W
ja
EQ 2
Table 2-5 • Package Thermal Resistivities
ja
Package Type Device Pin Count Still Air 200 ft./min. 500 ft./min. Units
jc
Quad Flat No Lead A3P030 132 0.4 21.4 16.8 15.3 C/W
A3P060 132 0.3 21.2 16.6 15.0 C/W
A3P125 132 0.2 21.1 16.5 14.9 C/W
A3P250 132 0.1 21.0 16.4 14.8 C/W
Very Thin Quad Flat Pack (VQFP) All devices 100 10.0 35.3 29.4 27.1 C/W
Thin Quad Flat Pack (TQFP) All devices 144 11.0 33.5 28.0 25.7 C/W
Plastic Quad Flat Pack (PQFP) All devices 208 8.0 26.1 22.5 20.8 C/W
PQFP with embedded heatspreader All devices 208 3.8 16.2 13.3 11.9 C/W
Fine Pitch Ball Grid Array (FBGA) See note* 144 3.8 26.9 22.9 21.5 C/W
See note* 256 3.8 26.6 22.8 21.5 C/W
See note* 484 3.2 20.5 17.0 15.9 C/W
A3P1000 144 6.3 31.6 26.2 24.2 C/W
A3P1000 256 6.6 28.1 24.4 22.7 C/W
A3P1000 484 8.0 23.3 19.0 16.7 C/W
Note: *This information applies to all ProASIC3 devices except the A3P1000. Detailed device/package thermal
information will be available in future revisions of the datasheet.
Revision 13 2-5
ProASIC3 DC and Switching Characteristics
Temperature and Voltage Derating Factors
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays
(normalized to T = 70°C, VCC = 1.425 V)
J
Junction Temperature (°C)
Array Voltage VCC
(V) –40°C 0°C 25°C 70°C 85°C 100°C
1.425 0.88 0.93 0.95 1.00 1.02 1.04
1.500 0.83 0.88 0.90 0.95 0.96 0.98
1.575 0.80 0.84 0.87 0.91 0.93 0.94
Calculating Power Dissipation
Quiescent Supply Current
Table 2-7 • Quiescent Supply Current Characteristics
A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000
Typical (25°C) 2 mA 2 mA 2 mA 2 mA 3 mA 3 mA 5 mA 8 mA
Max. (Commercial) 10 mA 10 mA 10 mA 10 mA 20 mA 20 mA 30 mA 50 mA
Max. (Industrial) 15 mA 15 mA 15 mA 15 mA 30 mA 30 mA 45 mA 75 mA
Note: IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static
contribution, which is shown in Table 2-11 and Table 2-12 on page 2-8.
Power per I/O Pin
Table 2-8 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
Applicable to Advanced I/O Banks
Static Power Dynamic Power
1 2
VMV (V) P (mW) PAC9 (µW/MHz)
DC2
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 16.22
3
3.3 V LVCMOS Wide Range 3.3 – 16.22
2.5 V LVCMOS 2.5 – 5.12
1.8 V LVCMOS 1.8 – 2.13
1.5 V LVCMOS (JESD8-11) 1.5 – 1.45
3.3 V PCI 3.3 – 18.11
3.3 V PCI-X 3.3 – 18.11
Differential
LVDS 2.5 2.26 1.20
LVPECL 3.3 5.72 1.87
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B
specification.
2-6 Revision 13
ProASIC3 Flash Family FPGAs
Table 2-9 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
Applicable to Standard Plus I/O Banks
Static Power Dynamic Power
1 2
VMV (V) PDC2 (mW) PAC9 (µW/MHz)
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 16.23
3
3.3 V LVCMOS Wide Range 3.3 – 16.23
2.5 V LVCMOS 2.5 – 5.14
1.8 V LVCMOS 1.8 – 2.13
1.5 V LVCMOS (JESD8-11) 1.5 – 1.48
3.3 V PCI 3.3 – 18.13
3.3 V PCI-X 3.3 – 18.13
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B
specification.
Table 2-10 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
Applicable to Standard I/O Banks
Static Power Dynamic Power
1 2
VMV (V) PDC2 (mW) PAC9 (µW/MHz)
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 17.24
3
3.3 V LVCMOS Wide Range 3.3 – 17.24
2.5 V LVCMOS 2.5 – 5.19
1.8 V LVCMOS 1.8 – 2.18
1.5 V LVCMOS (JESD8-11) 1.5 – 1.52
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B
specification.
Revision 13 2-7
ProASIC3 DC and Switching Characteristics
1
Table 2-11 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings
Applicable to Advanced I/O Banks
Static Power Dynamic Power
2 3
C (pF) VCCI (V) PDC3 (mW) PAC10 (µW/MHz)
LOAD
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 468.67
4
3.3 V LVCMOS Wide Range 35 3.3 – 468.67
2.5 V LVCMOS 35 2.5 – 267.48
1.8 V LVCMOS 35 1.8 – 149.46
1.5 V LVCMOS 35 1.5 – 103.12
(JESD8-11)
3.3 V PCI 10 3.3 – 201.02
3.3 V PCI-X 10 3.3 – 201.02
Differential
LVDS – 2.5 7.74 88.92
LVPECL – 3.3 19.54 166.52
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PDC3 is the static power (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCC and VCCI.
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
1
Table 2-12 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings
Applicable to Standard Plus I/O Banks
Static Power Dynamic Power
2 3
C (pF) VCCI (V) PDC3 (mW) PAC10 (µW/MHz)
LOAD
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 452.67
4
3.3 V LVCMOS Wide Range 35 3.3 – 452.67
2.5 V LVCMOS 35 2.5 – 258.32
1.8 V LVCMOS 35 1.8 – 133.59
1.5 V LVCMOS (JESD8-11) 35 1.5 – 92.84
3.3 V PCI 10 3.3 – 184.92
3.3 V PCI-X 10 3.3 – 184.92
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. P is the static power (where applicable) measured on VMV.
DC3
3. P is the total dynamic power measured on VCC and VMV.
AC10
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
2-8 Revision 13
ProASIC3 Flash Family FPGAs
1
Table 2-13 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings
Applicable to Standard I/O Banks
Static Power Dynamic Power
2 3
C (pF) VCCI (V) PDC3 (mW) PAC10 (µW/MHz)
LOAD
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 431.08
4
3.3 V LVCMOS Wide Range 35 3.3 – 431.08
2.5 V LVCMOS 35 2.5 – 247.36
1.8 V LVCMOS 35 1.8 – 128.46
1.5 V LVCMOS (JESD8-11) 35 1.5 – 89.46
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. P is the static power (where applicable) measured on VCCI.
DC3
3. P is the total dynamic power measured on VCC and VCCI.
AC10
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
Revision 13 2-9
ProASIC3 DC and Switching Characteristics
Power Consumption of Various Internal Resources
Table 2-14 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices
Device Specific Dynamic Contributions
(µW/MHz)
Parameter Definition
PAC1 Clock contribution of a Global Rib 14.50 12.80 12.80 11.00 11.00 9.30 9.30 9.30
PAC2 Clock contribution of a Global Spine 2.48 1.85 1.35 1.58 0.81 0.81 0.41 0.41
PAC3 Clock contribution of a VersaTile row 0.81
PAC4 Clock contribution of a VersaTile used as a 0.12
sequential module
PAC5 First contribution of a VersaTile used as a 0.07
sequential module
PAC6 Second contribution of a VersaTile used as a 0.29
sequential module
PAC7 Contribution of a VersaTile used as a 0.29
combinatorial Module
PAC8 Average contribution of a routing net 0.70
PAC9 Contribution of an I/O input pin (standard See Table 2-8 on page 2-6 through
dependent) Table 2-10 on page 2-7.
PAC10 Contribution of an I/O output pin (standard See Table 2-11 on page 2-8 through
dependent) Table 2-13 on page 2-9.
PAC11 Average contribution of a RAM block during a 25.00
read operation
PAC12 Average contribution of a RAM block during a 30.00
write operation
PAC13 Dynamic contribution for PLL 2.60
Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power
spreadsheet calculator or SmartPower tool in Libero SoC software.
2-10 Revision 13
A3P1000
A3P600
A3P400
A3P250
A3P125
A3P060
A3P030
A3P015
ProASIC3 Flash Family FPGAs
Table 2-15 • Different Components Contributing to the Static Power Consumption in ProASIC3 Devices
Definition Device Specific Static Power (mW)
Parameter
PDC1 Array static power in Active mode See Table 2-7 on page 2-6.
PDC2 I/O input pin static power (standard-dependent) See Table 2-8 on page 2-6 through
Table 2-10 on page 2-7.
PDC3 I/O output pin static power (standard-dependent) See Table 2-11 on page 2-8 through
Table 2-13 on page 2-9.
PDC4 Static PLL contribution 2.55 mW
PDC5 Bank quiescent power (VCCI-dependent) See Table 2-7 on page 2-6.
Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power
spreadsheet calculator or SmartPower tool in Libero SoC software.
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in Libero SoC software.
The power calculation methodology described below uses the following variables:
• The number of PLLs as well as the number and the frequency of each output clock generated
• The number of combinatorial and sequential cells used in the design
• The internal clock frequencies
• The number and the standard of I/O pins used in the design
• The number of RAM blocks used in the design
• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table2-16 on
page 2-13.
• Enable rates of output buffers—guidelines are provided for typical applications in Table 2-17 on
page 2-13.
• Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-17 on page 2-13. The calculation should be repeated for each clock domain defined in the
design.
Methodology
Total Power Consumption—P
TOTAL
P = P + P
TOTAL STAT DYN
P is the total static power consumption.
STAT
P is the total dynamic power consumption.
DYN
Total Static Power Consumption—P
STAT
P = P + N * P + N * P
STAT DC1 INPUTS DC2 OUTPUTS DC3
N is the number of I/O input buffers used in the design.
INPUTS
N is the number of I/O output buffers used in the design.
OUTPUTS
Revision 13 2-11
A3P1000
A3P600
A3P400
A3P250
A3P125
A3P060
A3P030
A3P015
ProASIC3 DC and Switching Characteristics
Total Dynamic Power Consumption—P
DYN
P = P + P + P + P + P + P + P + P
DYN CLOCK S-CELL C-CELL NET INPUTS OUTPUTS MEMORY PLL
Global Clock Contribution—P
CLOCK
P = (P + N *P + N *P + N * P ) * F
CLOCK AC1 SPINE AC2 ROW AC3 S-CELL AC4 CLK
N is the number of global spines used in the user design—guidelines are provided in the
SPINE
"Spine Architecture" section of the Global Resources chapter in the ProASIC3 FPGA
Fabric User's Guide.
N is the number of VersaTile rows used in the design—guidelines are provided in the "Spine
ROW
Architecture" section of the Global Resources chapter in the ProASIC3 FPGA Fabric
User's Guide.
F is the global clock signal frequency.
CLK
N is the number of VersaTiles used as sequential modules in the design.
S-CELL
P , P , P , and P are device-dependent.
AC1 AC2 AC3 AC4
Sequential Cells Contribution—P
S-CELL
P = N * (P + / 2 * P ) * F
S-CELL S-CELL AC5 1 AC6 CLK
N is the number of VersaTiles used as sequential modules in the design. When a multi-tile
S-CELL
sequential cell is used, it should be accounted for as 1.
is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-13.
1
F is the global clock signal frequency.
CLK
Combinatorial Cells Contribution—P
C-CELL
P = N * / 2 * P * F
C-CELL C-CELL 1 AC7 CLK
N is the number of VersaTiles used as combinatorial modules in the design.
C-CELL
is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-13.
1
F is the global clock signal frequency.
CLK
Routing Net Contribution—P
NET
P = (N + N ) * / 2 * P * F
NET S-CELL C-CELL 1 AC8 CLK
N is the number of VersaTiles used as sequential modules in the design.
S-CELL
N is the number of VersaTiles used as combinatorial modules in the design.
C-CELL
is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-13.
1
F is the global clock signal frequency.
CLK
I/O Input Buffer Contribution—P
INPUTS
P = N * / 2 * P * F
INPUTS INPUTS 2 AC9 CLK
N is the number of I/O input buffers used in the design.
INPUTS
is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-13.
2
F is the global clock signal frequency.
CLK
I/O Output Buffer Contribution—P
OUTPUTS
P = N * / 2 * * P * F
OUTPUTS OUTPUTS 2 1 AC10 CLK
N is the number of I/O output buffers used in the design.
OUTPUTS
is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-13.
2
is the I/O buffer enable rate—guidelines are provided in Table 2-17 on page 2-13.
1
F is the global clock signal frequency.
CLK
2-12 Revision 13
ProASIC3 Flash Family FPGAs
RAM Contribution—P
MEMORY
P = P * N * F * + P * N * F *
MEMORY AC11 BLOCKS READ-CLOCK 2 AC12 BLOCK WRITE-CLOCK 3
N is the number of RAM blocks used in the design.
BLOCKS
F is the memory read clock frequency.
READ-CLOCK
is the RAM enable rate for read operations.
2
F is the memory write clock frequency.
WRITE-CLOCK
is the RAM enable rate for write operations—guidelines are provided in Table 2-17 on page 2-13.
3
PLL Contribution—P
PLL
P = P + P *F
PLL DC4 AC13 CLKOUT
1
F is the output clock frequency.
CLKOUT
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are
some examples:
• The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the
clock frequency.
• The average toggle rate of an 8-bit counter is 25%:
– Bit 0 (LSB) = 100%
– Bit 1 = 50%
– Bit 2 = 25%
–…
– Bit 7 (MSB) = 0.78125%
– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
nontristate output buffers are used, the enable rate should be 100%.
Table 2-16 • Toggle Rate Guidelines Recommended for Power Calculation
Component Definition Guideline
Toggle rate of VersaTile outputs 10%
1
I/O buffer toggle rate 10%
2
Table 2-17 • Enable Rate Guidelines Recommended for Power Calculation
Component Definition Guideline
I/O output buffer enable rate 100%
1
RAM enable rate for read operations 12.5%
2
RAM enable rate for write operations 12.5%
3
1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula by adding its corresponding contribution (P * F product) to the total PLL contribution.
AC14 CLKOUT
Revision 13 2-13
ProASIC3 DC and Switching Characteristics
User I/O Characteristics
Timing Model
I/O Module
(Non-Registered)
Combinational Cell
Combinational Cell
LVPECL (Applicable to
Y
Y
Advanced I/O Banks Only)L
t = 0.56 ns t = 0.49 ns
PD PD
t = 1.34 ns
DP
I/O Module
(Non-Registered)
Combinational Cell
Y
Output drive strength = 12 mA
LVTTL
High slew rate
t = 2.64 ns (Advanced I/O Banks)
t = 0.87 ns DP
PD
I/O Module
Combinational Cell
(Non-Registered)
I/O Module
Y
(Registered)
Output drive strength = 8 mA
LVTTL
t = 1.05 ns
High slew rate
PY
t = 3.66 ns (Advanced I/O Banks)
DP
LVPECL
t = 0.47 ns
PD
I/O Module
DQ
(Applicable
(Non-Registered)
to Advanced
Combinational Cell
I/O Banks only)
Y
Output drive strength = 4 mA
LVCMOS 1.5 V
High slew rate
t = 0.24 ns
ICLKQ
t = 3.97 ns (Advanced I/O Banks)
t = 0.47 ns DP
t = 0.26 ns PD
ISUD
Input LVTTL
Clock
I/O Module
Register Cell (Registered)
Register Cell
Combinational Cell
t = 0.76 ns (Advanced I/O Banks)
PY
Y
DQ
DQ DQ
LVTTL 3.3 V Output drive
I/O Module strength = 12 mA High slew rate
t = 0.47 ns
PD t = 2.64 ns
(Non-Registered)
DP
(Advanced I/O Banks)
t = 0.55 ns t = 0.59 ns
CLKQ t = 0.55 ns
OCLKQ
CLKQ
LVDS,
t = 0.43 ns
t = 0.43 ns t = 0.31 ns
SUD
SUD OSUD
BLVDS,
M-LVDS Input LVTTL Input LVTTL
Clock Clock
(Applicable for
t = 1.20 ns
PY
Advanced I/O
Banks only) t = 0.76 ns
t = 0.76 ns PY
PY
(Advanced I/O Banks)
(Advanced I/O Banks)
Figure 2-2 • Timing Model
Operating Conditions: –2 Speed, Commercial Temperature Range (T = 70°C), Worst Case
J
VCC = 1.425 V
2-14 Revision 13
ProASIC3 Flash Family FPGAs
t t
PY DIN
D Q
PAD
DIN
Y
CLK To Array
I/O Interface
t = MAX(t (R), t (F))
PY PY PY
t = MAX(t (R), t (F))
DIN DIN DIN
VIH
V V
trip trip
VIL
PAD
VCC
50%
50%
Y
GND
t t
PY PY
(R) (F)
VCC
50% 50%
DIN
t
GND t
DIN
DIN
(R) (F)
Figure 2-3 • Input Buffer Timing Model and Delays (example)
Revision 13 2-15
ProASIC3 DC and Switching Characteristics
t
t
DOUT
DP
D Q
PAD
DOUT
CLK Std
D
Load
From Array
t = MAX(t (R), t (F))
DP DP DP
I/O Interface
t = MAX(t (R), t (F))
DOUT DOUT DOUT
t t
DOUT DOUT
VCC
(R)
(F)
50%
50%
D
0 V
VCC
50% 50%
DOUT
0 V
VOH
Vtrip
Vtrip
V
OL
PAD
t t
DP DP
(R) (F)
Figure 2-4 • Output Buffer Model and Delays (example)
2-16 Revision 13
ProASIC3 Flash Family FPGAs
t
EOUT
D Q
CLK
t , t , t , t , t , t
E
ZL ZH HZ LZ ZLS ZHS
EOUT
D Q
PAD
DOUT
CLK
D
t = MAX(t (r), t (f))
I/O Interface
EOUT EOUT EOUT
VCC
D
VCC
50% 50%
E
t
EOUT (F)
t
EOUT (R)
VCC
50%
50% 50%
50%
t
LZ
EOUT t
ZH
t
t
ZL
HZ VCCI
PAD 90% VCCI
Vtrip
Vtrip
VOL
10% V
CCI
VCC
D
VCC
50% 50%
E
t
t
EOUT (F)
EOUT (R)
VCC
50% 50%
EOUT 50%
t
ZHS
t
ZLS VOH
PAD
Vtrip Vtrip
VOL
Figure 2-5 • Tristate Output Buffer Timing Model and Delays (example)
Revision 13 2-17
ProASIC3 DC and Switching Characteristics
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Table 2-18 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Advanced I/O Banks
1 1
Equiv. VIL VIH VOL VOH IOL IOH
Software
Default
Drive
Drive Strength Slew Min. Max. Min. Max. Max. Min.
2
I/O Standard Strength Option Rate V V V V V VmAmA
3.3 V LVTTL / 12 mA 12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12
3.3 V
LVCMOS
3.3 V 100 µA 12 mA High –0.3 0.8 2 3.6 0.2 VCCI – 0.2 0.1 0.1
LVCMOS
3
Wide Range
2.5 V 12 mA 12 mA High –0.3 0.7 1.7 2.7 0.7 1.7 12 12
LVCMOS
1.8 V 12 mA 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 12 12
LVCMOS
1.5 V 12 mA 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.6 0.25 * VCCI 0.75 * VCCI 12 12
LVCMOS
3.3 V PCI Per PCI specifications
3.3 V PCI-X Per PCI-X specifications
Notes:
1. Currents are measured at 85°C junction temperature.
2. Please note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT
operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
2-18 Revision 13
ProASIC3 Flash Family FPGAs
Table 2-19 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Standard Plus I/O Banks
Equiv. IOH
1 1
Software VIL VIH VOL VOH IOL
Default
Drive
Drive Strength Slew Min. Max. Min. Max. Max. Min.
2
I/O Standard Strength Option Rate V V V V V VmAmA
3.3 V LVTTL / 12 mA 12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12
3.3 V
LVCMOS
3.3 V 100 µA 12 mA High –0.3 0.8 2 3.6 0.2 VCCI – 0.2 0.1 0.1
LVCMOS
3
Wide Range
2.5 V 12 mA 12 mA High –0.3 0.7 1.7 2.7 0.7 1.7 12 12
LVCMOS
1.8 V 8 mA 8 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 8 8
LVCMOS
1.5 V 4 mA 4 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.6 0.25 * VCCI 0.75 * VCCI 4 4
LVCMOS
3.3 V PCI Per PCI specifications
3.3 V PCI-X Per PCI-X specifications
Notes:
1. Currents are measured at 85°C junction temperature.
2. Please note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT
operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
Revision 13 2-19
ProASIC3 DC and Switching Characteristics
Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Standard I/O Banks
1 1
Equiv. VIL VIH VOL VOH IOL IOH
Software
Default
Drive
Drive Strength Slew Min. Max. Min. Max. Max. Min.
2
I/O Standard Strength Option Rate V V V V V VmAmA
3.3 V LVTTL / 8 mA 8 mA High –0.3 0.8 2 3.6 0.4 2.4 8 8
3.3 V
LVCMOS
3.3 V 100 µA 8 mA High –0.3 0.8 2 3.6 0.2 VCCI – 0.2 0.1 0.1
LVCMOS
3
Wide Range
2.5 V 8 mA 8 mA High –0.3 0.7 1.7 3.6 0.7 1.7 8 8
LVCMOS
1.8 V 4 mA 4 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4
LVCMOS
1.5 V 2 mA 2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2
LVCMOS
Notes:
1. Currents are measured at 85°C junction temperature.
2. Please note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT
operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
Table 2-21 • Summary of Maximum and Minimum DC Input Levels
Applicable to Commercial and Industrial Conditions
1 2
Industrial
Commercial
3 4 3 4
IIL IIH IIL IIH
µA µA µA µA
DC I/O Standards
3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15
3.3 V LVCMOS Wide Range 10 10 15 15
2.5 V LVCMOS 10 10 15 15
1.8 V LVCMOS 10 10 15 15
1.5 V LVCMOS 10 10 15 15
3.3 V PCI 10 10 15 15
3.3 V PCI-X 10 10 15 15
Notes:
1. Commercial range (0°C < T < 70°C)
A
2. Industrial range (–40°C < T < 85°C)
A
3. IIL is the input leakage current per I/O pin over recommended operation conditions where
–0.3V < V
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