256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM MT16VDDT3264A – 256MB DDR SDRAM MT16VDDT6464A – 512MB MT16VDDT12864A – 1GB ‡ MT16VDDT25664A – 2GB (ADVANCE)  UNBUFFERED DIMM For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/modules Features Figure 1: 184-Pin DIMM (MO-206) • 184-pin, dual in-line memory module (DIMM) Standard 1.25in. (31.75mm)  Fast data transfer rates: PC2100 or PC2700  Utilizes 266 MT/s and 333 MT/s DDR SDRAM components  256MB (32 Meg x 64), 512MB (64 Meg x 64), 1GB (128 Meg x 64), and 2GB (256 Meg x 64) VDD = VDDQ = +2.5V Low-Profile 1.15in. (29.21mm) VDDSPD = +2.3V to +3.6V  2.5V I/O (SSTL_2 compatible)  Commands entered on each positive CK edge  DQS edge-aligned with data for READs; center- aligned with data for WRITEs  Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle  Bidirectional data strobe (DQS) transmitted/ OPTIONS MARKING received with data—i.e., source-synchronous data capture Package G  Differential clock inputs (CK and CK#) 184-pin DIMM (standard) 1 Y  Four internal device banks for concurrent operation 184-pin DIMM (lead-free) 2  Programmable burst lengths: 2, 4, or 8  Memory Clock, Speed, CAS Latency  Auto precharge option -335 6ns/166MHz (333 MT/s) CL = 2.5 1  Auto Refresh and Self Refresh Modes -262 7.5ns/133 MHz (266 MT/s) CL = 2 1  15.6µs (256MB), 7.8125µs (512MB, 1GB, and 2GB) -26A 7.5ns/133 MHz (266 MT/s) CL = 2 maximum average periodic refresh interval -265 7.5ns/133 MHz (266 MT/s) CL = 2.5  Serial Presence Detect (SPD) with EEPROM PCB  Programmable READ CAS latency See page 2 note Standard 1.25in. (31.75mm) Gold edge contacts See page 2 note Low-Profile 1.20in. (30.48mm) NOTE: 1. Consult Micron for product availability. 2. CL = CAS (READ) Latency. Table 1: Address Table 256MB 512MB 1GB 2GB Refresh Count 4K 8K 8K 8K Row Addressing 4K (A0–A11) 8K (A0–A12) 8K (A0–A12) 16K (A0–A13) 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) Device Bank Addressing Device Configuration 128Mb (16 Meg x 8) 256Mb (32 Meg x 8) 512Mb (64 Meg x 8) 1Gb (128 Meg x 8) Column Addressing 1K (A0–A9) 1K (A0–A9) 2K (A0–A9, A11) 2K (A0–A9, A11) Module Rank Addressing 2 (S0#, S1#) 2 (S0#, S1#) 2 (S0#, S1#) 2 (S0#, S1#) pdf: 09005aef80739fa5, source: 09005aef807397e5 DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 1 ©2004 Micron Technology, Inc. ‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Table 2: Part Numbers and Timing Parameters LATENCY PART NUMBER MODULE CONFIGURATION MODULE MEMORY CLOCK/ t t DENSITY BANDWIDTH DATA RATE (CL - RCD - RP) MT16VDDT3264AG-335__ 256MB 32 Meg x 64 2.7 GB/s 6ns/333 MT/s 2.5-3-3 MT16VDDT3264AY-335__ 256MB 32 Meg x 64 2.7 GB/s 6ns/333 MT/s 2.5-3-3 256MB 32 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2 MT16VDDT3264AG-262__ MT16VDDT3264AY-262__ 256MB 32 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2 MT16VDDT3264AG-26A__ 256MB 32 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT16VDDT3264AY-26A__ 256MB 32 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT16VDDT3264AG-265__ 256MB 32 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 256MB 32 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT16VDDT3264AY-265__ MT16VDDT6464AG-335__ 512MB 64 Meg x 64 2.7 GB/s 6ns/333 MT/s 2.5-3-3 MT16VDDT6464AY-335__ 512MB 64 Meg x 64 2.7 GB/s 6ns/333 MT/s 2.5-3-3 MT16VDDT6464AG-262__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2 MT16VDDT6464AY-262__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT16VDDT6464AG-26A__ MT16VDDT6464AY-26A__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT16VDDT6464AG-265__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT16VDDT6464AY-265__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT16VDDT12864AG-335__ 1GB 128 Meg x 64 2.7 GB/s 6ns/333 MT/s 2.5-3-3 1GB 128 Meg x 64 2.7 GB/s 6ns/333 MT/s 2.5-3-3 MT16VDDT12864AY-335__ MT16VDDT12864AG-262__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2 MT16VDDT12864AY-262__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2 MT16VDDT12864AG-26A__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT16VDDT12864AY-26A__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT16VDDT12864AG-265__ MT16VDDT12864AY-265__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT16VDDT25664AG-335__ 2GB 256 Meg x 64 2.7 GB/s 6ns/333 MT/s 2.5-3-3 MT16VDDT25664AY-335__ 2GB 256 Meg x 64 2.7 GB/s 6ns/333 MT/s 2.5-3-3 MT16VDDT25664AG-262__ 2GB 256 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2 2GB 256 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2 MT16VDDT25664AY-262__ MT16VDDT25664AG-26A__ 2GB 256 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT16VDDT25664AY-26A__ 2GB 256 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT16VDDT25664AG-265__ 2GB 256 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT16VDDT25664AY-265__ 2GB 256 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT16VDDT6464AG-265A1. pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 2 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Table 3: Pin Assignment Table 4: Pin Assignment (184-Pin DIMM Front) (184-Pin DIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1VREF 24 DQ17 47 DNU 70 VDD 93 VSS 116 VSS 139 VSS 162 DQ47 2DQ0 25 DQS2 48 A0 71 NC 94 DQ4 117 DQ21 140 DNU 163 NC 3VSS 26 VSS 49 DNU 72 DQ48 95 DQ5 118 A11 141 A10 164 VDDQ 4DQ1 27 A9 50 VSS 73 DQ49 96 VDDQ 119 DM2 142 DNU 165 DQ52 5DQS0 28 DQ18 51 DNU 74 VSS 97 DM0 120 VDD 143 VDDQ 166 DQ53 2 6DQ2 29 A7 52 BA1 75 CK2# 98 DQ6 121 DQ22 144 DNU NC/A13 167 7VDD 30 VDDQ 53 DQ32 76 CK2 99 DQ7 122 A8 145 VSS 168 VDD 8DQ3 31 DQ19 54 VDDQ 77 VDDQ 100 VSS 123 DQ23 146 DQ36 169 DM6 9NC 32 A5 55 DQ33 78 DQS6 101 NC 124 VSS 147 DQ37 170 DQ54 10 NC 33 DQ24 56 DQS4 79 DQ50 102 NC 125 A6 148 VDD 171 DQ55 11 VSS 34 VSS 57 DQ34 80 DQ51 103 NC 126 DQ28 149 DM4 172 VDDQ 12 DQ8 35 DQ25 58 VSS 81 VSS 104 VDDQ 127 DQ29 150 DQ38 173 NC 13 DQ9 36 DQS3 59 BA0 82 NC 105 DQ12 128 VDDQ 151 DQ39 174 DQ60 14 DQS1 37 A4 60 DQ35 83 DQ56 106 DQ13 129 DM3 152 VSS 175 DQ61 15 VDDQ 38 VDD 61 DQ40 84 DQ57 107 DM1 130 A3 153 DQ44 176 VSS 16 CK1 39 DQ26 62 VDDQ 85 VDD 108 VDD 131 DQ30 154 RAS# 177 DM7 17 CK1# 40 DQ27 63 WE# 86 DQS7 109 DQ14 132 VSS 155 DQ45 178 DQ62 18 VSS 41 A2 64 DQ41 87 DQ58 110 DQ15 133 DQ31 156 VDDQ 179 DQ63 19 DQ10 42 VSS 65 CAS# 88 DQ59 111 CKE1 134 DNU 157 S0# 180 VDDQ 20 DQ11 43 A1 66 VSS 89 VSS 112 VDDQ 135 DNU 158 S1# 181 SA0 21 CKE0 44 DNU 67 DQS5 90 NC 113 NC 136 VDDQ 159 DM5 182 SA1 22 VDDQ 45 DNU 68 DQ42 91 SDA 114 DQ20 137 CK0 160 VSS 183 SA2 23 DQ16 46 VDD 69 DQ43 92 SCL 115 NC/A12 138 CK0# 161 DQ46 184 VDDSPD NOTE: 1. Pin 115 is No Connect for 256MB, or A12 for 512MB, 1GB, 2GB. 2. Pin 167 is No Connect (NC) for 256MB, 512MB, and 1GB, or A13 for 2GB. Figure 2: Pin Locations: 184-Pin DIMM Front View Standard 1.25in. (31.75mm) Front View Low-Profile 1.15in. (29.21mm) U10 U1 U2 U3 U4 U6 U7 U8 U9 U1 U2 U3 U4 U6 U7 U8 U9 PIN 1 PIN 52 PIN 53 PIN 92 PIN 92 PIN 1 PIN 52 PIN 53 Back View Back View U19 U10 U11 U12 U13 U15 U16 U17 U18 U19 U18 U17 U16 U14 U13 U12 U11 PIN 145 PIN 93 PIN 93 PIN 184 PIN 144 PIN 184 PIN 145 PIN 144 Indicates a VDD or VDDQ pin Indicates a VSS pin Indicates a VDD or VDDQ pin Indicates a VSS pin pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 3 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL TYPE DESCRIPTION 63, 65, 154 WE#, CAS#, RAS# Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. 16, 17, 75, 76, 137, 138 CK0, CK0#, CK1, Input Clock: CK, CK# are differential clock inputs. All address and CK1#, CK2, CK2# control input signals are sampled on the crossing of the positive edge of CK,and negative edge of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#. 21, 111 CKE0, CKE1 Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all device banks idle), or ACTIVE POWER- DOWN (row ACTIVE in any device bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied and until CKE is first brought HIGH. After CKE is brought HIGH, it becomes an SSTL_2 input only. 157, 158 S0#, S1# Input Chip Selects: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. 52, 59 BA0, BA1 Input Bank Address: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. 27, 29, 32, 37, 41, 43, 48, A0–A11 Input Address Inputs: Provide the row address for ACTIVE 115 (512MB, 1GB, 2GB), 118, (256MB) commands, and the column address and auto precharge bit 122, 125, 130, 141, 167 (2GB) A0–A12 (A10) for READ/WRITE commands, to select one location out of (512MB, 1GB) the memory array in the respective device bank. A10 sampled A0–A13 during a PRECHARGE command determines whether the (2GB) PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. 5, 14, 25, 36, 56, 67, 78, 86 DQS0–DQS7 Input/ Data Strobe: Output with READ data, input with WRITE data. Output DQS is edge-aligned with READ data, centered in WRITE data. Used to capture data. 97, 107, 119, 129, 149, 159, DM0–DM7 Input Data Write Mask: DM LOW allows WRITE operation. DM HIGH 169, 177 blocks WRITE operation. DM lines do not affect READ operation. pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 4 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Table 5: Pin Descriptions (Continued) Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL TYPE DESCRIPTION 2, 4, 6, 8, 12, 13, 19, 20, 23, DQ0–DQ63 Input/ Data I/Os: Data bus. 24, 28, 31, 33, 35, 39, 40, 53, Output 55, 57, 60, 61, 64, 68, 69, 72, 73, 79, 80, 83, 84, 87, 88, 94, 95, 98, 99, 105, 106, 109, 110, 114, 117, 121, 123, 126, 127, 131, 133, 146, 147, 150, 151, 153, 155, 161, 162, 165, 166, 170, 171, 174, 175, 178, 179 92 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. 181,182, 183 SA0–SA2 Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. 91 SDA Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to Output transfer addresses and data into and out of the presence- detect device. 1VREF Supply SSTL_2 reference voltage. 15, 22, 30, 54, 62, 77, 96, 104, VDDQ Supply DQ Power Supply: +2.5V ±0.2V. 112, 128, 136, 143, 156, 164, 172, 180 7, 38, 46, 70, 85, 108, 120, VDD Supply Power Supply: +2.5V ±0.2V. 148, 168 3, 11, 18, 26, 34, 42, 50, 58, VSS Supply Ground. 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 184 VDDSPD Supply Serial EEPROM positive power supply: +2.3V to +3.6V. 44, 45, 47, 49, 51, 134, 135, DNU — Do Not Use: These pins are not connected on these modules, 140, 142, 144 but are assigned pins on other modules in this product family. 9, 10, 71, 82, 90, 101, 102, NC — No Connect: These pins should be left unconnected. 103, 113, 115 (256MB), 163, 167 (256MB, 512MB, 1GB), 173 pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 5 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Figure 3: Functional Block Diagram – Standard PCB S1# S0# DQS0 DQS4 DM0 DM4 DM CS# DQS DM CS# DQS DM CS# DQS DM CS# DQS DQ0 DQ DQ DQ32 DQ DQ DQ U1 DQ U17 DQ33 DQ U13 DQ U5 DQ1 DQ DQ DQ34 DQ DQ DQ2 DQ3 DQ DQ DQ35 DQ DQ DQ DQ DQ36 DQ DQ DQ4 DQ DQ5 DQ DQ37 DQ DQ DQ6 DQ DQ DQ38 DQ DQ DQ DQ DQ39 DQ DQ DQ7 DQS1 DQS5 DM1 DM5 DM CS# DQS DM CS# DQS DM CS# DQS DM CS# DQS DQ8 DQ DQ DQ40 DQ DQ DQ9 DQ U16 DQ U2 DQ41 DQ U6 U12 DQ DQ10 DQ DQ DQ42 DQ DQ DQ11 DQ DQ DQ43 DQ DQ DQ12 DQ DQ44 DQ DQ DQ DQ13 DQ DQ DQ45 DQ DQ DQ14 DQ DQ DQ46 DQ DQ DQ DQ15 DQ DQ DQ47 DQ DQS2 DQS6 DM2 DM6 DM CS# DQS DM CS# DQS DM CS# DQS DM CS# DQS DQ16 DQ DQ DQ48 DQ DQ DQ17 DQ DQ49 U11 U3 DQ U15 DQ DQ U7 DQ18 DQ DQ DQ50 DQ DQ DQ19 DQ DQ51 DQ DQ DQ DQ20 DQ52 DQ DQ DQ DQ DQ21 DQ DQ DQ53 DQ DQ DQ22 DQ DQ54 DQ DQ DQ DQ23 DQ DQ DQ55 DQ DQ DQS3 DQS7 DM3 DM7 DM CS# DQS DM CS# DQS DM CS# DQS DM CS# DQS DQ24 DQ DQ DQ56 DQ DQ DQ25 DQ U14 DQ U4 DQ57 DQ U8 DQ U10 DQ DQ DQ DQ26 DQ58 DQ DQ27 DQ DQ DQ59 DQ DQ DQ28 DQ DQ DQ60 DQ DQ DQ29 DQ DQ DQ61 DQ DQ DQ30 DQ DQ DQ62 DQ DQ DQ DQ DQ63 DQ DQ31 DQ 120 3 CK0 U4, U6, BA0, BA1 BA0, BA1: DDR SDRAMS 3 CK0# U13, U15 A0-A11 (256MB) A0-A11: DDR SDRAMS 3 3pF A0-A12 (512MB, 1GB) A0-A12: DDR SDRAMS 3 120 A0-A13 (2GB) A0-A13: DDR SDRAMS 3 CK1 U1-U3, RAS# RAS#: DDR SDRAMS CK1# U16-U18 3 CAS# CAS#: DDR SDRAMS 120 3 WE# WE#: DDR SDRAMS CK2 CKE1 U7-U12 CKE0: DDR SDRAMS U1, U3, U6, U8, U11, U13, U14, U16 CK2# CKE0 CKE1: DDR SDRAMS U2, U4, U5, U7, U10, U12, U15, U17 SERIAL PD VDDSPD SPD/EEPROM SCL U19 SDA VDDQ DDR SDRAMS WP A0 A1 A2 VDD DDR SDRAMS SA0 SA1 SA2 VREF DDR SDRAMS VSS DDR SDRAMS Standard modules use the following SDRAM devices: MT46V16M8TG (256MB); MT46V32M8TG (512MB); MT46V64M8TG (1GB); NOTE: MT46V128M8TG (2GB) 1. All resistor values are 22Ω unless otherwise specified. 2. Per industry standard, Micron modules utilize various component speed Lead-free modules use the following SDRAM devices: grades, as referenced in the module part number guide at MT46V16M8P (256MB); MT46V32M8P (512MB); MT46V64M8P (1GB); www.micron.com/numberguide. MT46V128M8P (2GB) pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 6 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Figure 4: Functional Block Diagram – Low-Profile PCB S1# S0# DQS0 DQS4 DM0 DM4 DM CS# DQS DM CS# DQS DM CS# DQS DM CS# DQS DQ0 DQ DQ DQ32 DQ DQ DQ1 DQ DQ DQ33 DQ DQ DQ DQ DQ34 DQ DQ DQ2 U1 U11 U6 U16 DQ DQ DQ35 DQ DQ DQ3 DQ DQ DQ36 DQ DQ DQ4 DQ5 DQ DQ DQ37 DQ DQ DQ DQ DQ38 DQ DQ6 DQ DQ DQ DQ39 DQ DQ DQ7 DQS1 DQS5 DM1 DM5 DM CS# DQS DM CS# DQS DM CS# DQS DM CS# DQS DQ8 DQ DQ40 DQ DQ DQ DQ9 DQ DQ DQ41 DQ DQ DQ10 DQ DQ DQ42 DQ DQ U2 U12 U7 U17 DQ11 DQ DQ DQ43 DQ DQ DQ DQ12 DQ DQ DQ44 DQ DQ13 DQ DQ DQ45 DQ DQ DQ14 DQ DQ DQ46 DQ DQ DQ15 DQ DQ DQ47 DQ DQ DQS2 DQS6 DM2 DM6 DM CS# DQS DM CS# DQS DM CS# DQS DM CS# DQS DQ16 DQ DQ DQ48 DQ DQ DQ17 DQ DQ DQ49 DQ DQ DQ18 DQ50 DQ DQ DQ DQ U3 U8 U18 DQ19 DQ U13 DQ51 DQ DQ DQ DQ20 DQ DQ52 DQ DQ DQ DQ21 DQ DQ DQ53 DQ DQ DQ22 DQ DQ DQ54 DQ DQ DQ23 DQ DQ55 DQ DQ DQ DQS3 DQS7 DM3 DM7 DM CS# DQS DM CS# DQS DM CS# DQS DM CS# DQS DQ24 DQ DQ DQ56 DQ DQ DQ25 DQ DQ DQ57 DQ DQ DQ26 DQ DQ DQ58 DQ DQ U4 U14 U9 U19 DQ DQ DQ DQ27 DQ59 DQ DQ28 DQ DQ DQ60 DQ DQ DQ29 DQ DQ DQ61 DQ DQ DQ30 DQ DQ DQ62 DQ DQ DQ31 DQ DQ DQ63 DQ DQ BA0, BA1 SERIAL PD BA0, BA1: DDR SDRAMS VDDSPD SPD SCL A0-A11 (256MB) U10 A0-A11: DDR SDRAMS VDDQ SDA DDR SDRAMS WP A0 A1 A2 A0-A12 (512MB, 1GB) A0-A12: DDR SDRAMS VDD DDR SDRAMS RAS# RAS#: DDR SDRAMS VREF DDR SDRAMS SA0 SA1 SA2 CAS# CAS#: DDR SDRAMS VSS DDR SDRAMS CKE0 CKE0: DDR SDRAMS U1–U4, U6–U9 CKE1 CKE1: DDR SDRAMS U11, U14, U16–U19 WE# 120 120 120 WE#: DDR SDRAMS DDR DDR DDR CK1 CK2 CK0 SDRAM SDRAM SDRAM CK0# CK1# CK2# X 4 X 6 X 6 3pF 3pF 3pF Standard modules use NOTE: MT46V16M8TG for 256MB; MT46V32M8TG for 512MB; MT46V64M8TG 1. All resistor values are 22Ω unless otherwise specified. for 1GB 2. Per industry standard, Micron modules utilize various component speed Lead-free modules use grades, as referenced in the module part number guide at MT46V16M8P for 256MB; MT46V32M8P for 512MB; MT46V64M8P for www.micron.com/numberguide. 1GB pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 7 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM General Description The MT16VDDT3264A, MT16VDDT6464A, The pipelined, multibank architecture of DDR MT16VDDT12864A, and MT16VDDT25664A are high- SDRAM modules allows for concurrent operation, speed CMOS, dynamic random-access, 256MB, thereby providing high effective bandwidth by hiding 512MB, 1GB and 2GB memory modules organized in row precharge and activation time. x64 configuration. DDR SDRAM modules use inter- An auto refresh mode is provided, along with a nally configured quad-bank DDR SDRAM devices. power-saving power-down mode. All inputs are com- DDR SDRAM modules use a double data rate archi- patible with the JEDEC Standard for SSTL_2. All out- tecture to achieve high-speed operation. Double data puts are SSTL_2, Class II compatible. For more rate architecture is essentially a 2n-prefetch architec- information regarding DDR SDRAM operation, refer to ture with an interface designed to transfer two data the 128Mb, 256Mb, 512Mb, or 1Gb DDR SDRAM com- words per clock cycle at the I/O pins. A single read or ponent data sheets. write access for the DDR SDRAM module effectively consists of a single 2n-bit wide, one-clock-cycle data Serial Presence-Detect Operation transfer at the internal DRAM core and two corre- DDR SDRAM modules incorporate serial presence- sponding n-bit wide, one-half-clock-cycle data trans- detect (SPD). The SPD function is implemented using fers at the I/O pins. a 2,048-bit EEPROM. This nonvolatile storage device A bidirectional data strobe (DQS) is transmitted contains 256 bytes. The first 128 bytes can be pro- externally, along with data, for use in data capture at grammed by Micron to identify the module type and the receiver. DQS is an intermittent strobe transmitted various SDRAM organizations and timing parameters. by the DDR SDRAM during READs and by the memory The remaining 128 bytes of storage are available for controller during WRITEs. DQS is edge-aligned with use by the customer. System READ/WRITE operations data for READs and center-aligned with data for between the master (system logic) and the slave 2 WRITEs. EEPROM device (DIMM) occur via a standard I C bus DDR SDRAM modules operate from differential using the DIMM’s SCL (clock) and SDA (data) signals, clock inputs (CK and CK#); the crossing of CK going together with SA (2:0), which provide eight unique HIGH and CK# going LOW will be referred to as the DIMM/EEPROM addresses. Write protect (WP) is tied positive edge of CK. Commands (address and control to ground on the module, permanently disabling hard- signals) are registered at every positive edge of CK. ware write protect. Input data is registered on both edges of DQS, and out- put data is referenced to both edges of DQS, as well as Mode Register Definition to both edges of CK. The mode register is used to define the specific Read and write accesses to DDR SDRAM modules mode of operation of the DDR SDRAM. This definition are burst oriented; accesses start at a selected location includes the selection of a burst length, a burst type, a and continue for a programmed number of locations CAS latency and an operating mode, as shown in in a programmed sequence. Accesses begin with the Figure 5, Mode Register Definition Diagram, on page 9. registration of an ACTIVE command, which is then fol- The mode register is programmed via the MODE REG- lowed by a READ or WRITE command. The address ISTER SET command (with BA0 = 0 and BA1 = 0) and bits registered coincident with the ACTIVE command will retain the stored information until it is pro- are used to select the device bank and row to be grammed again or the device loses power (except for accessed (BA0, BA1 select devices bank; A0–A11 select bit A8, which is self-clearing). device row for 256MB; A0–A12 select device row for Reprogramming the mode register will not alter the 512MB, 1GB; A0–A13 select device row for 2GB). The contents of the memory, provided it is performed cor- address bits registered coincident with the READ or rectly. The mode register must be loaded (reloaded) WRITE command are used to select the device bank when all device banks are idle and no bursts are in and the starting device column location for the burst progress, and the controller must wait the specified access. time before initiating the subsequent operation. Vio- DDR SDRAM modules provide for programmable lating either of these requirements will result in READ or WRITE burst lengths of 2, 4, or 8 locations. An unspecified operation. auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 8 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Mode register bits A0–A2 specify the burst length, Figure 5: Mode Register Definition A3 specifies the type of burst (sequential or inter- Diagram leaved), A4–A6 specify the CAS latency, and A7–A11 (256MB) or A7–A12 (512MB, 1GB), or A7–A13 (2GB) 256MB Module BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus specify the operating mode. Burst Type 13 12 11 10 9 8 7 65 4 3 2 1 0 Mode Register (Mx) Accesses within a given burst may be programmed 0* 0* Operating Mode CAS Latency BT Burst Length to be either sequential or interleaved; this is referred to * M13 and M12 (BA0 and BA1) must be “0, 0” to select the as the burst type and is selected via bit M3. base mode register (vs. the extended mode register). The ordering of accesses within a burst is deter- 512MB and 1GB Modules mined by the burst length, the burst type and the start- BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus ing column address, as shown in Table6, Burst Definition Table, on page 10. 14 13 12 11 10 9 8 7 65 4 3 2 1 0 Mode Register (Mx) 0* 0* Operating Mode CAS Latency BT Burst Length Burst Length * M14 and M13 (BA0 and BA1) must be “0, 0” to select the Read and write accesses to the DDR SDRAM are base mode register (vs. the extended mode register). burst oriented, with the burst length being program- 2GB Module mable, as shown in Figure 5, Mode Register Definition BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, 15 14 13 12 11 109782 654310 Mode Register (Mx) or 8 locations are available for both the sequential and 0* 0* Operating Mode CAS Latency BT Burst Length the interleaved burst types. * M15 and M14 (BA1 and BA0) Reserved states should not be used, as unknown must be “0, 0” to select the Burst Length base mode register (vs. the operation or incompatibility with future versions may M2 M1 M0 M3 = 0 extended mode register). result. 0 0 0 Reserved 0 0 1 2 When a READ or WRITE command is issued, a block 0 1 0 4 of columns equal to the burst length is effectively 0 1 1 8 selected. All accesses for that burst take place within 1 0 0 Reserved this block, meaning that the burst will wrap within the 1 0 1 Reserved block if a boundary is reached. The block is uniquely 1 1 0 Reserved 1 1 1 Reserved selected by A1–Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3- Burst Type M3 Ai when the burst length is set to eight (where Ai is the 0 Sequential most significant column address bit for a given config- 1 Interleaved uration; see Note 5, of Table 6, Burst Definition Table, on page 10). The remaining (least significant) address M6 M5 M4 CAS Latency Reserved 0 0 0 bit(s) is (are) used to select the starting location within Reserved 0 0 1 the block. The programmed burst length applies to 0 1 0 2 both READ and WRITE bursts. 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved Read Latency 2.5 1 1 0 The READ latency is the delay, in clock cycles, Reserved 1 1 1 between the registration of a READ command and the availability of the first bit of output data. The latency M13 M12 M11 M10 M9 M8 M7 M6-M0 Operating Mode can be set to 2 or 2.5 clocks, as shown in Figure 6, CAS 0 0 0 0 0 0 0 Valid Normal Operation Latency Diagram. 0 0 0 0 0 1 0 Valid Normal Operation/Reset DLL - - - - - - - - All other states reserved pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 9 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Figure 6: CAS Latency Diagram Table 6: Burst Definition Table T0 T1 T2 T2n T3 T3n ORDER OF ACCESSES WITHIN CK# A BURST CK STARTING BURST COLUMN TYPE = TYPE = COMMAND READ NOP NOP NOP LENGTH ADDRESS SEQUENTIAL INTERLEAVED CL = 2 A0 DQS 2 00-1 0-1 11-0 1-0 DQ A1 A0 T0 T1 T2 T2n T3 T3n 0 0 0-1-2-3 0-1-2-3 CK# 4 0 1 1-2-3-0 1-0-3-2 CK 1 0 2-3-0-1 2-3-0-1 COMMAND READ NOP NOP NOP 1 1 3-0-1-2 3-2-1-0 CL = 2.5 A2 A1 A0 DQS 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 DQ 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 Burst Length = 4 in the cases shown t t t Shown with nominal AC, DQSCK, and DQSQ 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 TRANSITIONING DATA DON’T CARE 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available NOTE: nominally coincident with clock edge n + m. Figure 7, 1. For a burst length of two, A1–Ai select the two-data- CAS Latency (CL) Table, indicates the operating fre- element block; A0 selects the first access within the quencies at which each CAS latency setting can be block. used. 2. For a burst length of four, A2–Ai select the four-data- element block; A0–A1 select the first access within the Reserved states should not be used as unknown block. operation or incompatibility with future versions may 3. For a burst length of eight, A3–Ai select the eight-data- result. element block; A0–A2 select the first access within the block. Operating Mode 4. Whenever a boundary of the block is reached within a The normal operating mode is selected by issuing a given sequence above, the following access wraps MODE REGISTER SET command with bits A7–A11 within the block. 5. i = 9 for 256MB, 512MB; (256MB), A7–A12 (512MB, 1GB), or A7–A13 (2GB) each i = 9, 11 for 1GB, 2GB. set to zero, and bits A0–A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9–A11 (256MB), A7 and A9–A12 (512MB, 1GB), or A7 and A9–A13 Table 7: CAS Latency (CL) Table (2GB)each set to zero, bit A8 set to one, and bits A0–A6 set to the desired values. Although not required by the ALLOWABLE OPERATING CLOCK FREQUENCY (MHZ) Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to SPEED CL = 2 CL = 2.5 reset the DLL, it should always be followed by a LOAD -335 75 ≤ f ≤ 133 75 ≤ f ≤ 167 MODE REGISTER command to select normal operat- -262 75 ≤ f ≤ 133 75 ≤ f ≤ 133 ing mode. -26A 75 ≤ f ≤ 133 75 ≤ f ≤ 133 All other combinations of values for A7–A11 -265 75 ≤ f ≤ 100 75 ≤ f ≤ 133 (256MB), A7–A12 (512MB, 1GB), or A7–A13 (2GB) are reserved for future use and/or test modes. Test modes pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 10 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM and reserved states should not be used because Figure 7: Extended Mode Register unknown operation or incompatibility with future ver- Definition Diagram sions may result. 256MB Module BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus Extended Mode Register The extended mode register controls functions beyond those controlled by the mode register; these 13 12 11 10 9 8 7 65 4 3 2 1 0 Extended Mode additional functions are DLL enable/disable and out- 1 1 0 1 Operating Mode DS DLL Register (Ex) put drive strength. These functions are controlled via 512MB and 1GB Modules the bits shown in Figure 7, Extended Mode Register BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus Definition Diagram. The extended mode register is programmed via the LOAD MODE REGISTER com- mand to the mode register (with BA0 = 1 and BA1 = 0) 14 13 12 11 10 9 8 7 65 4 3 2 1 0 Extended Mode and will retain the stored information until it is pro- 1 1 0 1 Operating Mode DS DLL Register (Ex) grammed again or the device loses power. The 2GB Module enabling of the DLL should always be followed by a BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus LOAD MODE REGISTER command to the mode regis- ter (BA0/BA1 both LOW) to reset the DLL. The extended mode register must be loaded when 15 14 13 12 11 109782 654310 Extended Mode 1 1 all device banks are idle and no bursts are in progress, Operating Mode 0 1 DS DLL Register (Ex) and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified oper- E0 DLL 0 Enable ation. 1 Disable DLL Enable/Disable Drive Strength E1 0 Normal The DLL must be enabled for normal operation. DLL enable is required during power-up initialization E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1, E0 Operating Mode and upon returning to normal operation after having 0 0 0 0 0 0 0 0 0 0 0 0 Valid Reserved disabled the DLL for the purpose of debug or evalua- – – – – – – – – – – – – – Reserved tion. (When the device exits self refresh mode, the DLL NOTE: is enabled automatically.) Any time the DLL is enabled, 1. BA1 and BA0 (E13 and E12 for 256MB, E14 and E13 for 200 clock cycles with CKE HIGH must occur before a 512MB, 1GB, or E15 and E14 for 2GB) must be “0, 1” to READ command can be issued. select the Extended Mode Register (vs. the base Mode Register). 2. QFC# is not supported. pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 11 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Commands Table 8, Commands Truth Table, and Table 9, DM of commands and operations, refer to the 128Mb, Operation Truth Table, provide a general reference of 256Mb, 512Mb, or 1Gb DDR SDRAM component data available commands. For a more detailed description sheets. Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES DESELECT (NOP) H XXX X 1 NO OPERATION (NOP) L HHH X 1 ACTIVE (Select bank and activate row) L L H H Bank/Row 2 READ (Select bank and column, and start READ burst) L H L H Bank/Col 3 L H L L Bank/Col 3 WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE LH HL X 4 PRECHARGE (Deactivate row in bank or banks) L L H L Code 5 AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LLL H X 6, 7 LOAD MODE REGISTER L L L L Op-Code 8 NOTE: 1. DESELECT and NOP are functionally interchangeable. 2. BA0–BA1 provide device bank address and A0–A11 (256MB), A0–A12 (512MB, 1GB), or A0–A13 (2GB) provide row address. 3. BA0–BA1 provide device bank address; A0–A9 (256MB, 512MB) or A0–A9, A11(1GB, 2GB), provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature. 4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0– BA1 are “Don’t Care.” 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11 (256MB), A0–A12 (512MB, 1GB), or A0–A13 (2GB) provide the op-code to be written to the selected mode register. Table 9: DM Operation Truth Table Used to mask write data; provided coincident with the corresponding data NAME (FUNCTION) DM DQS L Valid WRITE Enable WRITE Inhibit HX pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 12 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Absolute Maximum Ratings Stresses greater than those listed may cause perma- tional sections of this specification is not implied. nent damage to the device. This is a stress rating only, Exposure to absolute maximum rating conditions for and functional operation of the device at these or any extended periods may affect reliability. other conditions above those indicated in the opera- Voltage on VDD Supply Voltage on I/O Pins Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Relative to VSS . . . . . . . . . . . . -0.5V to VDDQ +0.5V Voltage on VDDQ Supply Operating Temperature Relative to VSS. . . . . . . . . . . . . . . . . . . . -1V to +3.6V T (ambient) . . . . . . . . . . . . . . . . . . . . .. 0°C to +70°C A Voltage on VREF and Inputs Storage Temperature (plastic) . . . . . . -55°C to +150°C Relative to VSS. . . . . . . . . . . . . . . . . . . . -1V to +3.6V Short Circuit Output Current. . . . . . . . . . . . . . . 50mA Table 10: DC Electrical Characteristics and Operating Conditions Notes: 1–5, 14, 48; notes appear on pages 20–23; 0°C ≤ T ≤ +70°C A PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES Supply Voltage VDD 2.3 2.7 V 32, 36 VDDQ 2.3 2.7 V 32, 36, 39 I/O Supply Voltage I/O Reference Voltage VREF 0.49 × VDDQ0.51 × VDDQ V6, 39 I/O Termination Voltage (system) VTT VREF - 0.04 VREF + 0.04 V 7, 39 Input High (Logic 1) Voltage VIH(DC)VREF + 0.15 VDD + 0.3 V 25 Input Low (Logic 0) Voltage VIL(DC)-0.3 VREF - 0.15 V 25 INPUT LEAKAGE CURRENT Command/ -32 32 Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ Address, RAS#, 1.35V (All other pins not under test = 0V) CAS#, WE# CKE, S# -16 16 II µA 47 CK0, CK0# -8 8 CK1, CK1# -12 12 CK2, CK2# DM -4 4 IOZ -10 10 µA 47 OUTPUT LEAKAGE CURRENT DQ, DQS (DQs are disabled; 0V ≤ VOUT ≤ VDDQ) OUTPUT LEVELS High Current (VOUT = VDDQ-0.373V, minimum VREF, minimum VTT) IOH -16.8 – mA 33, 34 Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) IOL 16.8 – mA Table 11: AC Input Operating Conditions Notes: 1–5, 14, 48, 49; notes appear on pages 20–23; 0°C ≤ T ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V A PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES VIH(AC)VREF + 0.310 – V 12, 25, 35 Input High (Logic 1) Voltage Input Low (Logic 0) Voltage VIL(AC)– VREF - 0.310 V 12, 25, 35 I/O Reference Voltage VREF(AC) 0.49 × VDDQ0.51 × VDDQ V6 pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 13 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Table 12: IDD Specifications and Conditions – 256MB DDR SDRAM components only Notes: 1–5, 8, 10, 14, 48; notes appear on pages 20–23; 0°C ≤ T ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V A MAX -26A/ PARAMETER/CONDITION SYM -335 -262 -265 UNITS NOTES a t t 1,024 904 864 mA 20, 42 IDD0 OPERATING CURRENT: One device bank; Active-Precharge; RC = RC t t (MIN); CK = CK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles a OPERATING CURRENT: One device bank; Active -Read Precharge; 1,104 984 984 mA 20, 42 IDD1 t t t t Burst = 2; RC = RC (MIN); CK = CK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle b PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks IDD2N 48 48 48 mA 21, 28, t t 44 idle; Power-down mode; CK = CK (MIN); CKE = (LOW) b t t 720 720 640 mA 45 IDD2F IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; CK = CK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM b ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; IDD3P 400 400 320 mA 21, 28, t t 44 Power-down mode; CK = CK (MIN); CKE = LOW b ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device IDD3N 800 800 720 mA 40 t t t t bank; Active-Precharge; RC = RAS (MAX); CK = CK (MIN); DQ, DM andDQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle a OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank 1,144 1,064 1,024 mA 20, 42 IDD4R t active; Address and control inputs chan-ging once per clock cycle; CK t = CK (MIN); IOUT = 0mA a OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One 1,144 1,024 1,024 mA 20 IDD4W device bank active; Address and control inputs changing once per t t clock cycle; CK = CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle b t t AUTO REFRESH CURRENT IDD5 4,240 3,520 3,520 mA 20, 24, REFC = RFC (MIN) 44 b t 80 80 80 mA IDD5A REFC = 15.625µs b SELF REFRESH CURRENT: CKE ≤ 0.2V 48 48 32 mA 9 IDD6 a OPERATING CURRENT: Four device bank interleaving READs (BL = 4) IDD7 2,864 2,664 2,624 mA 20, 43 t t t t with auto precharge, RC = RC (MIN); CK = CK (MIN); Address and control inputs change only during Active READ, or WRITE commands NOTE: a: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode. b: Value calculated reflects all module ranks in this operating condition. pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 14 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Table 13: IDD Specifications and Conditions – 512MB DDR SDRAM Components only Notes: 1–5, 8, 10, 14, 48; notes appear on pages 20–23; 0°C ≤ T ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V A MAX -26A/ PARAMETER/CONDITION SYM -335 -262 -265 UNITS NOTES a OPERATING CURRENT: One device bank; Active-Precharge; 1,032 1,032 992 mA 20, 42 IDD0 t t t t RC = RC (MIN); CK = CK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles a OPERATING CURRENT: One device bank; Active -Read IDD1 1,392 1,312 1,192 mA 20, 42 t t t t Precharge; Burst = 4; RC = RC (MIN); CK = CK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle b 64 64 64 mA 21, 28, PRECHARGE POWER-DOWN STANDBY CURRENT: All device IDD2P t t 44 banks idle; Power-down mode; CK = CK (MIN); CKE = (LOW) b IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; DD2F 800 720 720 mA 45 I t t CK = CK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM b ACTIVE POWER-DOWN STANDBY CURRENT: One device IDD3P 480 400 400 mA 21, 28, t t 44 bank active; Power-down mode; CK = CK (MIN); CKE = LOW b ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One 960 800 800 mA 40 IDD3N t t device bank; Active-Precharge; RC = RAS (MAX); t t CK = CK (MIN); DQ, DM andDQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle a OPERATING CURRENT: Burst = 2; Reads; Continuous burst; 1,432 1,232 1,232 mA 20, 42 IDD4R One bank active; Address and control inputs changing once t t per clock cycle; CK = CK (MIN); IOUT = 0mA a OPERATING CURRENT: Burst = 2; Writes; Continuous burst; IDD4W 1,432 1,232 1,232 mA 20 One device bank active; Address and control inputs t t changing once per clock cycle; CK = CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle b t t 4,080 3,760 3,760 mA 20, 44 AUTO REFRESH CURRENT IDD5 REFC = RFC (MIN) b t 96 96 96 mA 20, 44 IDD5A REFC = 7.8125µs b SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6 64 64 64 mA 9 a OPERATING CURRENT: Four device bank interleaving READs 3,312 2,832 2,832 mA 20, 43 IDD7 t t t t (BL = 4) with auto precharge, RC = RC (MIN); CK = CK (MIN); Address and control inputs change only during Active READ, or WRITE commands NOTE: a: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode. b: Value calculated reflects all module ranks in this operating condition. pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 15 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Table 14: IDD Specifications and Conditions – 1GB DDR SDRAM Components only Notes: 1–5, 8, 10, 14, 48; notes appear on pages 20–23; 0°C ≤ T ≤ +70°C; VDD = VDDQ = +2.5V ±0.2VV A MAX -26A/ PARAMETER/CONDITION SYM -335 -262 -265 UNITS NOTES a t 1,080 1,080 960 mA 20, 42 IDD0 OPERATING CURRENT: One device bank; Active-Precharge; RC = t t t RC (MIN); CK = CK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles a OPERATING CURRENT: One device bank; Active -Read Precharge; 1,320 1,320 1,200 mA 20, 42 IDD1 t t t t Burst = 4; RC = RC (MIN); CK = CK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle b PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks IDD2P 80 80 80 mA 21, 28, t t 44 idle; Power-down mode; CK = CK (MIN); CKE = (LOW) b t 720 720 640 mA 45 IDD2F IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; CK = t CK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM b 560 560 480 mA 21, 28, ACTIVE POWER-DOWN STANDBY CURRENT: One device bank IDD3P t t 44 active; Power-down mode; CK = CK (MIN); CKE = LOW b ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device 800 800 720 mA 40 IDD3N t t t t bank; Active-Precharge; RC = RAS (MAX); CK = CK (MIN); DQ, DM andDQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle a OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One IDD4R 1,360 1,360 1,200 mA 20, 42 bank active; Address and control inputs changing once per clock t t cycle; CK = CK (MIN); IOUT = 0mA a OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One 1,440 1,280 1,120 mA 20 IDD4W device bank active; Address and control inputs changing once per t t clock cycle; CK = CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle b t t AUTO REFRESH CURRENT IDD5 4,640 4,640 4,480 mA 20, 44 REFC = RFC (MIN) b t 160 160 160 mA 20, 44 IDD5A REFC = 7.8125µs b SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6 80 80 80 mA 9 a OPERATING CURRENT: Four device bank interleaving READs (BL = 4) IDD7 3,280 3,240 2,840 mA 20, 43 t t t t with auto precharge, RC = RC (MIN); CK = CK (MIN); Address and control inputs change only during Active READ, or WRITE commands NOTE: a: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode. b: Value calculated reflects all module ranks in this operating condition. pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 16 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Table 15: IDD Specifications and Conditions – 2GB DDR SDRAM Components only Notes: 1–5, 8, 10, 14, 48; notes appear on pages 20–23; 0°C ≤ T ≤ +70°C; VDD = VDDQ = +2.5V ±0.2VV A MAX -26A/ PARAMETER/CONDITION SYM -335 -262 -265 UNITS NOTES a t 1,080 1,080 1,240 mA 20, 42 IDD0 OPERATING CURRENT: One device bank; Active-Precharge; RC = t t t RC (MIN); CK = CK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles a OPERATING CURRENT: One device bank; Active -Read Precharge; 1,320 1,320 1,520 mA 20, 42 IDD1 t t t t Burst = 4; RC = RC (MIN); CK = CK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle b PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks IDD2P 80 80 160 mA 21, 28, t t 44 idle; Power-down mode; CK = CK (MIN); CKE = (LOW) b t 720 720 960 mA 45 IDD2F IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; CK = t CK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM b 560 560 480 mA 21, 28, ACTIVE POWER-DOWN STANDBY CURRENT: One device bank IDD3P t t 44 active; Power-down mode; CK = CK (MIN); CKE = LOW b ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device 720 720 720 mA 40 IDD3N t t t t bank; Active-Precharge; RC = RAS (MAX); CK = CK (MIN); DQ, DM andDQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle a OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One IDD4R 1,360 1,360 1,680 mA 20, 42 bank active; Address and control inputs changing once per clock t t cycle; CK = CK (MIN); IOUT = 0mA a OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One 1,280 1,280 1,760 mA 20 IDD4W device bank active; Address and control inputs changing once per t t clock cycle; CK = CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle b t t AUTO REFRESH CURRENT IDD5 4,640 4,640 5,280 mA 20, 44 REFC = RFC (MIN) b t 160 160 160 mA 20, 44 IDD5A REFC = 7.8125µs b SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6 80 80 144 mA 9 a OPERATING CURRENT: Four device bank interleaving READs (BL = 4) IDD7 3,280 3,240 3,960 mA 20, 43 t t t t with auto precharge, RC = RC (MIN); CK = CK (MIN); Address and control inputs change only during Active READ, or WRITE commands NOTE: a: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode. b: Value calculated reflects all module ranks in this operating condition. pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 17 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Table 16: Capacitance Note: 11; notes appear on pages 20–23 PARAMETER SYMBOL MIN MAX UNITS CIO 810 pF Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address CI1 32 48 pF Input Capacitance: S#, CKE CI1 16 24 pF Input Capacitance: CK0, CK0# CI2 11 15 pF CI3 12 18 pF Input Capacitance: CK1, CK1#; CK2, CK2# Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions Notes: 1–5, 13-15, 29, 48, 49; notes appear on pages 20–23; 0°C ≤ T ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V A AC CHARACTERISTICS -335 -262 -26A/-265 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES t Access window of DQs from CK/ -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns AC CK# t t 0.45 0.55 0.45 0.55 0.45 0.55 26 CK high-level width CH CK t t CK low-level width 0.45 0.55 0.45 0.55 0.45 0.55 26 CL CK t Clock cycle time CL = 2.5 6 13 7.5 13 7.513ns 41, 46 CK (2.5) t CL = 2 7.5 13 7.5/10 13 7.5/10 13 ns 41, 46 CK (2) t DQ and DM input hold time relative to DQS 0.45 0.5 0.5 ns 23, 27 DH t 0.45 0.5 0.5 ns 23, 27 DQ and DM input setup time relative to DQS DS t DQ and DM input pulse width (for each input) 1.75 1.75 1.75 ns 27 DIPW t Access window of DQS from CK/ -0.60 +0.60 -0.75 +0.75 -0.75 +0.75 ns DQSCK CK# t t 0.35 0.35 0.35 DQS input high pulse width DQSH CK t t DQS input low pulse width 0.35 0.35 0.35 DQSL CK t DQS-DQ skew, DQS to last DQ valid, per group, 0.45 0.5 0.5 ns 22, 23 DQSQ per access t t 0.75 1.25 0.75 1.25 0.75 1.25 Write command to first DQS latching transition DQSS CK t t DQS falling edge to CK rising - 0.2 0.2 0.2 DSS CK setup time t t DQS falling edge from CK rising - 0.2 0.2 0.2 DSH CK hold time t t t t t t t Half clock period ns 31 HP CH, CL CH, CL CH, CL t Data-out high-impedance window from CK/CK# +0.70 +0.75 +0.75 ns 16, 37 HZ t Data-out low-impedance window from CK/CK# -0.70 -0.75 -0.75 ns 16, 37 LZ t 0.75 0.90 .90 ns 12 Address and control input hold time (fast slew IH F rate) t Address and control input setup time (fast slew 0.75 0.90 .90 ns 12 IS F rate) t Address and control input hold time (slow slew 0.80 1 1 ns 12 IH S rate) pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 18 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–5, 13-15, 29, 48, 49; notes appear on pages 20–23; 0°C ≤ T ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V A AC CHARACTERISTICS -335 -262 -26A/-265 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES t Address and control input setup time (slow slew 0.80 1 1 ns 12 IS S rate) t 2.2 2.2 2.2 ns Address and Control input pulse width (for IPW each input) t LOAD MODE REGISTER command cycle time 12 15 15 ns MRD t t t t DQ-DQS hold, DQS to first DQ to go non-valid, ns 22, 23 QH HP - HP - HP - per access t t t QHS QHS QHS t Data hold skew factor 0.55 0.75 0.75 ns QHS t ACTIVE to PRECHARGE command 42 70,000 40 120,000 40 120,000 ns 31, 49 RAS ACTIVE to READ with Auto precharge 15 15 20 ns t RAP command t ACTIVE to ACTIVE/AUTO REFRESH command 60 60 65 ns RC period AUTO REFRESH command period 256MB, 75 75 75 ns 44 t 512MB, 1GB RFC 2GB 120 120 120 ns t 15 15 20 ns ACTIVE to READ or WRITE delay RCD t PRECHARGE command period 15 15 20 ns RP t t DQS read preamble 0.9 1.1 0.9 1.1 0.9 1.1 38 RPRE CK t t DQS read postamble 0.4 0.6 0.4 0.6 0.4 0.6 38 RPST CK t ACTIVE bank a to ACTIVE bank b command 12 15 15 ns RRD t t 0.25 0.25 0.25 DQS write preamble WPRE CK t DQS write preamble setup time 00 0 ns 18, 19 WPRES t t DQS write postamble 0.4 0.6 0.4 0.6 0.4 0.6 17 WPST CK t Write recovery time 15 15 15 ns WR t t Internal WRITE to READ command delay 11 1 WTR CK t t t t t t na ns 22 Data valid output window QH - DQSQ QH - DQSQ QH - DQSQ REFRESH to REFRESH command 256MB 140.6 140.6 140.6 µs 21 t interval 512MB, 1GB, REFC 70.3 70.3 70.3 µs 21 2GB Average periodic refresh interval 256MB 15.6 15.6 15.6 µs 21 t 7.8 7.8 7.8 µs 21 512MB, 1GB, REFI 2GB t Terminating voltage delay to VDD 00 0 ns VTD t Exit SELF REFRESH to non-READ command 75 75 75 ns XSNR t t 200 200 200 Exit SELF REFRESH to READ command XSRD CK pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 19 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Notes 1. All voltages referenced to VSS. 25°C, VOUT (DC) = VDDQ/2, VOUT (peak to peak) = 2. Tests for AC timing, IDD, and electrical AC and DC 0.2V. DM input is grouped with I/O pins, reflecting characteristics may be conducted at nominal ref- the fact that they are matched in loading. erence/supply voltage levels, but the related spec- 12. For slew rates less than 1 V/ns and greater than or ifications and device operation are guaranteed for equal to 0.5 V/ns. If slew rate is less than 0.5 V/ns, t the full voltage range specified. timing must be derated: IS has an additional 50ps 3. Outputs measured with equivalent load: per each 100mV/ns reduction in slew rate from t 500mV/ns, while IH is unaffected. If slew rate VTT exceeds 4.5V/ns, functionality is uncertain. 50Ω 13. The CK/CK# input reference level (for timing ref- erenced to CK/CK#) is the point at which CK and Reference Output Point CK# cross; the input reference level for signals (VOUT) 30pF other than CK/CK# is VREF. 14. Inputs are not recognized as valid until VREF stabi- lizes. Exception: during the period before VREF 4. AC timing and IDD tests may use a VIL-to-VIH stabilizes, CKE ≤ 0.3 x VDDQ is recognized as LOW. swing of up to 1.5V in the test environment, but 15. The output timing reference level, as measured at input timing is still referenced to VREF (or to the the timing reference point indicated in Note 3, is crossing point for CK/CK#), and parameter speci- VTT. fications are guaranteed for the specified AC input t t 16. HZ and LZ transitions occur in the same access levels under normal use conditions. The mini- time windows as valid data transitions. These mum slew rate for the input signals used to test parameters are not referenced to a specific voltage the device is 1V/ns in the range between VIL(AC) level, but specify when the device output is no and VIH(AC). longer driving (HZ) or begins driving (LZ). 5. The AC and DC input level specifications are as 17. The intent of the Don’t Care state after completion defined in the SSTL_2 Standard (i.e., the receiver of the postamble is the DQS-driven signal should will effectively switch as a result of the signal either be high, low, or high-Z and that any signal crossing the AC input level, and will remain in that transition within the input switching region must state as long as the signal does not ring back follow valid input requirements. That is, if DQS above [below] the DC input LOW [HIGH] level). transitions high [above VIHDC (MIN)] then it must 6. VREF is expected to equal VDDQ/2 of the transmit- not transition low (below VIHDC) prior to ting device and to track variations in the DC level t DQSH(MIN). of the same. Peak-to-peak noise (non-common 18. This is not a device limit. The device will operate mode) on VREF may not exceed ±2 percent of the with a negative value, but system performance DC value. Thus, from VDDQ/2, VREF is allowed could be degraded due to bus turnaround. ±25mV for DC error and an additional ±25mV for 19. It is recommended that DQS be valid (HIGH or AC noise. This measurement is to be taken at the LOW) on or before the WRITE command. The nearest VREF bypass capacitor. case shown (DQS going from High-Z to logic 7. VTT is not applied directly to the device. VTT is a LOW) applies when no WRITEs were previously in system supply for signal termination resistors, is progress on the bus. If a previous WRITE was in expected to be set equal to VREF and must track progress, DQS could be HIGH during this time, variations in the DC level of VREF. t depending on DQSS. 8. IDD is dependent on output loading and cycle t t 20. MIN ( RC or RFC) for IDD measurements is the rates. Specified values are obtained with mini- t smallest multiple of CK that meets the minimum mum cycle time at CL = 2 for -262, and -26A, CL = t absolute value for the respective parameter. RAS 2.5 for -335 and -265 with the outputs open. (MAX) for IDD measurements is the largest multi- 9. Enables on-chip refresh and address counters. t ple of CK that meets the maximum absolute 10. IDD specifications are tested after the device is t value for RAS. properly initialized, and is averaged at the defined 21. The refresh period 64ms. This equates to an aver- cycle rate. age refresh rate of 15.625µs (256MB) or 7.8125µs 11. This parameter is sampled. VDD = +2.5V ±0.2V, (512MB, 1GB, 2GB). However, an AUTO REFRESH VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, T = A command must be asserted at least once every pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 20 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM 140.6µs (256MB) or 70.3µs (512MB, 1GB, 2GB); b. Reach at least the target AC level. burst refreshing or posting by the DRAM control- c. After the AC target level is reached, continue to ler greater than eight refresh cycles is not allowed. maintain at least the target DC level, VIL (DC) 22. The valid data window is derived by achieving or VIH (DC). t t t t other specifications: HP ( CK/2), DQSQ, and QH 26. JEDEC specifies CK and CK# input slew rate must t t t ( QH = HP - QHS). The data valid window derates be ≥ 1V/ns (2V/ns differentially). directly porportional with the clock duty cycle 27. DQ and DM input slew rates must not deviate and a practical data valid window can be derived. from DQS by more than 10 percent. If the DQ/ The clock is allowed a maximum duty cycle varia- DM/DQS slew rate is less than 0.5V/ns, timing t tion of 45/55, beyond which functionality is must be derated: 50ps must be added to DS and t uncertain. Figure 8, Derating Data Valid Window DH for each 100mv/ns reduction in slew rate. If t t HP - QHS, shows derating curves for duty cycles slew rate exceeds 4V/ns, functionality is uncer- ranging between 50/50 and 45/55. tain. 23. Each byte lane has a corresponding DQS. 28. VDD must not vary more than 4 percent if CKE is 24. This limit is actually a nominal value and does not not active while any bank is active. result in a fail value. CKE is HIGH during 29. The clock is allowed up to ±150ps of jitter. Each t REFRESH command period (RFC [MIN]) else timing parameter is allowed to vary by the same CKE is LOW (i.e., during standby). amount. t t t 25. To maintain a valid level, the transitioning edge of 30. HP min is the lesser of CL minimum and CH the input must: minimum actually applied to the device CK and a. Sustain a constant slew rate from the current CK# inputs, collectively during bank active. AC level through to the target AC level, VIL (AC) or VIH (AC). Figure 8: Derating Data Valid Window t t HP - QHS 3.8 3.750 3.700 3.6 3.650 3.600 3.550 3.500 3.4 3.450 3.400 3.350 3.300 3.2 3.250 t -262/-26A/-265 @ CK = 10ns t -262/-26A/-265 @ CK = 7.5ns t NA -335 @ CK = 6ns 3.0 2.8 2.6 2.500 2.463 2.425 2.388 2.350 2.4 2.313 2.275 2.238 2.200 2.163 2.125 2.2 2.0 1.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55 Clock Duty Cycle pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 21 ©2004 Micron Technology, Inc. ns 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM 31. READs and WRITEs with auto precharge are not drain-to-source voltages from 0.1V to 1.0 Volt, t allowed to be issued until RAS (MIN) can be satis- and at the same voltage and temperature. fied prior to the internal precharge command f. The full variation in the ratio of the nominal being issued. pull-up to pull-down current should be unity 32. Any positive glitch in the nominal voltage must be ±10 percent, for device drain-to-source volt- less than 1/3 of the clock and not more than ages from 0.1V to 1.0V. +400mV or 2.9V, whichever is less. Any negative 34. The voltage levels used are derived from a mini- glitch must be less than 1/3 of the clock cycle and mum VDD level and the referenced test load. In not exceed either 300mV or 2.2V, whichever is practice, the voltage levels obtained from a prop- more positive. However, the DC average cannot be erly terminated bus will provide significantly dif- below 2.3V minimum. ferent voltage values. 33. Normal Output Drive Curves: 35. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a a. The full variation in driver pull-down current pulse width ≤ 3ns and the pulse width can not be from minimum to maximum process, temper- greater than 1/3 of the cycle rate. VIL undershoot: ature and voltage will lie within the outer VIL (MIN) = -1.5V for a pulse width ≤ 3ns and the bounding lines of the V-I curve of Figure 9, pulse width can not be greater than 1/3 of the Pull-Down Characteristics. cycle rate. b. The variation in driver pull-down current 36. VDD and VDDQ must track each other. t t within nominal limits of voltage and tempera- 37. HZ (MAX) takes precedence over DQSCK (MAX) t t ture is expected, but not guaranteed, to lie + RPST (MAX) condition. LZ (MIN) will prevail t t within the inner bounding lines of the V-I over DQSCK (MIN) + RPRE (MAX) condition. t t curve of Figure 9, Pull-Down Characteristics. 38. RPST end point and RPRE begin point are not c. The full variation in driver pull-up current referenced to a specific voltage level but specify from minimum to maximum process, temper- when the device output is no longer driving t t ature and voltage will lie within the outer ( RPST), or begins driving ( RPRE). bounding lines of the V-I curve of Figure 10, 39. During initialization, VDDQ, VTT, and VREF must Pull-Up Characteristics. be equal to or less than VDD + 0.3V. Alternatively, d. The variation in driver pull-up current within VTT may be 1.35V maximum during power up, nominal limits of voltage and temperature is even if VDD/VDDQ are 0V, provided a minimum of expected, but not guaranteed, to lie within the 42Ω of series resistance is used between the VTT inner bounding lines of the V-I curve of Figure supply and the input pin. 10, Pull-Up Characteristics. 40. For -335, -262, -26A and -265 speed grades, IDD3N e. The full variation in the ratio of the maximum is specified to be 35mA per DDR SDRAM at 100 to minimum pull-up and pull-down current MHz. should be between 0.71 and 1.4, for device Figure 9: Pull-Down Characteristics Figure 10: Pull-Up Characteristics pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 22 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM 41. The current Micron part operates below the slow- address and control inputs to remain stable. est JEDEC operating frequency of 83 MHz. As Although IDD2F, IDD2N, and IDD2Q are similar, such, future die may not reflect this option. IDD2F is “worst case.” 42. Random addressing changing and 50 percent of 46. Whenever the operating frequency is altered, not data changing at every transfer. including jitter, the DLL is required to be reset. 43. Random addressing changing and 100 percent of This is followed by 200 clock cycles. data changing at every transfer. 47. Leakage number reflects the worst case leakage 44. CKE must be active (high) during the entire time a possible through the module pin, not what each refresh command is executed. That is, from the memory device contributes. time the AUTO REFRESH command is registered, 48. When an input signal is HIGH or LOW, it is CKE must be active at each rising clock edge, until defined as a steady state logic HIGH or logic LOW. t t REF later. 49. The -335 speed grade will operate with RAS (MIN) t 45. IDD2N specifies the DQ, DQS, and DM to be = 40ns and RAS (MAX) = 120,000ns at any slower driven to a valid high or low logic level. IDD2Q is frequency. similar to IDD2F except IDD2Q specifies the pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 23 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Initialization Figure 11: Initialization Flow Diagram To ensure device operation the DRAM must be ini- Step tialized as described below: 1. Simultaneously apply power to VDD and VDDQ. 1 VDD and VDDQ Ramp 2. Apply VREF and then VTT power. 3. Assert and hold CKE at a LVCMOS logic low. 2 Apply VREF and VTT 4. Provide stable CLOCK signals. 5. Wait at least 200µs. 6. Bring CKE high and provide at least one NOP or 3 CKE must be LVCMOS Low DESELECT command. At this point the CKE input changes from a LVCMOS input to a SSTL2 input 4 Apply stable CLOCKs only and will remain a SSTL_2 input unless a power cycle occurs. 5 Wait at least 200us 7. Perform a PRECHARGE ALL command. t 8. Wait at least RP time, during this time NOPs or 6 Bring CKE High with a NOP command DESELECT commands must be given. 9. Using the LMR command program the Extended Mode Register (E0 = 0 to enable the DLL and E1 = 7 PRECHARGE ALL 0 for normal drive or E1 = 1 for reduced drive, E2 through En must be set to 0; where n = most sig- t 8 Assert NOP or DESELECT for RP time nificant bit). t 10. Wait at least MRD time, only NOPs or DESELECT 9 Configure Extended Mode Register commands are allowed. 11. Using the LMR command program the Mode Reg- t 10 Assert NOP or DESELECT for MRD time ister to set operating parameters and to reset the DLL. Note at least 200 clock cycles are required 11 between a DLL reset and any READ command. Configure Load Mode Register and reset DLL t 12. Wait at least MRD time, only NOPs or DESELECT commands are allowed. t 12 Assert NOP or DESELECT for MRD time 13. Issue a PRECHARGE ALL command. t 14. Wait at least RP time, only NOPs or DESELECT 13 PRECHARGE ALL commands are allowed. 15. Issue an AUTO REFRESH command (Note this t 14 Assert NOP or DESELECT for RP time may be moved prior to step 13). t 16. Wait at least RFC time, only NOPs or DESELECT 15 commands are allowed. Issue AUTO REFRESH command 17. Issue an AUTO REFRESH command (Note this may be moved prior to step 13). t 16 Assert NOP or DESELECT commands for RFC t 18. Wait at least RFC time, only NOPs or DESELECT commands are allowed. 17 Issue AUTO REFRESH command 19. Although not required by the Micron device, JEDEC requires a LMR command to clear the DLL t 18 Assert NOP or DESELECT for RFC time bit (set M8 = 0). If a LMR command is issued the same operating parameters should be utilized as 19 in step 11. Optional LMR command to clear DLL bit t 20. Wait at least MRD time, only NOPs or DESELECT commands are allowed. t 20 Assert NOP or DESELECT for MRD time 21. At this point the DRAM is ready for any valid com- mand. Note 200 clock cycles are required between 21 DRAM is ready for any valid command step 11 (DLL Reset) and any READ command. pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 24 ©2004 Micron Technology, Inc. 2.0 1.0 0.5 0.0 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Figure 12: Component Case Temperature vs. Air Flow 100 Ambient Temperature = 25º C 90 T - memory stress software max 80 70 T - memory stress software ave 60 50 T - 3D gaming software ave 40 30 Minimum Air Flow 20 Air Flow (meters/sec) NOTE: 1. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM) across the module. 2. The component case temperature measurements shown above were obtained experimentally. The typical system to be used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered memory modules. Case temperatures charted represent worst-case component locations on modules installed in the internal slots of the system. 3. Temperature versus air speed data is obtained by performing experiments with the system motherboard removed from its case and mounted in a Eiffel-type low air speed wind tunnel. Peripheral devices installed on the system motherboard for testing are the processor(s) and video card, all other peripheral devices are mounted outside of the wind tunnel test chamber. 4. The memory diagnostic software used for determining worst-case component temperatures is a memory diagnostic soft- ware application developed for internal use by Micron Technology, Inc. pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 25 ©2004 Micron Technology, Inc. Degrees Celsius 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM SPD Clock and Data Conventions SPD Acknowledge Data states on the SDA line can change only during Acknowledge is a software convention used to indi- SCL LOW. SDA state changes during SCL HIGH are cate successful data transfers. The transmitting device, reserved for indicating start and stop conditions (as either master or slave, will release the bus after trans- shown in Figure 13, Data Validity, and Figure 14, Defi- mitting eight bits. During the ninth clock cycle, the nition of Start and Stop). receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (as shown in Fig- ure 15, Acknowledge Response From Receiver). SPD Start Condition The SPD device will always respond with an All commands are preceded by the start condition, acknowledge after recognition of a start condition and which is a HIGH-to-LOW transition of SDA when SCL its slave address. If both the device and a WRITE oper- is HIGH. The SPD device continuously monitors the ation have been selected, the SPD device will respond SDA and SCL lines for the start condition and will not with an acknowledge after the receipt of each subse- respond to any command until this condition has been quent eight-bit word. In the read mode the SPD device met. will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowl- SPD Stop Condition edge is detected and no stop condition is generated by All communications are terminated by a stop condi- the master, the slave will continue to transmit data. If tion, which is a LOW-to-HIGH transition of SDA when an acknowledge is not detected, the slave will termi- SCL is HIGH. The stop condition is also used to place nate further data transmissions and await the stop the SPD device into standby power mode. condition to return to standby power mode. Figure 13: Data Validity Figure 14: Definition of Start and Stop SCL SCL SDA SDA DATA STABLE DATA DATA STABLE CHANGE START STOP BIT BIT Figure 15: Acknowledge Response From Receiver SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 26 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Table 18: EEPROM Device Select Code The most significant bit (b7) is sent first DEVICE TYPE IDENTIFIER CHIP ENABLE RW SELECT CODE b7 b6 b5 b4 b3 b2 b1 b0 Memory Area Select Code (two arrays) 1010 SA2 SA1 SA0 RW Protection Register Select Code 0110 SA2 SA1 SA0 RW Table 19: EEPROM Operating Modes MODE RW BIT WC BYTES INITIAL SEQUENCE Current Address Read 1VIH or VIL 1 START, Device Select, RW = ‘1’ Random Address Read 0VIH or VIL 1 START, Device Select, RW = ‘0’, Address 1VIH or VIL 1 reSTART, Device Select, RW = ‘1’ Sequential Read 1VIH or VIL ≥ 1 Similar to Current or Random Address Read Byte Write 0VIL 1 START, Device Select, RW = ‘0’ Page Write 0VIL ≤ 16 START, Device Select, RW = ‘0’ Figure 16: SPD EEPROM Timing Diagram t t t F HIGH R t LOW SCL t t t t t SU:STA HD:STA HD:DAT SU:DAT SU:STO SDA IN t t t AA DH BUF SDA OUT UNDEFINED pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 27 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Table 20: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SYMBOL MIN MAX UNITS SUPPLY VOLTAGE VDDSPD 2.3 3.6 V INPUT HIGH VOLTAGE: Logic 1; All inputs VIH VDD × 0.7 VDD + 0.5 V INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 VDD +0.3 V OUTPUT LOW VOLTAGE: IOUT = 3mA VOL –0.4 V ILI –10 µA INPUT LEAKAGE CURRENT: VIN = GND to VDD OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO –10 µA STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD ISB –30 µA POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz ICC –2 mA Table 21: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES t SCL LOW to SDA data-out valid AA 0.2 0.9 µs 1 t BUF 1.3 µs Time the bus must be free before a new transition can start t Data-out hold time DH 200 ns t SDA and SCL fall time F 300 ns 2 t Data-in hold time HD:DAT 0 µs t Start condition hold time HD:STA 0.6 µs t HIGH 0.6 µs Clock HIGH period t Noise suppression time constant at SCL, SDA inputs I50ns t Clock LOW period LOW 1.3 µs t SDA and SCL rise time R0.3µs2 f SCL clock frequency SCL 400 KHz t SU:DAT 100 ns Data-in setup time t Start condition setup time SU:STA 0.6 µs 3 t Stop condition setup time SU:STO 0.6 µs t WRITE cycle time WRC 10 ms 4 NOTE: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a reSTART condition, or following a WRITE cycle. t 4. The SPD EEPROM WRITE cycle time ( WRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 28 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Table 22: Serial Presence-Detect Matrix (256MB, 512MB, and 1GB) “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 31 BYTE DESCRIPTION ENTRY (VERSION) MT16VDDT3264A MT16VDDT6464A MT16VDDT12864A 0 128 80 80 80 Number of SPD Bytes Used by Micron 1 Total Number of Bytes in SPD Device 256 08 08 08 2 Fundamental Memory Type SDRAM DDR 07 07 07 3 Number of Row Addresses on 12, 13 0C 0D 0D Assembly 4 10, 11 0A 0A 0B Number of Column Addresses on Assembly 5 Number of Physical Ranks on DIMM 202 2 2 6 Module Data Width 64 40 40 40 7 Module Data Width (Continued) 000 00 00 8 Module Voltage Interface Levels SSTL 2.5V 04 04 04 t 9 6ns (-335) 60 60 60 SDRAM Cycle Time, CK, (CAS Latency 7ns (-262/-26A) 70 70 70 = 2.5) (See note 1) 7.5ns (-265) 75 75 75 t 10 0.7ns (-335) 70 70 70 SDRAM Access From Clock, AC 0.75ns (-262/-26A/-265) 75 75 75 (CAS Latency = 2.5) 11 Module Configuration Type None 00 00 00 12 Refresh Rate/Type 15.62µs, 7.8µs/SELF 80 82 82 13 808 08 08 SDRAM Device Width (Primary DDR SDRAM) 14 Error-Checking DDR SDRAM Data Width None 00 00 00 15 Minimum Clock Delay, Back-to-Back 1 clock 01 01 01 Random Column Access 16 Burst Lengths Supported 2, 4, 8 0E 0E 0E 17 Number of Banks on DDR SDRAM Device 404 04 04 18 2, 2.5 0C 0C 0C CAS Latencies Supported 19 CS Latency 001 01 01 20 WE Latency 102 02 02 21 SDRAM Module Attributes Unbuffered/Diff. 20 20 20 Clock 22 SDRAM Device Attributes: General Fast/Concurrent AP C0 C0 C0 t 23 7.5ns (-335/-262/-26A) 75 75 75 SDRAM Cycle Time, CK 10ns (-265 A0 A0 A0 (CAS Latency = 2) t 24 0.7ns (-335) 70 70 70 SDRAM Access From CK, AC 0.75ns (-262/-26A/-265) 75 75 75 (CAS Latency = 2) t 25 N/A 00 00 00 SDRAM Cycle Time, CK (CAS Latency = 1.5) t 26 N/A 00 00 00 SDRAM Access From CK, AC (CAS Latency = 1.5) t 27 18ns (-335) 48 48 48 Minimum Row Precharge Time, RP 15ns (-262) 3C 3C 3C (see note 4) 20ns (-26A/-265) 50 50 50 pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 29 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Table 22: Serial Presence-Detect Matrix (256MB, 512MB, and 1GB) (Continued) “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 31 BYTE DESCRIPTION ENTRY (VERSION) MT16VDDT3264A MT16VDDT6464A MT16VDDT12864A 28 12ns (-335) 30 30 30 Minimum Row Active to Row Active, t 15ns (-262/-26A/-265) 3C 3C 3C RRD t 29 18ns (-335) 48 48 48 Minimum Ras# to CAS# Delay, RCD 15ns (-262) 3C 3C 3C (see note 4) 20ns (-26A/-265) 50 50 50 t 30 42ns (-335) 2A 2A 2A Minimum RAS# Pulse Width, RAS, 45ns (-262/-26A/-265) 2D 2D 2D (see note 2) 31 Module Rank Density 128MB, 256MB, 20 40 80 512MB 32 Address and Command Setup Time, 0.8ns (-335) 80 80 80 t 1.0ns (-262-26A/-265) A0 A0 A0 IS, (see note 3) 33 0.8ns (-335) 80 80 80 Address and Command Hold Time, t 1.0ns (-262/-26A/-265) A0 A0 A0 IH, (see note 3) 34 Data/Data Mask Input Setup Time, 0.45ns (-335) 45 45 45 t 0.5ns (-262/-26A/-265) 50 50 50 DS 35 0.45ns (-335) 45 45 45 Data/Data Mask Input t 0.5ns (-262/-26A/-265) 50 50 50 Hold Time, DH 36-40 Reserved 00 00 00 t 41 60ns (-335/-262) 3C 3C 3C Min Active Auto Refresh Time, RC 65ns (-26A/-265) 41 41 41 42 72ns (-335) 48 48 48 Minimum Auto Refresh to Active/ t 75ns (-262/-26A/-265) 4B 4B 4B Auto Refresh Command Period, RFC 43 SDRAM Device Max Cycle Time, 12ns (-335) 30 30 30 t 13ns (-262/-26A/-265) 34 34 34 CKMAX 44 0.45ns (-335) 2D 2D 2D SDRAM Device Max DQS-DQ Skew t 0.5ns (-262/-26A/-265) 32 32 32 Time, DQSQ 45 SDRAM Device Max Read Data Hold 0.55ns (-335) 55 55 55 t 0.75ns (-262/-26A/-265) 75 75 75 Skew Factor, QHS 46-61 Reserved 00 00 00 47 DIMM Height Standard/Low-Profile 01/11 01/11 01/11 46-61 Reserved 00 00 00 62 Release 1.0 10 10 10 SPD Revision 63 Checksum For Bytes 0-62 -335 05/15 28/38 69/79 -262 98/A8 BB/CB FC/0C -26A C5/D5 E8/F8 29/39 -265 F5/05 18/28 59/69 64 Manufacturer’s JEDEC ID Code MICRON 2C 2C 2C 65-71 Manufacturer’s JEDEC ID Code (Continued) FF FF FF 72 Manufacturing Location 01–12 01–0C 01–0C 01–0C 73-90 Module Part Number (ASCII) Variable Data Variable Data Variable Data 91 Variable Data Variable Data Variable Data PCB Identification Code 92 Identification Code (Continued) 000 00 00 93 Year of Manufacture in BCD Variable Data Variable Data Variable Data pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 30 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Table 22: Serial Presence-Detect Matrix (256MB, 512MB, and 1GB) (Continued) “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 31 BYTE DESCRIPTION ENTRY (VERSION) MT16VDDT3264A MT16VDDT6464A MT16VDDT12864A 94 Variable Data Variable Data Variable Data Week of Manufacture in BCD 95-98 Module Serial Number Variable Data Variable Data Variable Data 99-127 Manufacturer-Specific Data (RSVD) –– – NOTE: t 1. Value for -26A CK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. value is 7.5ns. t t t 2. The value of RAS used for -26A/-265 modules is calculated from RC - RP. Actual device spec. value is 40 ns. 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini- mum slew rate is met. t t t 4. The value of RP, RCD and RAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR SDRAM device specification is 15ns. pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 31 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Table 23: Serial Presence-Detect Matrix (2GB) “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 31 BYTE DESCRIPTION ENTRY (VERSION) MT16VDDT25664A 0 128 80 Number of SPD Bytes Used by Micron 1 Total Number of Bytes in SPD Device 256 08 2 Fundamental Memory Type SDRAM DDR 07 3 Number of Row Addresses on Assembly 14 0E 4 11 0B Number of Column Addresses on Assembly 5 Number of Physical Ranks on DIMM 202 6 Module Data Width 64 40 7 Module Data Width (Continued) 000 8 Module Voltage Interface Levels SSTL 2.5V 04 t 9 6ns (-335) 60 SDRAM Cycle Time, CK, (CAS Latency = 2.5) (See note 7ns (-262/-26A) 70 1) 7.5ns (-265) 75 t 10 0.7ns (-335) 70 SDRAM Access From Clock, AC, (CAS Latency = 2.5) 0.75ns (-262/-26A/-265) 75 11 None 00 Module Configuration Type 12 Refresh Rate/Type 15.62µs, 7.8µs/SELF 82 13 SDRAM Device Width (Primary DDR SDRAM) 808 14 Error-Checking DDR SDRAM Data Width None 00 15 Minimum Clock Delay, Back-to-Back Random Column 1 clock 01 Access 16 2, 4, 8 0E Burst Lengths Supported 17 Number of Banks on DDR SDRAM Device 404 18 CAS Latencies Supported 2, 2.5 0C 19 CS Latency 001 20 WE Latency 102 21 Unbuffered/Diff. Clock 20 SDRAM Module Attributes 22 SDRAM Device Attributes: General Fast/Concurrent AP C0 t 23 SDRAM Cycle Time, CK, (CAS Latency = 2) 7.5ns (-335/-262/-26A) 75 10ns (-265) A0 t 24 SDRAM Access From CK, AC, (CAS Latency = 2) 0.7ns (-335) 70 0.75ns (-262/-26A/-265) 75 t 25 N/A 00 SDRAM Cycle Time, CK, (CAS Latency = 1.5) t 26 N/A 00 SDRAM Access From CK, AC, (CAS Latency = 1.5) t 27 18ns (-335) 48 Minimum Row Precharge Time, RP (see note 4) 15ns (-262) 3C 20ns (-26A/-265) 50 t 28 12ns (-335) 30 Minimum Row Active to Row Active, RRD 15ns (-262/-26A/-265) 3C t 29 18ns (-335) 48 Minimum Ras# to CAS# Delay, RCD (see note 4) 15ns (-262) 3C 20ns (-26A/-265) 50 t 30 42ns (-335) 2A Minimum RAS# Pulse Width, RAS, (see note 2) 45ns (-262/-26A/-265) 2D 31 Module Rank Density 1GB 01 t 32 0.8ns (-335) 80 Address and Command Setup Time, IS, (see note 3) 1.0ns (-262-26A/-265) A0 pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 32 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Table 23: Serial Presence-Detect Matrix (2GB) (Continued) “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 31 BYTE DESCRIPTION ENTRY (VERSION) MT16VDDT25664A 33 t 0.8ns (-335) 80 Address and Command Hold Time, IH, (See note 2) 1.0ns (-262/-26A/-265) A0 t 0.45ns (-335) 45 34 Data/Data Mask Input Setup Time, DS 0.5ns (-262/-26A/-265) 50 t 0.45ns (-335) 45 35 Data/Data Mask Input Hold Time, DH 0.5ns (-262/-26A/-265) 50 36-40 Reserved 00 t 41 60ns (-335/-262) 3C Min Active Auto Refresh Time RC 65ns (-26A/-265) 41 42 Minimum Auto Refresh to Active/ Auto Refresh 120ns (all speed grades) 78 t Command Period, RFC t 43 12ns (-335) 30 SDRAM Device Max Cycle Time CKMAX 13ns (-262/-26A/-265) 34 t 44 0.45ns (-335) 2D SDRAM Device Max DQS-DQ Skew Time DQSQ 0.5ns (-262/-26A/-265) 32 45 0.55ns (-335) 55 SDRAM Device Max Read Data Hold Skew Factor t 0.75ns (-262/-26A/-265) 75 QHS 46-61 Reserved 00 47 DIMM Height Standard/Low-Profile 01/11 46-61 Reserved 00 62 SPD Revision Release 1.0 10 63 Checksum For Bytes 0-62 -335 1B/2B -262 AB/BB -26A D8/E8 -265 1C/2C 64 Manufacturer’s JEDEC ID Code MICRON 2C 65-71 Manufacturer’s JEDEC ID Code (Continued) FF 72 Manufacturing Location 01–12 01–0C 73-90 Variable Data Module Part Number (ASCII) 91 PCB Identification Code Variable Data 92 Identification Code (Continued) 000 93 Year of Manufacture in BCD Variable Data 94 Week of Manufacture in BCD Variable Data 95-98 Variable Data Module Serial Number 99-127 Manufacturer-specific Data (RSVD) – NOTE: t 1. Value for -26A CK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. value is 7.5ns. t t t 2. The value of RAS used for -26A/-265 modules is calculated from RC - RP. Actual device spec. value is 40 ns. 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini- mum slew rate is met. t t t 4. The value of RP, RCD and RAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR SDRAM device specification is 15ns. pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 33 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Figure 17: 184-PIN DDR DIMM Dimensions – Standard PCB 0.157 (4.00) FRONT VIEW MAX 5.256 (133.50) 5.244 (133.20) 0.079 (2.00) R (4X) U1 U4 U6 U7 U8 U9 U2 U3 1.256 (31.9) 1.244 (31.6) 0.700 (17.78) 0.098 (2.50) D (2X) TYP. 0.091 (2.30) TYP. 0.035 (0.90) R 0.054 (1.37) 0.046 (1.17) PIN 1 PIN 92 0.250 (6.35) TYP. 0.091 (2.30) 0.050 (1.27) 0.040 (1.02) TYP. TYP. TYP. 4.750 (120.65) BACK VIEW U19 U16 U10 U11 U12 U13 U15 U17 U18 0.150 (3.80) PIN 93 PIN 184 0.150 (3.80) 0.394 (10.00) TYP. TYP. 1.95 (49.53) 2.55 (64.77) NOTE: MAX All dimensions are in inches (millimeters); or typical where noted. MIN pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 34 ©2004 Micron Technology, Inc. 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Figure 18: 184-PIN DDR DIMM Dimensions – Low-Profile PCB 5.256 (133.50) 5.244 (133.20) U10 .00) R (4X) U1 U2 U3 U4 U6 U7 U8 U9 1.156 (29.36) 1.144 (29.06) 0.700 (17.78) .50) D TYP. (2X) 0) TYP. 0.035 (0.90) R 0. 0. PIN 92 PIN 1 0.250 (6.35) TYP. 0.091 (2.30) 0.050 (1.27) 0.040 (1.02) TYP. TYP. TYP. 4.750 (120.65) TYP. BACK VIEW U19 U18 U17 U16 U14 U13 U12 U11 PIN 184 PIN 93 0.150 (3.80) 0.394 (10.00) TYP TYP NOTE: MAX All dimensions arein inches (millimeters); or typical where noted. MIN Data Sheet Designation Advance: This datasheet contains initial descrip- devices. Although considered final, these specifica- tions of products still under development. The tions are subject to change, as further product devel- Advance designation applies to MT16VDDT25664A opment and data characterization sometimes occur. only. The Released designation applies to MT16VDDT3264A, Released (No Mark): This data sheet contains mini- MT16VDDT6464A, and MT16VDDT12864A only. mum and maximum limits specified over the complete power supply and temperature range for production ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. All other trademarks are the property of their respective owners. pdf: 09005aef80739fa5, source: 09005aef807397e5 Micron Technology, Inc., reserves the right to change products or specifications without notice.. DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 35 ©2004 Micron Technology, Inc