128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM MT8LSDT1664A – 128MB SYNCHRONOUS MT16LSDT3264A – 256MB ® DRAM MODULE For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/modules Features Figure 1: 168-Pin DIMM (MO-161) • 168-pin, dual in-line memory module (DIMM) Standard 1.375in. (34.93mm) PC100- and PC133-compliant Utilizes 125 MHz and 133 MHz SDRAM components Unbuffered 128MB (16 Meg x 64) and 256MB (32 Meg x 64) Single +3.3V power supply Fully synchronous; all signals registered on positive edge of system clock Low Profile 1.125in. (28.58mm) Internal pipelined operat ion; column address can be changed every clock cycle Internal SDRAM banks for hiding row access/ precharge Programmable burst lengths: 1, 2, 4, 8, or full page Auto Precharge, includes CONCURRENT AUTO PRECHARGE and Auto Refresh Modes Self Refresh Mode: 64ms, 4,096-cycle refresh Marking (15.625µs refresh interval) Options LVTTL-compatible inputs and outputs Package Serial Presence-Detect (SPD) G 168-pin DIMM (standard) 1 Gold edge contacts Y 168-pin DIMM (lead-free) Frequency/CAS Latency 133 MHz/CL = 2 -13E Table 1: Timing Parameters 133 MHz/CL = 3 -133 CL = CAS (READ) latency 100 MHz/CL = 2 -10E ACCESS TIME PCB MODULE CLOCK SETUP HOLD Standard 1.375in. (34.93mm) MARKING FREQUENCY CL = 2 CL = 3 TIME TIME 1 Low-Profile 1.125in. (28.58mm) -13E 133 MHz 5.4ns – 1.5 0.8 -133 133 MHz – 5.4ns 1.5 0.8 NOTE: 1. Contact Micron for product availability. -10E 100 MHz 9ns 7.5ns 2ns 1ns Table 2: Address Table 128MB 256MB Refresh Count 4K 4K Device Banks 4 (BA0, BA1) 4 (BA0, BA1) 128Mb (16 Meg x 8) 128Mb (16 Meg x 8) Device Configuration Row Addressing 4K (A0–A11) 4K (A0–A11) Column Addressing 1K (A0–A9) 1K (A0–A9) Module Ranks 1 (S0#, S2#) 2 (S0#, S2#; S1#, S3#) 09005aef80bccbe7 SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 1 ©2003, 2004 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Table 3: Part Numbers PART NUMBER MODULE DENSITY CONFIGURATION SYSTEM BUS SPEED 128MB 16 Meg x 64 133 MHz MT8LSDT1664AG-13E_ MT8LSDT1664AY-13E_ 128MB 16 Meg x 64 133 MHz MT8LSDT1664AG-133_ 128MB 16 Meg x 64 133 MHz MT8LSDT1664AY-133_ 128MB 16 Meg x 64 133 MHz 128MB 16 Meg x 64 100 MHz MT8LSDT1664AG-10E_ 128MB 16 Meg x 64 100 MHz MT8LSDT1664AY-10E_ MT16LSDT3264AG-13E_ 256MB 32 Meg x 64 133 MHz MT16LSDT3264AY-13E_ 256MB 32 Meg x 64 133 MHz MT16LSDT3264AG-133_ 256MB 32 Meg x 64 133 MHz 256MB 32 Meg x 64 133 MHz MT16LSDT3264AY-133_ 256MB 32 Meg x 64 100 MHz MT16LSDT3264AG-10E_ MT16LSDT3264AY-10E_ 256MB 32 Meg x 64 100 MHz NOTE: The designators for component and PCB revision are the last two characters of each part number Consult factory for cur- rent revision codes. Example: MT16LSDT3264AG-133B1. 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 2 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Table 4: Pin Assignment Table 5: Pin Assignment (168-Pin DIMM Front) (168-Pin DIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1VSS 22 NC 43 VSS 64 VSS 85 VSS 106 NC 127 VSS 148 VSS 2 DQ0 23 VSS 44 NC 65 DQ21 86 DQ32 107 VSS 128CKE0149 DQ53 3 DQ1 24 NC 45 S2# 66 DQ22 87 DQ33 108 NC 129 S3# 150 DQ54 4 DQ2 25 NC 46 DQMB2 67 DQ23 88 DQ34 109 NC 130 DQMB6 151 DQ55 5 DQ3 26 VDD 47 DQMB3 68 VSS 89 DQ35 110 VDD 131 DQMB7 152 VSS 6VDD 27 WE# 48 NC 69 DQ24 90 VDD 111CAS#132 NC 153 DQ56 7 DQ4 28 DQMB0 49 VDD 70 DQ25 91 DQ36 112 DQMB4 133 VDD 154 DQ57 8 DQ5 29 DQMB1 50 NC 71 DQ26 92 DQ37 113 DQMB5 134 NC 155 DQ58 9 DQ6 30 S0# 51 NC 72 DQ27 93 DQ38 114 S1# 135 NC 156 DQ59 10 DQ7 31 NC 52 NC 73 VDD 94 DQ39 115RAS#136 NC 157 VDD 11 DQ8 32 VSS 53 NC 74 DQ28 95 DQ40 116 VSS 137 NC 158 DQ60 SS 33 A0 54 VSS 75 DQ29 SS 117 A1 138 VSS 159 DQ61 12 V 96 V 13 DQ9 34 A2 55 DQ16 76 DQ30 97 DQ41 118 A3 139 DQ48 160 DQ62 14 DQ10 35 A4 56 DQ17 77 DQ31 98 DQ42 119 A5 140 DQ49 161 DQ63 SS SS 15 DQ11 36 A6 57 DQ18 78 V 99 DQ43 120 A7 141 DQ50 162 V 16 DQ12 37 A8 58 DQ19 79 CK2 100 DQ44 121 A9 142 DQ51 163 CK3 17 DQ13 38 A10 59 VDD 80 NC 101 DQ45 122 BA0 143 VDD 164 NC DD 39 BA1 60 DQ20 81 WP DD 123 A11 144 DQ52 165 SA0 18 V 102 V 19 DQ14 40 VDD 61 NC 82 SDA 103 DQ46 124 VDD 145 NC 166 SA1 20 DQ15 41 VDD 62 NC 83 SCL 104 DQ47 125 CK1 146 NC 167 SA2 DD DD 21 NC 42 CKO 63 CKE1 84 V 105 NC 126 NC 147 NC 168 V Figure 2: 168-Pin DIMM Pin Locations Front View U10 U1 U2 U3 U4 U6 U7 U8 U9 PIN 41 PIN 1 PIN 84 Back View (Populated only for 256MB module) U11 U12 U13 U14 U16 U17 U18 U19 PIN 168 PIN 125 PIN 85 Indicates a VDD pin Indicates a VSS pin 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 3 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Figure 3: Functional Block Diagram – 128MB S0# DQMB0 DQMB4 DQM CS# DQM CS# DQ0 DQ DQ32 DQ DQ1 DQ DQ33 DQ U2 U1 DQ2 DQ DQ34 DQ DQ3 DQ DQ35 DQ DQ4 DQ DQ36 DQ DQ5 DQ DQ37 DQ DQ6 DQ DQ38 DQ DQ7 DQ DQ39 DQ DQMB1 DQMB5 DQM CS# DQM CS# DQ8 DQ DQ40 DQ DQ9 DQ U3 DQ41 DQ U4 DQ10 DQ DQ42 DQ DQ11 DQ DQ43 DQ DQ12 DQ DQ44 DQ DQ13 DQ DQ45 DQ DQ14 DQ DQ46 DQ DQ15 DQ DQ47 DQ S2# DQMB2 DQMB6 DQM CS# DQM CS# DQ16 DQ DQ48 DQ DQ17 DQ U7 DQ49 DQ U6 DQ18 DQ DQ50 DQ DQ19 DQ DQ51 DQ DQ20 DQ DQ52 DQ DQ21 DQ DQ53 DQ DQ22 DQ DQ54 DQ DQ23 DQ DQ55 DQ DQMB3 DQMB7 DQM CS# DQM CS# DQ24 DQ DQ56 DQ DQ25 DQ U9 DQ57 DQ U8 DQ26 DQ DQ58 DQ DQ27 DQ DQ59 DQ DQ28 DQ DQ60 DQ DQ29 DQ DQ61 DQ DQ30 DQ DQ62 DQ DQ31 DQ DQ63 DQ RAS# RAS#: SDRAMs U1 U6 CK1, U2 U7 CAS# CAS#: SDRAMs CK0 CK2 CK3 U3 U8 10pF CKE0 CKE0: SDRAMs U4 U9 3.3pF WE# WE#: SDRAMs A0-A11 A0-A11: SDRAMs SPD BA0 BA0: SDRAMs U10 VDD SCL SDRAMs SDA BA1: SDRAMs BA1 WP A0 A1 A2 VSS SDRAMs SA0 SA1 SA2 Standard modules use the following SDRAM devices: NOTE: MT48LC16M8A2TG 1. All resistor values are 10Ω unless otherwise specified. 2. Per industry standard, Micron modules utilize various component Lead-free modules use the following SDRAM devices: speed grades, as referenced in the module part numbering guide MT48LC16M8A2P at www.micron.com/numberguide. 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 4 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Figure 4: Functional Block Diagram – 256MB S0# S1# DQMB0 DQMB4 DQM CS# DQM CS# DQM CS# DQM CS# DQ0 DQ DQ DQ32 DQ DQ DQ1 DQ U1 DQ U19 DQ33 DQ U2 DQ U18 DQ2 DQ DQ DQ34 DQ DQ DQ3 DQ DQ DQ35 DQ DQ DQ4 DQ DQ DQ36 DQ DQ DQ5 DQ DQ DQ37 DQ DQ DQ6 DQ DQ DQ38 DQ DQ DQ7 DQ DQ DQ39 DQ DQ DQMB1 DQMB5 DQM CS# DQM CS# DQM CS# DQM CS# DQ8 DQ DQ DQ40 DQ DQ U3 U17 U4 U16 DQ9 DQ DQ DQ41 DQ DQ DQ10 DQ DQ DQ42 DQ DQ DQ11 DQ DQ DQ43 DQ DQ DQ12 DQ DQ DQ44 DQ DQ DQ13 DQ DQ DQ45 DQ DQ DQ14 DQ DQ DQ46 DQ DQ DQ15 DQ DQ DQ47 DQ DQ S2# S3# DQMB2 DQMB6 DQM CS# DQM CS# DQM CS# DQM CS# DQ16 DQ DQ DQ48 DQ DQ DQ17 DQ U7 DQ U13 DQ49 DQ U6 DQ U14 DQ18 DQ DQ DQ50 DQ DQ DQ19 DQ DQ DQ51 DQ DQ DQ20 DQ DQ DQ52 DQ DQ DQ21 DQ DQ DQ53 DQ DQ DQ22 DQ DQ DQ54 DQ DQ DQ23 DQ DQ DQ55 DQ DQ DQMB3 DQMB7 DQM CS# DQM CS# DQM CS# DQM CS# DQ24 DQ DQ DQ56 DQ DQ DQ25 DQ U9 DQ U11 DQ57 DQ U8 DQ U12 DQ26 DQ DQ DQ58 DQ DQ DQ27 DQ DQ DQ59 DQ DQ DQ28 DQ DQ DQ60 DQ DQ DQ29 DQ DQ DQ61 DQ DQ DQ30 DQ DQ DQ62 DQ DQ DQ31 DQ DQ DQ63 DQ DQ VDD 10K U1 U16 CKE1 CKE: SDRAMs U11-U14; U16-U19 U2 U17 CK0 CK1 CKE0 CKE: SDRAMs U1-U4; U6-U9 U3 U18 U4 U19 CAS# CAS#: SDRAMs U1-U4; U6-U9; U11-U14; U16-U19 U6 U11 RAS# RAS#: SDRAMs U1-U4; U6-U9; U11-U14; U16-U19 U7 U12 WE# WE#: SDRAMs U1-U4; U6-U9; U11-U14; U16-U19 CK2 CK3 U8 U13 A0-A11: SDRAMs U1-U4; U6-U9; U11-U14; U16-U19 A0-A11 U9 U14 3.3pF 3.3pF BA0 BA0: SDRAMs U1-U4; U6-U9; U11-U14; U16-U19 BA1 BA1: SDRAMs U1-U4; U6-U9; U11-U14; U16-U19 SPD VDD SDRAMs U1-U4; U6-U9; U11-U14; U16-U19 SCL U10 SDA WP A0 A1 A2 VSS SDRAMs U1-U4; U6-U9; U11-U14; U16-U19 SA0 SA1 SA2 Standard modules use the following SDRAM devices: NOTE: MT48LC16M8A2TG 1. All resistor values are 10Ω unless otherwise specified. 2. Per industry standard, Micron modules utilize various component Lead-free modules use the following SDRAM devices: speed grades, as referenced in the module part numbering guide MT48LC16M8A2P at www.micron.com/numberguide. 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 5 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Table 6: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL TYPE DESCRIPTION 27, 115, 111 RAS#, Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command CAS#, being entered. WE# 42, 79, 125, 163 CK0–CK3 Input Clock: CK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. CK also increments the internal burst counter and controls the output registers. 63, 128 CKE0, Input Clock Enable: CKE0 activate (HIGH) and deactivate (LOW) the CK signal. CKE1 Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all device banks idle), ACTIVE POWER-DOWN (row ACTIVE in any device bank) or CLOCK SUSPEND operation (burst access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CK, are disabled during power-down and self refresh modes, providing low standby power. 30, 45, 114, 129 S0#–S3# Input Chip Select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. 28–29, 46–47, 112– DQMB0– Input Input/Output Mask: DQMB is an input mask signal for write accesses and an 113, 130–131 DQMB7 output enable signal for read accesses. Input data is masked when DQMB is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when DQMB is sampled HIGH during a READ cycle. 39, 122 BA0, BA1 Input Bank Address: BA0 and BA1 define to which device bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. 33, 34, 35, 36, 37, A0–A11 Input Address Inputs: Provide the row address for ACTIVE commands, and the 38, 117, 118, 119, column address and auto precharge bit (A10) for READ/WRITE commands, to 120, 121, 123 select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to once device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. 83 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. 165–167 SA0–SA2 Input Presence-Detect Address Inputs: These pins are used to configure the presence- detect device. 2–5, 7–11, 13–17, DQ0– Input/ Data I/O: Data bus. 19–20, 55–58, 60, DQ63 Output 65–67, 69–72, 74– 77, 86–89, 91–95, 97–101, 103–104, 139–142, 144, 149–151, 153–156, 158–161 82 SDA Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer Output addresses and data into and data out of the presence-detect portion of the module. 6, 18, 26, 40, 41, VDD Supply Power Supply: +3.3V ±0.3V. 49, 59, 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 6 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Table 6: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL TYPE DESCRIPTION 1, 12, 23, 32, 43, VSS Supply Ground. 54, 64, 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 21, 22, 24, 25, 31, NC – Not Connected: These pins are not connected on this module. 44, 48, 50–53, 61, 62, 80, 81, 105, 106, 108, 109, 126, 132, 134–137, 145–147, 164 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 7 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM General Description The MT8LSDT1664A and MT16LSDT3264A are Serial Presence-Detect Operation high-speed CMOS, dynamic random-access, 128MB SDRAM modules incorporate serial presence-detect and 256MB memory modules organized in a x64 con- (SPD). The SPD function is implemented using a figuration. These modules use internally configured 2,048-bit EEPROM. This nonvolatile storage device quad-bank SDRAMs with a synchronous interface (all contains 256 bytes. The first 128 bytes can be pro- signals are registered on the positive edge of the clock grammed by Micron to identify the module type and signals CK). various SDRAM organizations and timing parameters. Read and write accesses to the SDRAM modules are The remaining 128 bytes of storage are available for burst oriented; accesses start at a selected location and use by the customer. System READ/WRITE operations continue for a programmed number of locations in a between the master (system logic) and the slave programmed sequence. Accesses begin with the regis- EEPROM device (DIMM) occur via a standard IIC bus tration of an ACTIVE command, which is then fol- using the DIMM’s SCL (clock) and SDA (data) signals, lowed by a READ or WRITE command. The address together with SA (2:0), which provide eight unique bits registered coincident with the ACTIVE command DIMM/EEPROM addresses. are used to select the device bank and row to be accessed (BA0, BA1 select the device bank, A0–A11 Initialization select the device row). The address bits registered SDRAMs must be powered up and initialized in a coincident with the READ or WRITE command are predefined manner. Operational procedures other used to select the starting column location for the than those specified may result in undefined opera- burst access. tion. Once power is applied to VDD and VDDQ (simulta- The modules provide for programmable READ or neously) and the clock is stable (stable clock is defined WRITE burst lengths of 1, 2, 4, or 8 locations, or the full as a signal cycling within timing constraints specified page, with a burst terminate option. An AUTO PRE- for the clock pin), the SDRAM requires a 100µs delay CHARGE function may be enabled to provide a self- prior to issuing any command other than a COM- timed row precharge that is initiated at the end of the MAND INHIBIT or NOP. Starting at some point during burst sequence. this 100µs period and continuing at least through the SDRAM modules use an internal pipelined architec- end of this period, Command Inhibit or NOP com- ture to achieve high-speed operation. This architec- mands should be applied. ture is compatible with the 2n rule of prefetch Once the 100µs delay has been satisfied with at least architectures, but it also allows the column address to one Command Inhibit or NOP command having been be changed on every clock cycle to achieve a high- applied, a PRECHARGE command should be applied. speed, fully random access. Precharging one device All device banks must then be precharged, thereby bank while accessing one of the other three device placing the device in the all banks idle state. banks will hide the precharge cycles and provide Once in the idle state, two AUTO refresh cycles must seamless, high-speed, random-access operation. be performed. After the AUTO refresh cycles are com- SDRAM modules are designed to operate in 3.3V, plete, the SDRAM is ready for mode register program- low-power memory systems. An auto refresh mode is ming. Because the mode register will power up in an provided, along with a power-saving, power-down unknown state, it should be loaded prior to applying mode. All inputs and outputs are LVTTL-compatible. any operational command. SDRAM modules offer substantial advances in DRAM operating performance, including the ability to Mode Register Definition synchronously burst data at a high data rate with auto- The mode register is used to define the specific matic column-address generation, the ability to inter- mode of operation of the SDRAM. This definition leave between internal banks in order to hide includes the selection of a burst length, a burst type, a precharge time and the capability to randomly change CAS latency, an operating mode and a write burst column addresses on each clock cycle during a burst mode, as shown in the Mode Register Definition Dia- access. For more information regarding SDRAM opera- gram. The mode register is programmed via the LOAD tion, refer to the 128Mb SDRAM component data MODE REGISTER command and will retain the stored sheets. information until it is programmed again or the device loses power. 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 8 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Mode register bits M0–M2 specify the burst length, The ordering of accesses within a burst is deter- M3 specifies the type of burst (sequential or inter- mined by the burst length, the burst type and the start- leaved), M4–M6 specify the CAS latency, M7 and M8 ing column address, as shown in Table 7. specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future Figure 5: Mode Register Definition use. Diagram The mode register must be loaded when all device banks are idle, and the controller must wait the speci- A11 A8 A6 A5 A4 A1 Address Bus A10 A9 A7 A3 A2 A0 fied time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. 11 10 9 8 7 65 4 3 2 1 0 Mode Register (Mx) Reserved* WB Op Mode CAS Latency BT Burst Length Burst Length *Should program Read and write accesses to the SDRAM are burst ori- M11, M10 = “0, 0” to ensure compatibility Burst Length ented, with the burst length being programmable, as with future devices. M2 M1 M0 M3 = 0 M3 = 1 shown in Mode Register Definition Diagram. The burst 0 0 0 1 1 length determines the maximum number of column 0 0 1 2 2 locations that can be accessed for a given READ or 0 1 0 4 4 WRITE command. Burst lengths of 1, 2, 4, or 8 loca- 0 1 1 8 8 1 0 0 Reserved Reserved tions are available for both the sequential and the 1 0 1 Reserved Reserved interleaved burst types, and a full-page burst is avail- 1 1 0 Reserved Reserved able for the sequential type. The full-page burst is used 1 1 1 Full Page Reserved in conjunction with the BURST TERMINATE com- mand to generate arbitrary burst lengths. Reserved states should not be used, as unknown M3 Burst Type operation or incompatibility with future versions may 0 Sequential 1 Interleaved result. When a READ or WRITE command is issued, a block M6 M5 M4 CAS Latency of columns equal to the burst length is effectively 0 0 0 Reserved selected. All accesses for that burst take place within 0 0 1 Reserved 2 this block, meaning that the burst will wrap within the 0 1 0 0 1 1 3 block if a boundary is reached, as shown in the Burst 1 0 0 Reserved Definition Table. The block is uniquely selected by A1– 1 0 1 Reserved A9 when the burst length is set to two; by A2–A9 when Reserved 1 1 0 the burst length is set to four; and by A3–A9 when the 1 1 1 Reserved burst length is set to eight. The remaining (least signif- icant) address bit(s) is (are) used to select the starting M8 M7 M6-M0 Operating Mode location within the block. Full-page bursts wrap within 0 0 Defined Standard Operation the page if the boundary is reached, as shown in the - - - All other states reserved Table 7. M9 Write Burst Mode Burst Type 0 Programmed Burst Length Accesses within a given burst may be programmed 1 Single Location Access to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 9 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Table 7: Burst Definition Figure 6: CAS Latency Diagram T0 T1 T2 T3 ORDER OF ACCESSES WITHIN CLK A BURST ADDRESS BURST STARTING TYPE = TYPE = COMMAND READ NOP NOP LENGTH COLUMN SEQUENTIAL INTERLEAVED t t LZ OH A0 DQ DOUT 2 00-1 0-1 t AC 11-0 1-0 CAS Latency = 2 A1 A0 0 0 0-1-2-3 0-1-2-3 T0 T1 T2 T3 T4 4 0 1 1-2-3-0 1-0-3-2 CLK 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 COMMAND READ NOP NOP NOP t A2 A1 A0 t LZ OH 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 DOUT DQ t AC 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 CAS Latency = 3 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 DON’T CARE 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 UNDEFINED 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Full Page n = A0–A9 Cn, Cn + 1, Not Supported CAS Latency (y) (location 0-y) Cn + 2, Cn + 3, The CAS latency is the delay, in clock cycles, Cn + 4... …Cn - 1, Cn… between the registration of a READ command and the availability of the first piece of output data. The latency NOTE: can be set to two or three clocks. 1. For full-page accesses: y = 1,024. If a READ command is registered at clock edge n, 2. For a burst length of two, A1–A9 select the block-of- and the latency is m clocks, the data will be available two burst; A0 selects the starting column within the by clock edge n + m. The DQs will start driving as a block. result of the clock edge one cycle earlier (n + m - 1), 3. For a burst length of four,A2–A9 select the block-of- and provided that the relevant access times are met, four burst; A0–A1 select the starting column within the the data will be valid by clock edge n + m. For example, block. assuming that the clock cycle time is such that all rele- 4. For a burst length of eight, A3–A9 select the block-of- vant access times are met, if a read command is regis- eight burst; A0–A2 select the starting column within tered at T0 and the latency is programmed to two the block. clocks, the DQs will start driving after T1 and the data 5. For a full-page burst, the full row is selected and A0–A9 select the starting column. will be valid by T2, as shown in the CAS Latency Dia- 6. Whenever a boundary of the block is reached within a gram. The CAS Latency Table indicates the operating given sequence above, the following access wraps frequencies at which each CAS latency setting can be within the block. used. 7. For a burst length of one, A0–A9 select the unique col- umn to be accessed, and mode register bit M3 is Operating Mode ignored. The normal operating mode is selected by setting Reserved states should not be used as unknown M7 and M8 to zero; the other combinations of values operation or incompatibility with future versions may for M7 and M8 are reserved for future use and/or test result. modes. The programmed burst length applies to both read and write bursts. 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 10 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Test modes and reserved states should not be used Table 8: CAS Latency Table because unknown operation or incompatibility with ALLOWABLE OPERATING future versions may result. CLOCK FREQUENCY (MHZ) Write Burst Mode SPEED CAS LATENCY = 2 CAS LATENCY = 3 When M9 = 0, the burst length programmed via M0- -13E ≤ 133 ≤ 143 M2 applies to both read and write bursts; when M9 = 1, -133 ≤ 100 ≤ 133 the programmed burst length applies to read bursts, -10E ≤ 100 ≤ 125 but write accesses are single-location (nonburst) accesses. 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 11 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Commands Table 9, SDRAM Commands and DQMB Operation each command. For a more detailed description of Truth Table provides a quick reference of available commands and operations refer to 128Mb component commands. This is followed by a written description of data sheets. Table 9: SDRAM Commands and DQMB Operation Truth Table CKE is HIGH for all commands shown except SELF REFRESH NAME (FUNCTION) CS# RAS# CAS# WE# DQMB ADDR DQ NOTES COMMAND INHIBIT (NOP) H XXX X X X NO OPERATION (NOP) L HHH X X X ACTIVE (Select bank and activate row) L L H H X Bank/Row X 1 READ (Select bank and column, and start READ burst) LHLH L/H8 Bank/Col X 2 WRITE (Select bank and column, and start WRITE burst) L H L L L/H8 Bank/Col Valid 2 BURST TERMINATE LH HL X X Active PRECHARGE (Deactivate row in bank or banks) LL H L X Code X 3 AUTO refresh or Self Refresh (Enter self refresh mode) LLL H X X X 4, 5 LOAD MODE REGISTER L LLL X Op-code X 6 Write Enable/Output Enable –––– L – Active 7 NOTE: 1. A0–A11provide device row address, and BA0, BA1 determine which device bank is made active. 2. A0–A9 provide device column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is being read from or written to. 3. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and BA0, BA1 are “Don’t Care.” 4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 6. A0–A11 define the op-code written to the mode register. 7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 12 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Absolute Maximum Ratings Stresses greater than those listed may cause perma- tional sections of this specification is not implied. nent damage to the device. This is a stress rating only, Exposure to absolute maximum rating conditions for and functional operation of the device at these or any extended periods may affect reliability. other conditions above those indicated in the opera- Voltage on VDD, VDDQ Supply Operating Temperature Relative to VSS. . . . . . . . . . . . . . . . . . . . . . . . . -1V to +4.6V T (Commercial - ambient) . . . . . .0°C to +65°C OPR Voltage on Inputs, NC or I/O Pins Storage Temperature (plastic) . . . . . . . . -55°C to +150°C Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . -1V to +4.6V Table 10: DC Electrical Characteristics and Operating Conditions – 128MB Notes: 1, 5, 6; notes appear on page 18; VDD, VDDQ = +3.3V ±0.3V PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES SUPPLY VOLTAGE VDD, VDDQ3 3.6 V INPUT HIGH VOLTAGE: Logic 1; All inputs VIH 2VDD + 0.3 V 22 INPUT LOW VOLTAGE: Logic 0; All inputs VIL -0.3 0.8 V 22 INPUT LEAKAGE CURRENT: Command and Any input 0V ≤ VIN ≤ VDD Address Inputs, CKE -40 40 µA (All other pins not under test = 0V) CK, S# -20 20 µA II 33 DQMB -5 5 µA OUTPUT LEAKAGE CURRENT: DQ pins are DQ IOZ -5 5 µA 33 disabled; 0V ≤ VOUT ≤ VDDQ OUTPUT LEVELS: VOH 2.4 – V Output High Voltage (IOUT = -4mA) VOL –0.4 V Output Low Voltage (IOUT = 4mA) Table 11: DC Electrical Characteristics and Operating Conditions – 256MB Notes: 1, 5, 6; notes appear on page 18; VDD, VDDQ = +3.3V ±0.3V PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES SUPPLY VOLTAGE VDD, VDDQ3 3.6 V INPUT HIGH VOLTAGE: Logic 1; All inputs VIH 2VDD + 0.3 V 22 IL -0.3 0.8 V 22 INPUT LOW VOLTAGE: Logic 0; All inputs V INPUT LEAKAGE CURRENT: Command and -80 80 µA Any input 0V ≤ VIN ≤ VDD Address Inputs, CKE II 33 (All other pins not under test = 0V) CK, S# -20 20 µA DQMB -10 10 µA IOZ -10 10 µA 33 OUTPUT LEAKAGE CURRENT: DQ pins are DQ disabled; 0V ≤ VOUT ≤ VDDQ OUTPUT LEVELS: VOH 2.4 – V Output High Voltage (IOUT = -4mA) VOL –0.4 V Output Low Voltage (IOUT = 4mA) 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 13 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Table 12: IDD Specifications and Conditions – 128MB Notes: 1, 5, 6, 11, 13; notes appear on page 18; VDD, VDDQ = +3.3V ±0.3V; SDRAM components only MAX PARAMETER/CONDITION SYMBOL -13E -133 -10E UNITS NOTES IDD1 1,280 1,200 1,120 mA 3, 18, 19, OPERATING CURRENT: Active Mode; t t 30 Burst = 2; READ or WRITE; RC = RC (MIN) STANDBY CURRENT: Power-Down Mode; IDD2 16 16 16 mA 30 All device device banks idle; CKE = LOW STANDBY CURRENT: Active Mode; IDD3 400 400 320 mA 3, 12, 19, t CKE = HIGH; CS# = HIGH; All device banks active after RCD met; 30 No accesses in progress OPERATING CURRENT: Burst Mode; IDD4 1,320 1,280 1,200 mA 3, 18, 19, Continuous burst; READ or WRITE; All device banks active 30 t t RFC = RFC (MIN) IDD5 2,640 2,480 2,160 mA 3, 12, 18, AUTO REFRESH CURRENT t CKE = HIGH; CS# = HIGH 19, 30, 31 RFC = 15.625µs IDD6 24 24 24 mA SELF REFRESH CURRENT: CKE £ 0.2V IDD7 16 16 16 mA 4 Table 13: IDD Specifications and Conditions – 256MB Notes: 1, 5, 6, 11, 13; notes appear on page 18; VDD, VDDQ = +3.3V ±0.3V; SDRAM components only MAX PARAMETER/CONDITION SYMBOL -13E -133 -10E UNITS NOTES a OPERATING CURRENT: Active Mode; IDD1 1,296 1,216 1,136 mA 3, 18, 19, t t Burst = 2; READ or WRITE; RC = RC (MIN) 30 b STANDBY CURRENT: Power-Down Mode; IDD2 32 32 32 mA 30 All device banks idle; CKE = LOW a STANDBY CURRENT: Active Mode; IDD3 416 416 336 mA 3, 12, 19, t CKE = HIGH; CS# = HIGH; All device banks active after RCD met; 30 No accesses in progress a IDD4 1,336 1,216 1,136 mA 3, 18, 19, OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All device banks active 30 t t b AUTO REFRESH CURRENT RFC = RFC (MIN) IDD5 5,280 4,960 4,320 mA 3, 12, 18, t b CS# = HIGH; CKE = HIGH 19, 30, 31 RFC = 15.625µs IDD6 48 48 48 mA b SELF REFRESH CURRENT: CKE ≤ 0.2V IDD7 32 32 32 mA 4 a - Value calculated as one module rank in this operating condition, and all otherranks in Power-Down Mode. b - Value calculated reflects all module ranks in this operating condition. 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 14 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Table 14: Capacitance – 128MB PARAMETER SYMBOL MIN MAX UNITS CI1 2030.4pF Input Capacitance: Command and Address Input Capacitance: CK CI2 13.3 17.3 pF Input Capacitance: S# CI3 1015.2pF Input Capacitance: CKE CI4 2030.4pF CI5 2.5 3.8 pF Input Capacitance: DQMB CIO 4 6 pF Input/Output Capacitance: DQ Table 15: Capacitance – 256MB PARAMETER SYMBOL MIN MAX UNITS Input Capacitance: Command and Address CI1 4060.8pF Input Capacitance: CK CI2 13.3 17.3 pF Input Capacitance: S# CI3 1015.2pF CI4 2030.4pF Input Capacitance: CKE CI5 5 7.6 pF Input Capacitance: DQMB Input/Output Capacitance: DQ CIO 8 12 pF 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 15 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Table 16: Electrical Characteristics and Recommended AC Operating Conditions Notes: 5–9, 11, 32; notes appear on page 18; module AC timing parameters comply with PC100 and PC133 design specs, based on component parameters AC CHARACTERISTICS -13E -133 -10E PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES t AC(3) 5.4 5.4 6 ns 27 Access time from CLK (pos. CL = 3 t edge) CL = 2 AC(2) 5.4 6 6 ns t Address hold time AH 0.8 0.8 1 ns t Address setup time AS 1.5 1.5 2 ns t CH 2.5 2.5 3 ns CLK high-level width t CL 2.5 2.5 3 ns CLK low-level width t Clock cycle time CL = 3 CK(3) 7 7.5 8 ns 23 t CL = 2 CK(2) 7.5 10 10 ns 23 t CKE hold time CKH 0.8 0.8 1 ns t CKS 1.5 1.5 2 ns CKE setup time t CMH 0.8 0.8 1 ns CS#, RAS#, CAS#, WE#, DQM hold time t CS#, RAS#, CAS#, WE#, DQM setup time CMS 1.5 1.5 2 ns t Data-in hold time DH 0.8 0.8 1 ns t Data-in setup time DS 1.5 1.5 2 ns t HZ(3) 5.4 5.4 6 ns 10 Data-out high-impedance time CL = 3 t HZ(2) 5.4 6 6 ns 10 CL = 2 t Data-out low-impedance time LZ111 ns t Data-out hold time (load) OH3 3 3 ns t Data-out hold time (no load) OHN1.8 1.8 1.8 ns28 t RAS 37 120,000 44 120,000 50 120,000 ns . ACTIVE to PRECHARGE command t RC 60 66 70 ns ACTIVE to ACTIVE command period t ACTIVE to READ or WRITE delay RCD152020 ns t Refresh period (8,192 rows) REF 646464ms t AUTO REFRESH period RFC666670 ns t RP 15 20 20 ns PRECHARGE command period t RRD141520 ns ACTIVE bank a to ACTIVE bank b command t Transition time T 0.3 1.2 0.3 1.2 0.3 1.2 ns 7 t Write recovery time WR 1 CLK 1 CLK 1 CLK ns 24 + 7ns + 7.5ns + 7ns 14 15 15 ns 25 Exit self refresh to ACTIVE command tXSR 67 75 80 ns 20 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 16 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Table 17: AC Functional Characteristics (Notes: 5, 6, 7, 8, 9, 11, 32; notes appear following parameter tables) PARAMETER SYMBOL -13E -133 -10E UNITS NOTES t t READ/WRITE command to READ/WRITE command CCD 1 1 1 CK 17 t t CKE to clock disable or power-down entry mode CKED 111 CK 14 t CKE to clock enable or power-down exit setup mode tPED 1 1 1 CK 14 t t DQM to input data delay DQD 000 CK 17 t t DQM 000 CK 17 DQM to data mask during WRITEs t t DQM to data high-impedance during READs DQZ 222 CK 17 t t WRITE command to input data delay DWD 000 CK 17 t t Data-in to ACTIVE command DAL 4 5 4 CK 15, 21 t t Data-in to precharge command DPL 222 CK 16, 21 t t BDL 111 CK 17 Last data-in to burst stop command t t Last data-in to new READ/WRITE command CDL 111 CK 17 t t Last data-in to precharge command RDL 222 CK 16, 21 t t LOAD MODE REGISTER command to ACTIVE or MRD 222 CK 26 REFRESH command t t Data-out to high-impedance from CL = 3 ROH(3) 333 CK 17 t t precharge command CL = 2 ROH(2) 222 CK 17 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 17 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Notes t 1. All voltages referenced to Vss. 16. Timing actually specified by WR. 2. This parameter is sampled. VDD, VDDQ = +3.3V; 17. Required clocks are specified by JEDEC function- f = 1 MHz, TA = 25°C; pin under test biased at 1.4V. ality and are not dependent on any timing param- 3. Idd is dependent on output loading and cycle eter. rates. Specified values are obtained with mini- 18. The IDD current will increase or decrease propor- mum cycle time and the outputs open. tionally according to the amount of frequency 4. Enables on-chip refresh and address counters. alteration for the test condition. 5. The minimum specifications are used only to 19. Address transitions average one transition every indicate cycle time at which proper operation two clocks. over the full temperature range is ensured (0°C ≤ 20. CLK must be toggled a minimum of two times T ≤ +70°C). during this period. A t t 6. An initial pause of 100µs is required after power- 21. Based on CK = 10ns for -10E, and CK = 7.5ns for - up, followed by two AUTO Refresh commands, 133 and -13E. before proper device operation is ensured. (VDD 22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse and VDDQ must be powered up simultaneously. width ≤ 3ns, and the pulse width cannot be Vss and VssQ must be at same potential.) The two greater than one third of the cycle rate. VIL under- AUTO Refresh command wake-ups should be shoot: VIL (MIN) = -2V for a pulse width ≤ 3ns. t repeated any time the REF refresh requirement is 23. The clock frequency must remain constant (stable exceeded. clock is defined as a signal cycling within timing t 7. AC characteristics assume T = 1ns. constraints specified for the clock pin) during 8. In addition to meeting the transition rate specifi- access or precharge states (READ, WRITE, includ- t cation, the clock and CKE must transit between ing WR, and PRECHARGE commands). CKE may VIH and VIL (or between VIL and VIH) in a mono- be used to reduce the data rate. tonic manner. 24. Auto precharge mode only. The precharge timing t 9. Outputs measured at 1.5V with equivalent load: budget ( RP) begins 7ns for -13E; 7.5ns for -133 and 7ns for -10E after the first clock delay, after Q the last WRITE is executed. May not exceed limit 50pF set for precharge mode. 25. Precharge mode only. t 10. HZ defines the time at which the output achieves 26. JEDEC and PC100 specify three clocks. the open circuit condition; it is not a reference to t 27. AC for -133/-13E at CL = 3 with no load is 4.6ns VOH or VOL. The last valid data element will meet and is guaranteed by design. t OH before going High-Z. 28. Parameter guaranteed by design. 11. AC timing and Idd tests have VIL = 0V and VIH = 3V, t 29. For -10E, CL= 2 and CK = 10ns; for -133, CL = 3 with timing referenced to 1.5V crossover point. If t t and CK = 7.5ns; for -13E, CL = 2 and CK = 7.5ns. the input transition time is longer than 1 ns, then 30. CKE is HIGH during refresh command period the timing is referenced at VIL (MAX) and VIH t RFC (MIN) else CKE is LOW. The Idd6 limit is (MIN) and no longer at the 1.5V crossover point. actually a nominal value and does not result in a 12. Other input signals are allowed to transition no fail value. more than once every two clocks and are other- t 31. The value of RAS used in -13E speed grade mod- wise at valid VIH or VIL levels. t t ule SPDs is calculated from RC - RP = 45ns. 13. IDD specifications are tested after the device is 32. Refer to device data sheet for timing waveforms. properly initialized. 33. Leakage number reflects the worst case leakage t 14. Timing actually specified by CKS; clock(s) speci- possible through the module pin, not what each fied as a reference only at minimum cycle rate. memory device contributes. t t 15. Timing actually specified by WR plus RP; clock(s) specified as a reference only at minimum cycle rate. 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 18 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM SPD Clock and Data Conventions SPD Acknowledge Data states on the SDA line can change only during Acknowledge is a software convention used to indi- SCL LOW. SDA state changes during SCL HIGH are cate successful data transfers. The transmitting device, reserved for indicating start and stop conditions (as either master or slave, will release the bus after trans- shown in Figure 7, Data Validity, and Figure 8, Defini- mitting eight bits. During the ninth clock cycle, the tion of Start and Stop). receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (as shown in Fig- ure 9, Acknowledge Response From Receiver). SPD Start Condition The SPD device will always respond with an All commands are preceded by the start condition, acknowledge after recognition of a start condition and which is a HIGH-to-LOW transition of SDA when SCL its slave address. If both the device and a WRITE oper- is HIGH. The SPD device continuously monitors the ation have been selected, the SPD device will respond SDA and SCL lines for the start condition and will not with an acknowledge after the receipt of each subse- respond to any command until this condition has been quent eight-bit word. In the read mode the SPD device met. will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowl- SPD Stop Condition edge is detected and no stop condition is generated by All communications are terminated by a stop condi- the master, the slave will continue to transmit data. If tion, which is a LOW-to-HIGH transition of SDA when an acknowledge is not detected, the slave will termi- SCL is HIGH. The stop condition is also used to place nate further data transmissions and await the stop the SPD device into standby power mode. condition to return to standby power mode. Figure 7: Data Validity Figure 8: Definition of Start and Stop SCL SCL SDA SDA DATA STABLE DATA DATA STABLE START STOP CHANGE BIT BIT Figure 9: Acknowledge Response From Receiver SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 19 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Table 18: EEPROM Device Select Code Most significant bit (b7) is sent first DEVICE TYPE IDENTIFIER CHIP ENABLE RW SELECT CODE b7 b6 b5 b4 b3 b2 b1 b0 Memory Area Select Code (two arrays) 1010 SA2 SA1 SA0 RW Protection Register Select Code 0110 SA2 SA1 SA0 RW Table 19: EEPROM Operating Modes MODE RW BIT WC BYTES INITIAL SEQUENCE Current Address Read 1VIH or VIL 1 START, Device Select, RW = “1” Random Address Read 0VIH or VIL 1 START, Device Select, RW = “0”, Address 1VIH or VIL 1 reSTART, Device Select, RW = “1” Sequential Read 1VIH or VIL ≥ 1 Similar to Current or Random Address Read Byte Write 0VIL 1 START, Device Select, RW = “0” Page Write 0VIL ≤ 16 START, Device Select, RW = “0” Figure 10: SPD EEPROM Timing Diagram t t t F HIGH R t LOW SCL t t t t t SU:STA HD:STA HD:DAT SU:DAT SU:STO SDA IN t t t AA DH BUF SDA OUT UNDEFINED 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 20 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Table 20: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SYMBOL MIN MAX UNITS SUPPLY VOLTAGE VDDSPD 2.3 3.6 V INPUT HIGH VOLTAGE: Logic 1; All inputs Vih VDDSPD × 0.7 VDDSPD + 0.5 V INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 VDDSPD × 0.3 V OUTPUT LOW VOLTAGE: IOUT = 3mA VOL –0.4 V IN = GND to VDD ILI –10 µA INPUT LEAKAGE CURRENT: V OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO –10 µA STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VDD or VSS ISB –30 µA POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz ICC –2 mA Table 21: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES t SCL LOW to SDA data-out valid AA 0.2 0.9 µs 1 t BUF 1.3 µs Time the bus must be free before a new transition can start t Data-out hold time DH 200 ns t SDA and SCL fall time F 300 ns 2 t Data-in hold time HD:DAT 0 µs t Start condition hold time HD:STA 0.6 µs t HIGH 0.6 µs Clock HIGH period t Noise suppression time constant at SCL, SDA inputs I50ns t Clock LOW period LOW 1.3 µs t SDA and SCL rise time R0.3µs2 f SCL clock frequency SCL 400 KHz t SU:DAT 100 ns Data-in setup time t Start condition setup time SU:STA 0.6 µs 3 t Stop condition setup time SU:STO 0.6 µs t WRITE cycle time WRC 10 ms 4 NOTE: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a reSTART condition, or following a WRITE cycle. t WRC) is the time from a valid stop condition of a write sequence to the end of 4. The SPD EEPROM WRITE cycle time ( the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 21 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Table 22: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” BYTE DESCRIPTION ENTRY(VERSION) MT8LSDT1664AG MT16LSDT3264AG 0 Number of Bytes Used by Micron 128 80 80 1 Total Number of SPD Memory Bytes 256 08 08 2 Memory Type SDRAM 04 04 3 Number of Row Addresses 12 0C 0C 4 10 0A 0A Number of Column Addresses 5 Number of Module Ranks 1 or 2 01 02 6 Module Data Width 64 40 40 7 Module Data Width (Continued) 000 00 8 Module Voltage Interface Levels LVTTL 01 01 t 9 7 (-13E) 70 70 SDRAM Cycle Time, CK, (CAS Latency = 3) 7.5 (-133) 75 75 8 (-10E) 80 80 t 10 5.4 (-13E/-133) 54 54 SDRAM Access From Clock, AC, (CAS Latency = 6 (-10E) 60 60 3) 11 Module Configuration Type NONPARITY 00 00 12 Refresh Rate/type 15.625µs/SELF 80 80 13 808 08 SDRAM Width (Primary SDRAM) 14 NONE 00 00 Error-Checking SDRAM Data Width t 15 101 01 Minimum Clock Delay, CCD 16 1, 2, 4, 8, PAGE 8F 8F Burst Lengths Supported 17 404 04 Number of Banks on SDRAM Device 18 CAS Latencies Supported 2, 3 06 06 19 CS Latency 001 01 20 WE Latency 001 01 21 UNBUFFERED 00 00 SDRAM Module Attributes 22 0E 0E 0E SDRAM Device Attributes: General t 23 7.5 (13E) 75 75 SDRAM Cycle Time, CK, (CAS Latency = 2) 10 (-133/-10E) A0 A0 t 24 54 (-13E) 54 54 SDRAM Access From Clock, AC, (CAS Latency = 6 (-133/-10E) 60 60 2) t 25 00 00 SDRAM Cycle Time, CK ,(CAS Latency = 1) t 26 00 00 SDRAM Access From Clock, AC, (CAS Latency = 1) t 27 15 (-13E) 0F 0F Minimum Row Precharge Time, RP 20 (-133/-10E) 14 14 t 28 14 (-13E) 0E 0E Minimum Row Active to Row Active, RRD 15 (-133) 0F 0F 20 (-10E) 14 14 29 t 15 (-13E) 0F 0F Minimum RAS# to CAS# Delay, RCD 20 (-133/-10E) 14 14 t 30 45 (-13E) 2D 2D Minimum RAS# Pulse Width, RAS (See note 1) 44 (-133) 2C 2C 50 (-10E) 32 32 31 Module Rank Density 128MB 20 20 t 32 1.5 (-13E/-133) 15 15 Command Address Setup, AS 2 (-10E) 20 20 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 22 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Table 22: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” BYTE DESCRIPTION ENTRY(VERSION) MT8LSDT1664AG MT16LSDT3264AG t 33 0.8 (-13E/-133) 08 08 Command Address Hold, AH 1 (-10E) 10 10 t 34 1.5 (-13E/-133) 15 15 Data Signal Input Setup, DS 2 (-10E) 20 20 t 35 0.8 (-13E/-133) 08 08 Data Signal Input Hold, DH 1 (-10E) 10 10 36–40 Reserved Bytes 00 00 t 41 Device Minimum Active/Auto-Refresh Time, RC 60ns (-13E) 3C 3C 66ns (-133) 42 42 70ns (-10E) 46 46 42–61 Reserved Bytes 00 00 62 SPD Revision REV.2.0 02 12 63 Checksum For Bytes 0-62 (-13E) 94 95 (-133) E0 E1 (-10E) 2C 2D 64 Manufacturer's JEDEC ID Code MICRON 2C 2C 65-71 FF FF Manufacturer's JEDEC Code (Cont.) 72 00–12 00–0C 00–0C Manufacturing Location 73–90 Module Part Number (ASCII) Variable Data Variable Data 91 PCB Identification Code Variable Data Variable Data 92 Identification Code (Continuted) 000 00 93 Variable Data Variable Data Year of Manufacture in BCD 94 Variable Data Variable Data Week of Manufacture in BCD 95–98 Module Serial Number Variable Data Variable Data 99–125 Manufacturer-Specific Data (RSVD) 126 System Frequency 100 MHz 64 64 (-13E/-133, -10E) 127 Year of Manufacture in BCD AF FF NOTE: t t t 1. The value of RAS used for the -13E module is calculated from RC - RP. Actual device spec. vaule is 37ns. 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 23 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Figure 11: 168-Pin DIMM Dimensions – 128MB STANDARD PCB FRONT VIEW 0.125 (3.18) 5.256 (133.50) MAX 5.244 (133.20) 0.079 (2.00) R (2X) U1 U2 U3 U4 U6 U7 U8 U9 1.380 (35.05) 1.370 (34.80) 0.118 (3.00) 0.700 (17.78) TYP (2X) U10 0.118 (3.00) TYP 0.054 (1.37) 0.250 (6.35) TYP 0.128 (3.25) 0.046 (1.17) (2X) 0.118 (3.00) 1.661 (42.18) 0.118 (3.00) 0.039 (1.00)R TYP 0.050 (1.27) 0.039 (1.00) 2.625 (66.68) (2X) TYP TYP PIN 84 (PIN 168 ON BACKSIDE) PIN 1 (PIN 85 ON BACKSIDE) 4.550 (115.57) LOW PROFILE PCB 0.125 (3.18) MAX FRONT VIEW 5.256 (133.50) 5.244 (133.20) 0.079 (2.00) R (2X) U10 U1 U2 U3 U4 U6 U7 U8 U9 1.131 (28.73) 1.119 (28.42) 0.118 (3.00) 0.700 (17.78) (2X) TYP 0.118 (3.00) TYP 0.250 (6.35) TYP 0.054 (1.37) 0.128 (3.25) (2X) 0.046 (1.17) 0.118 (3.00) 1.661 (42.18) 0.118 (3.00) 0.039 (1.00)R TYP 0.050 (1.27) 0.039 (1.00) 2.625 (66.68) (2X) TYP TYP PIN 84 (PIN 168 ON BACKSIDE) PIN 1 (PIN 85 ON BACKSIDE) 4.550 (115.57) NOTE: MAX All dimensions in inches (millimeters); or typical where noted. MIN 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 24 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Figure 12: 168-Pin DIMM Dimensions – 256MB STANDARD PCB 0.157 (3.99) 5.256 (133.50) MAX 5.244 (133.20) FRONT VIEW 0.079 (2.00) R U1 U2 U3 U4 U6 U7 U8 U9 1.380 (35.05) (2X) 1.370 (34.80) 0.700 (17.78) 0.118 (3.00) TYP U10 (2X) 0.118 (3.00) TYP 0.054 (1.37) 0.250 (6.35) TYP 0.128 (3.25) 0.046 (1.17) (2X) 0.118 (3.00) 1.661 (42.18) 0.118 (3.00) 0.039 (1.00)R TYP 0.050 (1.27) 0.039 (1.00) 2.625 (66.68) (2X) TYP TYP PIN 84 PIN 1 4.550 (115.57) BACK VIEW U11 U12 U13 U14 U16 U17 U18 U19 PIN 168 PIN 85 0.157 (3.99) MAX LOW PROFILE PCB 5.256 (133.50) 5.244 (133.20) FRONT VIEW 0.079 (2.00) R U10 (2X) U1 U2 U3 U4 U6 U7 U8 U9 1.131 (28.73) 1.119 (28.42) 0.700 (17.78) 0.118 (3.00) TYP (2X) 0.118 (3.00) TYP 0.250 (6.35) TYP 0.054 (1.37) 0.128 (3.25) (2X) 0.046 (1.17) 0.118 (3.00) 1.661 (42.18) 0.118 (3.00) 0.039 (1.00)R TYP 0.050 (1.27) 0.039 (1.00) 2.625 (66.68) (2X) TYP TYP PIN 84 PIN 1 4.550 (115.57) BACK VIEW U11 U12 U13 U14 U16 U17 U18 U19 PIN 168 PIN 85 NOTE: MAX All dimensions in inches (millimeters); or typical where noted. MIN 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 25 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Data Sheet Designation Released (No Mark): This data sheet contains mini- devices. Although considered final, these specifica- mum and maximum limits specified over the complete tions are subject to change, as further product devel- power supply and temperature range for production opment and data characterization sometimes occur. ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 09005aef80bccbe7 Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C16_32x64AG.fm - Rev. E 12/05 EN 26 ©2003, 2004 Micron Technology, Inc. All rights reserved.