FDC37C669 PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support FEATURES • 5 Volt Operation - Alternate IR Pins (Optional) • Intelligent Auto Power Management - 96 Base I/O Address and Eight IRQ Options • 16 Bit Address Qualification (Optional) • Multi-Mode Parallel Port with ChiProtect • 2.88MB Super I/O Floppy Disk Controller - Standard Mode - Licensed CMOS 765B Floppy Disk Controller - IBM PC/XT, PC/AT, and PS/2 Compatible - Software and Register Compatible with SMSC's Bidirectional Parallel Port Proprietary 82077AA Compatible Core - Enhanced Parallel Port (EPP) Compatible - Supports Two Floppy Drives Directly - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) - Supports Vertical Recording Format - Enhanced Capabilities Port (ECP) Compatible - 16 Byte Data FIFO (IEEE 1284 Compliant) - 100% IBM Compatibility - Incorporates ChiProtect Circuitry for Protection - Detects All Overrun and Underrun Conditions Against Damage Due to Printer Power-On - Sophisticated Power Control Circuitry (PCC) - 192 Base I/O Address, Seven IRQ and Three Including Multiple Powerdown Modes for DMA Options Reduced Power Consumption • ISA Host Interface - DMA Enable Logic • IDE Interface (Optional) - Data Rate and Drive Control Registers - On-Chip Decode and Select Logic Compatible - Swap Drives A and B with IBM PC/XT and PC/AT Embedded Hard - Non-Burst Mode DMA option Disk Drives - 48 Base I/O Address, Seven IRQ and Three - 48 Base I/O Address and Seven IRQ Options DMA Options • Game Port Select Logic • Floppy Disk Available on Parallel Port Pins - 48 Base I/O Addresses • Enhanced Digital Data Separator • General Purpose Address Decoder - 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps - 16 Byte Block decode Data Rates - 48 Base I/O Address Options - Programmable Precompensation Modes • 100 Pin QFP and TQFP Packages; Lead-Free RoHS • Serial Ports Compliant Packages also available - Two High Speed NS16C550 Compatible UARTs with Send/Receive 16 Byte FIFOs - Supports 230k and 460k Baud - Programmable Baud Rate Generator - Modem Control Circuitry - Infrared - IrDA (HPSIR) and Amplitude Shift Keyed IR (ASKIR) ORDER NUMBER(S) FDC37C669QFP for 100 pin, QFP Package FDC37C669-MS for 100 pin, QFP Lead-Free RoHS Compliant Package FDC37C669TQFP for 100 pin, TQFP Package FDC37C669-MT for 100 pin, TQFP Lead-Free RoHS Compliant Package TABLE OF CONTENTS FEATURES.................................................................................................................................................................. 1 GENERAL DESCRIPTION .......................................................................................................................................... 3 PIN CONFIGURATION................................................................................................................................................. 4 DESCRIPTION OF PIN FUNCTIONS........................................................................................................................... 6 FUNCTIONAL DESCRIPTION................................................................................................................................... 17 SUPER I/O REGISTERS .......................................................................................................................................17 HOST PROCESSOR INTERFACE ....................................................................................................................... 17 FLOPPY DISK CONTROLLER ............................................................................................................................. 18 FLOPPY DISK CONTROLLER INTERNAL REGISTERS ......................................................................................18 COMMAND SET/DESCRIPTIONS ............................................................................................................................ 41 INSTRUCTION SET.................................................................................................................................................... 45 PARALLEL PORT FLOPPY DISK CONTROLLER ......................................................................................................71 SERIAL PORT (UART) ............................................................................................................................................... 73 INFRARED INTERFACE .............................................................................................................................................87 PARALLEL PORT...................................................................................................................................................... 88 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES ........................................................................90 EXTENDED CAPABILITIES PARALLEL PORT.................................................................................................... 96 AUTO POWER MANAGEMENT................................................................................................................................108 INTEGRATED DRIVE ELECTRONICS INTERFACE .............................................................................................. 114 CONFIGURATION.................................................................................................................................................... 118 OPERATIONAL DESCRIPTION ............................................................................................................................... 136 MAXIMUM GUARANTEED RATINGS ................................................................................................................ 136 DC ELECTRICAL CHARACTERISTICS ............................................................................................................ 136 TIMING DIAGRAMS ................................................................................................................................................. 139 ECP PARALLEL PORT TIMING ..........................................................................................................................156 2 GENERAL DESCRIPTION The SMSC FDC37C669 PC 95 Compatible Super I/O formats (used by Sharp, Apple Newton, and other PDAs). Floppy Disk Controller with Infrared Support utilizes The parallel port, the IDE interface, and the game port SMSC's proven SuperCell technology for increased select logic are compatible with IBM PC/AT product reliability and functionality. The FDC37C669 is architectures. The FDC37C669 incorporates PC95 compliant and is optimized for motherboard sophisticated power control circuitry (PCC). The PCC applications. The FDC37C669 supports both 1 Mbps and supports multiple low power down modes. 2 Mbps data rates and vertical vertical recording operation at 1 Mbps Data Rate. The FDC37C669 Floppy Disk Controller incorporates Software Configurable Logic (SCL) for ease of use. Use The FDC37C669 incorporates SMSC's true CMOS of the SCL feature allows programmable system 765B floppy disk controller, advanced digital data configuration of key functions such as the FDC, parallel separator, 16 byte data FIFO, two 16C550 compatible port, and UARTs. The parallel port ChiProtect prevents UARTs, one Multi-Mode parallel port which includes damage caused by the printer being powered when the ChiProtect circuitry plus EPP and ECP support, IDE FDC37C669 is not powered. interface, on-chip 12 mA AT bus drivers, game port chip select and two floppy direct drive support. The true The FDC37C669 does not require any external filter CMOS 765B core provides 100% compatibility with IBM components, and is, therefore easy to use and offers PC/XT and PC/AT architectures in addition to providing lower system cost and reduced board area. The data overflow and underflow protection. The SMSC FDC37C669 is software and register compatible with advanced digital data separator incorporates SMSC's SMSC's proprietary 82077AA core. patented data separator technology, allowing for ease of testing and use. Both on-chip UARTs are compatible with the NS16C550. One UART includes additional support for a Serial Infrared Interface, complying with IrDA, HPSIR, and ASKIR 3 PIN CONFIGURATION 50 D2 81 nRTS1 49 D1 82 nCTS1 48 D0 83 nDTR1 47 VSS 84 nRI1 46 AEN 85 nDCD1 45 nIOW 86 nRI2 44 nIOR 87 nDCD2 43 A9 88 RXD2/IRRX 42 A8 FDC37C669 TXD2/IRTX 89 41 A7 nDSR2 90 IRQ_F 40 nRTS2 91 IRQ_E 39 nCTS2 92 100 PIN QFP 38 IRQ_D nDTR2 93 37 IRQ_C DRV2/ADRX/IRQ_B 94 36 nDACK_B 95 VSS 35 TC nDACK_C 96 A6 34 97 A10 A5 33 NC 98 A4 32 DRQ_C 99 31 A3 IOCHRDY 100 4 nDSR1 80 DRVDEN0 1 TXD1 79 nMTR0 2 RXD1 78 nDS1 3 nSTROBE 77 nDS0 4 nAUTOFD 76 nMTR1 5 nERROR 6 75 VSS nINIT 74 7 nDIR nSLCTIN 73 8 nSTEP VCC 72 9 nWDATA PD0 71 10 nWGATE PD1 70 11 nHDSEL PD2 12 69 nINDEX 68 PD3 13 nTRK0 VSS 67 14 nWRTPRT PD4 66 15 VCC PD5 65 16 nRDATA PD6 64 17 nDSKCHG PD7 18 63 DRVDEN1 62 nACK 19 IRQ_A 61 BUSY 20 CLK14 PE 60 21 DRQ_A SLCT 59 22 nDACK_A PWRGD/GAMECS 58 23 IRQIN RESET 57 24 nIDEEN/IRQ_H 56 D7 25 nHDCS0/IRRX2 55 D6 26 nHDCS1/IRTX2 54 D5 27 nCS D4 53 28 A0 DRQ_B 52 29 A1 D3 51 30 A2 75 nERROR DRVDEN0 1 74 nINIT nMTR0 2 73 nSLCTIN nDS1 3 72 VCC nDS0 4 71 PD0 nMTR1 5 70 PD1 VSS 6 69 PD2 nDIR 7 68 PD3 nSTEP 8 67 VSS nWDATA 9 66 PD4 nWGATE 10 65 PD5 nHDSEL 11 FDC37C669 64 PD6 nINDEX 12 63 PD7 nTRK0 13 62 nACK nWRTPRT 14 100 PIN TQFP 61 BUSY VCC 15 60 PE nRDATA 16 59 SLCT nDSKCHG 17 58 PWRGD/GAMECS DRVDEN1 18 57 RESET IRQ_A 19 56 D7 CLK14 20 55 D6 DRQ_A 21 54 D5 nDACK_A 22 53 D4 IRQIN 23 52 DRQ_B nIDEEN/IRQ_H 24 51 D3 nHDCS0/IRRX2 25 5 26 nHDCS1/IRTX2 100 IOCHRDY 27 nCS 99 DRQ_C 28 A0 98 NC 29 A1 97 A10 30 A2 96 nDACK_C 31 A3 95 VSS 32 A4 94 DRV2/ADRX/IRQ_B 33 A5 93 nDTR2 34 A6 92 nCTS2 35 TC 91 nRTS2 36 nDACK_B 90 nDSR2 37 IRQ_C 89 TXD2/IRTX 38 IRQ_D 88 RXD2/IRRX 39 IRQ_E 87 nDCD2 40 IRQ_F 86 nRI2 41 A7 85 nDCD1 42 A8 84 nRI1 43 A9 83 nDTR1 44 nIOR 82 nCTS1 45 nIOW 81 nRTS1 46 AEN 80 nDSR1 47 VSS 79 TXD1 48 D0 78 RXD1 49 D1 77 nSTROBE 50 D2 76 nAUTOFD DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP BUFFER PIN NO. TYPE NAME SYMBOL DESCRIPTION HOST PROCESSOR INTERFACE 48-51 Data Bus 0-7 D0-D7 I/O24 The data bus connection used by the host microprocessor to transmit data to and from 53-56 the chip. These pins are in a high-impedance state when not in the output mode. 44 nI/O Read nIOR I This active low signal is issued by the host microprocessor to indicate a read operation. 45 nI/O Write nIOW I This active low signal is issued by the host microprocessor to indicate a write operation. 46 Address Enable AEN I Active high Address Enable indicates DMA operations on the host data bus. Used internally to qualify appropriate address decodes. 28-34 I/O Address A0-A10 I These host address bits determine the I/O address to be accessed during nIOR and 41-43, nIOW cycles. These bits are latched internally 97 by the leading edge of nIOR and nIOW. All internal address decodes use the full A0 to A10 address bits. 21,52, DMA Request DRQ_A O24 This active high output is the DMA request for byte transfers of data between the host and 99 A, B, C DRQ_B the chip. This signal is cleared on the last DRQ_C byte of the data transfer by the nDACK signal going low (or by nIOR going low if nDACK was already low as in demand mode). 22,36, nDMA nDACK_A I An active low input acknowledging the request for a DMA transfer of data between the host 96 Acknowledge nDACK_B and the chip. This input enables the DMA A, B, C nDACK_C read or write internally. 35 Terminal Count TC I This signal indicates to the chip that DMA data transfer is complete. TC is only accepted when nDACK_x is low. In AT and PS/2 model 30 modes, TC is active high and in PS/2 mode, TC is active low. 6 DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP BUFFER PIN NO. TYPE NAME SYMBOL DESCRIPTION 19, Interrupt Request IRQ_A O24 The interrupt request from the logical device or IRQIN is output on one of the IRQA-G 37-40, A, C, D, IRQ_C signals. Refer to the configuration registers E, F, IRQ_D for more information. IRQ_E IRQ_F If EPP or ECP Mode is enabled, this output is pulsed low, then released to allow sharing of OD24 interrupts. 27 Chip Select Input nCS I When enabled, this active low pin serves as an input for an external decoder circuit which is used to qualify address lines above A10. 57 Reset RESET IS This active high signal resets the chip and must be valid for 500 ns minimum. The effect on the internal registers is described in the appropriate section. The configuration registers are not affected by this reset. FLOPPY DISK INTERFACE 16 nRead Disk Data nRDATA IS Raw serial bit stream from the disk drive, low active. Each falling edge represents a flux transition of the encoded data. 10 nWrite nWGATE This active low high current driver allows OD48 current to flow through the write head. It Gate becomes active just prior to writing to the diskette. 9 nWrite nWDATA OD48 This active low high current driver provides the encoded data to the disk drive. Each falling Data edge causes a flux transition on the media. 11 nHead nHDSEL OD48 This high current output selects the floppy disk side for reading or writing. A logic "1" on this Select pin means side 0 will be accessed, while a logic "0" means side 1 will be accessed. 7 Direction nDIR OD48 This high current low active output determines the direction of the head movement. A logic Control "1" on this pin means outward motion, while a logic "0" means inward motion. 7 DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP BUFFER PIN NO. TYPE NAME SYMBOL DESCRIPTION 8 nStep Pulse nSTEP OD48 This active low high current driver issues a low pulse for each track-to-track movement of the head. 17 Disk Change nDSKCHG IS This input senses that the drive door is open or that the diskette has possibly been changed since the last drive selection. This input is inverted and read via bit 7 of I/O address 3F7H. 4,3 nDrive Select O,1 nDS0,1 OD48 Active low open drain outputs select drives 0- 1. 2,5 nMotor On 0,1 nMTR0,1 OD48 These active low open drain outputs select motor drives 0-1. 1 DRVDEN0 DRVDEN0 Indicates the drive and media selected. Refer OD48 to configuration registers CR03, CR0B, CR1F. 14 nWrite nWRTPRT IS This active low Schmitt Trigger input senses from the disk drive that a disk is write Protected protected. Any write command is ignored. 13 wTrack 00 nTRK00 IS This active low Schmitt Trigger input senses from the disk drive that the head is positioned over the outermost track. 12 nIndex nINDEX IS This active low Schmitt Trigger input senses from the disk drive that the head is positioned over the beginning of a track, as marked by an index hole. 18 DRVDEN1 DRVDEN 1 OD48 Indicates the drive and media selected. Refer to configuration registers CR03, CR0B, CR1F. SERIAL PORT INTERFACE 88 Receive Data 2 RXD2/IRRX I Receiver serial data input for port 2. IR Receive Data 89 Transmit Data 2 TXD2/IRTX Transmit serial data output for port 2. IR O24 transmit data. 78 Receive Data 1 RXD1 I Reciever serial data input for port 1. 79 Transmit Data 1 TXD1 024 Transmit serial data output for port 1. 8 DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP BUFFER PIN NO. TYPE NAME SYMBOL DESCRIPTION 81,91 nRequest to nRTS1 O4 Active low Request to Send outputs for the Send Serial Port. Handshake output signal notifies modem that the UART is ready to transmit nRTS2 data. This signal can be programmed by writing to bit 1 of Modem Control Register (SYSOPT) (MCR). The hardware reset will reset the (System Option) nRTS signal to inactive mode (high). Forced inactive during loop mode operation. At the trailing edge of hardware reset, the nRTS2 input is latched to determine the configuration base address. 0 : INDEX Base I/O Address = 3F0 Hex 1 : INDEX Base I/O Address = 370 Hex 83,93 nData Terminal nDTR1 O4 Active low Data Terminal Ready outputs for Ready the serial port. Handshake output signal notifies modem that the UART is ready to nDTR2 establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will reset the nDTR signal to inactive mode (high). Forced inactive during loop mode operation. 82,92 nClear to Send nCTS1 I Active low Clear to Send inputs for the serial port. Handshake signal which notifies the UART that the modem is ready to receive nCTS2 data. The CPU can monitor the status of nCTS signal by reading bit 4 of Modem Status Register (MSR). A nCTS signal state change from low to high after the last MSR read will set MSR bit 0 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nCTS changes state. The nCTS signal has no effect on the transmitter. Note: Bit 4 of MSR is the complement of nCTS. 9 DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP BUFFER PIN NO. TYPE NAME SYMBOL DESCRIPTION 80,90 nData Set Ready nDSR1 I Active low Data Set Ready inputs for the serial port. Handshake signal which notifies the UART that the modem is ready to establish nDSR2 the communication link. The CPU can monitor the status of nDSR signal by reading bit 5 of Modem Status Register (MSR). A nDSR signal state change from low to high after the last MSR read will set MSR bit 1 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDSR changes state. Note: Bit 5 of MSR is the complement of nDSR. 85,87 nData Carrier nDCD1 I Active low Data Carrier Detect inputs for the Detect serial port. Handshake signal which notifies the UART that carrier signal is detected by the nDCD2 modem. The CPU can monitor the status of nDCD signal by reading bit 7 of Modem Status Register (MSR). A nDCD signal state change from low to high after the last MSR read will set MSR bit 3 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDCD changes state. Note: Bit 7 of MSR is the complement of nDCD. 84,86 nRing Indicator nRI1 I Active low Ring Indicator inputs for the serial port. Handshake signal which notifies the UART that the telephone ring signal is nRI2 detected by the modem. The CPU can monitor the status of nRI signal by reading bit 6 of Modem Status Register (MSR). A nRI signal state change from low to high after the last MSR read will set MSR bit 2 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nRI changes state. Note: Bit 6 of MSR is the complement of nRI. PARALLEL PORT INTERFACE 10 DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP BUFFER PIN NO. TYPE NAME SYMBOL DESCRIPTION 73 nPrinter Select nSLCTIN OD24 This active low output selects the printer. This Input is the complement of bit 3 of the Printer Control Register. Refer to Parallel Port description for use of this 0P24 pin in ECP and EPP mode. 74 nInitiate Output nINIT OD24 This output is bit 2 of the printer control register. This is used to initiate the printer when low. Refer to Parallel Port description for use of this 0P24 pin in ECP and EPP mode. 76 nAutofeed Output nAUTOFD OD24 This output goes low to cause the printer to automatically feed one line after each line is printed. The nAUTOFD output is the complement of bit 1 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. 0P24 77 nStrobe Output nSTROBE OD24 An active low pulse on this output is used to strobe the printer data into the printer. The nSTROBE output is the complement of bit 0 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. 0P24 61 Busy BUSY I This is a status output from the printer, a high indicating that the printer is not ready to receive new data. Bit 7 of the Printer Status Register is the complement of the BUSY input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. 62 nAcknowledge nACK I A low active output from the printer indicating that it has received the data and is ready to accept new data. Bit 6 of the Printer Status Register reads the nACK input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. 11 DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP BUFFER PIN NO. TYPE NAME SYMBOL DESCRIPTION 60 Paper End PE I Another status output from the printer, a high indicating that the printer is out of paper. Bit 5 of the Printer Status Register reads the PE input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. 59 Printer Selected SLCT I This high active output from the printer Status indicates that it has power on. Bit 4 of the Printer Status Register reads the SLCT input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. 75 nError nERROR I A low on this input from the printer indicates that there is a error condition at the printer. Bit 3 of the Printer Status register reads the nERR input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. 63-66 Port Data PD0-PD7 The bi-directional parallel data bus is used to I/O24 transfer information between CPU and 68-71 peripherals. 100 IOCHRDY IOCHRDY OD24P In EPP mode, this pin is pulled low to extend the read/write command. This pin has an internal pull-up. IDE/ALT IR PINS 24 nIDE Enable nIDEEN O24P This active low signal is active when the IDE is (Note 1) enabled and the I/O address is accessing an IDE register. Interrupt Request IRQ_H 024 The interrupt request from a logical device or H IRQIN may be output on the IRQH signal. Refer to the configuration registers for more information. OD24 If EPP or ECP Mode is enabled, this output is pulsed low, then released to allow sharing of interrupts. 12 25 nIDE Chip nHDCS0 O24P This is the Hard Disk Chip select Select 0 (Note 1) corresponding to the eight control block addresses. IRRX2 IRRX2 I Alternate IR Receive input 26 nIDE Chip nHDCS1 This is the Hard Disk Chip select O24P Select 1 (Note 1) corresponding to the alternate status register. Alternate IR transmit output IR Transmit 2 IRTX2 O24P MISCELLANEOUS 20 CLOCK 14 CLK14 ICLK The external connection to a single source 14.318 MHz clock. 13 DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP BUFFER PIN NO. TYPE NAME SYMBOL DESCRIPTION 94 Drive 2 DRV2 I In PS/2 mode, this input indicates whether a second drive is connected; DRV2 should be low if a second drive is connected. This status is reflected in a read of Status Register A. Active low address decode out: used to Address X nADRX OD24 decode a 1, 8, or 16 byte address block. (An external pull-up is required). Refer to Configuration registers CR03, CR08 and CR09 for more information. This pin has a 30ua internal pull-up. The interrupt request from a logical device or IRQIN may be output on IRQ_B. Refer to the configuration registers Interrupt Request IRQ_B for more information. 024 B (If EPP or ECP Mode is enabled, this output is pulsed low, then released to allow sharing of interrupts.) (OD24) 23 IRQIN I This pin is used to steer an interrupt signal from an external device onto one of eight IRQ outputs IRQA-H. 58 PWRGD I This active high input indicates that the power (V ) is valid. For device operation, PWRGD CC must be active. When PWRGD is inactive, all inputs to Mercury are disconnected and put into a low power mode; all outputs are put into high impedance. The contents of all registers are preserved as long as V has a valid CC value. The driver current drain in this mode drops to ISTBY - standby current. This input has an internal 30ua pull-up. This is the Game Port Chip Select output - nGAMECS O4 active low. It will go active when the I/O address, qualified by AEN, matches that selected in Configuration register CR1E. 98 I/O Power NC No Connect 15,72 Power V Positive Supply Voltage. CC 14 DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP BUFFER PIN NO. TYPE NAME SYMBOL DESCRIPTION 6,47, Ground GND Ground Supply. 67,95 Note 1: Refer to Configuration Register 00 for information on the pull-ups for these pins! Note IDE does not decode for 377, 3F7 Note RI and the Serial interrupt is always active if system power is applied to the chip. BUFFER TYPE DESCRIPTIONS BUFFER TYPE DESCRIPTION I/O24 Input/Output. 24 mA sink; 12 mA source O24 Output. 24 mA sink; 12 mA source OD48 Open drain. 48 mA sink O4 Output. 4 mA sink; 2 mA source OD24 Output. 24 mA sink OD24P Open drain. 24 mA sink; 30μA source OP24 Output. 24 mA sink; 4 mA source 024P Output. 24 mA sink; 12 mA source; with 30μA pull-up OCLK Output to external crystal ICLK Input to Crystal Oscillator Circuit (CMOS levels) I Input TTL compatible. IS Input with Schmitt Trigger. 15 PWRGD 5 V Vss (4) Vcc (2) POWER MANAGEMENT PD0-7 MULTI-MODE PARALLEL BUSY, SLCT, PE, PORT/FDC MUX nERROR, nACK DATA BUS nSTROBE, nSLCTIN, nINIT, nAUTOFD nCS GENERAL ADDRESS BUS PURPOSE ADRX nIOR ADDRESS DECODER nIOW CONFIGURATION TXD1, nCTS1, nRTS1 AEN 16C550 REGISTERS COMPATIBLE RXD1 SERIAL A0-A10 PORT 1 nDSR1, nDCD1, nRI, nDTR1 CONTROL BUS D0-D7 HOST DRQ_A-C CPU WDATA INTERFACE 16C550 TXD2(IRTX),nCTS2,nRTS2 nDACK_A-C COMPATIBLE WCLOCK SERIAL RXD2(IRRX) PORT 2 WITH INFRARED nDSR2,nDCD2,nRI2,nDTR2 TC SMSC DIGITAL DATA PROPRIETARY SEPARATOR 82077 COMPATIBLE IRQA WITH WRITE VERTICAL PRECOM- nIDEEN(IRQH) FLOPPYDISK PENSATION IRQ_C-F CONTROLLER IDE CORE nHDCSO(IRRX2) INTERFACE RCLOCK RESET nHDCS1(IRTX2) RDATA IRQIN CLOCK IOCHRDY GEN nINDEX nDIR nDS0,1,2 GAME PORT nTRK0 nSTEP nMTR0,1,2 DECODER 14.318 nWDATA nRDATA DRVDEN0 nDSKCHG CLOCK nWRPRT DRVDEN1 nWGATE nGAMECS DRV2(nADRX)(IRQB) FIGURE 1 - FDC37C669 BLOCK DIAGRAM 16 FUNCTIONAL DESCRIPTION SUPER I/O REGISTERS HOST PROCESSOR INTERFACE The address map, shown below in Table 1, shows the The host processor communicates with the FDC37C669 addresses of the different blocks of the Super I/O through a series of read/write registers. The port immediately after power up. The base addresses of the addresses for these registers are shown in Table 1. FDC, IDE, serial and parallel ports can be moved via the Register access is accomplished through programmed configuration registers. Some addresses are used to I/O or DMA transfers. All registers are 8 bits wide except access more than one register. the IDE data register at port 1F0H which is 16 bits wide. All host interface output buffers are capable of sinking a minimum of 12 mA. Table 1 - FDC37C669 Block Addresses ADDRESS BLOCK NAME NOTES 3F0, 3F1 or 370, 371 Configuration Write only; Note 1, 2 Base +0,1 Floppy Disk Read only; Disabled at power up; Note 2 Base +[2:5, 7] Floppy Disk Disabled at power up; Note 2 Base +[0:7] Serial Port Com 1 Disabled at power up; Note 2 Base +[0:7] Serial Port Com 2 Disabled at power up; Note 2 Base +[0:3] all modes Parallel Port Disabled at power up; Note 2 Base +[4:7] for EPP Base +[400:403] for ECP Base1 +[0:7] IDE Disabled at power up; Note 2 Base2 +[6] Note 1: Configuration registers can only be modified in configuration mode, refer to the configuration register description for more information. Access to status registers A and B of the floppy disk is disabled in configuration mode. Note 2: The base addresses must be set in the configuration registers before accessing the logical devices. 17 FLOPPY DISK CONTROLLER FLOPPY DISK CONTROLLER INTERNAL REGISTERS The Floppy Disk Controller (FDC) provides the interface The Floppy Disk Controller contains eight internal between a host microprocessor and the floppy disk registers which facilitate the interfacing between the host drives. The FDC integrates the functions of the microprocessor and the disk drive. Table 2 shows the Formatter/Controller, Digital Data Separator, Write addresses required to access these registers. Registers Precompensation and Data Rate Selection logic for an other than the ones shown are not supported. The rest of IBM XT/AT compatible FDC. The true CMOS 765B core the FDC description assumes the Base I/O Address is guarantees 100% IBM PC XT/AT compatibility in addition 3F0. to providing data overflow and underflow protection. The FDC37C669 is compatible to the 82077AA using SMSC's proprietary floppy disk controller core. Table 2 - Status, Data and Control Registers BASE I/O ADDRESS REGISTER +0 R Status Register A SRA +1 R Status Register B SRB +2 R/W Digital Output Register DOR +3 R/W Tape Drive Register TSR +4 R Main Status Register MSR +4 W Data Rate Select Register DSR +5 R/W Data (FIFO) FIFO +6 Reserved +7 R Digital Input Register DIR +7 W Configuration Control Register CCR For information on the floppy disk on Parallel Port pins, refer to Configuration Register CR4 and Parallel Port Floppy Disk Controller description. 18 STATUS REGISTER A (SRA) in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the Address 3F0 READ ONLY data bus pins D0 - D7 are held in a high impedance state This register is read-only and monitors the state of the for a read of address 3F0. FINTR pin and several disk interface pins, PS/2 Mode 7 6 5 4 3 2 1 0 INT nDRV2 STEP nTRK0 HDSEL nINDX nWP DIR PENDING RESET 0 N/A 0 N/A 0 N/A N/A 0 COND. BIT 0 DIRECTION BIT 4 nTRACK 0 Active high status indicating the direction of head Active low status of the TRK0 disk interface input. movement. A logic "1" indicating inward direction a logic BIT 5 STEP "0" outward. Active high status of the STEP output disk interface BIT 1 nWRITE PROTECT output pin. Active low status of the WRITE PROTECT disk interface input. A logic "0" indicating that the disk is write protected. BIT 6 nDRV2 Active low status of the DRV2 disk interface input pin, BIT 2 nINDEX indicating that a second drive has been installed. Active low status of the INDEX disk interface input. BIT 7 INTERRUPT PENDING BIT 3 HEAD SELECT Active high bit indicating the state of the Floppy Disk Active high status of the HDSEL disk interface input. A Interrupt output. logic "1" selects side 1 and a logic "0" selects side 0. 19 PS/2 Model 30 Mode 7 6 5 4 3 2 1 0 INT DRQ STEP TRK0 nHDSEL INDX WP nDIR PENDING F/F RESET 0 0 0 N/A 1 N/A N/A 1 COND. BIT 0 nDIRECTION BIT 4 TRACK 0 Active low status indicating the direction of head Active high status of the TRK0 disk interface input. movement. A logic "0" indicating inward direction a logic "1" outward. BIT 5 STEP Active high status of the latched STEP disk interface BIT 1 WRITE PROTECT output pin. This bit is latched with the STEP output going Active high status of the WRITE PROTECT disk interface active, and is cleared with a read from the DIR register, or input. A logic "1" indicating that the disk is write protected. with a hardware or software reset. BIT 2 INDEX BIT 6 DMA REQUEST Active high status of the INDEX disk interface input. Active high status of the DRQ output pin. BIT 3 nHEAD SELECT BIT 7 INTERRUPT PENDING Active low status of the HDSEL disk interface input. A Active high bit indicating the state of the Floppy Disk logic "0" selects side 1 and a logic "1" selects side 0. Interrupt output. 20 STATUS REGISTER B (SRB) 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - Address F1 READ ONLY D7 are held in a high impedance state for a read of This register is read-only and monitors the state of address 3F1. several disk interface pins, in PS/2 and Model PS/2 Mode 7 6 5 4 3 2 1 0 1 1 DRIVE WDATA RDATA WGATE MOT MOT SEL0 TOGGLE TOGGLE EN1 EN0 RESET 1 1 0 0 0 0 0 0 COND. BIT 0 MOTOR ENABLE 0 BIT 4 WRITE DATA TOGGLE Active high status of the MTR0 disk interface output pin. Every inactive edge of the WDATA input causes this bit to This bit is low after a hardware reset and unaffected by a change state. software reset. BIT 5 DRIVE SELECT 0 BIT 1 MOTOR ENABLE 1 Reflects the status of the Drive Select 0 bit of the DOR Active high status of the MTR1 disk interface output pin. (address 3F2 bit 0). This bit is cleared after a hardware This bit is low after a hardware reset and unaffected by a reset, it is unaffected by a software reset. software reset. BIT 6 RESERVED BIT 2 WRITE GATE Always read as a logic "1". Active high status of the WGATE disk interface output. BIT 7 RESERVED BIT 3 READ DATA TOGGLE Always read as a logic "1". Every inactive edge of the RDATA input causes this bit to change state. 21 PS/2 Model 30 Mode 7 6 5 4 3 2 1 0 nDRV2 nDS1 nDS0 WDATA RDATA WGATE nDS3 nDS2 F/F F/F F/F RESET N/A 1 1 0 0 0 1 1 COND. BIT 0 nDRIVE SELECT 2 BIT 4 WRITE DATA Active low status of the DS2 disk interface output. Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA BIT 1 nDRIVE SELECT 3 and is cleared by the read of the DIR register. This bit is Active low status of the DS3 disk interface output. not gated with WGATE. BIT 2 WRITE GATE BIT 5 nDRIVE SELECT 0 Active high status of the latched WGATE output signal. Active low status of the DS0 disk interface output. This bit is latched by the active going edge of WGATE BIT 6 nDRIVE SELECT 1 and is cleared by the read of the DIR register. Active low status of the DS1 disk interface output. BIT 3 READ DATA Active high status of the latched RDATA output signal. BIT 7 nDRV2 This bit is latched by the inactive going edge of RDATA Active low status of the DRV2 disk interface input. and is cleared by the read of the DIR register. 22 DIGITAL OUTPUT REGISTER (DOR) contains the enable for the DMA logic and contains a software reset bit. The contents of the DOR are Address 3F2 READ/WRITE unaffected by a software reset. The DOR can be written The DOR controls the drive select and motor enables of to at any time. the disk interface outputs. It also 7 6 5 4 3 2 1 0 MOT MOT MOT MOT DMAEN nRESET DRIVE DRIVE EN3 EN2 EN1 EN0 SEL1 SEL0 RESET 0 0 0 0 0 0 0 0 COND. BIT 0 and 1 DRIVE SELECT BIT 4 MOTOR ENABLE 0 These two bit a are binary encoded for the four drive This bit controls the MTR0 disk interface output. A logic selects DS0-DS3, thereby allowing only one drive to be "1" in this bit will cause the output pin to go active. selected at one time. BIT 5 MOTOR ENABLE 1 BIT 2 nRESET This bit controls the MTR1 disk interface output. A logic A logic "0" written to this bit resets the Floppy disk "1" in this bit will cause the output pin to go active. controller. This reset will remain active until a logic "1" is BIT 6 MOTOR ENABLE 2 written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits This bit controls the MTR2 disk interface output. A logic of the DOR register. The minimum reset duration "1" in this bit will cause the output pin to go active. required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of BIT 7 MOTOR ENABLE 3 issuing a software reset. This bit controls the MTR3 disk interface output. A logic "1" in this bit causes the output to go active. BIT 3 DMAEN PC/AT and Model 30 Mode: Table 3 - Drive Activation Values Writing this bit to logic "1" will enable the DRQ, nDACK, DRIVE DOR VALUE TC and FINTR outputs. This bit being a logic "0" will 0 1CH disable the nDACK and TC inputs, and hold the DRQ and 1 2DH FINTR outputs in a high impedance state. This bit is a logic "0" after a reset and in these modes. 2 4EH 3 8FH PS/2 Mode: In this mode the DRQ, nDACK, TC and FINTR pins are always enabled. During a reset, the DRQ, nDACK, TC, and FINTR pins will remain enabled, but this bit will be cleared to a logic "0". 23 TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE This register is included for 82077 software compatability. Table 4- Tape Select Bits The robust digital data separator used in the FDC37C669 does not require its characteristics modified DRIVE for tape support. The contents of this register are not TAPE SEL1 TAPE SEL2 SELECTED used internal to the device. The TDR is unaffected by a 0 0 None software reset. Bits 2-7 are tri-stated when read in this 0 1 1 mode. 1 0 2 1 1 3 Table 5 - Internal 4 Drive Decode - Normal DRIVE SELECT OUTPUTS MOTOR ON OUTPUTS (ACTIVE LOW) (ACTIVE LOW) DIGITAL OUTPUT REGISTER Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS3 nDS2 nDS1 nDS0 nMTR3 nMTR2 nMTR1 nMTR0 X X X 1 0 0 1 1 1 0 nBIT 7 nBIT 6 nBIT 5 nBIT 4 X X 1 X 0 1 1 1 0 1 nBIT 7 nBIT 6 nBIT 5 nBIT 4 X 1 X X 1 0 1 0 1 1 nBIT 7 nBIT 6 nBIT 5 nBIT 4 1 X X X 1 1 0 1 1 1 nBIT 7 nBIT 6 nBIT 5 nBIT 4 0 0 0 0 X X 1 1 1 1 nBIT 7 nBIT 6 nBIT 5 nBIT 4 Table 6 - Internal 4 Drive Decode - Drives 0 and 1 Swapped DRIVE SELECT OUTPUTS MOTOR ON OUTPUTS (ACTIVE LOW) (ACTIVE LOW) DIGITAL OUTPUT REGISTER Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS3 nDS2 nDS1 nDS0 nMTR3 nMTR2 nMTR1 nMTR0 X X X 1 0 0 1 1 0 1 nBIT 7 nBIT 6 nBIT 4 nBIT 5 X X 1 X 0 1 1 1 1 0 nBIT 7 nBIT 6 nBIT 4 nBIT 5 X 1 X X 1 0 1 0 1 1 nBIT 7 nBIT 6 nBIT 4 nBIT 5 1 X X X 1 1 0 1 1 1 nBIT 7 nBIT 6 nBIT 4 nBIT 5 0 0 0 0 X X 1 1 1 1 nBIT 7 nBIT 6 nBIT 4 nBIT 5 24 Table 7 - External 2 to 4 Drive Decode - Normal DRIVE SELECT OUTPUTS MOTOR ON OUTPUTS DIGITAL OUTPUT REGISTER (ACTIVE LOW) (ACTIVE LOW) Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0 X X X 1 0 0 0 0 1 0 X X 1 X 0 1 0 1 1 0 X 1 X X 1 0 1 0 1 0 1 X X X 1 1 1 1 1 0 X X X 0 0 0 0 0 1 1 X X 0 X 0 1 0 1 1 1 X 0 X X 1 0 1 0 1 1 0 X X X 1 1 1 1 1 1 Table 8 - External 2 to 4 Drive Decode - Drives 0 and 1 Swapped DRIVE SELECT OUTPUTS MOTOR ON OUTPUTS DIGITAL OUTPUT REGISTER (ACTIVE LOW) (ACTIVE LOW) Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0 X X X 1 0 0 0 1 1 0 X X 1 X 0 1 0 0 1 0 X 1 X X 1 0 1 0 1 0 1 X X X 1 1 1 1 1 0 X X X 0 0 0 0 1 1 1 X X 0 X 0 1 0 0 1 1 X 0 X X 1 0 1 0 1 1 0 X X X 1 1 1 1 1 1 25 Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are a high impedance. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 REG 3F3 Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state tape sel1 tape sel0 Enhanced Floppy Mode 2 (OS2) Register 3F3 for Enhanced Floppy Mode 2 operation. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 REG 3F3 Reserved Reserved Drive Type ID Floppy Boot Drive tape sel1 tape sel0 For this mode, DRATE0 and DRATE1 pins are inputs, Which two bits depends on the last drive selected in the and these inputs are gated into bits 6 and 7 of the 3F3 Digital Output Register (3F2). (See Table 11) register. These two bits are not affected by a hard or soft reset. BITS 3 and 2 Floppy Boot Drive - These bits reflect the value of configuration register 7 bits 1, 0. Bit 3 = CR7 Bit BIT 7 Reserved DB1. Bit 2 = CR7 Bit DB0. BIT 6 Reserved Bits 1 and 0 - Tape Drive Select (READ/WRITE). Same as in Normal and Enhanced Floppy Mode. 1. BITS 5 and 4 Drive Type ID - These Bits reflect two of the bits of configuration register 6. Table 9 - Drive Type ID Digital Output Register Register 3F3 - Drive Type ID Bit 1 Bit 0 Bit 5 Bit 4 0 0 CR6 - Bit 1 CR6 - Bit 0 0 1 CR6 - Bit 3 CR6 - Bit 2 1 0 CR6 - Bit 5 CR6 - Bit 4 1 1 CR6 - Bit 7 CR6 - Bit 6 26 DATA RATE SELECT REGISTER (DSR) Microchannel applications. Other applications can set the data rate in the DSR. The data rate of the floppy Address 3F4 WRITE ONLY controller is the most recent write of either the DSR or This register is write only. It is used to program the data CCR. The DSR is unaffected by a software reset. A rate, amount of write precompensation, power down hardware reset will set the DSR to 02H, which status, and software reset. The data rate is programmed corresponds to the default precompensation setting and using the Configuration Control Register (CCR) not the 250 kbps. DSR, for PC/AT and PS/2 Model 30 and 7 6 5 4 3 2 1 0 S/W POWER 0 PRE- PRE- PRE- DRATE DRATE RESET DOWN COMP2 COMP1 COMP0 SEL1 SEL0 RESET 0 0 0 0 0 0 1 0 COND. BIT 0 and 1 DATA RATE SELECT floppy controller clock and data separator circuits will be These bits control the data rate of the floppy controller. turned off. The controller will come out of manual low See Table 13 for the settings corresponding to the power mode after a software reset or access to the Data individual data rates. The data rate select bits are Register or Main Status Register. unaffected by a software reset, and are set to 250 kbps after a hardware reset. BIT 7 SOFTWARE RESET This active high bit has the same function as the DOR BIT 2 through 4 PRECOMPENSATION SELECT RESET (DOR bit 2) except that this bit is self clearing. These three bits select the value of write precompensation that will be applied to the WDATA Table 10 - Precompensation Delays output signal. Table 12 shows the precompensation PRECOMP values for the combination of these bits settings. Track 0 432 PRECOMPENSATION DELAY is the default starting track number to start 111 0.00 ns-DISABLED precompensation. this starting track number can be 001 41.67 ns changed by the configure command. 010 83.34 ns 011 125.00 ns BIT 5 UNDEFINED 100 166.67 ns Should be written as a logic "0". 101 208.33 ns 110 250.00 ns BIT 6 LOW POWER 000 Default (See Table 14) A logic "1" written to this bit will put the floppy controller into Manual Low Power mode. The 27 Table 11 - Data Rates DRIVE RATE DATA RATE DATA RATE DENSEL (1) DRATE (2) DRT1 DRT0 SEL1 SEL0 MFM FM IDENT=1 IDENT=0 1 2 0 0 1 1 1Meg --- 1 0 1 1 0 0 0 0 500 250 1 0 0 0 0 0 0 1 300 150 0 1 0 1 0 0 1 0 250 125 0 1 1 0 0 1 1 1 1Meg --- 1 0 1 1 0 1 0 0 500 250 1 0 0 0 0 1 0 1 500 250 0 1 0 1 0 1 1 0 250 125 0 1 1 0 1 0 1 1 1Meg --- 1 0 1 1 1 0 0 0 500 250 1 0 0 0 1 0 0 1 2Meg --- 0 1 0 1 1 0 1 0 250 125 0 1 1 0 Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format 01 = 3-Mode Drive 10 = 2 Meg Tape Note 1: This is for DENSEL in normal mode. Note 2: This is for DRATE0, DRATE1 when Drive Opt are 00. Table 12 - Default Precompensation Delays PRECOMPENSATION DELAYS DATA RATE 2 Mbps 125 ns 1 Mbps 41.67 ns 500 Kbps 125 ns 300 Kbps 125 ns 250 Kbps 125 ns *The 2 Mbps data rate is only available if V = 5V. CC 28 MAIN STATUS REGISTER time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It should be read Address 3F4 READ ONLY before each byte transferring to or from the data register The Main Status Register is a read-only register and except in DMA mode. NO delay is required when reading indicates the status of the disk controller. The Main the MSR after a data transfer. Status Register can be read at any 7 6 5 4 3 2 1 0 RQM DIO NON CMD DRV3 DRV2 DRV1 DRV0 DMA BUSY BUSY BUSY BUSY BUSY BIT 0 - 3 DRV x BUSY BIT 5 NON-DMA These bits are set to 1s when a drive is in the seek This mode is selected in the SPECIFY command and will portion of a command, including implied and overlapped be set to a 1 during the execution phase of a command. seeks and recalibrates. This is for polled data transfers and helps differentiate between the data transfer phase and the reading of result BIT 4 COMMAND BUSY bytes. This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has been BIT 6 DIO accepted and goes inactive at the end of the results Indicates the direction of a data transfer once a RQM is phase. If there is no result phase (Seek, Recalibrate set. A 1 indicates a read and a 0 indicates a write is commands), this bit is returned to a 0 after the last required. command byte. BIT 7 RQM Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0. 29 DATA REGISTER (FIFO) FIFO. The data is based upon the following formula: Address 3F5 READ/WRITE Threshold # x 1 -1.5 µs = DELAY All command parameter information, disk data and result DATA RATE status are transferred between the host processor and the floppy disk controller through the Data Register. At the start of a command, the FIFO action is always disabled and command parameters must be sent based Data transfers are governed by the RQM and DIO bits in upon the RQM and DIO bit settings. As the command the Main Status Register. execution phase is entered, the FIFO is cleared of any data to ensure that invalid data is not transferred. The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT hardware An overrun or underrun will terminate the current compatibility. The default values can be changed through command and the transfer of data. Disk writes will the Configure command (enable full FIFO operation with complete the current sector by generating a 00 pattern threshold control). The advantage of the FIFO is that it and valid CRC. Reads require the host to remove the allows the system a larger DMA latency without causing a remaining data so that the result phase may be entered. disk error. Table 15 gives several examples of the delays with a Table 13- FIFO Service Delay FIFO THRESHOLD MAXIMUM DELAY TO EXAMPLES SERVICING AT 2 Mbps* DATA RATE 1 byte 1 x 4 µs - 1.5 µs = 2.5 µs 2 bytes 2 x 4 µs - 1.5 µs = 6.5 µs 8 bytes 8 x 4 µs - 1.5 µs = 30.5 µs 15 bytes 15 x 4 µs - 1.5 µs = 58.5 µs FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT 1 EXAMPLES Mbps DATA RATE 1 byte 1 x 8 µs - 1.5 µs = 6.5 µs 2 bytes 2 x 8 µs - 1.5 µs = 14.5 µs 8 bytes 8 x 8 µs - 1.5 µs = 62.5 µs 15 bytes 15 x 8 µs - 1.5 µs = 118.5 µs FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT EXAMPLES 500 Kbps DATA RATE 1 byte 1 x 16 µs - 1.5 µs = 14.5 µs 2 bytes 2 x 16 µs - 1.5 µs = 30.5 µs 8 bytes 8 x 16 µs - 1.5 µs = 126.5 µs 15 bytes 15 x 16 µs - 1.5 µs = 238.5 µs *The 2 Mbps data rate is only available if V = 5V. CC 30 DIGITAL INPUT REGISTER (DIR) Address 3F7 READ ONLY This register is read-only in all modes. PC-AT Mode 7 6 5 4 3 2 1 0 DSK CHG RESET N/A N/A N/A N/A N/A N/A N/A N/A COND. BIT 0 - 6 UNDEFINED BIT 7 DSKCHG The data bus outputs D0 - 6 will remain in a high This bit monitors the pin of the same name and reflects impedance state during a read of this register. the opposite value seen on the disk cable. PS/2 Mode 7 6 5 4 3 2 1 0 DSK 1 1 1 1 DRATE DRATE HIGH CHG SEL1 SEL0 DENS RESET N/A N/A N/A N/A N/A N/A N/A 1 COND. BIT 0 nHIGH DENS software reset, and are set to 250 Kbps after a hardware This bit is low whenever the 500 Kbps or 1 Mbps data reset. rates are selected, and high when 250 Kbps and 300 Kbps are selected. BITS 3 - 6 UNDEFINED Always read as a logic "1" BITS 1 - 2 DATA RATE SELECT These bits control the data rate of the floppy controller. BIT 7 DSKCHG See Table 13 for the settings corresponding to the This bit monitors the pin of the same name and reflects individual data rates. The data rate select bits are the opposite value seen on the disk cable. unaffected by a 31 Model 30 Mode 7 6 5 4 3 2 1 0 DSK 0 0 0 DMAENNOPRECDRATE DRATE CHG SEL1 SEL0 RESET N/A 0 0 0 0 0 1 0 COND. BITS 0 - 1 DATA RATE SELECT BIT 3 DMAEN These bits control the data rate of the floppy controller. This bit reflects the value of DMAEN bit set in the DOR See Table 13 for the settings corresponding to the register bit 3. individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250kb/s BITS 4 - 6 UNDEFINED after a hardware reset. Always read as a logic "0" BIT 2 NOPREC BIT 7 DSKCHG This bit reflects the value of NOPREC bit set in the CCR This bit monitors the pin of the same name and reflects register. the opposite value seen on the pin. 32 CONFIGURATION CONTROL REGISTER (CCR) Address 3F7 WRITE ONLY PC/AT and PS/2 Modes 7 6 5 4 3 2 1 0 DRATE DRATE SEL1 SEL0 RESET N/A N/A N/A N/A N/A N/A 1 0 COND. BIT 0 and 1 DATA RATE SELECT 0 and 1 BIT 2 - 7 RESERVED These bits determine the data rate of the floppy controller. Should be set to a logical "0" See Table 13 for the appropriate values. PS/2 Model 30 Mode 7 6 5 4 3 2 1 0 NOPRECDRATE DRATE SEL1 SEL0 RESET N/A N/A N/A N/A N/A N/A 1 0 COND. BIT 0 and 1 DATA RATE SELECT 0 and 1 BIT 3 - 7 RESERVED These bits determine the data rate of the floppy controller. Should be set to a logical "0" See Table 13 for the appropriate values. Table 13 shows the state of the DENSEL pin. The BIT 2 NO PRECOMPENSATION DENSEL pin is set high after a hardware reset and is This bit can be set by software, but it has no functionality. unaffected by the DOR and the DSR resets. It can be read by bit 2 of the DSR when in Model 30 register mode. Unaffected by software reset. 33 STATUS REGISTER ENCODING During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. Table 14 - Status Register 0 BIT NO. SYMBOL NAME DESCRIPTION 7,6 IC Interrupt Code 00 - Normal termination of command. The specified command was properly executed and completed without error. 01 - Abnormal termination of command. Command execution was started, but was not successfully completed. 10 - Invalid command. The requested command could not be executed. 11 - Abnormal termination caused by Polling. 5 SE Seek End The FDC completed a Seek, Relative Seek or Recalibrate command (used during a Sense Interrupt Command). 4 EC Equipment The TRK0 pin failed to become a "1" after: Check 1. 80 step pulses in the Recalibrate command. 2. The Relative Seek command caused the FDC to step outward beyond Track 0. 3 Unused. This bit is always "0". 2 H Head Address The current head address. 1,0 DS1,0 Drive Select The current selected drive. 34 Table 15 - Status Register 1 BIT NO. SYMBOL NAME DESCRIPTION 7 EN End of The FDC tried to access a sector beyond the final sector Cylinder of the track (255D). Will be set if TC is not issued after Read or Write Data command. 6 Unused. This bit is always "0". 5 DE Data Error The FDC detected a CRC error in either the ID field or the data field of a sector. 4 OR Overrun/ Becomes set if the FDC does not receive CPU or DMA Underrun service within the required time interval, resulting in data overrun or underrun. 3 Unused. This bit is always "0". 2 ND No Data Any one of the following: 1. Read Data, Read Deleted Data command - the FDC did not find the specified sector. 2. Read ID command - the FDC cannot read the ID field without an error. 3. Read A Track command - the FDC cannot find the proper sector sequence. 1 NW Not Writeable WP pin became a "1" while the FDC is executing a Write Data, Write Deleted Data, or Format A Track command. 0 MA Missing Any one of the following: Address Mark 1. The FDC did not detect an ID address mark at the specified track after encountering the index pulse from the IDX pin twice. 2. The FDC cannot detect a data address mark or a deleted data address mark on the specified track. 35 Table 16 - Status Register 2 BIT NO. SYMBOL NAME DESCRIPTION 7 Unused. This bit is always "0". 6 CM Control Mark Any one of the following: 1. Read Data command - the FDC encountered a deleted data address mark. 2. Read Deleted Data command - the FDC encountered a data address mark. 5 DD Data Error in The FDC detected a CRC error in the data field. Data Field 4 WC Wrong The track address from the sector ID field is different Cylinder from the track address maintained inside the FDC. 3 Unused. This bit is always "0". 2 Unused. This bit is always "0". 1 BC Bad Cylinder The track address from the sector ID field is different from the track address maintained inside the FDC and is equal to FF hex, which indicates a bad track with a hard error according to the IBM soft-sectored format. 0 MD Missing Data The FDC cannot detect a data address mark or a deleted Address Mark data address mark. 36 Table 17 - Status Register 3 BIT NO. SYMBOL NAME DESCRIPTION 7 Unused. This bit is always "0". 6 WP Write Indicates the status of the WP pin. Protected 5 Unused. This bit is always "1". 4 T0 Track 0 Indicates the status of the TRK0 pin. 3 Unused. This bit is always "1". 2 HD Head Address Indicates the status of the HDSEL pin. 1,0 DS1,0 Drive Select Indicates the status of the DS1, DS0 pins. RESET DOR Reset vs. DSR Reset (Software Reset) There are three sources of system reset on the FDC: The These two resets are functionally the same. Both will RESET pin of the FDC37C669, a reset generated via a reset the FDC core, which affects drive status information bit in the DOR, and a reset generated via a bit in the and the FIFO circuits. The DSR reset clears itself DSR. At power on, a Power On Reset initializes the automatically while the DOR reset requires the host to FDC. All resets take the FDC out of the power down manually clear it. DOR reset has precedence over the state. DSR reset. The DOR reset is set automatically upon a pin reset. The user must manually clear this reset bit in All operations are terminated upon a RESET, and the the DOR to exit the reset state. FDC enters an idle state. A reset while a disk write is in progress will corrupt the data and CRC. MODES OF OPERATION On exiting the reset state, various internal registers are The FDC has three modes of operation, PC/AT mode, cleared, including the Configure command information, PS/2 mode and Model 30 mode. These are determined and the FDC waits for a new command. Drive polling will by the state of the IDENT and MFM bits 6 and 5 start unless disabled by a new Configure command. respectively of configuration register 3. RESET Pin (Hardware Reset) PC/AT mode - (IDENT high, MFM a "don't care") The RESET pin is a global reset and clears all registers The PC/AT register set is enabled, the DMA enable bit of except those programmed by the Specify command. The the DOR becomes valid (FINTR and DRQ can be hi Z), DOR reset bit is enabled and must be cleared by the host and TC and DENSEL become active high signals. to exit the reset state. 37 PS/2 mode - (IDENT low, MFM high) set of command code bytes and parameter bytes has to be written to the FDC before the command phase is This mode supports the PS/2 models 50/60/80 complete. (Please refer to Table 18 for the command set configuration and register set. The DMA bit of the DOR descriptions). These bytes of data must be transferred in becomes a "don't care", (FINTR and DRQ are always valid), TC and DENSEL become active low. the order prescribed. Model 30 mode - (IDENT low, MFM low) Before writing to the FDC, the host must examine the This mode supports PS/2 Model 30 configuration and RQM and DIO bits of the Main Status Register. RQM register set. The DMA enable bit of ther DOR becomes and DIO must be equal to "1" and "0" respectively before valid (FINTR and DRQ can be hi Z), TC is active high and command bytes may be written. RQM is set false by the DENSEL is active low. FDC after each write cycle until the received byte is processed. The FDC asserts RQM again to request each DMA TRANSFERS parameter byte of the command unless an illegal command condition is detected. After the last parameter DMA transfers are enabled with the Specify command byte is received, RQM remains "0" and the FDC and are initiated by the FDC by activating the FDRQ pin automatically enters the next phase as defined by the during a data transfer command. The FIFO is enabled command definition. directly by asserting nDACK and addresses need not be valid. The FIFO is disabled during the command phase to provide for the proper handling of the "Invalid Command" Note that if the DMA controller (i.e. 8237A) is condition. programmed to function in verify mode, a pseudo read is performed by the FDC based only on nDACK. This Execution Phase mode is only available when the FDC has been configured into byte mode (FIFO disabled) and is All data transfers to or from the FDC occur during the programmed to do a read. With the FIFO enabled, the execution phase, which can proceed in DMA or non-DMA FDC can perform the above operation by using the new mode as indicated in the Specify command. Verify command; no DMA operation is needed. After a reset, the FIFO is disabled. Each data byte is CONTROLLER PHASES transferred by an FINT or FDRQ depending on the DMA mode. The Configure command can enable the FIFO For simplicity, command handling in the FDC can be and set the FIFO threshold value. divided into three phases: Command, Execution, and Result. Each phase is described in the following The following paragraphs detail the operation of the FIFO sections. flow control. In these descriptions, is defined as the number of bytes available to the FDC when service Command Phase is requested from the host and ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one After a reset, the FDC enters the command phase and is less and ranges from 0 to 15. ready to accept a command from the host. For each of the commands, a defined 38 DMA Mode - Transfers from the FIFO to the Host A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The FDC activates the DDRQ pin when the FIFO The host reads (writes) from (to) the FIFO until empty contains (16 - ) bytes, or the last byte of a full (full), then the transfer request goes inactive. The host sector transfer has been placed in the FIFO. The DMA must be very responsive to the service request. This is controller must respond to the request by reading data the desired case for use with a "fast" system. from the FIFO. The FDC will deactivate the DDRQ pin when the FIFO becomes empty. FDRQ goes inactive A high value of threshold (i.e. 12) is used with a "sluggish" after nDACK goes active for the last byte of a data system by affording a long latency period after a service transfer (or on the active edge of nIOR, on the last byte, request, but results in more frequent service requests. if no edge is present on nDACK). A data underrun may occur if FDRQ is not removed in time to prevent an Non-DMA Mode - Transfers from the FIFO to the Host unwanted cycle. The FINT pin and RQM bits in the Main Status Register DMA Mode - Transfers from the Host to the FIFO are activated when the FIFO contains (16-) bytes or the last bytes of a full sector have been placed in The FDC activates the FDRQ pin when entering the the FIFO. The FINT pin can be used for interrupt-driven execution phase of the data transfer commands. The systems, and RQM can be used for polled systems. The DMA controller must respond by activating the nDACK host must respond to the request by reading data from and nIOW pins and placing data in the FIFO. FDRQ the FIFO. This process is repeated until the last byte is remains active until the FIFO becomes full. FDRQ is transferred out of the FIFO. The FDC will deactivate the again set true when the FIFO has bytes FINT pin and RQM bit when the FIFO becomes empty. remaining in the FIFO. The FDC will also deactivate the FDRQ pin when TC becomes true (qualified by nDACK), Non-DMA Mode - Transfers from the Host to the FIFO indicating that no more data is required. FDRQ goes inactive after nDACK goes active for the last byte of The FINT pin and RQM bit in the Main Status Register a data transfer (or on the active edge of nIOW of the last are activated upon entering the execution phase of data byte, if no edge is present on nDACK). A data overrun transfer commands. The host must respond to the may occur if FDRQ is not removed in time to prevent an request by writing data into the FIFO. The FINT pin and unwanted cycle. RQM bit remain true until the FIFO becomes full. They are set true again when the FIFO has bytes Data Transfer Termination remaining in the FIFO. The FINT pin will also be deactivated if TC and nDACK both go inactive. The FDC The FDC supports terminal count explicitly through the enters the result phase after the last byte is taken by the TC pin and implicitly through the underrun/overrun and FDC from the FIFO (i.e. FIFO empty condition). end-of-track (EOT) functions. For full sector transfers, the EOT parameter can define the last sector to be transferred in a single or multi-sector transfer. 39 Result Phase If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector, and the FDC will continue to complete the sector as if a hardware The generation of FINT determines the beginning of the TC was received. The only difference between these result phase. For each of the commands, a defined set of implicit functions and TC is that they return "abnormal result bytes has to be read from the FDC before the result termination" result status. Such status indications can be phase is complete. These bytes of data must be read out ignored if they were expected. for another command to start. Note that when the host is sending data to the FIFO of RQM and DIO must both equal "1" before the result bytes the FDC, the internal sector count will be complete when may be read. After all the result bytes have been read, the FDC reads the last byte from its side of the FIFO. the RQM and DIO bits switch to "1" and "0" respectively, There may be a delay in the removal of the transfer and the CB bit is cleared, indicating that the FDC is ready request signal of up to the time taken for the FDC to read to accept the next command. the last 16 bytes from the FIFO. The host must tolerate this delay. 40 COMMAND SET/DESCRIPTIONS is issued. The user sends a Sense Interrupt Status command which returns an invalid command error. Refer Commands can be written whenever the FDC is in the to Table 18 or explanations of the various symbols used. command phase. Each command has a unique set of Table 19 lists the required parameters and the results needed parameters and status results. The FDC checks associated with each command that the FDC is capable to see that the first byte is a valid command and, if valid, of performing. proceeds with the command. If it is invalid, an interrupt Table 18 - Description of Command Symbols SYMBOL NAME DESCRIPTION C Cylinder Address The currently selected address; 0 to 255. D Data Pattern The pattern to be written in each sector data field during formatting. D0, D1, D2, Drive Select 0-3 Designates which drives are perpendicular drives on the D3 Perpendicular Mode Command. A "1" indicates a perpendicular drive. DIR Direction Control If this bit is 0, then the head will step out from the spindle during a relative seek. If set to a 1, the head will step in toward the spindle. DS0, DS1 Disk Drive Select DS1 DS0 DRIVE 0 0 drive 0 0 1 drive 1 1 0 drive 2 1 1 drive 3 DTL Special Sector By setting N to zero (00), DTL may be used to control the number of Size bytes transferred in disk read/write commands. The sector size (N = 0) is set to 128. If the actual sector (on the diskette) is larger than DTL, the remainder of the actual sector is read but is not passed to the host during read commands; during write commands, the remainder of the actual sector is written with all zero bytes. The CRC check code is calculated with the actual sector. When N is not zero, DTL has no meaning and should be set to FF HEX. EC Enable Count When this bit is "1" the "DTL" parameter of the Verify command becomes SC (number of sectors per track). EFIFO Enable FIFO This active low bit when a 0, enables the FIFO. A "1" disables the FIFO (default). EIS Enable Implied When set, a seek operation will be performed before executing any Seek read or write command that requires the C parameter in the command phase. A "0" disables the implied seek. EOT End of Track The final sector number of the current track. GAP Alters Gap 2 length when using Perpendicular Mode. 41 Table 18 - Description of Command Symbols SYMBOL NAME DESCRIPTION GPL Gap Length The Gap 3 size. (Gap 3 is the space between sectors excluding the VCO synchronization field). H/HDS Head Address Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector ID field. HLT Head Load Time The time interval that FDC waits after loading the head and before initializing a read or write operation. Refer to the Specify command for actual delays. HUT Head Unload Time The time interval from the end of the execution phase (of a read or write command) until the head is unloaded. Refer to the Specify command for actual delays. LOCK Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE COMMAND can be reset to their default values by a "Software Reset". (A reset caused by writing to the appropriate bits of either the DSR or DOR) MFM MFM/FM Mode A one selects the double density (MFM) mode. A zero selects single Selector density (FM) mode. MT Multi-Track When set, this flag selects the multi-track operating mode. In this Selector mode, the FDC treats a complete cylinder under head 0 and 1 as a single track. The FDC operates as this expanded track started at the first sector under head 0 and ended at the last sector under head 1. With this flag set, a multitrack read or write operation will automatically continue to the first sector under head 1 when the FDC finishes operating on the last sector under head 0. N Sector Size Code This specifies the number of bytes in a sector. If this parameter is "00", then the sector size is 128 bytes. The number of bytes transferred is determined by the DTL parameter. Otherwise the sector size is (2 raised to the "N'th" power) times 128. All values up to "07" hex are allowable. "07"h would equal a sector size of 16k. It is the user's responsibility to not select combinations that are not possible with the drive. N SECTOR SIZE 00 128 bytes 01 256 bytes 02 512 bytes 03 1024 bytes .. … 07 16 kbytes 42 Table 18 - Description of Command Symbols SYMBOL NAME DESCRIPTION NCN New Cylinder The desired cylinder number. Number ND Non-DMA Mode When set to 1, indicates that the FDC is to operate in the non-DMA Flag mode. In this mode, the host is interrupted for each data transfer. When set to 0, the FDC operates in DMA mode, interfacing to a DMA controller by means of the DRQ and nDACK signals. OW Overwrite The bits D0-D3 of the Perpendicular Mode Command can only be modified if OW is set to 1. OW id defined in the Lock command. PCN Present Cylinder The current position of the head at the completion of Sense Interrupt Number Status command. POLL Polling Disable When set, the internal polling routine is disabled. When clear, polling is enabled. PRETRK Precompensation Programmable from track 00 to FFH. Start Track Number R Sector Address The sector number to be read or written. In multi-sector transfers, this parameter specifies the sector number of the first sector to be read or written. RCN Relative Cylinder Relative cylinder offset from present cylinder as used by the Relative Number Seek command. SC Number of Sectors The number of sectors per track to be initialized by the Format Per Track command. The number of sectors per track to be verified during a Verify command when EC is set. SK Skip Flag When set to 1, sectors containing a deleted data address mark will automatically be skipped during the execution of Read Data. If Read Deleted is executed, only sectors with a deleted address mark will be accessed. When set to "0", the sector is read or written the same as the read and write commands. SRT Step Rate Interval The time interval between step pulses issued by the FDC. Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at the 1 Mbit data rate. Refer to the SPECIFY command for actual delays. ST0 Status 0 Registers within the FDC which store status information after a command has been executed. This status information is available to ST1 Status 1 the host during the result phase after command execution. ST2 Status 2 ST3 Status 3 WGATE Write Gate Alters timing of WE to allow for pre-erase loads in perpendicular drives. 43 INSTRUCTION SET Table 19 - Instruction Set READ DATA DATA BUS PHASE R/W REMARKS D7 D6 D5 D4 D3 D2 D1 D0 Command W MT MFM SK 0 0 1 1 0 Command Codes W 0 0 0 0 0 HDSDS1DS0 W ──────── C ──────── Sector ID information prior to Command execution. W ──────── H ──────── W ──────── R ──────── W ──────── N ──────── W ─────── EOT ─────── W ─────── GPL ─────── W ─────── DTL ─────── Execution Data transfer between the FDD and system. Result R ─────── ST0 ─────── Status information after Com- mand execution. R ─────── ST1 ─────── R ─────── ST2 ─────── R ──────── C ──────── Sector ID information after Command execution. R ──────── H ──────── R ──────── R ──────── R ──────── N ──────── 44 READ DELETED DATA DATA BUS PHASE R/W REMARKS D7 D6 D5 D4 D3 D2 D1 D0 Command W MT MFM SK 0 1 1 0 0 Command Codes W 0 0 0 0 0 HDSDS1DS0 W ──────── C ──────── Sector ID information prior to Command execution. W ──────── H ──────── W ──────── R ──────── W ──────── N ──────── W ─────── EOT ─────── W ─────── GPL ─────── W ─────── DTL ─────── Execution Data transfer between the FDD and system. Result R ─────── ST0 ─────── Status information after Com- mand execution. R ─────── ST1 ─────── R ─────── ST2 ─────── R ──────── C ──────── Sector ID information after Command execution. R ──────── H ──────── R ──────── R ──────── R ──────── N ──────── 45 WRITE DATA DATA BUS PHASE R/W REMARKS D7 D6 D5 D4 D3 D2 D1 D0 Command W MT MFM 0 0 0 1 0 1 Command Codes W 0 0 0 0 0 HDSDS1DS0 W ──────── C ──────── Sector ID information prior to Command execution. W ──────── H ──────── W ──────── R ──────── W ──────── N ──────── W ─────── EOT ─────── W ─────── GPL ─────── W ─────── DTL ─────── Execution Data transfer between the FDD and system. Result R ─────── ST0 ─────── Status information after Com- mand execution. R ─────── ST1 ─────── R ─────── ST2 ─────── R ──────── C ──────── Sector ID information after Command execution. R ──────── H ──────── R ──────── R ──────── R ──────── N ──────── 46 WRITE DELETED DATA DATA BUS PHASE R/W REMARKS D7 D6 D5 D4 D3 D2 D1 D0 Command W MT MFM 0 0 1 0 0 1 Command Codes W 0 0 0 0 0 HDS DS1 DS0 W ──────── C ──────── Sector ID information prior to Command execution. W ──────── H ──────── W ──────── R ──────── W ──────── N ──────── W ─────── EOT ─────── W ─────── GPL ─────── W ─────── DTL ─────── Execution Data transfer between the FDD and system. Result R ─────── ST0 ─────── Status information after Command execution. R ─────── ST1 ─────── R ─────── ST2 ─────── R ──────── C ──────── Sector ID information after Command execution. R ──────── H ──────── R ──────── R ──────── R ──────── N ──────── 47 READ A TRACK DATA BUS PHASE R/W REMARKS D7 D6 D5 D4 D3 D2 D1 D0 Command W 0 MFM 0 0 0 0 1 0 Command Codes W 0 0 0 0 0 HDS DS1 DS0 W ──────── C ──────── Sector ID information prior to Command execution. W ──────── H ──────── W ──────── R ──────── W ──────── N ──────── W ─────── EOT ─────── W ─────── GPL ─────── W ─────── DTL ─────── Execution Data transfer between the FDD and system. FDC reads all of cylinders' contents from index hole to EOT. Result R ─────── ST0 ─────── Status information after Command execution. R ─────── ST1 ─────── R ─────── ST2 ─────── R ──────── C ──────── Sector ID information after Command execution. R ──────── H ──────── R ──────── R ──────── R ──────── N ──────── 48 VERIFY DATA BUS PHASE R/W REMARKS D7 D6 D5 D4 D3 D2 D1 D0 Command W MT MFMSK 1 0 1 1 0 Command Codes W EC 0 0 0 0 HDS DS1 DS0 W ──────── C ──────── Sector ID information prior to Command execution. W ──────── H ──────── W ──────── R ──────── W ──────── N ──────── W ─────── EOT ─────── W ─────── GPL ─────── W ────── DTL/SC ────── Execution No data transfer takes place. Result R ─────── ST0 ─────── Status information after Command execution. R ─────── ST1 ─────── R ─────── ST2 ─────── R ──────── C ──────── Sector ID information after Command execution. R ──────── H ──────── R ──────── R ──────── R ──────── N ──────── VERSION DATA BUS PHASE R/W REMARKS D7 D6 D5 D4 D3 D2 D1 D0 Command W 0 0 0 1 0 0 0 0 Command Code Result R 1 0 0 1 0 0 0 0 Enhanced Controller 49 FORMAT A TRACK DATA BUS PHASE R/W REMARKS D7 D6 D5 D4 D3 D2 D1 D0 Command W 0 MFM 0 0 1 1 0 1 Command Codes W 0 0 0 0 0 HDS DS1 DS0 W ──────── N ──────── Bytes/Sector W ──────── SC ──────── Sectors/Cylinder W ─────── GPL ─────── Gap 3 W ──────── D ──────── Filler Byte Execution for W ──────── C ──────── Input Sector Parameters Each Sector Repeat: W ──────── H ──────── W ──────── R ──────── W ──────── N ──────── FDC formats an entire cylinder Result R ─────── ST0 ─────── Status information after Command execution R ─────── ST1 ─────── R ─────── ST2 ─────── R ────── Undefined ────── R ────── Undefined ────── R ────── Undefined ────── R ────── Undefined ────── 50 RECALIBRATE DATA BUS PHASE R/W REMARKS D7 D6 D5 D4 D3 D2 D1 D0 Command W 0 0 0 0 0 1 1 1 Command Codes W 0 0 0 0 0 0 DS1 DS0 Execution Head retracted to Track 0 Interrupt. SENSE INTERRUPT STATUS DATA BUS PHASE R/W REMARKS D7 D6 D5 D4 D3 D2 D1 D0 Command W 0 0 0 0 1 0 0 0 Command Codes Result R ─────── ST0 ─────── Status information at the end of each seek operation. R ─────── PCN ─────── SPECIFY DATA BUS PHASE R/W REMARKS D7 D6 D5 D4 D3 D2 D1 D0 Command W 0 0 0 0 0 0 1 1 Command Codes W ─── SRT ─── ─── HUT ─── W ────── HLT ────── ND 51 SENSE DRIVE STATUS DATA BUS PHASE R/W REMARKS D7 D6 D5 D4 D3 D2 D1 D0 Command W 0 0 0 0 0 1 0 0 Command Codes W 0 0 0 0 0 HDS DS1 DS0 Result R ─────── ST3 ─────── Status information about FDD SEEK DATA BUS PHASE R/W REMARKS D7 D6 D5 D4 D3 D2 D1 D0 Command W 0 0 0 0 1 1 1 1 Command Codes W 0 0 0 0 0 HDS DS1 DS0 W ─────── NCN ─────── Execution Head positioned over proper cylinder on diskette. CONFIGURE DATA BUS PHASE R/W REMARKS D7 D6 D5 D4 D3 D2 D1 D0 Command W 0 0 0 1 0 0 1 1 Configure Information W 0 0 0 0 0 0 0 0 W 0 EIS EFIFOPOLL ─── FIFOTHR ─── Execution W ───────── PRETRK ───────── 52 RELATIVE SEEK DATA BUS PHASE R/W REMARKS D7 D6 D5 D4 D3 D2 D1 D0 Command W 1 DIR 0 0 1 1 1 1 W 0 0 0 0 0 HDS DS1 DS0 W ─────── RCN ─────── DUMPREG DATA BUS PHASE R/W REMARKS D7 D6 D5 D4 D3 D2 D1 D0 Command W 0 0 0 0 1 1 1 0 *Note: Registers placed in FIFO Execution Result R ────── PCN-Drive 0 ─────── R ────── PCN-Drive 1 ─────── R ────── PCN-Drive 2 ─────── R ────── PCN-Drive 3 ─────── R ──── SRT ──── ─── HUT ─── R ─────── HLT ─────── ND R ─────── SC/EOT ─────── R LOCK 0 D3 D2 D1 D0 GAP WGATE R 0 EISEFIFOPOLL ── FIFOTHR ── R ──────── PRETRK ──────── 53 READ ID DATA BUS PHASE R/W REMARKS D7 D6 D5 D4 D3 D2 D1 D0 Command W 0 MFM 0 0 1 0 1 0 Commands W 0 0 0 0 0 HDS DS1 DS0 Execution The first correct ID information on the Cylinder is stored in Data Register Result R ──────── ST0 ──────── Status information after Command execution. Disk status after the Command has completed R ──────── ST1 ──────── R ──────── ST2 ──────── R ──────── C ──────── R ──────── H ──────── R ──────── R ──────── R ──────── N ──────── 54 PERPENDICULAR MODE DATA BUS PHASE R/W REMARKS D7 D6 D5 D4 D3 D2 D1 D0 Command W 0 0 0 1 0 0 1 0 Command Codes OW 0 D3 D2 D1 D0 GAP WGATE INVALID CODES DATA BUS PHASE R/W REMARKS D7 D6 D5 D4 D3 D2 D1 D0 Command W ───── Invalid Codes ───── Invalid Command Codes (No Op - FDC37C669 goes into Standby State) Result R ─────── ST0 ─────── ST0 = 80H LOCK DATA BUS PHASE R/W REMARKS D7 D6 D5 D4 D3 D2 D1 D0 Command W LOCK 0 0 1 0 1 0 0 Command Codes Result R 0 0 0 LOCK 0 0 0 0 SC is returned if the last command that was issued was the Format command. EOT is returned if the last command was a Read or Write. NOTE: These bits are used internally only. They are not reflected in the Drive Select pins. It is the user's responsibility to maintain correspondence between these bits and the Drive Select pins (DOR). 55 DATA TRANSFER COMMANDS N determines the number of bytes per sector (see Table 22 below). If N is set to zero, the sector size is set to 128. All of the Read Data, Write Data and Verify type The DTL value determines the number of bytes to be commands use the same parameter bytes and return the transferred. If DTL is less than 128, the FDC transfers same results information, the only difference being the the specified number of bytes to the host. For reads, it coding of bits 0-4 in the first byte. continues to read the entire 128-byte sector and checks for CRC errors. For writes, it completes the 128-byte An implied seek will be executed if the feature was sector by filling in zeros. If N is not set to 00 Hex, DTL enabled by the Configure command. This seek is should be set to FF Hex and has no impact on the completely transparent to the user. The Drive Busy bit for number of bytes transferred. the drive will go active in the Main Status Register during the seek portion of the command. If the seek portion Table 20 - Sector Sizes fails, it will be reflected in the results status normally N SECTOR SIZE returned for a Read/Write Data command. Status 00 128 bytes Register 0 (ST0) would contain the error code and C 01 256 bytes would contain the cylinder on which the seek failed. 02 512 bytes 03 1024 bytes Read Data .. ... 07 16 Kbytes A set of nine (9) bytes is required to place the FDC in the Read Data Mode. After the Read Data command has been issued, the FDC loads the head (if it is in the The amount of data which can be handled with a single unloaded state), waits the specified head settling time command to the FDC depends upon MT (multi-track) and (defined in the Specify command), and begins reading ID N (number of bytes/sector). Address Marks and ID fields. When the sector address read off the diskette matches with the sector address The Multi-Track function (MT) allows the FDC to read specified in the command, the FDC reads the sector's data from both sides of the diskette. For a particular data field and transfers the data to the FIFO. cylinder, data will be transferred starting at Sector 1, Side 0 and completing the last sector of the same track at Side After completion of the read operation from the current 1. sector, the sector address is incremented by one and the data from the next logical sector is read and output via If the host terminates a read or write operation in the the FIFO. This continuous read function is called "Multi- FDC, the ID information in the result phase is dependent Sector Read Operation". Upon receipt of TC, or an upon the state of the MT bit and EOT byte. Refer to implied TC (FIFO overrun/underrun), the FDC stops Table 23. sending data but will continue to read data from the current sector, check the CRC bytes, and at the end of At the completion of the Read Data command, the head the sector, terminate the Read Data Command. is not unloaded until after the Head Unload Time Interval (specified in the Specify command) has elapsed. If the host issues another command before the head unloads, then the head settling time may be saved between subsequent reads. If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette's index hole passes through index detect logic in the drive twice), the FDC sets the IC code in Status 56 Register 0 to "01" indicating abnormal termination, sets sector, the FDC checks the CRC bytes. If a CRC error the ND bit in Status Register 1 to "1" indicating a sector occurs in the ID or data field, the FDC sets the IC code in not found, and terminates the Read Data Command. Status Register 0 to "01" indicating abnormal termination, sets the DE bit flag in Status Register 1 to "1", sets the After reading the ID and Data Fields in each DD bit in Status Register 2 to "1" if CRC is incorrect in the ID field, and terminates the Read Data Command. Table 22 describes the effect of the SK bit on the Read Data command execution and results. Except where noted in Table 22, the C or R value of the sector address is automatically incremented (see Table 24). Table 21 - Effects of MT and N Bits MAXIMUM TRANSFER FINAL SECTOR READ CAPACITY FROM DISK MT N 0 1 256 x 26 = 6,656 26 at side 0 or 1 1 1 256 x 52 = 13,312 26 at side 1 0 2 512 x 15 = 7,680 15 at side 0 or 1 1 2 512 x 30 = 15,360 15 at side 1 0 3 1024 x 8 = 8,192 8 at side 0 or 1 1 3 1024 x 16 = 16,384 16 at side 1 Table 22 - Skip Bit vs Read Data Command DATA ADDRESS SK BIT MARK TYPE RESULTS VALUE ENCOUNTERED SECTOR CM BIT OF DESCRIPTION OF READ? ST2 SET? RESULTS 0 Normal Data Yes No Normal termination. 0 Deleted Data Yes Yes Address not incremented. Next sector not searched for. 1 Normal Data Yes No Normal termination. 1 Deleted Data No Yes Normal termination. Sector not read ("skipped"). 57 Read Deleted Data Table 25 describes the effect of the SK bit on the Read Deleted Data command execution and results. This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Except where noted in Table 25, the C or R value of the Address Mark at the beginning of a Data Field. sector address is automatically incremented (see Table 26). Table 23 - Skip Bit vs. Read Deleted Data Command DATA ADDRESS RESULTS SK BIT MARK TYPE SECTOR CM BIT OF DESCRIPTION OF VALUE ENCOUNTERED READ? ST2 SET? RESULTS 0 Normal Data Yes Yes Address not incremented. Next sector not searched for. 0 Deleted Data Yes No Normal termination. 1 Normal Data No Yes Normal termination. Sector not read ("skipped"). 1 Deleted Data Yes No Normal termination. Read A Track and sets the ND flag of Status Register 1 to a "1" if there is no comparison. Multi-track or skip operations are This command is similar to the Read Data command not allowed with this command. The MT and SK bits (bits except that the entire data field is read continuously from D7 and D5 of the first command byte respectively) should each of the sectors of a track. Immediately after always be set to "0". encountering a pulse on the nINDEX pin, the FDC starts to read all data fields on the track as continuous This command terminates when the EOT specified blocks of data without regard to logical sector numbers. If number of sectors has not been read. If the FDC does not the FDC finds an error in the ID or DATA CRC check find an ID Address Mark on the diskette after the second bytes, it continues to read data from the track and sets occurrence of a pulse on the IDX pin, then it sets the IC the appropriate error bits at the end of the command. code in Status Register 0 to "01" (abnormal termination), The FDC compares the ID information read from each sets the MA bit in Status Register 1 to "1", and terminates sector with the specified value in the command the command. 58 Table 24 - Result Phase Table FINAL SECTOR ID INFORMATION AT RESULT PHASE HEAD TRANSFERRED TO HOST C H R N MT 0 Less than EOT NC NC R + 1 NC Equal to EOT C + 1 NC 01 NC 0 1 Less than EOT NC NC R + 1 NC Equal to EOT C + 1 NC 01 NC 0 Less than EOT NC NC R + 1 NC Equal to EOT NC LSB 01 NC 1 1 Less than EOT NC NC R + 1 NC Equal to EOT C + 1 LSB 01 NC NC: No Change, the same value as the one at the beginning of command execution. LSB: Least Significant Bit, the LSB of H is complemented. Write Data Status Register 0 to "01" (abnormal termination), sets the DE bit of Status Register 1 to "1", and terminates the After the Write Data command has been issued, the FDC Write Data command. loads the head (if it is in the unloaded state), waits the specified head load time if unloaded (defined in the The Write Data command operates in much the same Specify command), and begins reading ID fields. When manner as the Read Data command. The following items the sector address read from the diskette matches the are the same. Please refer to the Read Data Command sector address specified in the command, the FDC reads for details: the data from the host via the FIFO and writes it to the sector's data field. ! Transfer Capacity ! EN (End of Cylinder) bit After writing data into the current sector, the FDC ! ND (No Data) bit computes the CRC value and writes it into the CRC field ! Head Load, Unload Time Interval at the end of the sector transfer. The Sector Number ! ID information when the host terminates the stored in "R" is incremented by one, and the FDC command continues writing to the next data field. The FDC ! Definition of DTL when N = 0 and when N does not = continues this "Multi-Sector Write Operation". Upon 0 receipt of a terminal count signal or if a FIFO over/under Write Deleted Data run occurs while a data field is being written, then the remainder of the data field is filled with zeros. This command is almost the same as the Write Data The FDC reads the ID field of each sector and checks the command except that a Deleted Data Address Mark is CRC bytes. If it detects a CRC error in one of the ID written at the beginning of the Data Field instead of the fields, it sets the IC code in normal Data Address Mark. This command is typically used to mark a bad sector containing an error on the floppy disk. Verify 59 The Verify command is used to verify the data stored on terminated by setting the EC bit to "0" and the EOT value a disk. This command acts exactly like a Read Data equal to the final sector to be checked. If EC is set to "0", command except that no data is transferred to the host. DTL/SC should be programmed to 0FFH. Refer to Table Data is read from the disk and CRC is computed and 26 and Table 27 for information concerning the values of checked against the previously-stored value. MT and EC versus SC and EOT value. Because data is not transferred to the host, TC (pin 25) Definitions: cannot be used to terminate this command. By setting the EC bit to "1", an implicit TC will be issued to the FDC. # Sectors Per Side = Number of formatted sectors per This implicit TC will occur when the SC value has each side of the disk. decremented to 0 (an SC value of 0 will verify 256 sectors). This command can also be # Sectors Remaining = Number of formatted sectors left which can be read, including side 1 of the disk if MT is set to "1". Table 25 - Verify Command Result Phase Table MT EC SC/EOT VALUE TERMINATION RESULT 0 0 SC = DTL Success Termination EOT < # Sectors Per Side Result Phase Valid 0 0 SC = DTL Unsuccessful Termination EOT > # Sectors Per Side Result Phase Invalid 0 1 SC < # Sectors Remaining AND Successful Termination EOT < # Sectors Per Side Result Phase Valid 0 1 SC > # Sectors Remaining OR Unsuccessful Termination EOT > # Sectors Per Side Result Phase Invalid 1 0 SC = DTL Successful Termination EOT < # Sectors Per Side Result Phase Valid 1 0 SC = DTL Unsuccessful Termination EOT > # Sectors Per Side Result Phase Invalid 1 1 SC < # Sectors Remaining AND Successful Termination EOT < # Sectors Per Side Result Phase Valid 1 1 SC > # Sectors Remaining OR Unsuccessful Termination EOT > # Sectors Per Side Result Phase Invalid NOTE: If MT is set to "1" and the SC value is greater than the number of remaining formatted sectors on Side 0, verifying will continue on Side 1 of the disk. 60 Format A Track After formatting each sector, the host must send new values for C, H, R and N to the FDC for the next sector The Format command allows an entire track to be on the track. The R value (sector number) is the only formatted. After a pulse from the IDX pin is detected, the value that must be changed by the host after each sector FDC starts writing data on the disk including gaps, is formatted. This allows the disk to be formatted with address marks, ID fields, and data fields per the IBM nonsequential sector addresses (interleaving). This System 34 or 3740 format (MFM or FM respectively). incrementing and formatting continues for the whole track The particular values that will be written to the gap and until the FDC encounters a pulse on the IDX pin again data field are controlled by the values programmed into and it terminates the command. N, SC, GPL, and D which are specified by the host during the command phase. The data field of the sector is filled Table 28 contains typical values for gap fields which are with the data byte specified by D. The ID field for each dependent upon the size of the sector and the number of sector is supplied by the host; that is, four data bytes per sectors on each track. Actual values can vary due to drive sector are needed by the FDC for C, H, R, and N electronics. (cylinder, head, sector number and sector size respectively). FORMAT FIELDS SYSTEM 34 (DOUBLE DENSITY) FORMAT DATA GAP4a SYNC IAM GAP1 SYNC IDAM C H S N C GAP2 SYNC AM C 80x 12x 50x 12x Y D E O R 22x 12x DATA R GAP3 GAP 4b 4E 00 4E 00 L C C 4E 00 C 3x FC 3xFE 3x FB C2 A1 A1 F8 SYSTEM 3740 (SINGLE DENSITY) FORMAT DATA GAP4a SYNC IAM GAP1 SYNC IDAM C H S N C GAP2 SYNC AM C 40x 6x 26x 6x Y D E O R 11x 6x DATA R GAP3 GAP 4b FF 00 FF 00 L C C FF 00 C FC FE FB or F8 PERPENDICULAR FORMAT DATA GAP4a SYNC IAM GAP1 SYNC IDAM C H S N C GAP2 SYNC AM C 80x 12x 50x 12x Y D E O R 41x 12x DATA R GAP3 GAP 4b 4E 00 4E 00 L C C 4E 00 C 3x FC 3xFE 3x FB C2 A1 A1 F8 61 Table 26 - Typical Values for Formatting FORMAT SECTOR SIZE N SC GPL1 GPL2 128 00 12 07 09 128 00 10 10 19 512 02 08 18 30 FM 1024 03 04 46 87 2048 04 02 C8 FF 5.25" 4096 05 01 C8 FF Drives ... ... 256 01 12 0A 0C 256 01 10 20 32 512* 02 09 2A 50 MFM 1024 03 04 80 F0 2048 04 02 C8 FF 4096 05 01 C8 FF ... ... 128 0 0F 07 1B 3.5" FM 256 1 09 0F 2A Drives 512 2 05 1B 3A 256 1 0F 0E 36 MFM 512** 2 09 1B 54 1024 3 05 35 74 GPL1 = suggested GPL values in Read and Write commands to avoid splice point between data field and ID field of contiguous sections. GPL2 = suggested GPL value in Format A Track command. *PC/AT values (typical) **PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives. NOTE: All values except sector size are in hex. 62 CONTROL COMMANDS The Recalibrate command does not have a result phase. The Sense Interrupt Status command must be issued Control commands differ from the other commands in that after the Recalibrate command to effectively terminate it no data transfer takes place. Three commands generate and to provide verification of the head position (PCN). an interrupt when complete: Read ID, Recalibrate, and During the command phase of the recalibrate operation, Seek. The other control commands do not generate an the FDC is in the BUSY state, but during the execution interrupt. phase it is in a NON-BUSY state. At this time, another Recalibrate command may be issued, and in this manner Read ID parallel Recalibrate operations may be done on up to four drives at once. The Read ID command is used to find the present position of the recording heads. The FDC stores the Upon power up, the software must issue a Recalibrate values from the first ID field it is able to read into its command to properly initialize all drives and the registers. If the FDC does not find an ID address mark controller. on the diskette after the second occurrence of a pulse on the nINDEX pin, it then sets the IC code in Status Seek Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command. The read/write head within the drive is moved from track to track under the control of the Seek command. The The following commands will generate an interrupt upon FDC compares the PCN, which is the current head completion. They do not return any result bytes. It is position, with the NCN and performs the following highly recommended that control commands be followed operation if there is a difference: by the Sense Interrupt Status command. Otherwise, valuable interrupt status information will be lost. PCN < NCN: Direction signal to drive set to "1" (step in) and issues step pulses. Recalibrate PCN > NCN: Direction signal to drive set to "0" (step out) and issues step pulses. This command causes the read/write head within the FDC to retract to the track 0 position. The FDC clears the The rate at which step pulses are issued is controlled by contents of the PCN counter and checks the status of the SRT (Stepping Rate Time) in the Specify command. nTR0 pin from the FDD. As long as the nTR0 pin is low, After each step pulse is issued, NCN is compared against the DIR pin remains 0 and step pulses are issued. When PCN, and when NCN = PCN the SE bit in Status Register the nTR0 pin goes high, the SE bit in Status Register 0 is 0 is set to "1" and the command is terminated. set to "1" and the command is terminated. If the nTR0 pin is still low after 79 step pulses have been issued, the During the command phase of the seek or recalibrate FDC sets the SE and the EC bits of Status Register 0 to operation, the FDC is in the BUSY state, but during the "1" and terminates the command. Disks capable of execution phase it is in the NON-BUSY state. At this handling more than 80 tracks per side may require more time, another Seek or Recalibrate command may be than one Recalibrate command to return the head back to issued, and in this manner, parallel seek operations may physical Track 0. be done on up to four drives at once. 63 Note that if implied seek is not enabled, the read and SE IC INTERRUPT DUE TO write commands should be preceded by: 0 11 Polling 1 00 Normal termination of Seek 1) Seek command - Step to the proper track or Recalibrate command 2) Sense Interrupt Status command - Terminate the Abnormal termination of Seek command 1 01 Seek or Recalibrate 3) Read ID - Verify head is on proper track command 4) Issue Read/Write command. Table 27 - Interrupt Identification The Seek command does not have a result phase. Therefore, it is highly recommended that the Sense The Seek, Relative Seek, and Recalibrate commands Interrupt Status command be issued after the Seek have no result phase. The Sense Interrupt Status command to terminate it and to provide verification of the command must be issued immediately after these head position (PCN). The H bit (Head Address) in ST0 commands to terminate them and to provide verification will always return to a "0". When exiting POWERDOWN of the head position (PCN). The H (Head Address) bit in mode, the FDC clears the PCN value and the status ST0 will always return a "0". If a Sense Interrupt Status is information to zero. Prior to issuing the POWERDOWN not issued, the drive will continue to be BUSY and may command, it is highly recommended that the user service affect the operation of the next command. all pending interrupts through the Sense Interrupt Status command. Sense Drive Status Sense Interrupt Status Sense Drive Status obtains drive status information. It has not execution phase and goes directly to the result An interrupt signal on FINT pin is generated by the FDC phase from the command phase. Status Register 3 for one of the following reasons: contains the drive status information. 1. Upon entering the Result Phase of: Specify a. Read Data command b. Read A Track command The Specify command sets the initial values for each of c. Read ID command the three internal times. The HUT (Head Unload Time) d. Read Deleted Data command defines the time from the end of the execution phase of e. Write Data command one of the read/write commands to the head unload state. f. Format A Track command The SRT (Step Rate Time) defines the time interval g. Write Deleted Data command between adjacent step pulses. Note that the spacing h. Verify command between the first and second step pulses may be shorter 2. End of Seek, Relative Seek, or Recalibrate command than the remaining step pulses. The HLT (Head Load 3. FDC requires a data transfer during the execution Time) defines the time between when the Head Load phase in the non-DMA mode signal goes high and the read/write operation starts. The Sense Interrupt Status command resets the interrupt signal and, via the IC code and SE bit of Status Register 0, identifies the cause of the interrupt. 64 The values change with the data rate speed selection values are the same for MFM and FM. and are documented in Table 30. The Table 28 - Drive Control Delays (ms) HUT SRT 2M 1M 500K 300K 250K 2M 1M 500K 300K 250K 0 64 128 256 426 512 4 8 16 26.7 32 1 4 8 16 26.7 32 3.75 7.5 15 25 30 .. .. .. .. .. .. .. .. .. .. .. E 56 112 224 373 448 0.5 1 2 3.33 4 F 60 120 240 400 480 0.25 0.5 1 1.67 2 HLT 2M 1M 500K 300K 250K 00 64 128 256 426 512 01 0.5 1 2 3.3 4 02 1 2 4 6.7 8 .. .. .. .. .. . 7F 63 126 252 420 504 7F 63.5 127 254 423 508 The choice of DMA or non-DMA operations is made by EIS - Enable Implied Seek. When set to "1", the FDC will the ND bit. When this bit is "1", the non-DMA mode is perform a Seek operation before executing a read or write selected, and when ND is "0", the DMA mode is selected. command. Defaults to no implied seek. In DMA mode, data transfers are signaled by the FDRQ pin. Non-DMA mode uses the RQM bit and the FINT pin EFIFO - A "1" disables the FIFO (default). This means to signal data transfers. data transfers are asked for on a byte-by-byte basis. Defaults to "1", FIFO disabled. The threshold defaults to Configure "1". The Configure command is issued to select the special POLL - Disable polling of the drives. Defaults to "0", features of the FDC. A Configure command need not be polling enabled. When enabled, a single interrupt is issued if the default values of the FDC meet the system generated after a reset. No polling is performed while the requirements. drive head is loaded and the head unload delay has not expired. Configure Default Values: FIFOTHR - The FIFO threshold in the execution phase of EIS - No Implied Seeks read or write commands. This is programmable from 1 to EFIFO - FIFO Disabled 16 bytes. Defaults to one byte. A "00" selects one byte; POLL - Polling Enabled "0F" selects 16 bytes. FIFOTHR - FIFO Threshold Set to 1 Byte PRETRK - Pre-Compensation Set to Track 0 65 PRETRK - Pre-Compensation Start Track Number. Seek command is 255 (D). Programmable from track 0 to 255. Defaults to track 0. A "00" selects track 0; "FF" selects track 255. The internal register, PCN, will overflow as the cylinder number crosses track 255 and will contain 39 (D). The Version resulting PCN value is thus (RCN + PCN) mod 256. Functionally, the FDC starts counting from 0 again as the The Version command checks to see if the controller is track number goes above 255 (D). It is the user's an enhanced type or the older type (765A). A value of 90 responsibility to compensate FDC functions H is returned as the result byte. (precompensation track number) when accessing tracks greater than 255. The FDC does not keep track that it is Relative Seek working in an "extended track area" (greater than 255). Any command issued will use the current PCN value The command is coded the same as for Seek, except for except for the Recalibrate command, which only looks for the MSB of the first byte and the DIR bit. the TRACK0 signal. Recalibrate will return an error if the head is farther than 79 due to its limitation of issuing a DIR Head Step Direction Control maximum of 80 step pulses. The user simply needs to issue a second Recalibrate command. The Seek DIR ACTION command and implied seeks will function correctly within 0 Step Head Out the 44 (D) track (299-255) area of the "extended track 1 Step Head In area". It is the user's responsibility not to issue a new track position that will exceed the maximum track that is present in the extended area. RCN Relative Cylinder Number that determines how many tracks to step the head in or out from the To return to the standard floppy range (0-255) of tracks, a current track number. Relative Seek should be issued to cross the track 255 boundary. The Relative Seek command differs from the Seek command in that it steps the head the absolute number of A Relative Seek can be used instead of the normal Seek, tracks specified in the command instead of making a but the host is required to calculate the difference comparison against an internal register. The Seek between the current head location and the new (target) command is good for drives that support a maximum of head location. This may require the host to issue a Read 256 tracks. Relative Seeks cannot be overlapped with ID command to ensure that the head is physically on the other Relative Seeks. Only one Relative Seek can be track that software assumes it to be. Different FDC active at a time. Relative Seeks may be overlapped with commands will return different cylinder results which may Seeks and Recalibrates. Bit 4 of Status Register 0 (EC) be difficult to keep track of with software without the Read will be set if Relative Seek attempts to step outward ID command. beyond Track 0. Perpendicular Mode As an example, assume that a floppy drive has 300 useable tracks. The host needs to read track 300 and the The Perpendicular Mode command should be issued head is on any track (0-255). If a Seek command is prior to executing Read/Write/Format commands that issued, the head will stop at track 255. If a Relative Seek access a disk drive with perpendicular recording command is issued, the FDC will move the head the capability. With this command, the length of the Gap2 specified number of tracks, regardless of the internal field and VCO enable timing can be altered to cylinder position register (but will increment the register). accommodate the unique requirements of these drives. If the head was on track 40 (d), the maximum track that Table 31 describes the effects of the WGATE and GAP the FDC could position the head on using Relative Seek bits for the Perpendicular Mode command. Upon a reset, will be 295 (D), the initial track + 255 (D). The maximum the FDC will default to the conventional mode (WGATE = count that the head can be moved with a single Relative 0, GAP = 0). 66 On the read back by the FDC, the controller must begin Selection of the 500 Kbps and 1 Mbps perpendicular synchronization at the beginning of the sync field. For the modes is independent of the actual data rate selected in conventional mode, the internal PLL VCO is enabled the Data Rate Select Register. The user must ensure (VCOEN) approximately 24 bytes from the start of the that these two data rates remain consistent. Gap2 field. But, when the controller operates in the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), The Gap2 and VCO timing requirements for VCOEN goes active after 43 bytes to accommodate the perpendicular recording type drives are dictated by the increased Gap2 field size. For both cases, and design of the read/write head. In the design of this head, approximate two-byte cushion is maintained from the a pre-erase head precedes the normal read/write head by beginning of the sync field for the purposes of avoiding a distance of 200 micrometers. This works out to about write splices in the presence of motor speed variation. 38 bytes at a 1 Mbps recording density. Whenever the write head is enabled by the Write Gate signal, the pre- For the Write Data case, the FDC activates Write Gate at erase head is also activated at the same time. Thus, the beginning of the sync field under the conventional when the write head is initially turned on, flux transitions mode. The controller then writes a new sync field, data recorded on the media for the first 38 bytes will not be address mark, data field, and CRC as shown in Figure 4. preconditioned with the pre-erase head since it has not With the pre-erase head of the perpendicular drive, the yet been activated. To accommodate this head activation write head must be activated in the Gap2 field to insure a and deactivation time, the Gap2 field is expanded to a proper write of the new sync field. For the 1 Mbps length of 41 bytes. The format field shown on page 61 perpendicular mode (WGATE = 1, GAP = 1), 38 bytes will illustrates the change in the Gap2 field size for the be written in the Gap2 space. Since the bit density is perpendicular format. proportional to the data rate, 19 bytes will be written in the Gap2 field for the 500 Kbps perpendicular mode (WGATE = 1, GAP =0). It should be noted that none of the alterations in Gap2 size, VCO timing, or Write Gate timing affect normal program flow. The information provided here is just for background purposes and is not needed for normal operation. Once the Perpendicular Mode command is invoked, FDC software behavior from the user standpoint is unchanged. The perpendicular mode command is enhanced to allow specific drives to be designated Perpendicular recording drives. This enhancement allows data transfers between Conventional and Perpendicular drives without having to issue Perpendicular mode commands between the accesses of the different drive types, nor having to change write pre-compensation values. When both GAP and WGATE bits of the PERPENDICULAR MODE COMMAND are both programmed to "0" (Conventional mode), then D0, D1, D2, D3, and D4 can be programmed independently to "1" for that drive to be set automatically to Perpendicular mode. In this mode the following set of conditions also apply: 1. The GAP2 written to a perpendicular drive during a write operation will depend upon the programmed 67 data rate. Note: Bits D0-D3 can only be overwritten when OW is 2. The write pre-compensation given to a perpendicular programmed as a "1". mode drive wil be 0ns. If either GAP or WGATE is a "1" then D0-D3 are 3. For D0-D3 programmed to "0" for conventional mode ignored. drives any data written will be at the currently programmed write pre-compensation. Software and hardware resets have the following effect on the PERPENDICULAR MODE COMMAND: 1. "Software" resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to "0". D0-D3 are unaffected and retain their previous value. 2. "Hardware" resets will clear all bits (GAP, WGATE and D0-D3) to "0", i.e all conventional mode. Table 29 - Effects of WGATE and GAP Bits PORTION OF GAP 2 LENGTH OF WRITTEN BY GAP2 FORMAT WRITE DATA WGATE GAP MODE FIELD OPERATION 0 0 Conventional 22 Bytes 0 Bytes 0 1 Perpendicular 22 Bytes 19 Bytes (500 Kbps) 1 0 Reserved 22 Bytes 0 Bytes (Conventional) 1 1 Perpendicular 41 Bytes 38 Bytes (1 Mbps) LOCK The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE In order to protect systems with long DMA latencies command can be RESET by the DOR and DSR against older application software that can disable the registers. When the LOCK bit is set to logic "1" all FIFO the LOCK Command has been added. This subsequent "software RESETS by the DOR and DSR command should only be used by the FDC routines, and registers will not change the previously set parameters to application software should refrain from using it. If an their default values. All "hardware" RESET from the application calls for the FIFO to be disabled then the RESET pin will set the LOCK bit to logic "0" and return CONFIGURE command should be used. the EFIFO, FIFOTHR, and PRETRK to 68 COMPATIBILITY their default values. A status byte is returned immediately after issuing a LOCK command. This byte reflects the value of the LOCK bit set by the command byte. The FDC37C669 was designed with software compatibility in mind. It is a fully backwards-compatible ENHANCED DUMPREG solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for The DUMPREG command is designed to support system compatibility with the PS/2, as well as PC/AT and PC/XT, run-time diagnostics and application software floppy disk controller subsystems. After a hardware reset development and debug. To accommodate the LOCK of the FDC, all registers, functions and enhancements command and the enhanced PERPENDICULAR MODE default to a PC/AT, PS/2 or PS/2 Model 30 compatible command the eighth byte of the DUMPREG command operating mode, depending on how the IDENT and MFM has been modified to contain the additional data from bits are configured by the system bios. these two commands. 69 PARALLEL PORT FLOPPY DISK CONTROLLER In this mode, the Floppy Disk Control signals are The following parallel port pins are read as follows by a available on the parallel port pins. When this mode is read of the parallel port register: selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. These modes 1. Data Register (read) = last Data Register (write) can be selected in Configuration Register 4. PPFD1 has 2. Control Register are read as "cable not connected" only drive 1 on the parallel port pins; PPFD2 has drive 0 STROBE, AUTOFD and SLC = 0 and nINIT = 1; and 1 on the parallel port pins. 3. Status Register reads: nBUSY = 0, PE = 0, SLCT = 0, nACK = 1, nERR = 1. PPFD1: Drive 0 is on the FDC pins Drive 1 is on the Parallel port pins The following FDC pins are all in the high impedence state when the PPFDC is actually selected by the drive PPFD2: Drive 0 is on the Parallel port pins select register: Drive 1 is on the Parallel port pins 1. nWDATA, DENSEL, nHDSEL, nWGATE, nDIR, When the PPFDC is selected the following pins are set as nSTEP, nDS1, nDS0, nMTRO, nMTR1. follows: 2. If PPFDx is selected, then the parallel port can not 1. nDACK: Assigned to the parallel port device during be used as a parallel port until "Normal" mode is configuration. selected. 2. PDRQ (assigned to the parallel port): not ECP = high-Z, ECP & dmaEn = 0, ECP & not dmaEn = The FDC signals are muxed onto the Parallel Port pins as high-Z shown in Table 32. 3. IRQ assigned to the parallel port: not active, this is hi-Z or Low depending on settings. 70 Table 30 - FDC Parallel Port Pins CONNECTOR PIN # CHIP PIN # SPP MODE PIN FDC MODE PIN DIRECTION DIRECTION 1 77 nSTB I/O (nDS0) I/(0) 2 71 PD0 I/O nINDEX I 3 70 PD1 I/O nTRKO I 4 69 PD2 I/O nWP I 5 68 PD3 I/O nRDATA I 6 66 PD4 I/O nDSKCHG I 7 65 PD5 I/O nMEDIA_ID0 I 8 64 PD6 I/O (nMTR0) I/(0) 9 63 PD7 I/O nMEDIA_ID1 I 10 62 nACK I nDS1 0 11 61 BUSY I nMTR1 0 12 60 PE I nWDATA 0 13 59 SLCT I nWGATE 0 14 76 nAFD I/O nDENSEL 0 15 75 nERR I nHDSEL 0 16 74 nINIT I/O nDIR 0 17 73 nSLIN I/O nSTEP 0 These pins are outputs in mode PPFD2. Inputs in mode PPFD1 71 SERIAL PORT (UART) The FDC37C669 incorporates two full function UARTs. information on disabling, power down and changing the They are compatible with the NS16450, the 16450 ACE base address of the UARTs. The interrupt from a UART registers and the NS16550A. The UARTs perform is enabled by programming OUT2 of that UART to a logic serial-to-parallel conversion on received characters and "1". OUT2 being a logic "0" disables that UART's parallel-to-serial conversion on transmit characters. The interrupt. data rates are independently programmable from 115.2K baud down to 50 baud. The character options are REGISTER DESCRIPTION programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs Addressing of the accessible registers of the Serial Port is each contain a programmable baud rate generator that is shown below. The base addresses of the serial ports are capable of dividing the input clock or crystal by a number defined by the configuration registers (see Configuration from 1 to 65535. The UARTs are also capable of section). The Serial Port registers are located at supporting the MIDI data rate. Refer to the FDC37C669 sequentially increasing addresses above these base Configuration Registers for addresses. The FDC37C669 contains two serial ports, each of which contain a register set as described below. Table 31 - Addressing the Serial Port DLAB* A2 A1 A0 REGISTER NAME 0 0 0 0 Receive Buffer (read) 0 0 0 0 Transmit Buffer (write) 0 0 0 1 Interrupt Enable (read/write) X 0 1 0 Interrupt Identification (read) X 0 1 0 FIFO Control (write) X 0 1 1 Line Control (read/write) X 1 0 0 Modem Control (read/write) X 1 0 1 Line Status (read/write) X 1 1 0 Modem Status (read/write) X 1 1 1 Scratchpad (read/write) 1 0 0 0 Divisor LSB (read/write) 1 0 0 1 Divisor MSB (read/write) *NOTE: DLAB is Bit 7 of the Line Control Register 72 Bit 1 The following section describes the operation of the registers. This bit enables the Transmitter Holding Register Empty Interrupt when set to logic "1". RECEIVE BUFFER REGISTER (RB) Address Offset = 0H, DLAB = 0, READ ONLY Bit 2 This bit enables the Received Line Status Interrupt when This register holds the received incoming data byte. Bit 0 set to logic "1". The error sources causing the interrupt is the least significant bit, which is transmitted and are Overrun, Parity, Framing and Break. The Line Status received first. Received data is double buffered; this uses Register must be read to determine the source. an additional shift register to receive the serial data stream and convert it to a parallel 8 bit word which is Bit 3 transferred to the Receive Buffer register. The shift This bit enables the MODEM Status Interrupt when set to register is not accessible. logic "1". This is caused when one of the Modem Status Register bits changes state. TRANSMIT BUFFER REGISTER (TB) Address Offset = 0H, DLAB = 0, WRITE ONLY Bits 4 through 7 These bits are always logic "0". This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an FIFO CONTROL REGISTER (FCR) additional shift register (not accessible) to convert the 8 Address Offset = 2H, DLAB = X, WRITE bit data word to a serial format. This shift register is loaded from the Transmit Buffer when the transmission of This is a write only register at the same location as the the previous byte is complete. IIR. This register is used to enable and clear the FIFOs, set the RCVR FIFO trigger level. Note: DMA is not INTERRUPT ENABLE REGISTER (IER) supported. Address Offset = 1H, DLAB = 0, READ/WRITE Bit 0 The lower four bits of this register control the enables of Setting this bit to a logic "1" enables both the XMIT and the five interrupt sources of the Serial Port interrupt. It is RCVR FIFOs. Clearing this bit to a logic "0" disables possible to totally disable the interrupt system by resetting both the XMIT and RCVR FIFOs and clears all bytes from bits 0 through 3 of this register. Similarly, setting the both FIFOs. When changing from FIFO Mode to non- appropriate bits of this register to a high, selected FIFO (16450) mode, data is automatically cleared from interrupts can be enabled. Disabling the interrupt system the FIFOs. This bit must be a 1 when other bits in this inhibits the Interrupt Identification Register and disables register are written to or they will not be properly any Serial Port interrupt out of the FDC37C669. All other programmed. system functions operate in their normal manner, including the Line Status and MODEM Status Registers. Bit 1 The contents of the Interrupt Enable Register are Setting this bit to a logic "1" clears all bytes in the RCVR described below. FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing. Bit 0 This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic "1". 73 Bit 2 3. Transmitter Holding Register Empty Setting this bit to a logic "1" clears all bytes in the XMIT 4. MODEM Status (lowest priority) FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing. Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Bit 3 Identification Register (refer to Interrupt Control Table). Writing to this bit has no effect on the operation of the When the CPU accesses the IIR, the Serial Port freezes UART. The RXRDY and TXRDY pins are not available all interrupts and indicates the highest priority pending on this chip. interrupt to the CPU. During this CPU access, even if the Serial Port records new interrupts, the current indication Bit 4,5 does not change until access is completed. The contents Reserved of the IIR are described below. Bit 6,7 Bit 0 These bits are used to set the trigger level for the RCVR This bit can be used in either a hardwired prioritized or FIFO interrupt. polled environment to indicate whether an interrupt is INTERRUPT IDENTIFICATION REGISTER (IIR) pending. When bit 0 is a logic "0", an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate internal service routine. When bit 0 is a RCVR FIFO logic "1", no interrupt is pending. Trigger Level Bit 7 Bit 6 (BYTES) Bits 1 and 2 0 0 1 These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt 0 1 4 Control Table. 1 0 8 1 1 14 Bit 3 In non-FIFO mode, this bit is a logic "0". In FIFO mode this bit is set along with bit 2 when a timeout interrupt is Address Offset = 2H, DLAB = X, READ pending. Bits 4 and 5 By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of These bits of the IIR are always logic "0". priority interrupt exist. They are in descending order of priority: Bits 6 and 7 These two bits are set when the FIFO CONTROL 1. Receiver Line Status (highest priority) Register bit 0 equals 1. 2. Received Data Ready 74 Table 32 - Interrupt Control Table FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER INTERRUPT SET AND RESET FUNCTIONS PRIORITY INTERRUPT INTERRUPT INTERRUPT LEVEL TYPE SOURCE RESET BIT 3 BIT 2 BIT 1 BIT 0 CONTROL 0 0 0 1 - None None - 0 1 1 0 Highest Receiver Line Overrun Error, Reading the Line Status Parity Error, Status Register Framing Error or Break Interrupt 0 1 0 0 Second Received Data Receiver Data Read Receiver Available Available Buffer or the FIFO drops below the trigger level. 1 1 0 0 Second Character No Characters Reading the Timeout Have Been Receiver Buffer Indication Removed From or Register Input to the RCVR FIFO during the last 4 Char times and there is at least 1 char in it during this time 0 0 1 0 Third Transmitter Transmitter Reading the IIR Holding Register Holding Register Register (if Source Empty Empty of Interrupt) or Writing the Transmitter Holding Register 0 0 0 0 Fourth MODEM Status Clear to Send or Reading the Data Set Ready or MODEM Status Ring Indicator or Register Data Carrier Detect 75 LINE CONTROL REGISTER (LCR) checked (receive data) between the last data word bit and Address Offset = 3H, DLAB = 0, READ/WRITE the first stop bit of the serial data. (The parity bit is used to generate an even or odd number of 1s when the data This register contains the format information of the serial word bits and the parity bit are summed). line. The bit definitions are: Bit 4 Bits 0 and 1 Even Parity Select bit. When bit 3 is a logic "1" and bit 4 These two bits specify the number of bits in each is a logic "0", an odd number of logic "1"'s is transmitted transmitted or received serial character. The encoding of or checked in the data word bits and the parity bit. When bits 0 and 1 is as follows: bit 3 is a logic "1" and bit 4 is a logic "1" an even number of bits is transmitted and checked. BIT 1 BIT 0 WORD LENGTH Bit 5 0 0 5 Bits Stick Parity bit. When bit 3 is a logic "1" and bit 5 is a 0 1 6 Bits logic "1", the parity bit is transmitted and then detected by 1 0 7 Bits the receiver in the opposite state indicated by bit 4. 1 1 8 Bits Bit 6 Set Break Control bit. When bit 6 is a logic "1", the The Start, Stop and Parity bits are not included in the transmit data output (TXD) is forced to the Spacing or word length. logic "0" state and remains there (until reset by a low level bit 6) regardless of other transmitter activity. This feature Bit 2 enables the Serial Port to alert a terminal in a This bit specifies the number of stop bits in each communications system. transmitted or received serial character. The following table summarizes the information. Bit 7 Divisor Latch Access bit (DLAB). It must be set high NUMBER OF (logic "1") to access the Divisor Latches of the Baud Rate BIT 2 WORD LENGTH STOP BITS Generator during read or write operations. It must be set 0 -- 1 low (logic "0") to access the Receiver Buffer Register, the Transmitter Holding Register, or the Interrupt Enable 1 5 bits 1.5 Register. 1 6 bits 2 MODEM CONTROL REGISTER (MCR) 1 7 bits 2 Address Offset = 4H, DLAB = X, READ/WRITE 1 8 bits 2 This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The Note: The receiver will ignore all stop bits beyond the contents of the MODEM control register are described first, regardless of the number used in transmitting. below. Bit 3 Parity Enable bit. When bit 3 is a logic "1", a parity bit is generated (transmit data) or 76 Bit 0 This feature allows the processor to verify the transmit This bit controls the Data Terminal Ready (nDTR) output. and receive data paths of the Serial Port. In the When bit 0 is set to a logic "1", the nDTR output is diagnostic mode, the receiver and the transmitter forced to a logic "0". When bit 0 is a logic "0", the nDTR interrupts are fully operational. The MODEM Control output is forced to a logic "1". Interrupts are also operational but the interrupts' sources are now the lower four bits of the MODEM Control Bit 1 Register instead of the MODEM Control inputs. The This bit controls the Request To Send (nRTS) output. Bit interrupts are still controlled by the Interrupt Enable 1 affects the nRTS output in a manner identical to that Register. described above for bit 0. Bits 5 through 7 Bit 2 These bits are permanently set to logic zero. This bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or written by LINE STATUS REGISTER (LSR) the CPU. Address Offset = 5H, DLAB = X, READ/WRITE Bit 3 Bit 0 Output 2 (OUT2). This bit is used to enable an UART Data Ready (DR). It is set to a logic "1" whenever a interrupt. When OUT2 is a logic "0", the serial port complete incoming character has been received and interrupt output is forced to a high impedance state - transferred into the Receiver Buffer Register or the FIFO. disabled. When OUT2 is a logic "1", the serial port Bit 0 is reset to a logic "0" by reading all of the data in the interrupt outputs are enabled. Receive Buffer Register or the FIFO. Bit 1 Bit 4 This bit provides the loopback feature for diagnostic Overrun Error (OE). Bit 1 indicates that data in the testing of the Serial Port. When bit 4 is set to logic "1", Receiver Buffer Register was not read before the next character was transferred into the register, thereby the following occur: destroying the previous character. In FIFO mode, an 1. The TXD is set to the Marking State(logic "1"). overrunn error will occur only when the FIFO is full and 2. The receiver Serial Input (RXD) is disconnected. the next character has been completely received in the 3. The output of the Transmitter Shift Register is "looped shift register, the character in the shift register is back" into the Receiver Shift Register input. overwritten but not transferred to the FIFO. The OE 4. All MODEM Control inputs (nCTS, nDSR, nRI and indicator is set to a logic "1" immediately upon detection nDCD) are disconnected. of an overrun condition, and reset whenever the Line 5. The four MODEM Control outputs (nDTR, nRTS, Status Register is read. OUT1 and OUT2) are internally connected to the four MODEM Control inputs (nDSR, nCTS, RI and Bit 2 DCD) respectively. Parity Error (PE). Bit 2 indicates that the received data 6. The Modem Control output pins are forced inactive character does not have the correct even or odd parity, as high. selected by the even parity select bit. The PE is set to a 7. Data that is transmitted is immediately received. logic "1" upon detection of a parity error and is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. Bit 3 Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic "1" whenever the stop bit following the last data bit 77 Bit 5 or parity bit is detected as a zero bit (Spacing level). The FE is reset to a logic "0" whenever the Line Status Transmitter Holding Register Empty (THRE). Bit 5 Register is read. In the FIFO mode this error is indicates that the Serial Port is ready to accept a new associated with the particular character in the FIFO it character for transmission. In addition, this bit causes the applies to. This error is indicated when the associated Serial Port to issue an interrupt when the Transmitter character is at the top of the FIFO. The Serial Port will try Holding Register interrupt enable is set high. The THRE to resynchronize after a framing error. To do this, it bit is set to a logic "1" when a character is transferred assumes that the framing error was due to the next start from the Transmitter Holding Register into the Transmitter bit, so it samples this 'start' bit twice and then takes in the Shift Register. The bit is reset to logic "0" whenever the 'data'. CPU loads the Transmitter Holding Register. In the FIFO mode this bit is set when the XMIT FIFO is empty, it is Bit 4 cleared when at least 1 byte is written to the XMIT FIFO. Break Interrupt (BI). Bit 4 is set to a logic "1" whenever Bit 5 is a read only bit. the received data input is held in the Spacing state (logic "0") for longer than a full word transmission time (that is, Bit 6 the total time of the start bit + data bits + parity bits + stop Transmitter Empty (TEMT). Bit 6 is set to a logic "1" bits). The BI is reset after the CPU reads the contents of whenever the Transmitter Holding Register (THR) and the Line Status Register. In the FIFO mode this error is Transmitter Shift Register (TSR) are both empty. It is associated with the particular character in the FIFO it reset to logic "0" whenever either the THR or TSR applies to. This error is indicated when the associated contains a data character. Bit 6 is a read only bit. In the character is at the top of the FIFO. When break occurs FIFO mode this bit is set whenever the THR and TSR are only one zero character is loaded into the FIFO. both empty, Restarting after a break is received, requires the serial data (RXD) to be logic "1" for at least 1/2 bit time. Bit 7 This bit is permanently set to logic "0" in the 450 mode. Note: Bits 1 through 4 are the error conditions that In the FIFO mode, this bit is set to a logic "1" when there produce a Receiver Line Status Interrupt whenever any of is at least one parity error, framing error or break the corresponding conditions are detected and the indication in the FIFO. This bit is cleared when the LSR interrupt is enabled. is read if there are no subsequent errors in the FIFO. MODEM STATUS REGISTER (MSR) Address Offset = 6H, DLAB = X, READ/WRITE This 8 bit register provides the current state of the control lines from the MODEM (or peripheral device). In addition to this current state information, four bits of the MODEM Status Register (MSR) provide change information. These bits are set to logic "1" whenever a control input from the MODEM changes state. They are reset to logic "0" whenever the MODEM Status Register is read. 78 Bit 0 to logic "1", this bit is equivalent to OUT2 in the MCR. Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the SCRATCHPAD REGISTER (SCR) last time the MSR was read. Address Offset =7H, DLAB =X, READ/WRITE Bit 1 This 8 bit read/write register has no effect on the Delta Data Set Ready (DDSR). Bit 1 indicates that the operation of the Serial Port. It is intended as a nDSR input has changed state since the last time the scratchpad register to be used by the programmer to hold MSR was read. data temporarily. Bit 2 PROGRAMMABLE BAUD RATE GENERATOR (AND Trailing Edge of Ring Indicator (TERI). Bit 2 indicates DIVISOR LATCHES DLH, DLL) that the nRI input has changed from logic "0" to logic "1". The Serial Port contains a programmable Baud Rate Bit 3 Generator that is capable of taking any clock input (DC to Delta Data Carrier Detect (DDCD). Bit 3 indicates that 3 MHz) and dividing it by any divisor from 1 to 65535. the nDCD input to the chip has changed state. This output frequency of the Baud Rate Generator is 16x the Baud rate. Two 8 bit latches store the divisor in 16 bit NOTE: Whenever bit 0, 1, 2, or 3 is set to a logic "1", a binary format. These Divisor Latches must be loaded MODEM Status Interrupt is generated. during initialization in order to insure desired operation of the Baud Rate Generator. Upon loading either of the Bit 4 Divisor Latches, a 16 bit Baud counter is immediately This bit is the complement of the Clear To Send (nCTS) loaded. This prevents long counts on initial load. If a 0 is input. If bit 4 of the MCR is set to logic "1", this bit is loaded into the BRG registers the output divides the clock equivalent to nRTS in the MCR. by the number 3. If a 1 is loaded the output is the inverse of the input oscillator. If a two is loaded the output is a Bit 5 divide by 2 signal with a 50% duty cycle. If a 3 or greater This bit is the complement of the Data Set Ready (nDSR) is loaded the output is low for 2 bits and high for the input. If bit 4 of the MCR is set to logic "1", this bit is remainder of the count. The input clock to the BRG is the equivalent to DTR in the MCR. 24 MHz crystal divided by 13, giving a 1.8462 MHz clock. Bit 6 Table 33 shows the baud rates possible with a 1.8462 This bit is the complement of the Ring Indicator (nRI) MHz crystal. input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT1 in the MCR. Effect Of The Reset on Register File Bit 7 The Reset Function Table (Table 34) details the effect of This bit is the complement of the Data Carrier Detect the Reset input on each of the registers of the Serial Port. (nDCD) input. If bit 4 of the MCR is set 79 FIFO INTERRUPT MODE OPERATION B. Character times are calculated by using the RCLK input for a clock signal (this makes the delay When the RCVR FIFO and receiver interrupts are proportional to the baudrate). enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR interrupts occur as follows: C. When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one A. The receive data available interrupt will be issued character from the RCVR FIFO. when the FIFO has reached its programmed trigger level; it is cleared as soon as the FIFO drops below its D. When a timeout interrupt has not occurred the timeout programmed trigger level. timer is reset after a new character is received or after the CPU reads the RCVR FIFO. B. The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is cleared When the XMIT FIFO and transmitter interrupts are when the FIFO drops below the trigger level. enabled (FCR bit 0 = "1", IER bit 1 = "1"), XMIT interrupts occur as follows: C. The receiver line status interrupt (IIR=06H), has higher priority than the received data available A. The transmitter holding register interrupt (02H) occurs (IIR=04H) interrupt. when the XMIT FIFO is empty; it is cleared as soon as the transmitter holding register is written to (1 of 16 D. The data ready bit (LSR bit 0)is set as soon as a characters may be written to the XMIT FIFO while character is transferred from the shift register to the servicing this interrupt) or the IIR is read. RCVR FIFO. It is reset when the FIFO is empty. B. The transmitter FIFO empty indications will be When RCVR FIFO and receiver interrupts are enabled, delayed 1 character time minus the last stop bit time RCVR FIFO timeout interrupts occur as follows: whenever the following occurs: THRE=1 and there have not been at least two bytes at the same time in A. A FIFO timeout interrupt occurs if all the following the transmitter FIFO since the last THRE=1. The conditions exist: transmitter interrupt after changing FCR0 will be - At least one character is in the FIFO immediate, if it is enabled. - The most recent serial character received was longer than 4 continuous character times ago. (If 2 Character timeout and RCVR FIFO trigger level interrupts stop bits are programmed, the second one is have the sme priority as the current received data included in this time delay.) available interrupt; XMIT FIFO empty has the same - The most recent CPU read of the FIFO was longer priority as the current transmitter holding register empty than 4 continuous character times ago. interrupt. This will cause a maximum character received to FIFO POLLED MODE OPERATION interrupt issued delay of 160 msec at 300 BAUD with a 12 bit character. With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of operation. Since the RCVR and 80 mode, the IIR is not affected since EIR bit 2=0. XMITTER are controlled separately, either one or both can be in the polled mode of operation. - Bit 5 indicates when the XMIT FIFO is empty. - Bit 6 indicates that both the XMIT FIFO and shift In this mode, the user's program will check RCVR and register are empty. XMITTER status via the LSR. LSR definitions for the - Bit 7 indicates whether there are any errors in the FIFO Polled Mode are as follows: RCVR FIFO. - Bit 0=1 as long as there is one byte in the RCVR There is no trigger level reached or timeout condition FIFO. indicated in the FIFO Polled Mode, however, the RCVR - Bits 1 to 4 specify which error(s) have occurred. and XMIT FIFOs are still fully capable of holding Character error status is handled the same way as characters. when in the interrupt Table 33 - Baud Rates Using 1.8462 MHz Clock (24 MHz/13) DESIRED DIVISOR USED TO PERCENT ERROR DIFFERENCE CROC: GENERATE 16X CLOCK BETWEEN DESIRED AND ACTUAL* BAUD RATE BIT 7 OR 6 50 2307 0.03 X 75 1538 0.03 X 110 1049 0.005 X 134.5 858 0.01 X 150 769 0.03 X 300 384 0.16 X 600 192 0.16 X 1200 96 0.16 X 1800 64 0.16 X 2000 58 0.5 X 2400 48 0.16 X 3600 32 0.16 X 4800 24 0.16 X 7200 16 0.16 X 9600 12 0.16 X 19200 6 0.16 X 38400 3 0.16 X 57600 2 1.6 X 115200 1 0.16 X 230400 32770 0.16 1 460800 32769 0.16 1 81 Table 34 - Reset Function Table REGISTER/SIGNAL RESET CONTROL RESET STATE Interrupt Enable Register RESET All bits low Interrupt Identification Reg. RESET Bit 0 is high; Bits 1 thru 7 low FIFO Control RESET All bits low Line Control Reg. RESET All bits low MODEM Control Reg. RESET All bits low Line Status Reg. RESET All bits low except 5, 6 high MODEM Status Reg. RESET Bits 0 - 3 low; Bits 4 - 7 input TXD1, TXD2 RESET High INTRPT (RCVR errs) RESET/Read LSR Low INTRPT (RCVR Data Ready) RESET/Read RBR Low INTRPT (THRE) RESET/ReadIIR/Write THR Low OUT2B RESET High RTSB RESET High DTRB RESET High OUT1B RESET High RCVR FIFO RESET/FCR1*FCR0/FCR0 All Bits Low XMIT FIFO RESET/FCR1*FCR0/FCR0 All Bits Low 82 Table 35 - Register Summary for an Individual UART Channel REGISTER REGISTER ADDRESS* REGISTER NAME SYMBOL BIT 0 BIT 1 ADDR = 0 Receive Buffer Register (Read Only) RBR Data Bit 0 Data Bit 1 DLAB = 0 (Note 1) ADDR = 0 Transmitter Holding Register (Write THR Data Bit 0 Data Bit 1 DLAB = 0 Only) ADDR = 1 Interrupt Enable Register IER Enable Enable DLAB = 0 Received Transmitter Data Holding Available Register Interrupt Empty (ERDAI) Interrupt (ETHREI) ADDR = 2 Interrupt Ident. Register (Read Only) IIR "0" if Interrupt Interrupt ID Pending Bit ADDR = 2 FIFO Control Register (Write Only) FCR FIFO Enable RCVR FIFO Reset Word Length ADDR = 3 Line Control Register LCR Word Length Select Bit 0 Select Bit 1 (WLS0) (WLS1) ADDR = 4 MODEM Control Register MCR Data Request to Terminal Send (RTS) Ready (DTR) Data Ready ADDR = 5 Line Status Register LSR Overrun Error (DR) (OE) Delta Clear to ADDR = 6 MODEM Status Register MSR Delta Data Send (DCTS) Set Ready (DDSR) ADDR = 7 Scratch Register (Note 4) SCR Bit 0 Bit 1 ADDR = 0 Divisor Latch (LS) DDL Bit 0 Bit 1 DLAB = 1 ADDR = 1 Divisor Latch (MS) DLM Bit 8 Bit 9 DLAB = 1 *DLAB is Bit 7 of the Line Control Register (ADDR = 3). Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received. Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty. 83 Table 35 - Register Summary for an Individual UART Channel (continued) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Enable 0 Enable 0 0 0 Receiver Line MODEM Status Status Interrupt Interrupt (ELSI) (EMSI) FIFOs Interrupt ID Bit Interrupt ID Bit 0 0 FIFOs Enabled (Note (Note 5) Enabled (Note 5) 5) XMIT FIFO DMA Mode Reserved Reserved RCVR Trigger RCVR Trigger Reset Select (Note LSB MSB 6) Divisor Latch Number of Parity Enable Even Parity Stick Parity Set Break Access Bit Stop Bits (PEN) Select (EPS) (DLAB) (STB) OUT1 OUT2 Loop 0 0 0 (Note 3) (Note 3) Parity Error Framing Error Break Transmitter Transmitter Error in RCVR (PE) (FE) Interrupt (BI) Holding Empty (TEMT) FIFO (Note 5) Register (Note 2) (THRE) Data Carrier Trailing Edge Delta Data Clear to Send Data Set Ring Indicator Detect (DCD) Ring Indicator Carrier Detect (CTS) Ready (DSR) (RI) (TERI) (DDCD) Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Note 3: This bit no longer has a pin associated with it. Note 4: When operating in the XT mode, this register is not available. Note 5: These bits are always zero in the non-FIFO mode. Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip. 84 NOTES ON SERIAL PORT OPERATION This one character Tx interrupt delay will remain FIFO MODE OPERATION: active until at least two bytes have been loaded into the FIFO, concurrently. When the Tx FIFO empties GENERAL after this condition, the Tx interrupt will be activated without a one character delay. The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected. Rx support functions and operation are quite different from those described for the transmitter. The Rx FIFO TX AND RX FIFO OPERATION receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if The Tx portion of the UART transmits data through TXD Rx interrupts are enabled, the UART will issue an as soon as the CPU loads a byte into the Tx FIFO. The interrupt to the CPU. The Rx FIFO will continue to store UART will prevent loads to the Tx FIFO if it currently bytes until it holds 16 of them. It will not accept any more holds 16 characters. Loading to the Tx FIFO will again data when it is full. Any more data entering the Rx shift be enabled as soon as the next character is transferred to register will set the Overrun Error flag. Normally, the the Tx shift register. These capabilities account for the FIFO depth and the programmable trigger levels will give largely autonomous operation of the Tx. the CPU ample time to empty the Rx FIFO before an overrun occurs. The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt whenever the Tx One side-effect of having a Rx FIFO is that the selected FIFO is empty and the Tx interrupt is enabled, except in interrupt trigger level may be above the data level in the the following instance. Assume that the Tx FIFO is empty FIFO. This could occur when data at the end of the block and the CPU starts to load it. When the first byte enters contains fewer bytes than the trigger level. No interrupt the FIFO the Tx FIFO empty interrupt will transition from would be issued to the CPU and the data would remain in active to inactive. Depending on the execution speed of the UART. To prevent the software from having to the service routine software, the UART may be able to check for this situation the chip incorporates a transfer this byte from the FIFO to the shift register before timeout interrupt. the CPU loads another byte. If this happens, the Tx FIFO will be empty again and typically the UART's interrupt line The timeout interrupt is activated when there is a least would transition to the active state. This could cause a one byte in the Rx FIFO, and neither the CPU nor the Rx system with an interrupt control unit to record a Tx FIFO shift register has accessed the Rx FIFO within 4 empty condition, even though the CPU is currently character times of the last byte. The timeout interrupt is servicing that interrupt. cleared or reset when the CPU reads the Rx FIFO or another character enters it. Therefore, after the first byte has been loaded into the FIFO the UART will wait one serial character These FIFO related features allow optimization of transmission time before issuing a new Tx FIFO CPU/UART transactions and are especially useful given empty interrupt. the higher baud rate capability (256 kbaud). 85 INFRARED INTERFACE The FDC37C669's infrared interface provides a two- the duration of the serial bit time. A one is signaled by way wireless communications port using infrared as a sending no transmission the bit time. Please refer to transmission medium. Two infrared implementations the AC timing for the parameters of the ASKIR have been provided in the FDC37C669, IrDA and waveform. Amplitude Shift Keyed IR. If the Half Duplex option is chosen, there is a time-out IrDA allows serial communication at baud rates up to when the direction of the transmission is changed. This 115K Baud. Each word is sent serially beginning with a time-out starts at the last bit transferred during a zero value start bit. A zero is signaled by sending a transmission and blocks the receiver input until the time- single infrared pulse at the beginning of the serial bit time. out expires. If the transmit buffer is loaded with more A one is signaled by sending no infrared pulse during the data before the time-out expires, the timer is restarted bit time. Please refer to the AC timing for the parameters after the new byte is transmitted. If data is loaded into the of these pulses and the IrDA waveform. transmit buffer while a character is being received, the transmission will not start until the time-out expires after The Amplitude Shift Keyed infrared allows serial the last receive bit has been received. If the start bit of communication at baud rates up to 19.2K Baud. Each another character is received during this time-out, the word is sent serially beginning with a zero value start timer is restarted after the new character is received. The bit. A zero is signaled by sending a 500kHz waveform time-out is four character times. A character time is for defined as 10 bit times regardless of the actual word length being used. 86 PARALLEL PORT The FDC37C669 incorporates an IBM XT/AT The FDC37C669 also incorporates SMSC's ChiProtect compatible parallel port. The FDC37C669 supports the circuitry, which prevents possible damage to the parallel optional PS/2 type bi-directional parallel port (SPP), the port due to printer power-up. Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the The functionality of the Parallel Port is achieved through FDC37C669 Configuration Registers and FDC37C669 the use of eight addressable ports, with their Hardware Configuration description for information on associated registers and control gating. The control and disabling, power down, changing the base address of the data port are read/write by the CPU, the status port is parallel port, and selecting the mode of operation. read/write in the EPP mode. The address map of the Parallel Port is shown below: DATA PORT BASE ADDRESS + 00H EPP DATA PORT 0 BASE ADDRESS + 04H STATUS PORT BASE ADDRESS + 01H EPP DATA PORT 1 BASE ADDRESS + 05H CONTROL PORT BASE ADDRESS + 02H EPP DATA PORT 2 BASE ADDRESS + 06H EPP ADDR PORT BASE ADDRESS + 03H EPP DATA PORT 3 BASE ADDRESS + 07H The bit map of these registers is: D0 D1 D2 D3 D4 D5 D6 D7 Note DATA PORT PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 1 STATUS TMOUT 0 0 nERR SLCT PE nACK nBUSY 1 PORT CONTROL STROBE AUTOFD nINIT SLC IRQE PCD 0 0 1 PORT EPP ADDR PD0 PD1 PD2 PD3 PD4 PD5 PD6 AD7 2,3 PORT EPP DATA PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2,3 PORT 0 EPP DATA PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2,3 PORT 1 EPP DATA PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2,3 PORT 2 EPP DATA PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2,3 PORT 3 Note 1: These registers are available in all modes. Note 2: These registers are only available in EPP mode. Note 3: For EPP mode, IOCHRDY must be connected to the ISA bus. 87 Table 36 - Parallel Port Connector HOST CONNECTOR PIN NUMBER STANDARD EPP ECP 1 77 nStrobe nWrite nStrobe 2-9 71-68, 66-63 PData<0:7> PData<0:7> PData<0:7> 10 62 nAck Intr nAck 11 61 Busy nWait Busy, PeriphAck(3) 12 60 PE (NU) PError, nAckReverse(3) 13 59 Select (NU) Select 14 76 nAutofd nDatastb nAutoFd, HostAck(3) 15 75 nError (NU) nFault(1) nPeriphRequest(3) 16 74 nInit (NU) nInit(1) nReverseRqst(3) 17 73 nSelectin nAddrstrb nSelectIn(1,3) (1) = Compatible Mode (3) = High Speed Mode Note: For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.09, Jan. 7, 1993. This document is available from Microsoft. 88 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP BIT 3 nERR - nERROR MODES The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic O means an DATA PORT error has been detected; a logic 1 means no error has ADDRESS OFFSET = 00H been detected. The Data Port is located at an offset of '00H' from the BIT 4 SLCT - PRINTER SELECTED STATUS base address. The data register is cleared at initialization The level on the SLCT input is read by the CPU as bit 4 by RESET. During a WRITE operation, the Data of the Printer Status Register. A logic 1 means the printer Register latches the contents of the data bus with the is on line; a logic 0 means it is not selected. rising edge of the nIOW input. The contents of this register are buffered (non inverting) and output onto the BIT 5 PE - PAPER END PD0 - PD7 ports. During a READ operation in SPP The level on the PE input is read by the CPU as bit 5 of mode, PD0 - PD7 ports are buffered (not latched) and the Printer Status Register. A logic 1 indicates a paper output to the host CPU. end; a logic 0 indicates the presence of paper. STATUS PORT BIT 6 nACK - nACKNOWLEDGE ADDRESS OFFSET = 01H The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic 0 means that the The Status Port is located at an offset of '01H' from the printer has received a character and can now accept base address. The contents of this register are latched another. A logic 1 means that it is still processing the last for the duration of an nIOR read cycle. The bits of the character or has not received the data. Status Port are defined as follows: BIT 7 nBUSY - nBUSY BIT 0 TMOUT - TIME OUT The complement of the level on the nBUSY input is read This bit is valid in EPP mode only and indicates that a 10 by the CPU as bit 7 of the Printer Status Register. A logic usec time out has occured on the EPP bus. A logic O 0 in this bit means that the printer is busy and cannot means that no time out error has occured; a logic 1 accept a new character. A logic 1 means that it is ready means that a time out error has been detected. This bit is to accept the next character. cleared by a RESET. Writing a one to this bit clears the time out status bit. On a write, this bit is self clearing and CONTROL PORT does not require a write of a zero. Writing a zero to this ADDRESS OFFSET = 02H bit has no effect. The Control Port is located at an offset of '02H' from the BITS 1, 2 - are not implemented as register bits, during a base address. The Control Register is initialized by the read of the Printer Status Register these bits are a low RESET input, bits 0 to 5 only being affected; bits 6 and 7 level. are hard wired low. 89 BIT 0 STROBE - STROBE IOR causes an EPP ADDRESS READ cycle to be This bit is inverted and output onto the nSTROBE output. performed and the data output to the host CPU, the deassertion of ADDRSTB latches the PData for the BIT 1 AUTOFD - AUTOFEED duration of the IOR cycle. This register is only available This bit is inverted and output onto the nAUTOFD output. in EPP mode. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed. EPP DATA PORT 0 ADDRESS OFFSET = 04H BIT 2 nINIT - nINITIATE OUTPUT This bit is output onto the nINIT output without inversion. The EPP Data Port 0 is located at an offset of '04H' from the base address. The data register is cleared at BIT 3 SLCTIN - PRINTER SELECT INPUT initialization by RESET. During a WRITE operation, the This bit is inverted and output onto the nSLCTIN output. contents of DB0-DB7 are buffered (non inverting) and A logic 1 on this bit selects the printer; a logic 0 means output onto the PD0 - PD7 ports, the leading edge of the printer is not selected. nIOW causes an EPP DATA WRITE cycle to be performed, the trailing edge of IOW latches the data for BIT 4 IRQE - INTERRUPT REQUEST ENABLE the duration of the EPP write cycle. During a READ The interrupt request enable bit when set to a high level operation, PD0 - PD7 ports are read, the leading edge of may be used to enable interrupt requests from the IOR causes an EPP READ cycle to be performed and the Parallel Port to the CPU. An interrupt request is data output to the host CPU, the deassertion of generated on the IRQ port by a positive going nACK DATASTB latches the PData for the duration of the IOR input. When the IRQE bit is programmed low the IRQ is cycle. This register is only available in EPP mode. disabled. EPP DATA PORT 1/ADDRESS OFFSET = 05H BIT 5 PCD - PARALLEL CONTROL DIRECTION Parallel Control Direction is valid in extended mode only The EPP Data Port 1 is located at an offset of '05H' from (CR#1<3>=0). In printer mode, the direction is always the base address. Refer to EPP DATA PORT 0 for a out regardless of the state of this bit. In bi-directional description of operation. This register is only available in mode, a logic 0 means that the printer port is in output EPP mode. mode (write); a logic 1 means that the printer port is in input mode (read). EPP DATA PORT 2/ADDRESS OFFSET = 06H Bits 6 and 7 during a read are a low level, and cannot be The EPP Data Port 2 is located at an offset of '06H' from written. the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP ADDRESS PORT EPP mode. ADDRESS OFFSET = 03H EPP DATA PORT 3 The EPP Address Port is located at an offset of '03H' ADDRESS OFFSET = 07H from the base address. The address register is cleared The EPP Data Port 3 is located at an offset of '07H' from at initialization by RESET. During a WRITE operation, the the base address. Refer to EPP DATA PORT 0 for a contents of DB0-DB7 are buffered (non inverting) and description of operation. This register is only available in output onto the PD0 - PD7 ports, the leading edge of EPP mode. nIOW causes an EPP ADDRESS WRITE cycle to be performed, the trailing edge of IOW latches the data for EPP 1.9 OPERATION the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read, the leading edge of When the EPP mode is selected in the configuration 90 register, the standard and bi-directional modes are also changing the state of nDATASTB, nWRITE or available. If no EPP Read, Write or Address cycle is nADDRSTB. The write can complete once nWAIT currently executing, then the PDx bus is in the standard is determined inactive. or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and Write Sequence of operation direction is controlled by PCD of the Control port. 1. The host selects an EPP register, places data on the In EPP mode, the system timing is closely coupled to the SData bus and drives nIOW active. EPP timing. For this reason, a watchdog timer is required 2. The chip drives IOCHRDY inactive (low). to prevent system lockup. The timer indicates if more 3. If WAIT is not asserted, the chip must wait until than 10usec have elapsed from the start of the EPP cycle WAIT is asserted. (nIOR or nIOW asserted) to nWAIT being deasserted 4. The chip places address or data on PData bus, (after command). If a time-out occurs, the current EPP clears PDIR, and asserts nWRITE. cycle is aborted and the time-out condition is indicated in 5. Chip asserts nDATASTB or nADDRSTRB indicating Status bit 0. that PData bus contains valid information, and the WRITE signal is valid. During an EPP cycle, if STROBE is active, it overrides 6. Peripheral deasserts nWAIT, indicating that any the EPP write signal forcing the PDx bus to always be in setup requirements have been satisfied and the chip a write mode and the nWRITE signal to always be may begin the termination phase of the cycle. asserted. 7. a) The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the Software Constraints termination phase. If it has not already done so, the peripheral should latch the information byte Before an EPP cycle is executed, the software must now. ensure that the control register bit PCD is a logic "0" (i.e. b) The chip latches the data from the SData bus a 04H or 05H should be written to the Control port). If the for the PData bus and asserts (releases) user leaves PCD as a logic "1", and attempts to perform IOCHRDY allowing the host to complete the an EPP write, the chip is unable to perform the write write cycle. (because PCD is a logic "1") and will appear to perform 8. Peripheral asserts nWAIT, indicating to the host that an EPP read on the parallel bus, no error is indicated. any hold time requirements have been satisfied and acknowledging the termination of the cycle. EPP 1.9 Write 9. Chip may modify nWRITE and nPDATA in preparation for the next cycle. The timing for a write operation (address or data) is shown in timing diagram EPP 1.9 Write Data or Address EPP 1.9 Read cycle. IOCHRDY is driven active low at the start of each EPP write and is released when it has been determined The timing for a read operation (data) is shown in timing that the write cycle can complete. The write cycle can diagram EPP Read Data cycle. IOCHRDY is driven complete under the following circumstances: active low at the start of each EPP read and is released when it has been determined that the read cycle can 1. If the EPP bus is not ready (nWAIT is active low) complete. The read cycle can complete under the when nDATASTB or nADDRSTB goes active then following circumstances: the write can complete when nWAIT goes inactive high. 1. If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can 2. If the EPP bus is ready (nWAIT is inactive high) complete when nWAIT goes inactive high. then the chip must wait for it to go active low before 91 2. If the EPP bus is ready (nWAIT is inactive high) to prevent system lockup. The timer indicates if more then the chip must wait for it to go active low before than 10usec have elapsed from the start of the EPP cycle changing the state of WRITE or before nDATASTB (nIOR or nIOW asserted) to the end of the cycle nIOR goes active. The read can complete once nWAIT is or nIOW deasserted). If a time-out occurs, the current determined inactive. EPP cycle is aborted and the time-out condition is indicated in Status bit 0. Read Sequence of Operation Software Constraints 1. The host selects an EPP register and drives nIOR active. Before an EPP cycle is executed, the software must 2. The chip drives IOCHRDY inactive (low). ensure that the control register bits D0, D1 and D3 are set 3. If WAIT is not asserted, the chip must wait until to zero. Also, bit D5 (PCD) is a logic "0" for an EPP write WAIT is asserted. or a logic "1" for and EPP read. 4. The chip tri-states the PData bus and deasserts nWRITE. EPP 1.7 Write 5. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the The timing for a write operation (address or data) is nWRITE signal is valid. shown in timing diagram EPP 1.7 Write Data or Address 6. Peripheral drives PData bus valid. cycle. IOCHRDY is driven active low when nWAIT is 7. Peripheral deasserts nWAIT, indicating that active low during the EPP cycle. This can be used to PData is valid and the chip may begin the extend the cycle time. The write cycle can complete termination phase of the cycle. when nWAIT is inactive high. 8. a) The chip latches the data from the PData bus for the SData bus, deasserts nDATASTB or Write Sequence of Operation nADDRSTRB, this marks the beginning of the termination phase. 1. The host sets PDIR bit in the control register to a b) The chip drives the valid data onto the SData logic "0". This asserts nWRITE. bus and asserts (releases) IOCHRDY allowing 2. The host selects an EPP register, places data on the the host to complete the read cycle. SData bus and drives nIOW active. 9. Peripheral tri-states the PData bus and asserts 3. The chip places address or data on PData bus. nWAIT, indicating to the host that the PData bus is 4. Chip asserts nDATASTB or nADDRSTRB indicating tri-stated. that PData bus contains valid information, and the 10. Chip may modify nWRITE, PDIR and nPDATA in WRITE signal is valid. preparation for the next cycle. 5. If nWAIT is asserted, IOCHRDY is deasserted until the peripheral deasserts nWAIT or a time-out EPP 1.7 OPERATION occurs. 6. When the host deasserts nI0W the chip deasserts When the EPP 1.7 mode is selected in the configuration nDATASTB or nADDRSTRB and latches the data register, the standard and bi-directional modes are also from the SData bus for the PData bus. available. If no EPP Read, Write or Address cycle is 7. Chip may modify nWRITE, PDIR and nPDATA in currently executing, then the PDx bus is in the standard preparation of the next cycle. or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required 92 EPP 1.7 Read The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. IOCHRDY is driven active low when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The read cycle can complete when nWAIT is inactive high. Read Sequence of Operation 1. The host sets PDIR bit in the control register to a logic "1". This deasserts nWRITE and tri-states the PData bus. 2. The host selects an EPP register and drives nIOR active. 3. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid. 4. If nWAIT is asserted, IOCHRDY is deasserted until the peripheral deasserts nWAIT or a time-out occurs. 5. The Peripheral drives PData bus valid. 6. The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. 7. When the host deasserts nI0R the chip deasserts nDATASTB or nADDRSTRB. 8. Peripheral tri-states the PData bus. 9. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle. Table 37 - EPP Pin Descriptions EPP SIGNAL EPP NAME TYPE EPP DESCRIPTION nWRITE nWrite O This signal is active low. It denotes a write operation. PD<0:7> Address/Data I/O Bi-directional EPP byte wide address and data bus. INTR Interrupt I This signal is active high and positive edge triggered. (Pass through with no inversion, Same as SPP). WAIT nWait I This signal is active low. It is driven inactive as a positive acknowledgement from the device that the transfer of data is completed. It is driven active as an indication that the device is ready for the next transfer. DATASTB nData Strobe O This signal is active low. It is used to denote data read or write operation. RESET nReset O This signal is active low. When driven active, the EPP device is reset to its initial operational mode. 93 EPP SIGNAL EPP NAME TYPE EPP DESCRIPTION ADDRSTB nAddress O This signal is active low. It is used to denote address read or Strobe write operation. PE Paper End I Same as SPP mode. SLCT Printer Selected I Same as SPP mode. Status nERR Error I Same as SPP mode. PDIR Parallel Port O This output shows the direction of the data transfer on the Direction parallel port bus. A low means an output/write condition and a high means an input/read condition. This signal is normally a low (output/write) unless PCD of the control register is set or if an EPP read cycle is in progress. Note 1: SPP and EPP can use 1 common register. Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct EPP read cycles, PCD is required to be a low. 94 EXTENDED CAPABILITIES PARALLEL PORT PWord A port word; equal in size to the width of the ISA interface. For this implementation, PWord ECP provides a number of advantages, some of which is always 8 bits. are listed below. The individual features are explained in 1 A high level. greater detail in the remainder of this section. 0 A low level. • High performance half-duplex forward and reverse channel These terms may be considered synonymous: • Interlocked handshake, for fast reliable transfer • PeriphClk, nAck • Optional single byte RLE compression for improved • HostAck, nAutoFd throughput (64:1) • PeriphAck, Busy • Channel addressing for low-cost peripherals • nPeriphRequest, nFault • Maintains link and data layer separation • nReverseRequest, nInit • Permits the use of active output drivers • nAckReverse, PError • Permits the use of adaptive signal timing • Xflag, Select • Peer-to-peer capability • ECPMode, nSelectln • HostClk, nStrobe Vocabulary The following terms are used in this document: Reference Document: assert When a signal asserts it transitions to a IEEE 1284 Extended Capabilities Port Protocol and ISA "true" state, when a signal deasserts it Interface Standard, Rev 1.09, Jan 7, 1993. This transitions to a "false" state. document is available from Microsoft. forward Host to Peripheral communication. reverse Peripheral to Host communication. The bit map of the Extended Parallel Port registers is: D7 D6 D5 D4 D3 D2 D1 D0 Note data PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 ecpAFifo Addr/RLE Address or RLE field 2 dsr nBusy nAck PError Select nFault 0 0 0 1 dcr 0 0 Direction ackIntEn SelectIn nInit autofd strobe 1 cFifo Parallel Port Data FIFO 2 ecpDFifo ECP Data FIFO 2 tFifo Test FIFO 2 cnfgA 0 0 0 1 0 0 0 0 cnfgB compress intrValue 0 0 0 0 0 0 nErrIntrEn serviceIntr ecr MODE dmaEn full empty Note 1: These registers are available in all modes. Note 2: All FIFOs use one common 16 byte FIFO. ISA IMPLEMENTATION STANDARD the Extended Capabilities Port (ECP). All ISA devices supporting ECP must meet the requirements contained in This specification describes the standard ISA interface to this section or the port will not be supported by Microsoft. 95 For a description of the ECP Protocol, please refer to the it provides an automatic high burst-bandwidth channel IEEE 1284 Extended Capabilities Port Protocol and ISA that supports DMA for ECP in both the forward and Interface Standard, Rev. 1.09, Jan.7, 1993. This reverse directions. document is available from Microsoft. Small FIFOs are employed in both forward and reverse Description directions to smooth data flow and improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes The port is software and hardware compatible with deep. The port supports an automatic handshake for the existing parallel ports so that it may be used as a standard parallel port to improve compatibility mode standard LPT port if ECP is not required. The port is transfer speed. designed to be simple and requires a small number of gates to implement. It does not do any "protocol" The port also supports run length encoded (RLE) negotiation, rather decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. Hardware support for compression is optional. 96 Table 38 - ECP Pin Descriptions NAME TYPE DESCRIPTION nStrobe O During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). PData 7:0 I/O Contains address or data or RLE data. nAck I Indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse. PeriphAck (Busy) I This signal deasserts to indicate that the peripheral can accept data. This signal handshakes with nStrobe in the forward direction. In the reverse direction this signal indicates whether the data lines contain ECP command information or data. The peripheral uses this signal to flow control in the forward direction. It is an "interlocked" handshake with nStrobe. PeriphAck also provides command information in the reverse direction. PError I Used to acknowledge a change in the direction the transfer (asserted = (nAckReverse) forward). The peripheral drives this signal low to acknowledge nReverseRequest. It is an "interlocked" handshake with nReverseRequest. The host relies upon nAckReverse to determine when it is permitted to drive the data bus. Select I Indicates printer on line. nAutoFd O Requests a byte of data from the peripheral when asserted, handshaking (HostAck) with nAck in the reverse direction. In the forward direction this signal indicates whether the data lines contain ECP address or data. The host drives this signal to flow control in the reverse direction. It is an "interlocked" handshake with nAck. HostAck also provides command information in the forward phase. nFault I Generates an error interrupt when asserted. This signal provides a (nPeriphRequest) mechanism for peer-to-peer communication. This signal is valid only in the forward direction. During ECP Mode the peripheral is permitted (but not required) to drive this pin low to request a reverse transfer. The request is merely a "hint" to the host; the host has ultimate control over the transfer direction. This signal would be typically used to generate an interrupt to the host CPU. nInit O Sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. The peripheral is only allowed to drive the bi-directional data bus while in ECP Mode and HostAck is low and nSelectIn is high. nSelectIn O Always deasserted in ECP mode. 97 Register Definitions avoid conflict with standard ISA devices. The port is equivalent to a generic parallel port interface and may be The register definitions are based on the standard IBM operated in that mode. The port registers vary depending addresses for LPT. All of the standard printer ports are on the mode field in the ecr. The table below lists these supported. The additional registers attach to an upper bit dependencies. Operation of the devices in modes other decode of the standard LPT port definition to that those specified is undefined. Table 39 - ECP Register Definitions NAME ADDRESS (Note 1) ECP MODES FUNCTION data +000h R/W 000-001 Data Register ecpAFifo +000h R/W 011 ECP FIFO (Address) dsr +001h R/W All Status Register dcr +002h R/W All Control Register cFifo +400h R/W 010 Parallel Port Data FIFO ecpDFifo +400h R/W 011 ECP FIFO (DATA) tFifo +400h R/W 110 Test FIFO cnfgA +400h R 111 Configuration Register A cnfgB +401h R/W 111 Configuration Register B ecr +402h R/W All Extended Control Register Note 1: These addresses are added to the parallel port base address as selected by configuration register or jumpers. Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition. Table 40 - Mode Descriptions MODE DESCRIPTION* 000 SPP mode 001 PS/2 Parallel Port mde 010 Parallel Port Data FIFO mode 011 ECP Parallel Port mode 100 EPP mode (If this option is enabled in the configuration registers) 101 (Reserved) 110 Test mode 111 Configuration mode *Refer to ECR Register Description 98 DATA and ecpAFifo PORT BIT 5 PError ADDRESS OFFSET = 00H The level on the PError input is read by the CPU as bit 5 of the Device Status Register. Printer Status Register. Modes 000 and 001 (Data Port) BIT 6 nAck The Data Port is located at an offset of '00H' from the The level on the nAck input is read by the CPU as bit 6 base address. The data register is cleared at initialization of the Device Status Register. by RESET. During a WRITE operation, the Data Register latches the contents of the data bus on the rising BIT 7 nBusy edge of the nIOW input. The contents of this register The complement of the level on the BUSY input is read are buffered (non inverting) and output onto the PD0 - by the CPU as bit 7 of the Device Status Register. PD7 ports. During a READ operation, PD0 - PD7 ports are read and output to the host CPU. DEVICE CONTROL REGISTER (dcr) ADDRESS OFFSET = 02H Mode 011 (ECP FIFO - Address/RLE) The Control Register is located at an offset of '02H' from A data byte written to this address is placed in the FIFO the base address. The Control Register is initialized to and tagged as an ECP Address/RLE. The hardware at zero by the RESET input, bits 0 to 5 only being affected; the ECP port transmits this byte to the peripheral bits 6 and 7 are hard wired low. automatically. The operation of this register is only defined for the forward direction (direction is 0). Refer to BIT 0 STROBE - STROBE the ECP Parallel Port Forward Timing Diagram, located in This bit is inverted and output onto the nSTROBE output. the Timing Diagrams section of this data sheet. BIT 1 AUTOFD - AUTOFEED DEVICE STATUS REGISTER (dsr) This bit is inverted and output onto the nAUTOFD output. ADDRESS OFFSET = 01H A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed. The Status Port is located at an offset of '01H' from the base address. Bits 0 - 2 are not implemented as register BIT 2 nINIT - nINITIATE OUTPUT bits, during a read of the Printer Status Register these This bit is output onto the nINIT output without inversion. bits are a low level. The bits of the Status Port are defined as follows: BIT 3 SELECTIN This bit is inverted and output onto the nSLCTIN output. BIT 3 nFault A logic 1 on this bit selects the printer; a logic 0 means The level on the nFault input is read by the CPU as bit 3 the printer is not selected. of the Device Status Register. BIT 4 ackIntEn - INTERRUPT REQUEST ENABLE BIT 4 Select The interrupt request enable bit when set to a high level The level on the Select input is read by the CPU as bit 4 may be used to enable interrupt of the Device Status Register. 99 requests from the Parallel Port to the CPU due to a low to tFifo (Test FIFO Mode) high transition on the nACK input. Refer to the ADDRESS OFFSET = 400H description of the interrupt under Operation, Interrupts. Mode = 110 Data bytes may be read, written or DMAed to or from the BIT 5 DIRECTION system to this FIFO in any direction. If mode=000 or mode=010, this bit has no effect and the Data in the tFIFO will not be transmitted to the to the direction is always out regardless of the state of this bit. parallel port lines using a hardware protocol handshake. In all other modes, Direction is valid and a logic 0 means However, data in the tFIFO may be displayed on the that the printer port is in output mode (write); a logic 1 parallel port data lines. means that the printer port is in input mode (read). The tFIFO will not stall when overwritten or underrun. If Bits 6 and 7 during a read are a low level, and cannot be an attempt is made to write data to a full tFIFO, the new written. data is not accepted into the tFIFO. If an attempt is made to read data from an empty tFIFO, the last data byte is re- cFifo (Parallel Port Data FIFO) read again. The full and empty bits must always keep ADDRESS OFFSET = 400h track of the correct FIFO state. The tFIFO will transfer Mode = 010 data at the maximum ISA rate so that software may generate performance metrics. Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral The FIFO size and interrupt threshold can be determined using the standard parallel port protocol. Transfers to the by writing bytes to the FIFO and checking the full and FIFO are byte aligned. This mode is only defined for the serviceIntr bits. forward direction. The writeIntrThreshold can be determined by starting with ecpDFifo (ECP Data FIFO) a full tFIFO, setting the direction bit to 0 and emptying it a ADDRESS OFFSET = 400H byte at a time until serviceIntr is set. This may generate Mode = 011 a spurious interrupt, but will indicate that the threshold has been reached. Bytes written or DMAed from the system to this FIFO, when the direction bit is 0, are transmitted by a hardware The readIntrThreshold can be determined by setting the handshake to the peripheral using the ECP parallel port direction bit to 1 and filling the empty tFIFO a byte at a protocol. Transfers to the FIFO are byte aligned. time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has Data bytes from the peripheral are read under automatic been reached. hardware handshake from ECP into this FIFO when the direction bit is 1. Reads or DMAs from the FIFO will return bytes of ECP data to the system. 100 Data bytes are always read from the head of tFIFO nFault is asserted (interrupting) and this bit is written regardless of the value of the direction bit. For example if from a 1 to a 0. This prevents interrupts from being 44h, 33h, 22h is written to the FIFO, then reading the lost in the time between the read of the ecr and the tFIFO will return 44h, 33h, 22h in the same order as was write of the ecr. written. BIT 3 dmaEn cnfgA (Configuration Register A) Read/Write ADDRESS OFFSET = 400H 1: Enables DMA (DMA starts when serviceIntr is 0). Mode = 111 0: Disables DMA unconditionally. This register is a read only register. When read, 10H is BIT 2 serviceIntr returned. This indicates to the system that this is an 8-bit Read/Write implementation. (PWord = 1 byte) 1: Disables DMA and all of the service interrupts. 0: Enables one of the following 3 cases of interrupts. cnfgB (Configuration Register B) Once one of the 3 service interrupts has occurred ADDRESS OFFSET = 401H serviceIntr bit shall be set to a 1 by hardware, it must Mode = 111 be reset to 0 to re-enable the interrupts. Writing this bit to a 1 will not cause an interrupt. BIT 7 compress case dmaEn=1: This bit is read only. During a read it is a low level. During DMA (this bit is set to a 1 when terminal count This means that this chip does not support hardware RLE is reached). compression. It does support hardware de-compression! case dmaEn=0 direction=0: This bit shall be set to 1 whenever there are BIT 6 intrValue writeIntrThreshold or more bytes free in the FIFO. Returns the value on the ISA iRq line to determine case dmaEn=0 direction=1: possible conflicts. This bit shall be set to 1 whenever there are readIntrThreshold or more valid bytes to be read BITS 5:0 Reserved from the FIFO. During a read are a low level. These bits cannot be written. BIT 1 full Read only ecr (Extended Control Register) 1: The FIFO cannot accept another byte or the FIFO is ADDRESS OFFSET = 402H completely full. Mode = all 0: The FIFO has at least 1 free byte. This register controls the extended ECP parallel port BIT 0 empty functions. Read only 1: The FIFO is completely empty. BITS 7,6,5 0: The FIFO contains at least 1 byte of data. These bits are Read/Write and select the Mode. BIT 4 nErrIntrEn Read/Write (Valid only in ECP Mode) 1: Disables the interrupt generated on the asserting edge of nFault. 0: Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be generated if 101 Table 41 - Extended Control Register R/W MODE 000: Standard Parallel Port mode . In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will not tri-state the output drivers in this mode. 001: PS/2 Parallel Port mode. Same as above except that direction may be used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register. All drivers have active pull-ups (push-pull). 010: Parallel Port FIFO mode. This is the same as 000 except that bytes are written or DMAed to the FIFO. FIFO data is automatically transmitted using the standard parallel port protocol. Note that this mode is only useful when direction is 0. All drivers have active pull-ups (push-pull). 011: ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFOand transmitted automatically to the peripheral using ECP Protocol. In the reverse direction (direction is1) bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. All drivers have active pull-ups (push-pull). 100: Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in configuration register CR4. All drivers have active pull-ups (push-pull). 101: Reserved 110: Test Mode. In this mode the FIFO may be written and read, but the data will not be transmitted on the parallel port. All drivers have active pull-ups (push-pull). 111: Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and 0x401. All drivers have active pull-ups (push-pull). 102 OPERATION • Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state. Mode Switching/Software Control • Set mode = 011 (ECP Mode) Software will execute P1284 negotiation and all operation ECP address/RLE bytes or data bytes may be sent prior to a data transfer phase under programmed I/O automatically by writing the ecpAFifo or ecpDFifo control (mode 000 or 001). Hardware provides an respectively. automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer Note that all FIFO data transfers are byte wide and byte phase (modes 011 or 010). aligned. Address/RLE transfers are byte-wide and only allowed in the forward direction. Setting the mode to 011 or 010 will cause the hardware to initiate data transfer. The host may switch directions by first switching to mode = 001, negotiating for the forward or reverse channel, If the port is in mode 000 or 001 it may switch to any setting direction to 1 or 0, then setting mode = 011. other mode. If the port is not in mode 000 or 001 it can When direction is 1 the hardware shall handshake for only be switched into mode 000 or 001. The direction can each ECP read data byte and attempt to fill the FIFO. only be changed in mode 001. Bytes may then be read from the ecpDFifo as long as it is not empty . Once in an extended forward mode the software should wait for the FIFO to be empty before switching back to ECP transfers may also be accomplished (albeit slowly) mode 000 or 001. In this case all control signals will be by handshaking individual bytes under program control in deasserted before the mode switch. In an ecp reverse mode = 001, or 000. mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001. Termination from ECP Mode Since the automatic hardware ecp reverse handshake only cares about the state of the FIFO it may have Termination from ECP Mode is similar to the termination acquired extra data which will be discarded. It may in fact from Nibble/Byte Modes. The host is permitted to be in the middle of a transfer when the mode is changed terminate from ECP Mode only in specific well-defined back to 000 or 001. In this case the port will deassert states. The termination can only be executed while the nAutoFd independent of the state of the transfer. The bus is in the forward direction. To terminate while the design shall not cause glitches on the handshake signals channel is in the reverse direction, it must first be if the software meets the constraints above. transitioned into the forward direction. ECP Operation Prior to ECP operation the Host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol. This is a somewhat complex negotiation carried out under program control in mode 000. After negotiation, it is necessary to initialize some of the port bits. The following are required: • Set Direction = 0, enabling the drivers. • Set strobe = 0, causing the nStrobe signal to default to the deasserted state. 103 Command/Data The most significant bit of the command indicates whether it is a run-length count (for compression) or a ECP Mode supports two advanced features to improve channel address. the effectiveness of the protocol for some applications. The features are implemented by allowing the transfer of When in the reverse direction, normal data is transferred normal 8-bit data or 8-bit commands. when PeriphAck is high and an 8-bit command is transferred when PeriphAck is low. The most significant When in the forward direction, normal data is transferred bit of the command is always zero. Reverse channel when HostAck is high and an 8 bit command is addresses are seldom used and may not be supported in transferred when HostAck is low. hardware. Table 42 Forward Channel Commands (HostAck Low) Reverse Channel Commands (PeripAck Low) D7 D[6:0] 0 Run-Length Count (0-127) (mode 0011 0X00 only) 1 Channel Address (0-127) Data Compression The FDC37C669 supports run length encoded (RLE) indicates that the next byte should be expanded to 128 decompression in hardware and can transfer compressed bytes. To prevent data expansion, however, run-length data to a peripheral. Run length encoded (RLE) counts of zero should be avoided. compression in hardware is not supported. To transfer compressed data in ECP mode, the compression count is Pin Definition written to the ecpAFifo and the data byte is written to the ecpDFifo. The drivers for nStrobe, nAutoFd, nInit and nSelectIn are open-collector in mode 000 and are push-pull in all Compression is accomplished by counting identical bytes other modes. and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression ISA Connections simply intercepts the RLE byte and repeats the following byte the specified number of times. When a run-length The interface can never stall causing the host to hang. count is received from a peripheral, the subsequent data The width of data transfers is strictly controlled on an I/O byte is replicated the specified number of times. A address basis per this specification. All FIFO-DMA run-length count of zero specifies that only one byte of transfers are byte wide, byte aligned and end on a byte data is represented by the next data byte, whereas a boundary. (The PWord value can be obtained by reading run-length count of 127 Configuration Register A, cnfgA, described in the next section). Single byte wide transfers 104 are always possible with standard or PS/2 mode using b. (1) When serviceIntr is 0, dmaEn is 0, program control of the control signals. direction is 1 and there are readIntrThreshold or more bytes in the Interrupts FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 The interrupts are enabled by serviceIntr in the ecr whenever there are readIntrThreshold register. or more bytes in the FIFO. serviceIntr = 1 Disables the DMA and all of the 3. When nErrIntrEn is 0 and nFault transitions from high service interrupts. to low or when nErrIntrEn is set from 1 to 0 and nFault is asserted. serviceIntr = 0 Enables the selected interrupt condition. If the interrupting condition 4. When ackIntEn is 1 and the nAck signal transitions is valid, then the interrupt is generated from a low to a high. immediately when this bit is changed from a 1 to a 0. This can occur during FIFO Operation Programmed I/O if the number of bytes removed or added from/to the FIFO The FIFO threshold is set in the chip configuration does not cross the threshold. registers. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) The interrupt generated is ISA friendly in that it must mode as indicated by the selected mode. The FIFO is pulse the interrupt line low, allowing for interrupt sharing. used by selecting the Parallel Port FIFO mode or ECP After a brief pulse low following the interrupt event, the Parallel Port Mode. (FIFO test mode will be addressed interrupt line is tri-stated so that other interrupts may separately). After a reset, the FIFO is disabled. Each assert. data byte is transferred by a Programmed I/O cycle or PDRQ depending on the selection of DMA or An interrupt is generated when: Programmed I/O mode. 1. For DMA transfers: When serviceIntr is 0, dmaEn is The following paragraphs detail the operation of the FIFO 1 and the DMA TC is received. flow control. In these descriptions, ranges from 1 to 16. The parameter FIFOTHR, which the user 2. For Programmed I/O: programs, is one less and ranges from 0 to 15. a. When serviceIntr is 0, dmaEn is 0, direction is 0 and there are writeIntrThreshold or more free A low threshold value (i.e. 2) results in longer periods of bytes in the FIFO. Also, an interrupt is time between service requests, but requires faster generated when serviceIntr is cleared to 0 servicing of the request for both read and write cases. whenever there are writeIntrThreshold or more The host must be very responsive to the service request. free bytes in the FIFO. This is the desired case for use with a "fast" system. 105 A high value of threshold (i.e. 12) is used with a "sluggish" Restarting the DMA is accomplished by enabling DMA in system by affording a long latency period after a service the host, setting dmaEn to 1, followed by setting request, but results in more frequent service requests. serviceIntr to 0. DMA TRANSFERS DMA Mode - Transfers from the FIFO to the Host Note: PDRQ - Currently selected Parallel Port DRQ (Note: In the reverse mode, the peripheral may not channel continue to fill the FIFO if it runs out of data to transfer, nPDACK - Currently selected Parallel Port even if the chip continues to request more data from the DACK channel peripheral.) PINTR - Currently selected Parallel Port IRQ channel he ECP activates the PDRQ pin whenever there is data in the FIFO. The DMA controller must respond to DMA transfers are always to or from the ecpDFifo, the request by reading data from the FIFO. The ECP will tFifo or CFifo. DMA utilizes the standard PC DMA deactivate the PDRQ pin when the FIFO becomes empty services. To use the DMA transfers, the host first sets up or when the TC becomes true (qualified by nPDACK), the direction and state as in the programmed I/O case. indicating that no more data is required. PDRQ goes Then it programs the DMA controller in the host with the inactive after nPDACK goes active for the last byte of a desired count and memory address. Lastly it sets dmaEn data transfer (or on the active edge of nIOR, on the last to 1 and serviceIntr to 0. The ECP requests DMA byte, if no edge is present on nPDACK). If PDRQ goes transfers from the host by activating the PDRQ pin. The inactive due to the FIFO going empty, then PDRQ is DMA will empty or fill the FIFO using the appropriate active again as soon as there is one byte in the FIFO. If direction and mode. When the terminal count in the DMA PDRQ goes inactive due to the TC, then PDRQ is active controller is reached, an interrupt is generated and again when there is one byte in the FIFO, and serviceIntr serviceIntr is asserted, disabling DMA. In order to prevent has been re-enabled. (Note: A data underrun may occur possible blocking of refresh requests dReq shall not be if PDRQ is not removed in time to prevent an unwanted asserted for more than 32 DMA cycles in a row. The cycle.) FIFO is enabled directly by asserting nPDACK and addresses need not be valid. PINTR is generated when Programmed I/O Mode or Non-DMA Mode a TC is received. PDRQ must not be asserted for more than 32 DMA cycles in a row. After the 32nd cycle, The ECP or parallel port FIFOs may also be operated PDRQ must be kept unasserted until nPDACK is using interrupt driven programmed I/O. Software can deasserted for a minimum of 350nsec. (Note: The only determine the writeIntrThreshold, readIntrThreshold, and way to properly terminate DMA transfers is with a TC). FIFO depth by accessing the FIFO in Test Mode. DMA may be disabled in the middle of a transfer by first Programmed I/O transfers are to the ecpDFifo at 400H disabling the host DMA controller. Then setting serviceIntr and ecpAFifo at 000H or from the ecpDFifo located at to 1, followed by setting dmaEn to 0, and waiting for the 400H, or to/from the tFifo at 400H. To use the FIFO to become empty or full. programmed I/O transfers, the host first sets up the direction and state, sets dmaEn to 0 and serviceIntr to 0. 106 The ECP requests programmed I/O transfers from the the FIFO. If at this time the FIFO is full, it can be host by activating the PINTR pin. The programmed I/O completely emptied in a single burst, otherwise a will empty or fill the FIFO using the appropriate minimum of (16-) bytes may be read from the direction and mode. FIFO in a single burst. Note: A threshold of 16 is equivalent to a threshold of 15. Programmed I/O - Transfers from the Host to the These two cases are treated the same. FIFO Programmed I/O - Transfers from the FIFO to the In the forward direction an interrupt occurs when Host serviceIntr is 0 and there are writeIntrThreshold or more bytes free in the FIFO. At this time if the FIFO is empty it In the reverse direction an interrupt occurs when can be filled with a single burst before the empty bit serviceIntr is 0 and readIntrThreshold bytes are needs to be re-read. Otherwise it may be filled with available in the FIFO. If at this time the FIFO is full it writeIntrThreshold bytes. can be emptied completely in a single burst, otherwise readIntrThreshold bytes may be read from the FIFO in a writeIntrThreshold = (16-) free bytes in single burst. FIFO readIntrThreshold = (16-) data bytes An interrupt is generated when serviceIntr is 0 and the in FIFO number of bytes in the FIFO is less than or equal to . (If the threshold = 12, then the interrupt is An interrupt is generated when serviceIntr is 0 and the set whenever there are 12 or less bytes of data in the number of bytes in the FIFO is greater than or equal to FIFO). The PINT pin can be used for interrupt-driven (16-). (If the threshold = 12, then the interrupt systems. The host must respond to the request by writing is set whenever there are 4-16 bytes in the FIFO). The data to the FIFO. If at this time the FIFO is empty, it can PINT pin can be used for interrupt-driven systems. The be completely filled in a single burst, otherwise a host must respond to the request by reading data from minimum of (16-) bytes may be written to the the FIFO. This process is repeated until the last byte is FIFO in a single burst. This process is repeated until the transferred out of last byte is transferred into the FIFO. 107 AUTO POWER MANAGEMENT Power management capabilities are provided for the An internal timer is initiated as soon as the auto following logical devices: floppy disk, UART 1, UART 2 powerdown command is enabled. The part is then and the parallel port. For each logical device, two types powered down when all the conditions are met. During of power management are provided; direct powerdown the countdown of the powerdown timer, any operation of and auto powerdown. read MSR or read/write data (FIFO) will reinitiate the timer. Direct powerdown is controlled by the powerdown bits in the configuration registers. One bit is provided for each Disabling the auto powerdown mode cancels the timer logical device. Auto Powerdown can be enabled for each and holds the FDC37C669 out of auto powerdown. logical device by setting the Auto Powerdown Enable bit in the configluration registers. In addition, a chip DSR From Powerdown powerdown has been provided by using the POWERGOOD pin. Refer to the description of the If DSR powerdown is used when the part is in auto POWERGOOD pin for more information. powerdown, the DSR powerdown will override the auto powerdown. However, when the part is awakened from FDC Power Management DSR powerdown, the auto powerdown will once again become effective. Direct power management is controlled by bit 3 of Configuration Register 0(CR0). Refer to CR0 bit 3 for Wake Up From Auto Powerdown more information. If the part enters the powerdown state through the auto Auto Power Management is enabled by CR7 bit 7. When powerdown mode, then the part can be awakened by set, this bit allows FDC to enter powerdown when all of reset or by appropriate access to certain registers. the following conditions have been met: If a hardware or software reset is used then the part will 1. The motor enable pins of register DOR (3F2H/372H) go through the normal reset sequence. If the access is are inactive (zero). through the selected registers, then the FDC37C669 2. The part must be idle; MSR=80H and INT = 0 (INT resumes operation as though it was never in powerdown. may be high even if MSR = 80H due to polling Besides activating the RESET pin or one of the software interrupts). reset bits in the DOR or DSR, the following register 3. The internal head unload timer must have expired. accesses will wake up the part: 4. The Auto powerdown timer (10msec) must have 1. Enabling any one of the motor enable bits in the timed out. DOR register (reading the DOR does not awaken the part). 2. A read from the MSR register. 3. A read or write to the Data register. 108 Once awake, the FDC37C669 will reinitiate the auto will revert back to its low power mode when the powerdown timer for 10 ms. The part will powerdown access has been completed. again when all the powerdown conditions are satisfied. Pin Behavior Register Behavior The FDC37C669 is specifically designed for portable PC Table 43 reiterates the AT and PS/2 (including modes 30) systems in which power conservation is a primary configuration registers available. It also shows the type of concern. This makes the behavior of the pins during access permitted. In order to maintain software powerdown very important. transparency, access to all the registers must be maintained. As Table 43 shows, two sets of registers are The pins of the FDC37C669 can be divided into two distinguished based on whether their access results in the major categories: system interface and floppy disk drive part remaining in powerdown state or exiting it. interface. The floppy disk drive pins are disabled so that no power will be drawn through the part as a result of any Access to all other registers is possible without voltage applied to the pin within the part's power supply awakening the part. These registers can be accessed range. Most of the system interface pins are left active to during powerdown without changing the status of the part. monitor system accesses that may wake up the part. A read from these registers will reflect the true status as shown in the register description in the FDC description. System Interface Pins A write to the part will result in the part retaining the data and subsequently reflecting it when the part awakens. Table 44 gives the state of the system interface pins in Accessing the part during powerdown may cause an the powerdown state. Pins unaffected by the increase in the power consumption by the part. The part powerdown are labeled "Unchanged". Input pins are "Disabled" to prevent them from causing currents internal to the FDC37C669 when they have indeterminate input values. 109 Table 43 - PC/AT and PS/2 Available Registers Available Registers Base + Address PC-AT PS/2 (Model 30) Access Permitted Access to these registers DOES NOT wake up the part 00H ---- SRA R 01H ---- SRB R 02H DOR (1) DOR (1) R/W 03H --- --- --- 04H DSR (1) DSR (1) W 06H --- --- --- 07H DIR DIR R 07H CCR CCR W Access to these registers wakes up the part 04H MSR MSR R 05H Data Data R/W Note 1: Writing to the DOR or DSR does not wake up the part, however, writing any of the motor enable bits or doing a software reset (via DOR or DSR reset bits) will wake up the part. Table 44 - State of System Pins in Auto Powerdown System Pins State in Auto Powerdown Input Pins IOR Unchanged IOW Unchanged A[0:9] Unchanged D[0:7] Unchanged RESET Unchanged IDENT Unchanged DACK Unchanged TC Unchanged Output Pins FINTR Unchanged (low) DB[0:7] Unchanged FDRQ Unchanged (low) 110 FDD Interface Pins used for local logic control or part programming are All pins in the FDD interface which can be connected unaffected. Table 47 depicts the state of the floppy disk directly to the floppy disk drive itself are either DISABLED drive interface pins in the powerdown state. or TRISTATED. Pins Table 45 - State of Floppy Disk Drive Interface Pins in Powerdown FDD Pins State in Auto Powerdown Input Pins RDATA Input WP Input TRK0 Input INDX Input DRV2 Input DSKCHG Input Output Pins MOTEN[0:3] Tristated DS[0:3} Tristated DIR Active STEP Active WRDATA Tristated WE Tristated HDSEL Active DENSEL Active DRATE[0:1] Active 111 UART Power Management Parallel Port Direct power management is controlled by CR2 bits 3 and Direct power management is controlled by CR1 bit 2. 7. Refer to CR2 bits 3 and 7 for more information. Refer to CR1 bit 2 for more information. Auto Power Management is enabled by CR7 bits 5 and 6. Auto Power Management is enabled by CR7 bit 4. When When set, these bit allows the following auto power set, this bit allows the ECP or EPP logical parallel port management operations: blocks to be placed into powerdown when not being used. 1. The transmitter enters auto powerdown when the The EPP logic is in powerdown under any of the following transmit buffer and shift register are empty. conditions: 2. The receiver enters powerdown when the following 1. EPP is not enabled in the configuration registers. conditions are all met: 2. EPP is not selected through ecr while in ECP mode. a. Receive FIFO is empty b. The receiver is waiting for a start bit. The ECP logic is in powerdown under any of the following conditions: Note: While in powerdown the Ring Indicator interrupt is still valid and transitions when the RI input 1. ECP is not enabled in the configuration registers. changes. 2 SPP, PS/2 Parallel port or EPP mode is selected Exit Auto Powerdown through ecr while in ECP mode. The transmitter exits powerdown on a write to the XMIT Exit Auto Powerdown buffer. The receiver exits auto powerdown when RXDx changes state. The parallel port logic can change powerdown modes when the ECP mode is changed through the ecr register or when the parallel port mode is changed through the configuration registers. 112 INTEGRATED DRIVE ELECTRONICS INTERFACE The IDE interface enables hard disks with embedded ADDRESS (CR21) Base +[0:7] controllers (AT and XT) to be interfaced to the host processor. The following definitions are for reference These AT registers contain the Task File Registers. only. These registers are not implemented in the These registers communicate data, command, and status FDC37C669. Access to these registers is controlled by information with the AT host, and are addressed when the FDC37C669. For more information, refer to the IDE nHDCS0 is low. pin descriptions and the ATA specification. ADDRESS (CR22) Base +6 HOST FILE REGISTERS This AT register may be used by the BIOS for drive The HOST FILE REGISTERS are accessed by the AT control. It is accessed by the AT interface when nHDSC1 Host, rather than the Local Processor. There are two is active. groups of registers, the AT Task File, and the Miscellaneous AT Registers. Figure 2 shows the AT Host Register Map of the FDC37C669. REGISTER ADDRESS (CR21) IDE BASE I/O TASK FILE REGISTERS ADDRESS +[0:7] (CR22) BASE I/O MISC AT REGISTER ADDRESS +6 FIGURE 2 - HOST PROCESSOR REGISTER ADDRESS MAP (AT MODE) TASK FILE REGISTERS compatible. Please refer to the ATA and EATA specifications. These are available from: Task File Registers may be accessed by the host AT when pin nHDCS0 is active (low). The Data Register Global Engineering (1F0H) is 16 bits wide; the remaining task file registers 2805 McGaw Street are 8 bits wide. The task file registers are ATA and Irvine, CA 92714 EATA (800) 854-7179 (714) 261-1455 113 COMMAND D7 D6 D5 D4 D3 D2 D1 D0 RESTORE (RECALIBRATE) 0 0 0 1 r r r r SEEK 0 1 1 1 r r r r READ SECTOR 0 0 1 0 D 0 L T WRITE SECTOR 0 0 1 1 D 0 L T FORMAT TRACK 0 1 0 1 D 0 0 0 READ VERIFY 0 1 0 0 D 0 0 T DIAGNOSE 1 0 0 1 0 0 0 0 SET PARAMETERS 1 0 0 1 0 0 0 1 Bit definitions: r: specifies the step rate to be used for the command. D: If set, 16 bit DMA is to be used for the data transfer. (Optional for high performance) L: If set, the ECC will be transferred following the data. T: if set, retries are inhibited for the command. 114 R/W D1 D1 D1 D1 D1 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ADD NAME 5 4 3 2 1 0 R 000H DATA REGISTER (REDIRECTED TO FIFO) DATA REG ADDR R/W D7 D6 D5 D4 D3 D2 D1 D0 NAME 001H R BB CRC - ID - AC TK DM ERROR FLAGS WRITE PRECOMP 001H W CYLINDER NUMBER +4 CYLINDER 002H R/W NUMBER OF SECTORS SECTOR COUNT 003H R/W SECTOR NUMBER SECTOR NUMBER 004H R/W CYLINDER NUMBER (LSB’s) CYLINDER LOW 005H R/W CYLINDER NUMBER (MSB’s) CYLINDER HIGH 006H R/W - - DRIVE HEAD HEAD, DRIVE INDE 007H R BSY RDY WF SC DRQ CD ERR STATUS X 007H W COMMAND COMMAND 115 ADD R/ D7 D6 D5 D4 D3 D2 D1 D0 NAME R W INDEX 3F6H R BSY RDY WF SC DRQ CD ERR ERROR /376H FLAGS HS3E ADPTR DISAB RE- FIXED DISK 3F6HW RESERVED N RESET LE IRQ SERVE /376H D 3F7H R - nW nHS nHS nHS nHS0 nDS1 nDS0 DIGITAL /377H G 3 2 1 INPUT 3F7H W - - - - - - - - RESERVED /377H 116 CONFIGURATION The configuration of the chip is programmable through software selectable configuration registers. CONFIGURATION REGISTER ADDRESS The address at which the Configuration Registers are located is controlled by the nRTS2 pin. The state of the nRTS2 pin is latched by the trailing edge of hardware reset. If this latched state is a 0, the Configuration Registers are located at address 3F0H-3F1H. If the latched state is a 1, then the Configuration Registers are located at address 370H-371H. CONFIGURATION REGISTERS The configuration registers are used to select programmable options of the chip. After power up, the chip is in the default mode. The default modes are identified in the Configuration Mode Register Description. To program the configuration registers, the following sequence must be followed: 1. Enter Configuration Mode. 2. Configure the Configuration Registers. 3. Exit Configuration Mode. Enter Configuration Mode To enter the configuration mode, two writes in succession to port 3F0H (or 370H) with 55H data are required. If a write to another address or port occurs between these two writes, the chip does not enter the configuration mode. It is strongly recommended that interrupts be disabled for the duration of these two writes. Configuration Mode The chip contains configuration registers CR00-CR29. These registers are accessed by first writing the number (0- 29H) of the desired register to port 3F0H (or 370H) and then writing or reading the configuration register through port 3F1H (or 371H). Exit Configuration Mode The configuration mode is exited by writing an AAH to port 3F0H (or 370H). Programming Example The following is an example of a configuration program in Intel 8086 assembly language. 117 ;-----------------------------. ; ENTER CONFIGURATION MODE | ;-----------------------------' MOV DX,3F0H MOV AX,055H ; CLI ; disable interrupts OUT DX,AL OUT DX,AL STI ; enable interrupts ;-----------------------------. ; CONFIGURE REGISTERS CR0-CRx | ;-----------------------------' MOV DX,3F0H MOV AL,00H OUT DX,AL ; Point to CR0 MOV DX,3F1H MOV AL,3FH OUT DX,AL ; Update CR0 ; MOV DX,3F0H ; MOV AL,01H OUT DX,AL ; Point to CR1 MOV DX,3F1H MOV AL,9FH OUT DX,AL ; Update CR1 ; ; Repeat for all CRx registers ; ;-----------------------------. ; EXIT CONFIGURATION MODE | ;-----------------------------' MOV DX,3F0H MOV AX,0AAH OUT DX,AL 118 Table 46 - Configuration Registers Default DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 28H CR00 Valid Reserved FDC PWR Reserved IDE EN 9CH CR01 Lock CRx Reserved PP MODE PP PWR Reserved 88H CR02 UART2 PWR Reserved UART1 Reserved PWR 78H CR03 ADRX/ IDENT MFM DRVDEN 1Reserved ADRX/ Enhanced PWRGD/ FDC Mode 2 DRV2/ DRV2/ GAMECS IRQ_B IRQ_B 00H CR04 ALT I/O EPP Type MIDI 2 MIDI 1 Parallel Port FDC PP Ext. Modes 00H CR05 Reserved EXTx4 DRV 0X1 DEN SEL DMA Mode Reserved FFH CR06 Floppy Drive D Floppy Drive C Floppy Drive B Floppy Drive A 00H CR07 Auto Power Management Reserved Floppy Boot Drive 00H CR08 ADRA7 ARDA6 ADRA5 ADRA4 0 0 0 0 00H CR09 ADRx Config Reserved ADRA10 ADRA9 ADRA8 00H CR0A Reserved ECP FIFO Threshold 00H CR0B FDD3-DRTx FDD2-DRTx FDD1-DRTx FDD0-DRTx 00H CR0C UART 2 UART 1 UART 2 Mode UART 2 UART 2 UART 2 Speed Speed Duplex XMIT RCV Polarity Polarity 03H CR0D Device ID 02H CR0E Device Revision 00H CR0F Test 7 Test 6 Test 5 Test 4 Test 3 Test 2 Test 1 Test 0 00H CR10 IR_Test PLL_Clk AceStop Pll Stop Pll Gain Reserved 00H CR11 Reserved Test 10ms IR loop Back 00H CR12- Reserved CR1D 3CH CR1E GAMECS - ADR[9:4] GAMECS Config 00H CR1F FDD3-DTx FDD2-DTx FDD1-DTx FDD0-DTx 3CH CR20 FDC - ADR[9:4] 0 0 3CH CR21 IDE - nHDCS0 - ADR[9:4] 0 0 3DH CR22 IDE - nHDCS1 - ADR[9:4] 0 1 00H CR23 Parallel Port - ADR[9:2] 00H CR24 Serial Port 1 - ADR[9:3] 0 00H CR25 Serial Port 2 - ADR[9:3] 0 00H CR26 FDC DRQ Parallel Port DRQ 00H CR27 FDC IRQ Parallel Port IRQ 00H CR28 Serial 1 IRQ Serial 2 IRQ 00H CR29 Reserved IRQIN IRQ 119 Configuration Register Description accessed and is used to select which of the Configuration Registers are to be accessed at port 3F1H (371H). The configuration registers consist of the Configuration Select Register (CSR) and Configuration Registers CR- Configuration Registers CR00 -CR29 00 -CR-29. The configuration select register is written to These registers are set to their default values at power up by writing to port 3F0H (or 370H). The Configuration and are not affected by RESET (except where explicitly Registers CR-00; CR-29 are accessed by reading or defined that a hardware reset causes that bit to be reset writing to port 3F1H (or 371H). to default). They are accessed at port 3F1H (or 371H). Refer to the following descriptions for the function of each Configuration Select Register (CSR) configuration register. This register can only be accessed when the chip is in the Configuration Mode. This register, located at port 3F0H CR00 (370H), must be initialized upon entering the This register can only be accessed when the chip is in the Configuration Mode before the configuration registers can Configuration Mode and after the CSR has been be initialized to 00H. The default value of this register after power up is 28H. Table 47 - CR00 BIT NO. BIT NAME DESCRIPTION 0, 1 IDE ENABLE/ Bits (Note 1) Alternate 10 Function 00 - IDE, IRRX2, IRTX2, IRQ_H disabled (Default) 01 - Reserved (IDE, IRRX2, IRTX2, IRQ_H disabled) 10 - IDE Enabled 11 - IRRX2, IRTX2, IRQ_H Enabled 2 Reserved Read only. Read as 0 3 FDC Power (see A high level on this bit, supplies power to the FDC (default). A low note _PWRDN) level on this bit puts the FDC in low power mode. 4,5,6 Reserved Read only. A read returns bit 5 as a 1 and bits 4 and 6 as a 0. 7 Valid A high level on this software controlled bit can be used to indicate that a valid configuration cycle has occurred. The control software must take care to set this bit at the appropriate times. Set to zero after power up. This bit has no effect on any other hardware in the chip. Note 1: When "0x" is selected, 30ua pull-ups are active on the "nIDEEN, nHDCS0 and nHDCS1 pins", at all other times, the pull-ups are disabled. When "11" is selected, IRQ_H is available as an IRQ output, and IRRX2 and IRTX2 are available as alternate IR pins (pull-ups disabled). When "10" is selected, nIDEEN, nHDCS0 and nHDCS1 are used to control the IDE interface (pull-ups disabled). 120 CR01 been initialized to 01H. The default value of this register This register can only be accessed in the Configuration after power up is 9CH. Mode and after the CSR has Table 48 - CR01 BIT NO. BIT NAME DESCRIPTION 0,1 Reserved Read Only. A read returns a 0. 2 Parallel Port A high level on this bit, supplies power to the Parallel Port (Default). Power (see note A low level on this bit puts the Parallel Port in low power mode. _PWRDN) 3 Parallel Port Parallel Port Mode. A high level on this bit, sets the Parallel Port for Mode Printer Mode (Default). A low level on this bit enables the Extended Parallel port modes. Refer to Bits 0 and 1 of CR4 4 Reserved Read Only. A read returns a 1. 5,6 Reserved Read Only. A read returns a 0. 7 Lock CRx A high level on this bit enables the reading and writing of CR00- CR18 (Default). A low level on this bit disables the reading and writing of CR0-CRF. Once set to 0, this bit can only be set to 1 by a hard reset or power-up reset. CR02 initialized to 02H. The default value of this register after This register can only be accessed in the power up is 88H. Configuration Mode and after the CSR has been Table 49 - CR02 BIT NO. BIT NAME DESCRIPTION 0:2 Reserved Read Only. A read returns a 0. 3 UART1 Power A high level on this bit, allows normal operation of the Primary Serial down (see note Port (Default). A low level on this bit places the Primary Serial Port _PWRDN) into Power Down Mode. 4:6 Reserved Read Only. A read returns a 0. 7 UART2 Power A high level on this bit, allows normal operation of the Secondary down Serial Port (Default). A low level on this bit places the Secondary Serial Port into Power Down Mode. Note_PWRDN: Power Down bits disable the respective logical device and associated pins, however the power down bit does not disable the selected address range registers for the logical device. To disable the host address registers the logical device's base address must be set below 100h. Therefore devices which are powered down, but still reside at a valid I/O base address will participate in Plug-and-Play range checking. 121 CR03 This register can only be accessed in the initialized to 03H. The default value after power up is Configuration Mode and the CSR has been 780H. Table 50 - CR03 BIT NO. BIT NAME DESCRIPTION 0 PWRGD/ Bit 0 Pin function GAMECS 0 PWRGD (default) 1 GAMECS 1 Enhanced Floppy Mode Bit 1 Floppy Mode - Refer to the description of the 2 TAPE DRIVE REGISTER (TDR) for more information on these modes. 0 NORMAL Floppy Mode (Default) 1 Enhanced Floppy Mode 2 (OS2) 3 Reserved Reserved - Read as zero 4 DRVDEN1 Bit 4 Pin DRVDEN1 output 0 DRVDEN 1 output 1 DRVDEN 1 high (default) 5 MFM IDENT is used in conjunction with MFM to define the interface mode of operation 6 IDENT IDENT MFM MODE 1 1 AT Mode (Default) 1 0 Reserved 0 1 PS/2 0 0 Model 30 7,2 ADRx/ Bit - 7 Bit - 2 Pin 94 DRV2 EN/ 0 x DRV2 (input) IRQ_B 1 0 ADRX 1 1 IRQ_B 122 CR04 initialized to 04H. The default value after power up is This register can only be accessed in the 00H. Configuration Mode and the CSR has been Table 51 - CR04 - Parallel and Serial Extended Setup Register BIT NO. BIT NAME DESCRIPTION 1,0 Parallel Port Bit 1 Bit 0 If CR1 bit 3 is a low level then: Extended Modes 0 0 Standard and Bidirectional Modes (SPP) (Default) 0 1 EPP Mode and SPP 1 0 ECP Mode (Note CR4_2) 1 1 ECP Mode & EPP Mode (Note CR4_1, 2) 2,3 Parallel Port FDC Refer to Parallel Port Floppy Disk Controller description. Bit 3 Bit 2 0 0 Normal 0 1 PPFD1 1 0 PPFD2 1 1 Reserved 4 MIDI 1 Serial Clock Select Port 1: A low level on this bit, disables MIDI support, clock = divide by 13 (Default). A high level on this bit enables MIDI support, clock = divide by 12. (Note CR4_3) 5 MIDI 2 Serial Clock Select Port 2: A low level on this bit, disables MIDI support, clock = divide by 13 (Default). A high level on this bit enables MIDI support, clock = divide by 12. (Note CR4_3) 6 EPP Type 0 = EPP 1.9 (Default) 1 = EPP 1.7 7 ALT I/O 1 = use pins IRRX2, IRTX2 (pins 25, 26) 0 = use pins IRRX, IRTX (Default) (pins 88, 89) note: If this bit is set, the Infrared receive and transmit functions will not be available on pins 25 and 26 unless bits [0,1] of CR00 are set to [1,1]. Note CR4_1: In this mode, EPP can be selected through the ecr register of ECP as mode 100. Note CR4_2: In these modes, 2 drives can be supported directly, 3 or 4 drives must use external 4 drive support. SPP can be selected through the ecr register of ECP as mode 000. Note CR4_3: MIDI Support: The Musical Instrumental Digital Interface (MIDI) operates at 31.25Kbaud (+/-1%) which can be derived from 125KHz. (24MHz/12=2MHz, 2MHz/16=125KHz). 123 CR05 initialized to 05H. The default value after power up is This register can only be accessed in the Configuration 00H. Mode and the CSR has been Table 52 - CR05- Floppy Disk and IDE Extended Setup Register BIT NO. BIT NAME DESCRIPTION 0,1 Reserved Read Only. A read returns a 0. 2 FDC DMA Mode 0=(default) Burst mode is enabled for the FDC FIFO execution phase data transfers. 1=Non-Burst mode enabled. The FDRQ and FIRQ pins are strobed once for each byte transferred while the FIFO is enabled. 4,3 DenSel Bit 4 Bit 3 Densel output 0 0 Normal (Default) 0 1 Reserved 1 0 1 1 1 0 5 Swap Drv 0,1 A high level on this bit, swaps drives and motor sel 0 and 1 of the FDC. A low level on this bit does not (Default). 6 EXTx4 External 4 drive support: 0=Internal 2 drive decoder (default). 1=External 4 drive decoder (External 2 to 4 decoder required). 7 Reserved Read Only. A read of this bit returns a 0 CR06 of this register after power up is FFH. This register This register can only be accessed in the Configuration holds the floppy disk drive types for up to four floppy disk Mode and after the CSR has been initialized to drives. 06H. The default value 124 CR07 this register after power up is 00H. This register holds the This register can only be accessed in the Configuration value for the auto power management, and floppy boot Mode and after the CSR has been initialized to 07H. drive. The default value of Table 53 - CR07 BIT NO. BIT NAME DESCRIPTION 0,1 Floppy Boot This bit is used to define the boot floppy. 0 = Drive A (default) 1 = Drive B 2 Reserved Read as 0. 3 Reserved Read as 0. 4 Parallel Port This bit controls the AUTOPOWER DOWN feature of the Parallel Enable Port. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled This bit is reset to the default state by POR or a hardware reset. 5 UART 2 Enable This bit controls the AUTOPOWER DOWN feature of the UART2. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled This bit is reset to the default state by POR or a hardware reset. 6 UART 1 Enable This bit controls the AUTOPOWER DOWN feature of the UART1. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled This bit is reset to the default state by POR or a hardware reset. 7 Floppy Disk This bit controls the AUTOPOWER DOWN feature of the Floppy Enable Disk. The function is: 0 = Auto powerdown disabled (default) 1 = Auto powerdown enabled This bit is reset to the default state by POR or a hardware reset. 125 CR08 CR09 This register can only be accessed in the Configuration This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 08H. Mode and after the CSR has been initialized to 09H. The The default value of this register after power up is 00H. default value of this register after power up is 00H. This This is the lower 4 bits (ADRA7:4) for the ADRx address is the upper 3 bits (ADRA10:8) (D2 - MSB, D0 - LSB) for decode. The non-programmable address bits 3:0 the ADRx address decode. ADRx Config (bits 7:6) define default to 0000b. the configuration of the ADRx decoder as follows: D7 D6 ADRx Configuration 0 0 ADRx disabled 0 1 1 Byte decode A[3:0]=0000b 1 0 8 Byte block decode A[3:0]=0XXXb 1 1 16 byte block decode A[3:0]=XXXXb Upper Address Decode requirements : nCS='0' is required to qualify the ADRx output. CR0A register after power up is 00H. This byte defines the This register can only be accessed in the Configuration FIFO threshold for the ECP mode parallel port. Mode and after the CSR has been initialized to 0AH. The default value of this Table 54 - CR0A D7 D6 D5 D4 D3 D2 D1 D0 RESERVED - READ ONLY 0 HEX ECP F I F O T H R E S H O L D THR3 THR2 THR1 THR0 CR0B this register after power up is 00H. This register indicates This register can only be ac1cessed in the Configuration the data rate table used for each drive. Refer to CR1F for Mode and after the CSR has been initialized to Drive Type register. 0BH. The default value of Table 55 - CR0B FDD3 FDD2 FDD1 FDD0 D7 D6 D5 D4 D3 D2 D1 D0 DRT1 DRT0 DRT1 DRT0 DRT1 DRT0 DRT1 DRT0 126 CR0C register after power up is 00H. This register controls the This register can only be accessed in the Configuration operating mode of the UART. This register is reset to the Mode and after the CSR has been initialized to 0CH. The default state by a POR or a hardware reset. default value of this Table 56 - CR0C BIT NO. BIT NAME DESCRIPTION 0 UART 2 RCV 1 = RX input inverted. Polarity 0 = RX input non - inverted (default). 1 UART 2 XMIT 1 = TX output inverted. Polarity 0 = TX output non - inverted (default). 2 UART 2 Duplex This bit is used to define the FULL/HALF DUPLEX operation of UART 2. 1 = Half duplex 0 = Full duplex (default) 3, 4, 5 UART 2 MODE UART 2 Mode 5 4 3 0 0 0Standard (default) 0 0 1IrDA (HPSIR) 0 1 0Amplitude Shift Keyed IR @ 500Khz 0 1 1Reserved 1 x xReserved 6 UART 1 Speed This bit enables the high speed mode of UART 1 = High speed enabled 0 = Standard (default) 7 UART Speed This bit enables the high speed mode of UART 1 = High speed enabled 0 = Standard (default) CR0D CR0E This register can only be accessed in the Configuration This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 0DH. Mode and after the CSR has been initialized to 0EH. This register is read only. This is the Device ID. The This register is read only. The default value of this default value of this register after power up is 03H. register after power up is 02H. This is used to identify the chip revision level. 127 CR0F This register can only be accessed in the CSR has been initialized to 0FH. The default value of Configuration Mode and after the this register after power up is 00H. Table 57 - CR0F BIT NO. BIT NAME DESCRIPTION 0 Test 0 Reserved - Set to zero 1 Test 1 Reserved - Set to zero 2 Test 2 Reserved - Set to zero 3 Test 3 Reserved - Set to zero 4 Test 4 Reserved - Set to zero 5 Test 5 Reserved - Set to zero 6 Test 6 Reserved - Set to zero 7 Test 7 Reserved - Set to zero 128 CR10 initialized to 10H. The default value of this register after This register can only be accessed in the power up is 00H. Configuration Mode and after the CSR has been Table 58 - CR10 BIT NO. BIT NAME DESCRIPTION 0 - 2 Reserved Reserved - READ ONLY. A read returns a 0. 3 Pll Gain This bit controls the gain of the frequency multiplying phase lock loops. When a 0 (default) the gain is set to a value expected for 5 volt operation. When set to a 1 the gain is doubled to a value for possible 3 volt operation. 4 Pll Stop A 1 in this bit position stops the frequency multiplying phase lock loops. A 0 (default) allows normal operation. 5 ACE_STOP This bit when set to a 1 will inhibit the 24MHz clock to the divide by 12/13 that generates the UART clocks, and reset those dividers. When at a 0 (default) these dividers and clocks are enabled. 6 PLL Clock This bit enables the PLL clock generator to run with either a 14.318MHz Control or 24MHz input clock. A 0 enables the 14.318MHz clock (default), a 1 enables the 24MHz clock. 7 Infra Red Test This bit enables the IR test mode. When this bit is set to a 1 the serial data seen by UART RX and TX ports is output on SOUT. A 0 gives normal operation (default). CR11 been initialized to 11H. The default value of this register This register can only be accessed in the after power up is 00H. Configuration Mode and after the CSR has Table 59 - CR11 BIT NO. BIT NAME DESCRIPTION 0 IR Loop Back When a 1 the IROUT is looped back internally to the IRIN input. When a 0 (default) normal operation. 1 Test 10ms This bit when a 1 tests the 10ms timeout of the FDC autopower down mode. A 0 (default) allows normal operation. 2 - 7 Reserved Reserved - READ ONLY. A read returns a 0. 129 CR12-CR1D initialized to 1EH. The default value of this register after These registers are reserved. The default value of these power up is 80H. This register is used to select the base registers after power up is 00H. address of the Game Chip Select decoder (GAMECS). The GAMECS can be set to 48 locations, on 16 byte CR1E boundaries from 100H-3F0H. To disable the GAMECS, This register can only be accessed in the set DB1 and DB0 to zero. Configuration Mode and after the CSR has been DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 GAMECS Config DB1 DB0 GAMECS Configuration 0 0 GAMECS disabled 0 1 1 Byte decode, ADR[3:0] = 0001b 1 0 8 Byte block decode, ADR[3:0] = 0XXXb 1 1 16 byte block decode, ADR[3:0] = XXXXb Upper Address Decode requirements: nCS='0' and A10='0' are required to qualify the GAMECS output. CR03, bit DB0 is the PWRGD/GAMECS control bit and overrides the selection made by the above configuration. 130 CR1F of this register after power up is 00H. This register This register can only be accessed in the Configuration indicates the Drive Type used for each drive. Refer to Mode and after the CSR has been initialized to CR0B for Data Rate Table register. 1FH. The default value FDD3 FDD2 FDD1 FDD0 D7 D6 D5 D4 D3 D2 D1 D0 DT0 DT1 DT0 DT1 DT0 DT1 DT0 DT1 DTx = Drive Type select DRVDEN0 DRVDEN1 DT0 DT1 (Note) (Note) Drive Type 0 0 DENSEL DRATE0 4/2/1 MB 3.5" 2/1 MB 5.25" FDDS 2/1.6/1 MB 3.5" (3-MODE) 0 1 DRATE1 DRATE0 1 0 nDENSEL DRATE0 PS/2 1 1 DRATE0 DRATE1 Note: DENSEL, DRATE1 and DRATE0 map onto two output pins DRVDEN0 and DRVDEN1. CR20 be set to 48 locations, on 16 byte boundaries from This register can only be accessed in the Configuration 100H-3F0H. To disable the FDC, set ADR9 and ADR8 Mode and after the CSR has been initialized to 20H. to zero. The default value of this register after power up is 3CH. This register is used to select the base address of the Upper Address Decode requirements: nCS='0' and floppy disk controller (FDC). The FDC can A10='0' are required to access the FDC registers. A[3:0] are decoded as 0XXXb. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 0 0 131 CR21 can be set to 48 locations, on 16 byte boundaries from This register can only be accessed in the Configuration 100H-3F0H. To disable this decode, set ADR9 and Mode and after the CSR has been initialized to 21H. ADR8 to zero. The default value of this register after power up is 3CH. This register is used to select the base address Upper Address Decode requirements : nCS='0' and of the IDE Interface Control Registers (0-7). This A10='0' are required to access the IDE registers. A[3:0] are decoded as 0XXXb. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 0 0 CR22 boundaries+6 from 106H-3F6H. To disable this decode, This register can only be accessed in the Configuration set ADR9 and ADR8 to zero. Mode and after the CSR has been initialized to 22H. The default value of this register after power up is 3DH. Upper Address Decode requirements : nCS='0' and This register is used to select the base address of A10='0' are required to access the IDE Alternate Status the IDE Interface Alternate Status Register. This can register. A[3:0] must be 0110b. be set to 48 locations, on 16 byte DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 0 1 CR23 port can be set to 96 locations, on 8 byte boundaries from This register can only be accessed in the Configuration 100H-3F8H. To disable the parallel port, set ADR9 and Mode and after the CSR has been initialized to 23H. The ADR8 to zero. default value of this register after power up is 00H. This register is used to select the base address of the Upper Address Decode requirements : nCS='0' and parallel port. If EPP is not enabled, the parallel port can A10='0' are required to access the Parallel Port when in be set to 192 locations, on 4 byte boundaries from 100H- Compatible, Bi-directional, or EPP modes (A10 is active 3FCH. If EPP is enabled, the parallel when in ECP mode). DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 EPP Enabled Addressing (low bits) Decode No A[1:0] = XXb Yes A[2:0] = XXXb 132 CR24 locations, on 8 byte boundaries from 100H-3F8H. To This register can only be accessed in the Configuration disable the serial port, set ADR9 and ADR8 to zero. Mode and after the CSR has been initialized to 25H. The default value of this register after power up is 00H. Upper Address Decode requirements : nCS='0' and This register is used to select the base address of UART1 A10='0' are required to access UART1 registers. A[2:0] (serial port 1). The serial port can be set to 96 are decoded as XXXb. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 0 CR25 locations, on 8 byte boundaries from 100H-3F8H. To This register can only be accessed in the Configuration disable the serial port, set ADR9 and ADR8 to zero. Mode and after the CSR has been initialized to 25H. The default value of this register after power up is 00H. This Upper Address Decode requirements : nCS='0' and register is used to select the base address of UART2 A10='0' are required to access UART2 registers. A[2:0] (serial port 2). The serial port can be set to 96 are decoded as XXXb. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 0 CR26 register after power up is 00H. This register is used to This register can only be accessed in the Configuration select the DMA for the FDC (Bits 4:7) and the parallel Mode and after the CSR has been initialized to 26H. port (bits 3:0). Any unselected DMA REQ output is in The default value of this tristate. D3-D0 D7-D4 DMA Selected 0000 None 0001 DMA_A 0010 DMA_B 0011 DMA_C 133 CR27 used to select the IRQ for serial port 1 (bits 7:4) and for This register can only be accessed in the Configuration serial port 2 (bits 3:0). Refer to IRQ Table for CR27. Any Mode and after the CSR has been initialized to 27H. unselected IRQ output (registers CR27 - CR29) is in The default value of this register after power up is 00H. tristate. This register is used to select the IRQ for the FDC (Bits 4:7) and the parallel port (bits 3:0). Any unselected IRQ To properly share an IRQ among UART1 and UART2: output (registers CR27-CR29) is in tristate. 1) Configure UART1 to use the desired IRQ pin. 2) Set UART2 to 0Fh i.e., set CR28 bits[3:0]=1111. CR28 This selects the share IRQ mechanism. Refer This register can only be accessed in the Configuration to Table 60 on the following page: Mode and after the CSR has been initialized to 28H. The default value of this register after power up is 00H. This register is D3-D0 or D7-D4 IRQ Selected 0000 None 0001 IRQ_A 0010 IRQ_B 0011 IRQ_C 0100 IRQ_D 0101 IRQ_E 0110 IRQ_F 0111 Reserved 1000 IRQ_H CR29 used to select the IRQ for IRQIN (bits 3:0). Refer to IRQ This register can only be accessed in the Configuration Table for CR27. Bits 7:4 are reserved and return zero Mode and after the CSR has been initialized to 29H. The when read. Any unselected IRQ output (registers default value of this register after power up is 00H. This CR27-CR29) is in tristate. register is 134 Table 60 - UART Interrupt Operation Table UART1 UART2 IRQ PINS UART1 UART1 IRQ UART2 UART2 IRQ Output UART1 UART2 OUT2 bit Output State OUT2 bit State Share IRQ Pin State Pin State 0 Z 0 Z No Z Z 1 asserted 0 Z No 1 Z 1 de-asserted 0 Z No 0 Z 0 Z 1 asserted No Z 1 0 Z 1 de-asserted No Z 0 1 asserted 1 asserted No 1 1 1 asserted 1 de-asserted No 1 0 1 de-asserted 1 asserted No 0 1 1 de-asserted 1 de-asserted No 0 0 0 Z 0 Z Yes Z Z 1 asserted 0 Z Yes 1 Z 1 de-asserted 0 Z Yes 0 Z 0 Z 1 asserted Yes 1 Z 0 Z 1 de-asserted Yes 0 Z 1 asserted 1 asserted Yes 1 Z 1 asserted 1 de-asserted Yes 1 Z 1 de-asserted 1 asserted Yes 1 Z 1 de-asserted 1 de-asserted Yes 0 Z It is the responsibility of the software to ensure that two IRQ's are not set to the same IRQ number. Potential damage to chip may result. 135 OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* o o Operating Temperature Range.....................................................................................................0 C to +70 C o o Storage Temperature Range ..................................................................................................... -55 to +150 C o Lead Temperature Range (soldering, 10 seconds)...............................................................................+325 C Positive Voltage on any pin, with respect to Ground ......................................................................... V +0.3V CC Negative Voltage on any pin, with respect to Ground............................................................................... -0.3V Maximum V .............................................................................................................................................. +7V CC *Stresses above those listed above could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used. DC ELECTRICAL CHARACTERISTICS (T = 0°C - 70°C, V = 5 V ± 10%) A cc PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS I Type Input Buffer Low Input Level V 0.8 V TTL Levels ILI High Input Level V 2.0 V IHI IS Type Input Buffer Low Input Level V 0.8 V Schmitt Trigger ILIS High Input Level V 2.2 V Schmitt Trigger IHIS Schmitt Trigger Hysteresis V 250 mV HYS I Input Buffer CLK Low Input Level V 0.4 V ILCK High Input Level V 3.0 V IHCK 136 PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS Input Leakage (All I and IS buffers except PWRGD) Low Input Leakage I -10 +10 µA V = 0 IL IN High Input Leakage I -10 +10 µA V = V IH IN CC Input Current I OH PWRGD 75 150 µA V = 0 IN I/O24 Type Buffer Low Output Level V 0.5 V I = 24 mA OL OL High Output Level V 2.4 V I = -12 mA OH OH Output Leakage I -10 +10 µA V = 0 to V (Note 1) OL IN CC O24 Type Buffer V 0.5 V = 24 mA Low Output Level I OL OL High Output Level V 2.4 V I = -12 mA OH OH Output Leakage I -10 +10 µA V = 0 to V (Note 1) OL IN CC OD48 Type Buffer Low Output Level V 0.5 V I =48 mA OL OL Output Leakage I -10 +10 µA V = 0 to V (Note 2) OH OH CC O24P Type Buffer Low Output Level V 0.4 V I =24mA OL OL High Output Level V 2.4 V I = -12 mA OH OH Output Leakage I -10 +10 µA V = 0 to V (Note 1) OL IN CC 04 Type Buffer Low Output Level V 0.4 V I =4mA OL OL High Output Level V 2.4 V I = -2 mA OH OH Output Leakage I -1.0 +10 µA V = 0 to V (Note 1) OL IN CC 137 PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS OD24 Type Buffer Low Output Level V 0.5 V I = 24 mA OL OL Output Leakage I -10 +10 µA V = 0 to V (Note 1) OL IN CC OD24P Type Buffer Low Output Level V 0.5 V I = 24mA OL OL High Output Level V 2.4 V I =-30μA OH OH Output Leakage I -10 +10 µA V = 0 to V (Note 1) OL IN CC OP24 Type Buffer V 0.5 V I = 24 mA OL OL Low Output Level V 2.4 V I =-4mA OH OH High Output level I -10 +10 µA V = 0 to V OL IN CC Output Leakage (Note 1) Supply Current Active I 25 35 mA All outputs open. CC Supply Current Standby I 100 µA Note 3, 4 CSBY ChiProtect I ±10 µA Chip in circuit: IL (SLCT, PE, BUSY, nACK, V = 0V CC nERROR) V = 6V Max. IN Note 1: All output leakages are measured with the current pins in high impedance as defined by the PWRGD pin. Note 2: Output leakage is measured with the low driving output off, either for a high level output or a high impedance state defined by PWRGD. Note 3: Defined by the device configuration with the PWRGD input low and 14 MHz clock inactive. Note 4: Max standby supply current given is for Rev. H and K parts. Contact SMSC for Rev. J and all other Revs. CAPACITANCE T = 25°C; fc = 1MHz; V = 5V A CC LIMITS PARAMETER SYMBOL MIN TYP MAX UNIT TEST CONDITION Clock Input Capacitance C 20 pF All pins except pin IN under test tied to AC Input Capacitance C 10 pF IN ground Output Capacitance C 20 pF OUT 138 t 3 A X, AEN, nIOCS16 t 1 t 6 t 2 nIOR t 4 t 5 DATA DATA VALID (D0-D7) PD0-PD7, nERR, PE, SLCT, nACK, BUSY t 7 FINTR t 8 nIOR/nIOW t 9 PINTR NOTE: PINTR is the interrupt assigned to the Parallel Port FINTR is the inte rrupt assigned to the Floppy Disk Pa ram eter m in typ max units t1 40 ns A0-A9, AEN, nIOCS16 Set Up to nIOR Low t2 nIOR Width 150 ns t3 10 ns A0-A9, AEN, nIOCS16 Hol d from nIOR H igh Data Access Time from nIOR Low t4 100 ns t5 10 60 ns D ata to Float Delay from nIOR High t6 20 ns Parallel Port Setup t7 Read Strobe to Clear FINTR 40 55 ns t8 nIOR or nIOW Inactive for Transfers to 150 ns and from ECP FIFO t9 260 ns nIOR Active to PINTR Inacti v e FIGURE 3 - MICROPROCESSOR READ TIMING 139 TIMING DIAGRAMS t3 AX , A EN, nI OCS16 t2 t1 t4 nIOW t5 DA TA DATA VALID (D0-D7) t6 FI NTR t7 PI NTR NOTE: PINTR is the interrupt assigned to the Parallel Port FINTR is the interrupt assigned to the Floppy Disk Parameter min typ max u nits t1 A0-A9, AEN, nIOCS16 Set Up to 40 ns n IOW Lo w t2 nIOW Width 150 ns t3 A0-A9, AEN, nIOCS16 Hold from 10 ns nIOW High t4 Data Set Up Time to nIOW High 40 ns t5 Data Hold Time from n IOW High 10 ns t6 Write Strobe to Clear FINTR 40 55 ns t7 nIOW Inactive to PINTR Inactive 260 ns FIGURE 4 - MICROPROCESSOR WRITE TIMING 0 14 t15 AEN t16 t3 t2 FD RQ, PDRQ t1 t4 FDA CKX PDA CKX t12 t14 t11 t6 nIOR t5 t8 or nIOW t10 t7 t9 DATA DATA VA LID (DO-D7) t13 TC NOTE: FDRQ refers to the DRQ assigned to the Floppy Disk PDRQ refers to the DRQ assigned to the Parallel Port FDACKX r ef ers to t he DRQ as si gned to t he to the Floppy Disk PDACKX refers to the DRQ assigned to the Parallel Port Parameter min typ max units 0 ns t1 n DACK Delay Time from FDRQ High 100 ns t2 DRQ Reset Delay from nIOR or nIOW 100 ns FDRQ Reset Delay from nDACK Low t3 150 ns t4 nDACK Wid th 0 ns nIOR Delay from FDRQ High t5 0 ns t6 n IOW Delay from FDRQ High 100 ns Da ta Access Time from n IOR Low t7 40 ns t8 Data Set Up Time to nIOW High 60 10 ns t9 D ata to Float Delay from nIOR High 10 ns t10 Data Hold Time from nIOW High 5 ns t11 n DACK Set Up to nIOW/n IOR Low 10 ns t12 n DACK Hold Afte r nIOW/nIOR High 60 ns t13 TC Pulse Width 40 ns t14 AEN Set Up to nIOR/nIOW 10 ns t15 AEN Hold from nDACK 100 ns TC Active to PDRQ Inactive t16 FIGURE 5 - DMA TIMING 1 14 t1 t2t2 t4 EnR typ Des cription m miin n max Name Units ns Clo ck Cycl eTime for 14.318MH Z 65 t1 Clock High Time/Low Time for t2 25nsec ns 1 4.318MH Z Clo ck Cycle Time for 32KH Z ns t1 t2 Clock High Time/Low Time for 32KHz ns 5 Clock Rise Time/Fall T ime (not shown) ns t6 nRESET Low Time 1.5us ns NOTE 1: The nRESET low time is dependent upon the processor clock. The nRESET must be active for a minimum of 24 x16MHz clock cycle s. FIGURE 6 - CLOCK TIMING 2 14 SET X1K t 3 nDI R t 4 t 1 t 2 nSTEP t 5 nD S0-3 t 6 nI NDEX t 7 nRDATA t 8 nWDATA nIOW t 9 t 9 nDS0-1, nM TR0-1 (AT Mode timing only) Parameter m in typ max units t1 nDIR Set Up to nSTEP Low 4 X* t2 nSTEP Active Time Low 24 X* t3 nDIR Hold Time After nSTEP 96 X* t4 nSTEP Cycle Time 132 X* t5 nDS0-1 Hold Time from nSTEP Low 20 X* t6 nINDEX Pulse Width 2 X* t7 nRDATA Active Time Low 40 ns t8 nWDATA Write Data Width Low .5 Y* t9 nDS0-1, MTR0-1 from End of nIOW 25 ns *X speci fies one MCLK period and Y specifies on e WCLK pe riod . MCLK = Controller Cl ock to FDC (See Table 6). WCLK = 2 x D ata Rate (See Table 6 ). FIGURE 7 - DISK DRIVE TIMING 3 14 nIOW t1 nRTSx, nDTRx t5 IRQx nCTSx, nD SRx, nDC Dx t6 t2 t4 IRQx nIOW t3 IRQx nIOR nR Ix Parameter min typ max units t1 nRTSx, nDTRx Delay from nIOW 200 ns t2 IRQx Active Del ay from nC TSx, nDSRx, 100 ns nDCDx t3 IRQx Inactive Delay from nIOR (Leadin g 120 ns Edg e) t4 IRQx Inacti ve Delay from nIOW (Trailing 125 ns Edg e) t5 IRQx Inacti ve Delay from nIOW 10 100 ns t6 IRQx Acti v e Delay from nRIx 100 ns FIGURE 8 - SERIAL PORT TIMING 4 14 AEN, nIOCS 16 AX t2 t1 nIDEEN , nHD CS x t3 Par ameter min ty p max units t1 n IDEENL O, n IDE ENHI, nHDCSx Delay 40 ns from AEN, nIOC S16 nIDEENLO, nIDEENH I, nHDCSx Delay t2 ns from AX n IDEENLO Delay from nIDEENHI, t3 40 ns n IOCS16, AEN FIGURE 9 - IDE INTERFACE TIMING 5 14 DATA 0 1 0 1 0 0 1 1 0 1 1 t2 t1 t2 t1 IRRX n IRRX Parameter min typ max units t1 Pul s e Wid th at 115kbau d 1.4 1.6 2 .7 1 µs t1 Pulse Width at 57 .6kbau d 1.4 3 .2 2 3 .6 9 µs t1 Pulse Width at 38 .4kbau d 1.4 4.8 5 .5 3 µs t1 Pulse Width at 19 .2kbau d 1.4 9.7 11 .07 µs t1 Pulse Width at 9.6kbau d 1.4 19.5 22 .13 µs t1 Pulse Width at 4.8kbau d 1.4 39 44 .27 µs t1 Pulse Width at 2.4kbau d 1.4 78 88 .55 µs t2 Bit Time at 115kbaud 8 .6 8 µs t2 Bit Time at 5 7.6kbaud 17.4 µs t2 Bit Time at 3 8.4kbaud 26 µs t2 Bit Time at 1 9.2kbaud 52 µs t2 Bit Time at 9.6kbaud 10 4 µs t2 Bit Time at 4.8kbaud 20 8 µs t2 Bit Time at 2.4kbaud 41 6 µs Notes: 1. Receive Pulse Detection Cri teria: A recei ved pulse i s considered detected if the recei ved pulse i s a minimum of 1 .4 1µs. 2. IRTX: CRC Bit 0: 1 = RCV active low nIRTX: CRC Bit 0: 0 = RCV active high FIGURE 10 - IrDA RECEIVE TIMING 6 14 DATA 1 0 1 0 0 1 1 1 1 0 0 t2 t1 t2 t1 IRTX nIRTX Parameter mi n typ max un its t1 Pulse Width at 1 15kba ud 1.41 1.6 2.71 µs t1 Pulse Width at 57.6kba ud 1.41 3.22 3.69 µs t1 Pulse Width at 38.4kba ud 1.41 4.8 5.53 µs t1 Pulse Width at 19.2kba ud 1.41 9.7 11.07 µs t1 Pulse Wid th at 9.6kba ud 1.41 19.5 22.13 µs t1 Pulse Wid th at 4.8kba ud 1.41 39 44.27 µs t1 Pulse Wid th at 2.4kba ud 1.41 78 88.55 µs t2 Bit Time at 115kba ud 8.68 µs t2 Bit Time at 57.6kbaud 17.4 µs t2 Bit Time at 38.4kbaud 26 µs t2 Bit Time at 19.2kbaud 52 µs t2 Bit Time at 9.6kba ud 1 04 µs t2 Bit Time at 4.8kba ud 2 08 µs t2 Bit Time at 2.4kba ud 4 16 µs No te s: 1. IrDA @ 115k is HPSIR compatible. IrDA @ 2400 will allow comp ati bil ity with HP95LX and 48 SX. 2. IRTX: CRC Bit 1: 1 = XMIT active low nIRTX: CRC Bit 1: 0 = XMIT acti ve high FIGURE 11 - IrDA TRANSMIT TIMING 7 14 DATA 0 1 0 1 0 0 1 1 0 1 1 t1 t2 IRTX nIRTX t3 t4 MIRTX t5 t6 nMIRTX Parameter min typ max uni ts t1 Modulated Output Bit Time µs t2 Off Bit Time µs t3 Modul ated Output " On" 0 .8 1 1 .2 µs t4 Modul ated Outp ut "Off" 0 .8 1 1 .2 µs t5 Modul ated Output " On" 0 .8 1 1 .2 µs t6 Modul ated Outp ut "Off" 0 .8 1 1 .2 µs N otes: 1. IRTX: CRC Bit 1: 1 = XMIT active low nIRTX: CRC Bit 1: 0 = XMIT active high MIRTX, nMIRTX are the modulated ou tp uts FIGURE 12 - AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING 8 14 DATA 0 1 0 1 0 0 1 1 0 1 1 t1 t2 IRRX n IRRX t3 t4 MIRRX t5 t6 nMIRRX Parameter min typ max units t1 Mo dula ted Ou tput Bit Time µs t2 Off Bit Time µs t3 Modu lated Output "On" 0.8 1 1.2 µs t4 Modu lated Output "Off" 0.8 1 1.2 µs t5 Modu lated Output "On" 0.8 1 1.2 µs t6 Modu lated Output "Off" 0.8 1 1.2 µs Notes: 1. IRRX: CRC Bit 0: 1 = RCV active low nIRR X: CRC Bit 0: 0 = RCV active high MIRRX, nMIRRX are the modulated o utputs FIGURE 13 - AMPLITUDE SHIFT KEYED IR RECEIVE TIMING 149 PD0- P D7 t6 nI OW t1 nINIT, nSTROBE. nAUTOFD, SLCTIN PIN TR (SP P) nACK t2 t4t3PINTR ( ECP or EPP E nabled) n FAULT (ECP) nERROR (E CP) t5 t2 t3 PINTR Par ame ter min typ m ax units t1 nINIT, n STROBE, nAUTOFD Delay from 1 00 ns nIOW Inactive t2 PINTR Del ay from nACK, nFAULT 60 ns t3 PIN TR Active Low in ECP and EPP 3 00 ns 2 00 Mo des PINTR Delay from nACK t4 1 05 ns nERROR Active to PINTR Active t5 1 05 ns PD0-PD7 Delay from nIOW Active t6 1 00 ns NOTE: PI NTR is the i nt err upt assigned to the Parallel Port FIGURE 14 - PARALLEL PORT TIMING 0 15 t 18 AX t9 SD<7:0> t 17 t8 t 12 t 19 n IOW t 10 t 11 IO CH RDY t 13 t 20 t2 n WR ITE t1 t5 PD<7: 0> t 16 t3 t 14 t4 nDATAST nADDRSTB t 15 t6 t7 nWAIT Parameter min max units N ot es t1 n IOW Ass erted to PDATA Valid 0 50 ns t2 nWAIT As se rt ed to nWRITE Chan ge 60 1 85 ns 1 t3 n WR ITE to Comman d As sert ed 5 35 ns t4 nWAIT Deass erted to Co mmand Deasserted 60 1 90 ns 1 t5 nWAIT Asserted t o PD ATA Inv alid 0 ns 1 t6 Time O ut 10 12 µs t7 Com ma nd D easserted to nWAIT Asserted 0 ns t8 SD A TA Valid to IOW As se rt ed 10 ns t9 nIOW Deasserted to DATA Inv alid 0 ns t 10 n IOW Ass erted to IOC HRDY As se rt ed 0 24 ns t 11 WAIT Deass er ted to nI OCH RDY Deas se rt ed 60 1 60 ns 1 t 12 I OCH RDY Deassert ed to nIOW De as sert ed 10 ns t 13 n IOW Asserted to nW RITE As se rt ed 0 70 ns t 14 nWAIT As se rt ed to Command As se rt ed 60 2 10 ns 1 t 15 Com ma nd Asserted to nWAIT Deas sert ed 0 10 µs t 16 PDATA Valid to Command As se rt ed 10 ns t 17 Ax Valid to nIOW As se rt ed 40 ns t 18 n IOW De as ser ted to Ax Inv alid 10 ns t 19 n IOW Deasserted to nIOW or nIOR Asserted 40 ns t 20 nWA IT Ass er te d to nWR ITE Ass erted 60 1 85 ns 1 1. WAIT must be filt er ed to com pe ns at e f or ringing on the paralle l bus cable. WAIT is considered to have settled aft er it d oes not t ransiti on for a minimum of 50 ns ec. 1 15 FIGURE 15 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE t20 AX t19 t11 t22 IOR t13 t12 SD<7:0> t18 t8 t10 IOCHRDY t9 t21 t17 nWRITE ens driva bautt2 t25 t5 t4 t16lby pe PD<7:0> t28 t1 t14 t3 DATASTB AD DRSTB t15 t7 t6 nWAIT Timing parame te r table fo r the EPP Data or Addre ss Read Cycle is found on next pag e. 2 15 FIGURE 16A - EPP 1.9 DATA OR ADDRESS READ CYCLE riphera PD Parameter min max units Notes t1 PDATA Hi-Z to Command Asserted 30 ns 0 t2 nIOR Asserted to PDATA Hi -Z 50 ns 0 nWAIT Deasser ted to Com ma nd 1 80 ns 1 t3 60 Deasserted t4 Command Deasserted to PDATA Hi-Z ns 0 t5 C ommand Asser ted to PDATA Val id ns 0 t6 PDATA Hi-Z to n WAIT Deasserted µs 0 t7 PDATA Valid to nWAIT Deasserted ns 0 t8 n IOR Assertd to IOCHRDY Asserted 24 ns 0 t9 nWR ITE Deasser ted to n IOR Asserted ns 2 0 t10 nWAIT Deasserted to IOCHRDY 1 60 ns 1 60 Deasserted t11 IOCHRDY Dea sserted to n IOR 0 ns Deasserted t12 nIOR De asserted to SDATA Hi-Z (Ho ld 40 ns 0 Time) t13 PDATA Vali d to SDATA Val id 75 ns 0 t14 nWAIT Asserted to Command Asserted 0 1 95 ns t15 Time Ou t 12 µs 10 t16 nWAIT Deasserted to PDATA D riven 1 90 ns 1 60 t17 nWAIT Deasser ted to nWRITE Modi fied 1 90 ns 1,2 60 t18 SDATA Valid to IOCHR DY Deasserted 85 ns 3 0 t19 Ax Valid to nIOR Asserted ns 40 t20 nIOR Deasserted to Ax Invalid 10 ns 10 t21 nWAIT Asserted to nWRITE Deasserted 1 85 ns 0 t22 nIOR Deasser te d to nIOW or nIOR ns 40 Asserted t25 1 80 ns 1 60 n WAIT Asserted to PDATA Hi-Z t28 ns 1 WRITE Deasserted to Co mma nd 1. n WAIT is considered to ha ve settled a fter it does not transition for a minimum of 50 ns . 2. When not executing a write cycle, EPP nWRITE is inacti ve h igh . 3. 85 is tru e only if t7 = 0 . 3 15 FIGURE 16B - EPP 1.9 DATA OR ADDRESS READ CYCLE TIMING PARAMETERS t18 AX t 9 SD<7:0> t17 t 6 t 8 t12 t19 nIOW t10 t20 t11 IOCHRDY t13 t 2 nWRITE t 1 t 5 PD<7:0> t16 t 3 t 4 nDATAST nA DDRSTB t21 nWAIT Para meter min max units N ot es t1 nIOW Ass erted to PD AT A Valid 0 50 ns t2 Command D esssert ed to nWRITE Chan ge 0 40 ns t3 nWRITE to Command 5 35 ns t4 nIOW De ass erted to Co mmand De assert ed 50 ns 2 t5 Command Deasserted to PDATA Invalid 50 ns t6 Time Out 10 12 µs t8 SDATA Valid to nIOW As sert ed 10 ns t9 nIOW Deasserted to DATA Inv alid 0 ns t 10 n IOW Ass erted to IOCHRDY As se rt ed 0 24 ns t 11 n WAIT Deassert ed to IOCHRDY Deas sert ed 40 ns t 12 I OCH RDY Deassert ed to nIOW De assert ed 10 ns t 13 nIOW As serted to nW RITE Asserted 0 50 ns t 16 PD A TA Valid to Command As se rt ed 10 35 ns t 17 Ax Valid to nIOW As sert ed 40 ns t 18 nIOW De as serted to Ax Inv alid 10 µs t 19 nIOW Deasserted to nIOW or nIOR Asserted 100 ns t 20 n WAIT As serted to IOCHRD Y Deasserted 45 ns t 21 Command Deasserted to nWAIT Deas sert ed 0 ns 1. WRITE is controlled by clearing the PDIR b it to "0" in the control register be fore performing an EPP Write. 2. This number is only valid if WAIT is active when nIOW goes active. 4 15 FIGURE 17 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE t20 AX t15 t19 t11 t22 nIOR t13 t12 S D<7:0> t8 t3 t10 IOCHRDY nWRITE t5 t4 P D<7:0> t23 t2 nDATAS TB nA DD RS TB t21 nWAIT Parameter mi n max unit s Notes t 2 nIOR De as se rt ed to Command Deass erted 5 0 ns t 3 nWAIT Asserted to IOC HRDY D eass erted 0 4 0 ns t 4 Co mmand Deasserted to PDATA Hi-Z 0 ns t 5 Com ma nd Asserted to PDATA Valid 0 ns t 8 n IO R As serted to IOCHRDY Asserted 2 4 ns t10 nWA IT Deasserted to nIOCHRDY Deasserted 5 0 ns t11 n IOC HRDY D easserted to nIOR D eass erted 0 ns t12 nI OR De as serted to SDATA Hi gh-Z (Hold Time) 0 4 0 ns t13 PData V alid to SDATA Valid 4 0 ns t15 Time Ou t 1 0 1 2 µs t19 Ax Valid to nI OR Asserted 4 0 ns t20 n IO R Deasse rt ed to Ax Invalid 1 0 ns t21 Com mand Deasserted to nWAIT Deasserted 0 ns t22 nIOR Deass erted to nIOW or nI OR Asserted 4 0 ns t23 nIOR Asserted t o C ommand Asserted 5 5 ns 1. nWRITE is controlled by setting the PDIR bit to "1 " in the control register before performing an EPP Read . 5 15 FIGURE 18 - EPP 1.7 DATA OR ADDRESS READ CYCLE ECP PARALLEL PORT TIMING Parallel Port FIFO (Mode 101)peripheral then accepts the data and sets PeriphAck (Busy) low, completing the transfer. The standard parallel port is run at or near the peak 500 Kbps allowed in the forward direction using DMA. The state machine does notThe timing is designed to provide 3 cable examine nAck and begins the next transfer-trip times for data setup if Data is driven simultaneously with HostClk (nStrobe). ECP Parallel Port Timing-Idle Phase The timing is designed to allow operation atThe peripheral has no data to send and keeps approximately 2.0Mbytes/sec over a 15ft cable.PeriphClk high. The host is idle and keeps If a shorter cable is used then the bandwidth willHostAck low. The interface transfers data and commands When the host has no data to send it keepsfrom the peripheral to the host using an HostClk (nStrobe) high and the peripheral will leave PeriphClk (Busy) low. The Reverse Data Transfer Phase may be entered from the Reverse-Idle Phase. After the previous byte has beed accepted the host sets The interface transfers data and commandsHostAck (nAutoFd) low. The peripheral then from the host to the peripheral using ansets PeriphClk (nAck) low when it has data interlocked PeriphAck and HostClk. Theto send. The data must be stable for the peripheral may indicate its desire to send dataspecified setup time prior to the falling edge of PeriphClk. When the host is ready it to accept a byte it sets. HostAck (nAutoFd) high to The Forward Data Transfer Phase may beacknowledge the handshake. The peripheral entered from the Forward-Idle Phase. While inthen sets PeriphClk (nAck) high. After the host the Forward Phase the peripheral mayhas accepted the data it sets HostAck (nAutoFd) asynchronously assert the nPeriph Requestlow, completing the transfer. This sequence is (nFault) to request that the channel be reversed.shown in Figure 21. When the peripheral is not busy it sets PeriphAck (Busy) low. The host then sets OutputDrivers HostClk (nStrobe) low when it is prepared to send data. The data must be stable for theTo facilitate higher performance data transfer, specified setup time prior to the falling edge ofthe use of balanced CMOS active drivers for HostClk. The peripheral then sets PeriphAckcritical signals (Data, HostAck, HostClk, (Busy) high to acknowledge the handshake. ThePeriphAck, PeriphClk) are used ECP Mode. host then sets HostClk (nStrobe) high. TheBecause the use of active drivers can present 6 15 to the host by asserting nPeriph Request. Forward Data Transfer Phase interlocked HostAck and PeriphClk. Forward-Idle Reverse Data Transfer Phase increase. Reverse based on Busy. Refer to Figure 19. round This sequence is shown in Figure 20. compatibility problems in Compatible Mode (thein the IEEE 1284 Extended Capabilities Port control signals, by tradition, are specifiedProtocol and ISA Interface Standard, Rev. 1.09, as open-collector), the drivers are dynamicallyJan. 7, 1993, available from Microsoft. changed from open-collector to totem-pole. Thedynamic driver change must be implemented timing for the dynamic driver change is specifiedproperly to prevent glitching the outputs. t 6 t 3 PDATA t 1 t 2 t 5 nS TROBE t 4 BUSY Parameter min max units Notes t1 DATA Valid to nSTROBE Active 600 ns t2 nSTROBE Active Pulse Width 600 ns t3 DATA Hold from nSTROBE Inactive 450 ns 1 t4 n STROBE Active to BUSY Active 500 ns t5 BUSY Inactive to nSTROBE Active 680 ns t6 BUSY Inactive to PDA TE Invalid 80 ns 1 1. The da ta i s held un til BUSY goes inactive or for ti me t3, whi chever is longer. Th is only applie s if ano ther data tra nsfer is pending. If no other data transfer is pending, the data is held i ndefinitely. FIGURE 19 - PARALLEL PORT FIFO TIMING 7 15 The t3 nAUTOFD t4 PDATA<7:0> t2 t1 t7 t8 nS TROBE t6 t5 t6 BUSY Parameter min max units Notes t1 n AUTOFD Va lid to nSTROBE Asserted 0 60 ns t2 PDATA Va lid to nSTROBE Asserted 0 60 ns t3 BUSY Deasserted to nAUTOFD 80 180 ns 1 ,2 Cha nged t4 n BU SY Deasser ted to PDATA Cha nged 80 180 ns 1 ,2 t5 nSTROBE Asserted to BUSY Asserted 0 ns t6 nSTROBE Dea sserted to Busy 0 ns Deasserted t7 nBUSY Deasser ted to n STROBE 80 200 ns 1 ,2 Asserted t8 nBUSY Asserted to nSTR OBE 80 180 ns 2 Deasserted 1. Maximum value only ap plie s if there is da ta in th e FIFO waiting to be written out. 2. BU SY is not considered asserted or deasserted u ntil it is stable for a minimum of 75 to 130 ns. FIGURE 20 - ECP PARALLEL PORT FORWARD TIMING 8 15 t 2 PDATA< 7: 0> t 1 t 5 t 6 nACK t 4 t 3 t 4 nAUTOFD Parameter min max units Notes t1 PDATA Valid to nACK Asserted 0 ns t2 nAUTOFD Deasserted to PDATA 0 ns C hanged t3 nACK Asse rted to n AUT OFD 80 2 00 ns 1,2 Deasserted t4 nACK D easser ted to n AUTOFD 80 2 00 ns 2 Asserted t5 n AUTOFD Asserted to nACK Asserted 0 ns t6 nAU TOFD Deasser ted to nACK 0 ns Deasserted 1. Maximum value only applies if there is room in the FIFO and a terminal count has no t been received. ECP can stal l b y keeping nAU TOFD lo w. 2. nACK is not considered asserted or deasserted un ti l it is stable for a minimum of 75 to 130 ns. FIGURE 21 - ECP PARALLEL PORT REVERSE TIMING 159 D D1 E E1 e W A A2 TD /TE H 0 0. 10 A1 L -C- L1 D IM MIN MAX MIN MAX Not es : A 2. 80 3. 15 .1 10 .1 24 1) C oplan arity is 0.100mm (. 00 4") maximum. A1 0.1 0. 45 .0 04 .0 18 2) Tolera nce on the posit ion of the leads is A2 2. 57 2. 87 .1 01 .1 13 0.2 00mm (. 00 8") maximum. D 23 .4 24. 15 .9 21 .9 51 3) Pack age bo dy d imensions D1 and E1 do n ot D1 19 .9 20 .1 .7 83 .7 91 include the mold p ro tr us ion. Maximum mold 17 .4 18. 15 .6 85 .7 15 E pr otrusio n is 0.25mm (. 01 0"). 13 .9 14 .1 .5 47 .5 55 E1 4) Dimensions TD and TE are impo rt ant f or testing 0.1 0.2 .0 04 .0 08 H by ro botic handler. Only above c ombinations of (1) 0. 65 0. 95 .0 26 .0 37 or (2) are acc eptable. L 1.8 2.6 .0 71 .1 02 5) Co nt rolling dimension: millimeter . Dimensions L1 in inches for r eference only and not n ec es sarily 0.65 BSC .0256 BS C e accurate. 0 0° 12° 0° 12° W .2 .4 .0 08 .0 16 21 .8 TD(1) 22 .2 .8 58 .8 74 15 .8 TE(1) 16 .2 .6 22 .6 38 22. 21 TD(2) 22. 76 .8 74 .8 96 16. 27 TE(2) 16. 82 .6 41 .6 62 FIGURE 22 - 100 PIN QFP PACKAGE OUTLINE 0 16 D 3 D1 3 e E E1 5 W 2 D1/4 E1/4 DETAIL "A" R1 R2 0 L 4 A A2 L1 H SEE DETAIL "A" 0.10 1 A1 -C- NOM DIM MIN MAX 1.6 A A1 0.05 1.40 1.45 A2 1.35 16.00 16.25 D 15.75 14.00 14.10 D1 13.90 15.75 16.00 16.25 E 14.00 13.90 14.10 E1 0.20 H 0.60 L 0.45 0.75 1.00 L1 e 0.50 BSC 0 0° 8° 0.25 W 0.20 R1 0.20 R2 Notes: Coplanarity is 0.100mm maximum. 1 Tolerance on the position of the leads is 0.13mm maximum. 2 Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25mm per side. 3 4 Dimension for foot length L are measured at the gauge plane 0.25mm above the seating plane. 5 Details of pin 1 identifier are optional but must be located within the zone indicated. 6. Controlling dimension: millimeter FIGURE 23 - 100 PIN TQFP PACKAGE OUTLINE 161 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. FDC37C669 Rev. 06/29/2007 162