MCP601/2/3/4 M 2.7V to 5.5V Single Supply CMOS Op Amps FEATURES DESCRIPTION • Single Supply: 2.7V to 5.5V The Microchip Technology Inc. MCP601/2/3/4 family of low-power op amps (operational amplifiers) are offered • Rail-to-Rail Output in single (MCP601), single with Chip Select (MCP603), • Input Range Includes Ground dual (MCP602) and quad (MCP604) configurations. • Gain Bandwidth Product: 2.8 MHz (typ.) These op amps utilize an advanced CMOS technology, • Unity Gain Stable which provides low bias current, high-speed operation, • Low Quiescent Current: 230 µA/amplifier (typ.) high open-loop gain, and rail-to-rail output swing. This product offering operates with a single supply voltage • Chip Select: MCP603 that can be as low as 2.7V, while drawing 230 µA (typ.) • Temperature Ranges: of quiescent current per amplifier. In addition, the - Industrial: -40°C to +85°C common mode input voltage range goes 0.3V below - Extended: -40°C to +125°C ground, making these amplifiers ideal for single supply • Available in Single, Dual and Quad operation. These devices are appropriate for low-power, battery- TYPICAL APPLICATIONS operated circuits due to the low quiescent current, for A/D convert driver amplifiers because of their wide • Portable Equipment bandwidth or for anti-aliasing filters by virtue of their low • A/D Converter Driver input bias current. • Photo Diode Pre-amp The MCP601, MCP602 and MCP603 are available in • Analog Filters standard 8-lead PDIP, SOIC and TSSOP packages. • Data Acquisition The MCP601 and MCP601R are also available in a standard 5-lead SOT23 package and the MCP603 in a • Notebooks and PDAs standard 6-lead SOT23 package. The MCP604 is • Sensor Interface offered in standard 14-lead PDIP, SOIC and TSSOP packages. AVAILABLE TOOLS The MCP601/2/3/4 family is available in the Industrial • SPICE Macro Models at www.microchip.com and Extended temperature ranges and also has a ® power supply range of 2.7V to 5.5V. • FilterLab Software at www.microchip.com PACKAGE TYPES MCP601 MCP604 MCP602 MCP603 PDIP, SOIC, TSSOP PDIP, SOIC, TSSOP PDIP, SOIC, TSSOP PDIP, SOIC, TSSOP NC V NC V V 1 8 NC 1 V 1 OUTA 8 1 8 CS OUTA 14 OUTD DD V V 2 7 V 2 V V V 2 13 7 V 2 7 V IN– DD INA– OUTB DD INA– IN– IND– V V V 3 6 V 3 V V 3 12 IN+ INA+ 6 3 6 V INA+ V OUT INB– IN+ IND+ OUT V V V V 4 5 4 4 11 SS NC SS 5 SS 4 5 DD V V NC SS INB+ V 10 5 INB+ V INC+ MCP601 MCP601R MCP603 V 6 9 V INB– INC– SOT23-5 SOT23-5 SOT23-6 V 7 8 OUTB V V V V OUTC 1 5 V 1 5 V 1 6 V OUT OUT OUT DD SS DD V 2 V 2 V 2 5 CS SS DD SS V V V 3 4 V 3 4 V 3 4 V IN+ IN+ IN+ IN– IN– IN–  2003 Microchip Technology Inc. DS21314E-page 1 MCP601/2/3/4 1.0 ELECTRICAL PIN FUNCTION TABLE CHARACTERISTICS Name Function V , V , V , V , V Non-inverting Inputs IN+ INA+ INB+ INC+ IND+ Absolute Maximum Ratings † V , V , V , V , V Inverting Inputs IN– INA– INB– INC– IND– V - V .........................................................................7.0V DD SS V Positive Power Supply DD All inputs and outputs...................... V - 0.3V to V + 0.3V SS DD V Negative Power Supply SS Difference Input voltage ........................................ |V - V | DD SS V , V , V , V , Outputs Output Short Circuit Current...................................continuous OUT OUTA OUTB OUTC V Current at Input Pin.......................................................±2 mA OUTD Current at Output and Supply Pins .............................±30 mA CS Chip Select Storage temperature .....................................-65°C to +150°C NC No Internal Junction temperature ..................................................+150°C Connection ESD protection on all pins (HBM; MM) ................ ≥ 3 kV; 200V † Notice: Stresses above those listed under “Maximum Rat- ings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Expo- sure to maximum rating conditions for extended periods may affect device reliability. DC CHARACTERISTICS Electrical Specifications: Unless otherwise specified, T = +25°C, V = +2.7V to +5.5V, V = GND, V = V /2, A DD SS CM DD V ≈ V /2, and R = 100 kΩ to V /2. OUT DD L DD Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage V -2 ±0.7 +2 mV OS Industrial Temperature V -3 ±1 +3 mV T = -40°C to +85°C (Note 1) OS A Extended Temperature V -4.5 ±1 +4.5 mV T = -40°C to +125°C (Note 1) OS A Input Offset Temperature Drift ΔV /ΔT —±2.5 — µV/°CT = -40°C to +125°C OS A A Power Supply Rejection PSRR 80 88 — dB V = 2.7V to 5.5V DD Input Current and Impedance Input Bias Current I —1 — pA B Industrial Temperature I —20 60 pAT = +85°C (Note 2) B A Extended Temperature I — 450 5000 pA T = +125°C (Note 2) B A Input Offset Current I —±1 — pA OS 13 Common Mode Input Impedance Z — — Ω||pF CM 10 ||6 13 Differential Input Impedance Z — — Ω||pF DIFF 10 ||3 Common Mode Common Mode Input Range V V -0.3 — V -1.2 V CMR SS DD Common Mode Rejection Ratio CMRR 75 90 — dB V = 5.0V, V = -0.3V to 3.8V DD CM Open-loop Gain DC Open-loop Gain (large signal) A 100 115 — dB R = 25 kΩ to V /2, OL L DD V = 100 mV to V - 100 mV OUT DD A 95 110 — dB R = 5 kΩ to V /2, OL L DD V = 100 mV to V - 100 mV OUT DD Output Maximum Output Voltage Swing V , V V +15 — V -20 mV R = 25 kΩ to V /2, Output overdrive = 0.5V OL OH SS DD L DD V , V V +45 — V -60 mV R = 5 kΩ to V /2, Output overdrive = 0.5V OL OH SS DD L DD Linear Output Voltage Swing V V +100 — V -100 mV R = 25 kΩ to V /2, A ≥ 100 dB OUT SS DD L DD OL V V +100 — V -100 mV R = 5 kΩ to V /2, A ≥ 95 dB OUT SS DD L DD OL Output Short Circuit Current I —±22 — mAV = 5.5V SC DD I —±12 — mAV = 2.7V SC DD Power Supply Supply Voltage V 2.7 — 5.5 V DD Quiescent Current per Amplifier I —230 325 µAI = 0 Q O Note 1: Maximum and minimum specified for PDIP and SOIC packages only. Typical specs refer to all packages. 2: Maximum and minimum specified for PDIP, SOIC and TSSOP packages only. Typical specs refer to all packages. DS21314E-page 2  2003 Microchip Technology Inc. MCP601/2/3/4 AC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, T = +25°C, V = +2.7V to +5.5V, V = GND, V = V /2, A DD SS CM DD V ≈ V /2, R = 100 kΩ to V /2,and C = 50 pF. OUT DD L DD L Parameters Sym Min Typ Max Units Conditions Frequency Response Gain Bandwidth Product GBWP — 2.8 — MHz Phase Margin PM — 50 — ° G = +1 V/V Step Response Slew Rate SR — 2.3 — V/µs G = +1 V/V Settling Time (0.01%) t — 4.5 — µs G = +1 V/V, 3.8V step settle Noise Input Noise Voltage E —7 — µV f = 0.1 Hz to 10 Hz ni P-P Input Noise Voltage Density e —29 —nV/√Hz f = 1 kHz ni e —21 —nV/√Hz f = 10 kHz ni Input Noise Current Density i —0.6 — fA/√Hz f = 1 kHz ni MCP603 CHIP SELECT CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, T = +25°C, V = +2.7V to +5.5V, V = GND, V = V /2, A DD SS CM DD V ≈ V /2, R = 100 kΩ to V /2, and C = 50 pF. OUT DD L DD L Parameters Sym Min Typ Max Units Conditions DC Characteristics CS Logic Threshold, Low V V —0.2 V V IL SS DD CS Input Current, Low I -1.0 — — µA CS = 0.2V CSL DD CS Logic Threshold, High V 0.8 V —V V IH DD DD CS Input Current, High I —0.7 2.0 µACS = V CSH DD Shutdown V current I -2.0 -0.7 — µA CS = V SS Q_SHDN DD Amplifier Output Leakage in Shutdown I —1 — nA O_SHDN CS Threshold Hysteresis HYST — 0.3 — V Internal switch Timing CS Low to Amplifier Output Turn-on t —3.1 10 µs CS ≤ 0.2V , G = +1 V/V ON DD Time CS High to Amplifier Output High-Z Time t —100 — ns CS ≥ 0.8V , G = +1 V/V, No Load OFF DD CS t t ON OFF V Hi-Z Output Active Hi-Z OUT I 2 nA (typ.) 230 µA (typ.) DD I -700 nA (typ.) -230 µA (typ.) SS CS 2nA (typ.) 700 nA (typ.) Current FIGURE 1-1: MCP603 Chip Select (CS) timing diagram.  2003 Microchip Technology Inc. DS21314E-page 3 MCP601/2/3/4 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V = +2.7V to +5.5V and V = GND. DD SS Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +85 °C Industrial temperature parts A T -40 — +125 °C Extended temperature parts A Operating Temperature Range T -40 — +125 °C Note A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 5L-SOT23 θ — 256 — °C/W JA Thermal Resistance, 6L-SOT23 θ — 230 — °C/W JA Thermal Resistance, 8L-PDIP θ —85 — °C/W JA Thermal Resistance, 8L-SOIC θ — 163 — °C/W JA Thermal Resistance, 8L-TSSOP θ — 124 — °C/W JA Thermal Resistance, 14L-PDIP θ —70 — °C/W JA Thermal Resistance, 14L-SOIC θ — 120 — °C/W JA Thermal Resistance, 14L-TSSOP θ — 100 — °C/W JA Note: The Industrial temperature parts operate over this extended range, but with reduced performance. The Extended temperature specs do not apply to Industrial temperature parts. In any case, the internal Junction temperature (T ) must not exceed the absolute maximum specification of 150°C. J DS21314E-page 4  2003 Microchip Technology Inc. MCP601/2/3/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T = +25°C, V = +2.7V to +5.5V, V = GND, V = V /2, R = 100 kΩ to V /2, A DD SS CM DD L DD V ≈ V /2, and C = 50 pF. OUT DD L 120 0 300 I = 0 -40°C O 100 -30 250 Gain +25°C 80 -60 Phase 200 60 -90 +85°C 150 40 -120 +125°C 20 -150 100 0 -180 50 -20 -210 0 -40 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 -240 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.1 1 10 100 1k 10k 100k 1M 10M Supply Voltage (V) Frequency (Hz) FIGURE 2-1: Open-Loop Gain, Phase vs. FIGURE 2-4: Quiescent Current vs. Frequency. Supply Voltage. 300 3.5 V = 5.0V I = 0 DD O 3.0 250 Falling Edge V = 5.5V DD 2.5 200 2.0 150 Rising Edge V = 2.7V DD 1.5 100 1.0 50 0.5 0 0.0 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-2: Slew Rate vs. Temperature. FIGURE 2-5: Quiescent Current vs. Temperature. 10,000 10µ 5.5 110 5.0 100 GBWP 4.5 90 4.0 80 1,000 1µ 3.5 70 3.0 60 2.5 50 PM, G = +1 2.0 40 100n 100 1.5 30 1.0 20 0.5 10 0.0 0 10n10 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 -50 -25 0 25 50 75 100 125 0.1 1 10 100 1k 10k 100k 1M Ambient Temperature (°C) Frequency (Hz) FIGURE 2-3: Gain Bandwidth Product, FIGURE 2-6: Input Noise Voltage Density Phase Margin vs. Temperature. vs. Frequency.  2003 Microchip Technology Inc. DS21314E-page 5 Gain Bandwidth Product Slew Rate (V/µs) Open-Loop Gain (dB) (MHz) Phase Margin, G = +1 (°) Open-Loop Phase (°) Quiescent Current per Input Noise Voltage Density Quiescent Current per (V/ Hz) Amplifier (µA) √ Amplifier (µA) MCP601/2/3/4 = +25°C, V = +2.7V to +5.5V, V = GND, V = V /2, R = 100 kΩ to V /2, Note: Unless otherwise indicated, T A DD SS CM DD L DD V ≈ V /2, and C = 50 pF. OUT DD L 18% 16% 1200 Samples 1200 Samples 16% 14% T = -40 to +125°C A 14% 12% 12% 10% 10% 8% 8% 6% 6% 4% 4% 2% 2% 0% 0% -2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 -10 -8 -6 -4 -2 0 2 4 6 8 10 Input Offset Voltage (mV) Input Offset Voltage Drift (µV/°C) FIGURE 2-7: Input Offset Voltage. FIGURE 2-10: Input Offset Voltage Drift. 0.5 100 0.4 V = 5.5V 0.3 DD 95 0.2 0.1 90 PSRR V = 2.7V DD 0.0 -0.1 85 CMRR -0.2 -0.3 80 -0.4 -0.5 75 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-8: Input Offset Voltage vs. FIGURE 2-11: CMRR, PSRR vs. Temperature. Temperature. 800 800 V = 2.7V V = 5.5V DD DD 700 700 T = -40°C A T = -40°C A 600 600 T = +25°C A T = +25°C A 500 500 T = +85°C A T = +85°C A 400 400 T = +125°C A T = +125°C A 300 300 200 200 100 100 T = +125°C A 0 0 T = +125°C A -100 -100 -200 -200 -0.5 0.0 0.5 1.0 1.5 2.0 Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-9: Input Offset Voltage vs. FIGURE 2-12: Input Offset Voltage vs. Common Mode Input Voltage with V = 2.7V. Common Mode Input Voltage with V = 5.5V. DD DD DS21314E-page 6  2003 Microchip Technology Inc. Input Offset Voltage (mV) Input Offset Voltage (µV) Percentage of Occurrences CMRR, PSRR (dB) Percentage of Occurrences Input Offset Voltage (µV) -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 MCP601/2/3/4 = +25°C, V = +2.7V to +5.5V, V = GND, V = V /2, R = 100 kΩ to V /2, Note: Unless otherwise indicated, T A DD SS CM DD L DD V ≈ V /2, and C = 50 pF. OUT DD L 150 100 No Load PSRR+ 90 140 PSRR- 80 130 70 CMRR 60 120 50 110 40 30 100 20 V = 5.0V DD 90 1.E+03 1.E+04 1.E+05 1.E+06 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 10 1k 10k 100k 1M 100 1k 10k 100k Frequency (Hz) Frequency (Hz) FIGURE 2-13: Channel-to-Channel FIGURE 2-16: CMRR, PSRR vs. Separation vs. Frequency. Frequency. 1000 1000 V = 5.5V DD I , +125°C B V = 4.3V CM V =5.5V DD 100 100 max. V ≥ 4.3V CMR I , +85°C B I B I , +125°C I 10 OS 10 OS I , +85°C OS 1 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 25 35 45 55 65 75 85 95 105 115 125 Ambient Temperature (°C) Common Mode Input Voltage (V) FIGURE 2-14: Input Bias Current, Input FIGURE 2-17: Input Bias Current, Input Offset Current vs. Ambient Temperature. Offset Current vs. Common Mode Input Voltage. 120 120 R =25 kΩ L 110 V =5.5V 110 DD 100 100 90 V =2.7V DD 90 80 80 1.E+02 1.E+03 1.E+04 1.E+05 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 100 1k 10k 100k Load Resistance (Ω) Supply Voltage (V) FIGURE 2-15: DC Open-Loop Gain vs. FIGURE 2-18: DC Open-Loop Gain vs. Load Resistance. Supply Voltage.  2003 Microchip Technology Inc. DS21314E-page 7 Input Bias and Offset Currents Channel to Channel Separation DC Open-Loop Gain (dB) (pA) (dB) DC Open-Loop Gain (dB) Input Bias and Offset Currents CMRR, PSRR (dB) (pA) MCP601/2/3/4 = +25°C, V = +2.7V to +5.5V, V = GND, V = V /2, R = 100 kΩ to V /2, Note: Unless otherwise indicated, T A DD SS CM DD L DD V ≈ V /2, and C = 50 pF. OUT DD L 3.5 100 130 V =5.0V DD V =5.5V, R =25 kΩ DD L 3.0 90 120 GBWP 2.5 80 110 2.0 70 1.5 60 100 V =5.5V, R =5 kΩ DD L 1.0 50 V =2.7V, R =25 kΩ PM, G = +1 90 DD L 0.5 40 V =2.7V, R =5 kΩ DD L 80 0.0 1.E+02 1.E+03 1.E+04 1.E+05 30 100 1k 10k 100k -50 -25 0 25 50 75 100 125 Load Resistance (Ω) Ambient Temperature (°C) FIGURE 2-19: Gain Bandwidth Product, FIGURE 2-22: DC Open-Loop Gain vs. Phase Margin vs. Load Resistance. Temperature. 1000 1,000 V =5.5V DD R tiedtoV /2 L DD V -V ,R =5 kΩ DD OH L 100 100 V -V ,R =5 kΩ OL SS L V -V DD OH V -V OL SS 10 10 V -V ,R =25 kΩ DD OH L V -V ,R =25 kΩ OL SS L 1 1 -50 -25 0 25 50 75 100 125 0.01 0.1 1 10 Output Current Magnitude (mA) Ambient Temperature (°C) FIGURE 2-20: Output Voltage Headroom FIGURE 2-23: Output Voltage Headroom vs. Output Current. vs. Temperature. 10 30 T = -40°C V = 5.0V A DD 25 T = +25°C A T = +85°C A 20 T = +125°C A 15 1 10 5 0 0.1 1.E+04 1.E+05 1.E+06 1.E+07 10k 100k 1M 10M 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Frequency (Hz) Supply Voltage (V) FIGURE 2-21: Maximum Output Voltage FIGURE 2-24: Output Short-Circuit Current Swing vs. Frequency. vs. Supply Voltage. DS21314E-page 8  2003 Microchip Technology Inc. Maximum Output Voltage Output Headroom (mV); Gain Bandwidth Product Swing (V ) V - V and V - V (MHz) P-P DD OH OL SS Phase Margin, G = +1 (°) Output Short Circuit Current Output Headroom (mV); DC Open-Loop Gain (dB) Magnitude (mA) V -V and V -V DD OH OL SS MCP601/2/3/4 = +25°C, V = +2.7V to +5.5V, V = GND, V = V /2, R = 100 kΩ to V /2, Note: Unless otherwise indicated, T A DD SS CM DD L DD V ≈ V /2, and C = 50 pF. OUT DD L 5.0 5.0 V = 5.0V V = 5.0V DD DD 4.5 4.5 G = +1 G = -1 4.0 4.0 3.5 3.5 3.0 3.0 2.5 2.5 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0.0 0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 1.E-05 0.0 0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 1.E-05 Time (1 µs/div) Time (1 µs/div) FIGURE 2-25: Large Signal Non-Inverting FIGURE 2-28: Large Signal Inverting Pulse Pulse Response. Response. 2.59 2.59 V = 5.0V V = 5.0V DD DD 2.57 2.57 G = -1 G = +1 2.55 2.55 2.53 2.53 2.51 2.51 2.49 2.49 2.47 2.47 2.45 2.45 2.43 2.43 2.41 2.41 0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 1.E-05 0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 1.E-05 Time (1 µs/div) Time (1 µs/div) FIGURE 2-26: Small Signal Non-Inverting FIGURE 2-29: Small Signal Inverting Pulse Pulse Response. Response. 5.5 0 V = 5.5V DD 5.0 CS -100 4.5 V =5.0V DD -200 4.0 G=+1 3.5 -300 V =2.5V IN 3.0 R = 100 kΩ to GND -400 L 2.5 -500 V Active OUT 2.0 1.5 -600 1.0 -700 0.5 -800 0.0 V High-Z OUT 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -0.5 0.0E+00 5.0E-06 1.0E-05 1.5E-05 2.0E-05 2.5E-05 3.0E-05 3.5E-05 4.0E-05 4.5E-05 5.0E-05 Time (5µs/div) Chip Select Voltage (V) FIGURE 2-27: Chip Select Timing FIGURE 2-30: Quiescent Current Through (MCP603). V vs. Chip Select Voltage (MCP603). SS  2003 Microchip Technology Inc. DS21314E-page 9 Output Voltage (20 mV/div) Output Voltage (V) Output Voltage, Chip Select Voltage (V) Quiescent Current Output Voltage (20 mV/div) Output Voltage (V) through V (µA) SS MCP601/2/3/4 = +25°C, V = +2.7V to +5.5V, V = GND, V = V /2, R = 100 kΩ to V /2, Note: Unless otherwise indicated, T A DD SS CM DD L DD V ≈ V /2, and C = 50 pF. OUT DD L 0.8 6 V = 5.5V V = +5.0V DD DD 0.7 5 G = +2 0.6 4 0.5 3 0.4 0.3 2 V IN 0.2 1 V OUT 0.1 0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -1 0.0E+00 5.0E-06 1.0E-05 1.5E-05 2.0E-05 2.5E-05 Chip Select Voltage (V) Time (5 µs/div) FIGURE 2-31: Chip Select Pin Input FIGURE 2-33: The MCP601/2/3/4 family of Current vs. Chip Select Voltage. op amps shows no phase reversal under input overdrive. 3.0 V = 5.0V Amplifier On DD 2.5 2.0 1.5 CS Hi to Low CS Low to Hi 1.0 0.5 Amplifier Hi-Z 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Chip Select Voltage (V) FIGURE 2-32: Hysteresis of Chip Select’s Internal Switch. DS21314E-page 10  2003 Microchip Technology Inc. Internal Chip Select Switch Chip Select Pin Current (µA) Output Voltage (V) (Input and Output Voltages (V) MCP601/2/3/4 The second specification that describes the output 3.0 APPLICATIONS INFORMATION swing capability of these amplifiers is the Linear Output The MCP601/2/3/4 family of operational amplifiers are Voltage Swing. This specification defines the maximum fabricated on Microchip’s state-of-the-art CMOS output swing that can be achieved while the amplifier is process. They are unity-gain stable and suitable for a still operating in its linear region. To verify linear wide range of general purpose applications. operation in this range, the large signal, DC Open-Loop Gain (A ), is measured at points 100 mV inside the OL 3.1 Input supply rails. The measurement must exceed the specified gains in the spec table. The MCP601/2/3/4 amplifier family is designed to not exhibit phase reversal when the input pins exceed the 3.3 MCP603 Chip Select supply rails. Figure 2-33 shows an input voltage that exceeds both supplies with no resulting phase The MCP603 is a single amplifier with Chip Select inversion. (CS). When CS is pulled high, the supply current drops to -0.7 µA (typ.), which is pulled through the CS pin to The Common Mode Input Voltage Range (V ) CMR V . When this happens, the amplifier output is put into includes ground in single supply systems (V ), but SS SS a high impedance state. Pulling CS low enables the does not include V . This means that the amplifier DD amplifier. If the CS pin is left floating, the amplifier may input behaves linearly as long as the Common Mode not operate properly. Figure1-1 is the Chip Select Input Voltage (V ) is kept within the specified V CM CMR timing diagram and shows the output voltage, supply limits (V -0.3V to V -1.2V at +25°C). SS DD currents and CS current in response to a CS pulse. Input voltages that exceed the input voltage range Figure2-27 shows the measured output voltage (V -0.3V to V -1.2V at +25°C) can cause excessive SS DD response to a CS pulse. current to flow into, or out of, the input pins. Current beyond ±2mA may cause reliability problems. 3.4 Capacitive Loads Applications that exceed this rating must externally limit the input current with a resistor (R ), as shown in IN Driving large capacitive loads can cause stability Figure 3-1. problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is R IN reduced. This produces gain peaking in the frequency V IN response with overshoot and ringing in the step response. MCP60X When driving large capacitive loads with these op amps (e.g., > 40 pF when G = +1), a small series resistor at the output (R in Figure 3-2) improves the ISO feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The (maximum expected V ) - V IN DD R ≥ bandwidth will be generally lower than the bandwidth IN 2mA with no capacitive load. V - (minimum expected V ) SS IN R ≥ IN 2mA R ISO V MCP60X OUT FIGURE 3-1: R limits the current flow IN into an input pin. C L 3.2 Rail-to-Rail Output R R G F There are two specifications that describe the output FIGURE 3-2: Output resistor R ISO swing capability of the MCP601/2/3/4 family of stabilizes large capacitive loads. operational amplifiers. The first specification, Maximum Output Voltage Swing, defines the absolute maximum Figure3-3 gives recommended R values for ISO swing that can be achieved under the specified load different capacitive loads and gains. The x-axis is the conditions. For instance, the output voltage swings to normalized load capacitance (C /G ) to make it easier L N within 15 mV of the negative rail with a 25 kΩ load to to interpret the plot for arbitrary gains. G is the circuit’s N V /2. Figure 2-33 shows how the output voltage is noise gain. For non-inverting gains, G and the gain DD N limited when the input goes beyond the linear region of are equal. For inverting gains, G is 1+|Gain| N operation. (e.g., -1 V/V gives G = +2 V/V). N  2003 Microchip Technology Inc. DS21314E-page 11 MCP601/2/3/4 1. Connect the guard ring to the inverting input pin 1,000 1k (V ) for non-inverting gain amplifiers, including IN– unity-gain buffers. This biases the guard ring to the common mode input voltage. 2. Connect the guard ring to the non-inverting input pin (V ) for inverting gain amplifiers and 100 100 IN+ G = +1 transimpedance amplifiers (convert current to N G t +2 N voltage, such as photo detectors). This biases the guard ring to the same reference voltage as the op amp (e.g., V /2 or ground). DD 1010 10 100 1,000 10,000 10p 100p 1n 10n 3.7 Typical Applications Normalized Load Capacitance; C / G (F) L N 3.7.1 ANALOG FILTERS FIGURE 3-3: Recommended R values ISO Figure3-5 and Figure3-6 show low-pass, second- for capacitive loads. order, Butterworth filters with a cutoff frequency of After selecting R for your circuit, double-check the ISO 10 Hz. The filter in Figure 3-5 has a non-inverting gain resulting frequency response peaking and step of +1 V/V, and the filter in Figure 3-6 has an inverting response overshoot in your circuit. Evaluation on the gain of -1 V/V. bench and simulations with the MCP601/2/3/4 SPICE macro model are very helpful. Modify R ’s value until ISO G = +1 V/V the response is reasonable. C 1 f = 10 Hz 47 nF P 3.5 Supply Bypass R R 2 With this family of operational amplifiers, the power 1 641 kΩ 382 kΩ supply pin (V for single supply) should have a local DD V IN bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-frequency performance. It also needs a C V MCP60X 2 OUT bulk capacitor (i.e., 1 µF or larger) within 100 mm to 22 nF provide large, slow currents. This bulk capacitor can be shared with other parts. nd FIGURE 3-5: 2 order, low-pass Sallen- 3.6 PCB Surface Leakage Key filter. In applications where low input bias current is critical, PCB (printed circuit board) surface leakage effects G = -1 V/V R 2 need to be considered. Surface leakage is caused by f = 10 Hz P 618 kΩ humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance 12 R R C between nearby traces is 10 Ω. A 5V difference would 3 1 1 cause 5 pA of current to flow. This is greater than the 618 kΩ 1.00 MΩ 8.2 nF MCP601/2/3/4 family’s bias current at +25°C (1 pA, V V IN OUT typ.). C 2 The easiest way to reduce surface leakage is to use a 47 nF MCP60X guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. V /2 DD An example of this type of layout is shown in Figure 3-4. nd FIGURE 3-6: 2 order, low-pass Multiple- Feedback filter. Guard Ring V V IN– IN+ The MCP601/2/3/4 family of operational amplifiers have low input bias current, which allows the designer to select larger resistor values and smaller capacitor values for these filters. This helps produce a compact PCB layout. These filters, and others, can be designed ® using Microchip’s FilterLab software. FIGURE 3-4: Example guard ring layout. DS21314E-page 12  2003 Microchip Technology Inc. Recommended R (:) ISO MCP601/2/3/4 3.7.2 INSTRUMENTATION AMPLIFIER 3.7.3 PHOTO DETECTION CIRCUITS The MCP601/2/3/4 op amps can be used to easily convert the signal from a sensor that produces an Instrumentation amplifiers have a differential input, output current (such as a photo diode) into a voltage (a which subtracts one input voltage from another and transimpedance amplifier). This is implemented with a rejects common mode signals. These amplifiers also single resistor (R ) in the feedback loop of the provide a single-ended output voltage. 2 amplifiers shown in Figure 3-9 and Figure 3-10. The The three op amp instrumentation amplifier is optional capacitor (C ) sometimes provides stability for 2 illustrated in Figure3-7. One advantage of this these circuits. approach is unity-gain operation. A disadvantage is A photodiode configured in the photovoltaic mode has that the common mode input range is reduced as R /R gets larger. zero voltage potential placed across it (Figure 3-9). In 2 G this mode, the light sensitivity and linearity is maximized, making it best suited for precision V 1 R R 3 4 applications. The key amplifier specifications for this MCP60X application are: low input bias current, low noise, common mode input voltage range (including ground) and rail-to-rail output. V MCP60X OUT R 2 R G C 2 R R R 2 3 4 R 2 V V OUT MCP60X REF I D1 V DD V 2 D1 Light 2R R MCP60X 2 4 V = (V - V ) 1 + + V OUT 1 2 REF R R G 3 FIGURE 3-7: Three op amp V = I R OUT D1 2 instrumentation amplifier. FIGURE 3-9: Photovoltaic mode detector. The two op amp instrumentation amplifier is shown in Figure 3-8. Its power consumption is lower than the In contrast, a photodiode that is configured in the three op amp version. Its main drawbacks are that the photoconductive mode has a reverse bias voltage common mode range is reduced with higher gains and across the photo sensing element (Figure 3-10). This it must be configured in gains of two or higher. decreases the diode capacitance, which facilitates high-speed operation (e.g., high-speed digital communications). The design trade off is increased R G diode leakage current and linearity errors. The op amp V OUT needs to have a wide Gain Bandwidth Product. R R R R 1 2 2 1 C 2 V REF MCP60X MCP60X R V 2 2 I V D1 OUT V V 1 DD D 1 R 2R 1 1 Light MCP60X V = (V - V ) 1 + + + V OUT 1 2 REF R R 2 G V = I R V OUT D1 2 BIAS FIGURE 3-8: Two op amp instrumentation V < 0V BIAS amplifier. Both instrumentation amplifiers should use a bulk FIGURE 3-10: Photoconductive Mode bypass capacitor of at least 1 µF. The CMRR of these Detector. amplifiers will be set by the op amp CMRR and by resistor matching.  2003 Microchip Technology Inc. DS21314E-page 13 MCP601/2/3/4 4.0 DESIGN TOOLS Microchip provides the basic design tools needed for the MCP601/2/3/4 family of op amps. 4.1 SPICE Macro Model The latest SPICE macro model of the MCP601/2/3/4 operational amplifiers is available on our website (at www.microchip.com). This model is intended as an initial design tool that works well in the op amp’s linear region of operation at room temperature. See the SPICE model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specs and plots. ® 4.2 FilterLab 2.0 ® FilterLab 2.0 is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from our web site (at www.microchip.com), the FilterLab active filter soft- ware design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the Macro Model to simulate actual filter perfor- mance. DS21314E-page 14  2003 Microchip Technology Inc. MCP601/2/3/4 5.0 PACKAGING INFORMATION 5.1 Package Marking Information Example: 5-Lead SOT-23 (MCP601 and MCP601R Only) XXNN SANN 6-Lead SOT-23A (MCP603 Only) Example: XXNN AUNN Legend: XX...X Customer specific information* YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.  2003 Microchip Technology Inc. DS21314E-page 15 MCP601/2/3/4 Package Marking Information 8-Lead PDIP (300 mil) Example: XXXXXXXX MCP601 XXXXXNNN I/P256 YYWW 0324 8-Lead SOIC (150 mil) Example: XXXXXXXX MCP601 XXXXYYWW I/SN0324 NNN 256 Example: 8-Lead TSSOP XXXX 601 XYWW I324 NNN 256 14-Lead PDIP (300 mil) (MCP604 Only) Example: XXXXXXXXXXXXXX MCP604-I/P XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 0324256 14-Lead SOIC (150 mil) (MCP604 Only) Example: MCP604ISL XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 0324256 14-Lead TSSOP (4.4mm) (MCP604 Only) Example: XXXXXXXX 604I YYWW 0324 NNN 256 DS21314E-page 16  2003 Microchip Technology Inc. MCP601/2/3/4 5-Lead Plastic Small Outline Transistor (OT) (SOT-23) E E1 p B p1 D n 1 α c A A2 φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 5 5 p Pitch .038 0.95 p1 Outside lead pitch (basic) .075 1.90 Overall Height A .035 .046 .057 0.90 1.18 1.45 Molded Package Thickness A2 .035 .043 .051 0.90 1.10 1.30 Standoff § A1 .000 .003 .006 0.00 0.08 0.15 Overall Width E .102 .110 .118 2.60 2.80 3.00 Molded Package Width E1 .059 .064 .069 1.50 1.63 1.75 Overall Length D .110 .116 .122 2.80 2.95 3.10 Foot Length L .014 .018 .022 0.35 0.45 0.55 φ Foot Angle 0 5 10 0 5 10 c Lead Thickness .004 .006 .008 0.09 0.15 0.20 Lead Width B .014 .017 .020 0.35 0.43 0.50 α Mold Draft Angle Top 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-178 Drawing No. C04-091  2003 Microchip Technology Inc. DS21314E-page 17 MCP601/2/3/4 6-Lead Plastic Small Outline Transistor (CH) (SOT-23) E E1 B p1 D n 1 α c A A2 φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX n Number of Pins 6 6 p Pitch .038 0.95 Outside lead pitch (basic) p1 .075 1.90 Overall Height A .035 .046 .057 0.90 1.18 1.45 Molded Package Thickness A2 .035 .043 .051 0.90 1.10 1.30 Standoff A1 .000 .003 .006 0.00 0.08 0.15 Overall Width E .102 .110 .118 2.60 2.80 3.00 Molded Package Width E1 .059 .064 .069 1.50 1.63 1.75 Overall Length D .110 .116 .122 2.80 2.95 3.10 Foot Length L .014 .018 .022 0.35 0.45 0.55 Foot Angle φ 0 5 10 0 5 10 c Lead Thickness .004 .006 .008 0.09 0.15 0.20 Lead Width B .014 .017 .020 0.35 0.43 0.50 α Mold Draft Angle Top 0 5 10 0 5 10 β Mold Draft Angle Bottom 0 5 10 0 5 10 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEITA (formerly EIAJ) equivalent: SC-74A Drawing No. C04-120 DS21314E-page 18  2003 Microchip Technology Inc. MCP601/2/3/4 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX n Number of Pins 88 p Pitch .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 c Lead Thickness .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 α Mold Draft Angle Top 510 15 5 10 15 β Mold Draft Angle Bottom 510 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018  2003 Microchip Technology Inc. DS21314E-page 19 MCP601/2/3/4 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A2 A φ β L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX n Number of Pins 8 8 p Pitch .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .237 .244 5.79 6.02 6.20 Molded Package Width E1 .146 .154 .157 3.71 3.91 3.99 Overall Length D .189 .193 .197 4.80 4.90 5.00 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .019 .025 .030 0.48 0.62 0.76 φ Foot Angle 048 048 c Lead Thickness .008 .009 .010 0.20 0.23 0.25 Lead Width B .013 .017 .020 0.33 0.42 0.51 α Mold Draft Angle Top 0 12 15 0 12 15 β Mold Draft Angle Bottom 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21314E-page 20  2003 Microchip Technology Inc. MCP601/2/3/4 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c φ A1 A2 β L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 8 8 p Pitch .026 0.65 Overall Height A .043 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .114 .118 .122 2.90 3.00 3.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 Foot Angle φ 0 48048 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .007 .010 .012 0.19 0.25 0.30 α Mold Draft Angle Top 0 5 10 0 5 10 β Mold Draft Angle Bottom 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-086  2003 Microchip Technology Inc. DS21314E-page 21 MCP601/2/3/4 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 B1 β eB p B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 p Pitch .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .740 .750 .760 18.80 19.05 19.30 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 c Lead Thickness .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 α Mold Draft Angle Top 5 10 15 5 10 15 β Mold Draft Angle Bottom 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 DS21314E-page 22  2003 Microchip Technology Inc. MCP601/2/3/4 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A2 A φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX n Number of Pins 14 14 p Pitch .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff § A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .236 .244 5.79 5.99 6.20 Molded Package Width E1 .150 .154 .157 3.81 3.90 3.99 Overall Length D .337 .342 .347 8.56 8.69 8.81 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .016 .033 .050 0.41 0.84 1.27 φ Foot Angle 0 48048 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .014 .017 .020 0.36 0.42 0.51 α Mold Draft Angle Top 0 12 15 0 12 15 β Mold Draft Angle Bottom 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065  2003 Microchip Technology Inc. DS21314E-page 23 MCP601/2/3/4 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 n 1 B α A c φ A1 A2 β L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX n Number of Pins 14 14 p Pitch .026 0.65 Overall Height A .043 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .193 .197 .201 4.90 5.00 5.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 φ Foot Angle 0 4 8 0 4 8 c Lead Thickness .004 .006 .008 0.09 0.15 0.20 Lead Width B .007 .010 .012 0.19 0.25 0.30 α Mold Draft Angle Top 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 DS21314E-page 24  2003 Microchip Technology Inc. MCP601/2/3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Examples: PART NO. X /XX a) MCP601-I/P: Single Op Amp, Industrial Device Temperature Package Temp., 8LD PDIP package. Range b) MCP601-E/SN: Single Op Amp, Extended Temp., 8LD SOIC package. c) MCP601T-I/OT: Tape and Reel, Industrial Temp., Device MCP601 Single Op Amp Single Op Amp, MCP601T Single Op Amp 5-LD SOT23 package. (Tape and Reel for SOT23, SOIC and TSSOP) d) MCP601T-E/ST: Tape and Reel, MCP601RT Single Op Amp Extended Temp., (Tape and Reel for SOT23-5) Single Op Amp, MCP602 Dual Op Amp 8LD TSSOP package MCP602T Dual Op Amp e) MCP601RT-E/OT: Tape and Reel, (Tape and Reel for SOIC and TSSOP) Extended Temp., MCP603 Single Op Amp with Chip Select Single Op Amp, Rotated, MCP603T Single Op Amp with Chip Select 5-LD SOT23 package. (Tape and Reel for SOT23, SOIC and TSSOP) MCP604 Quad Op Amp a) MCP602-I/SN: Dual Op Amp, MCP604T Quad Op Amp Industrial Temp., (Tape and Reel for SOIC and TSSOP) 8LD SOIC package. b) MCP602-E/P: Dual Op Amp, Extended Temp., Temperature Range I = -40°C to +85°C E= -40°C to +125°C 8LD PDIP package. c) MCP602T-E/ST: Tape and Reel, Extended Temp., Package Dual Op Amp, OT = Plastic SOT23, 5-lead (MCP601 only) 8LD TSSOP package. CH = Plastic SOT23, 6-lead (MCP603 only) P = Plastic DIP (300 mil Body), 8, 14-lead a) MCP603-I/SN: Industrial Temp., SN = Plastic SOIC (150 mil Body), 8-lead Single Op Amp with Chip SL = Plastic SOIC (150 mil Body), 14-lead Select, 8LD SOIC package. ST = Plastic TSSOP (4.4mm Body), 8, 14-lead b) MCP603-E/P: Extended Temp., Single Op Amp with Chip Select, 8LD PDIP package. c) MCP603T-E/ST: Tape and Reel, Extended Temp., Single Op Amp with Chip Select, 8LD TSSOP package. d) MCP603T-I/SN: Tape and Reel, Industrial Temp., Single Op Amp with Chip Select, 8LD SOIC package. a) MCP604-I/P: Industrial Temp., Quad Op Amp, 14LD PDIP package. b) MCP604-E/SL: Extended Temp., Quad Op Amp, 14LD SOIC package. c) MCP604T-I/ST: Tape and Reel, Industrial Temp., Quad Op Amp, 14LD TSSOP package. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2003 Microchip Technology Inc. DS21314E-page 25 MCP601/2/3/4 NOTES: DS21314E-page 26  2003 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PRO MATE and PowerSmart are registered trademarks of No representation or warranty is given and no liability is Microchip Technology Incorporated in the U.S.A. and other assumed by Microchip Technology Incorporated with respect countries. to the accuracy or use of such information, or infringement of AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, patents or other intellectual property rights arising from such SEEVAL and The Embedded Control Solutions Company are use or otherwise. Use of Microchip’s products as critical com- registered trademarks of Microchip Technology Incorporated ponents in life support systems is not authorized except with in the U.S.A. express written approval by Microchip. No licenses are con- veyed, implicitly or otherwise, under any intellectual property Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, rights. ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its ® ® PICmicro 8-bit MCUs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. DS21314E-page 27  2003 Microchip Technology Inc. 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B505A, Fullhope Plaza, Fax: 39-0331-466781 San Jose, CA 95131 No. 12 Hong Kong Central Rd. Tel: 408-436-7950 Qingdao 266071, China Netherlands Fax: 408-436-7955 Tel: 86-532-5027355 Fax: 86-532-5027205 P. A. De Biesbosch 14 NL-5152 SC Drunen, Netherlands India Toronto Tel: 31-416-690399 Divyasree Chambers 6285 Northam Drive, Suite 108 Fax: 31-416-690340 1 Floor, Wing A (A3/A4) Mississauga, Ontario L4V 1X5, Canada No. 11, O’Shaugnessey Road United Kingdom Tel: 905-673-0699 Bangalore, 560 025, India 505 Eskdale Road Fax: 905-673-6509 Tel: 91-80-2290061 Fax: 91-80-2290062 Winnersh Triangle Japan Wokingham Berkshire, England RG41 5TU Benex S-1 6F Tel: 44-118-921-5869 3-18-20, Shinyokohama Fax: 44-118-921-5820 Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan 07/28/03 Tel: 81-45-471- 6166 Fax: 81-45-471-6122 DS21314E-page 28  2003 Microchip Technology Inc.