24AA512/24LC512/24FC512 2 ™ 512K I C CMOS Serial EEPROM Device Selection Table Description: Part VCC Max. Clock Temp. The Microchip Technology Inc. 24AA512/24LC512/ Number Range Frequency Ranges 24FC512 (24XX512*) is a 64K x 8 (512 Kbit) Serial (1) Electrically Erasable PROM, capable of operation 24AA512 1.8-5.5V 400 kHz I across a broad voltage range (1.8V to 5.5V). It has 24LC512 2.5-5.5V 400 kHz I, E been developed for advanced, low-power applications 24FC512 2.5-5.5V 1 MHz I such as personal communications and data acquisi- tion. This device also has a page write capability of up Note 1: 100 kHz for VCC < 2.5V to 128 bytes of data. This device is capable of both random and sequential reads up to the 512K boundary. Features: Functional address lines allow up to eight devices on • Low-power CMOS technology: the same bus, for up to 4 Mbit address space. This device is available in the standard 8-pin plastic DIP, - Maximum write current 5 mA at 5.5V SOIC, DFN and 14-lead TSSOP packages. - Maximum read current 400 μA at 5.5V - Standby current 100 nA, typical at 5.5V Block Diagram 2 ™ 2-wire serial interface bus, I C compatible Cascadable for up to eight devices A0 A1 A2 WP HV Generator Self-timed erase/write cycle 128-byte Page Write mode available 5 ms max. write cycle time I/O Memory EEPROM Control Control XDEC ArrayHardware write-protect for entire array Logic Logic Schmitt Trigger inputs for noise suppression Page Latches 1,000,000 erase/write cycles I/OElectrostatic discharge protection > 4000V SCL YDECData retention > 200 years SDA 8-pin PDIP, SOIC (208 mil), and DFN packages 14-lead TSSOP package VCC Pb-free finishes available VSS Sense Amp. Temperature ranges: R/W Control - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C Package Type PDIP SOIC TSSOP DFN 1 14 VCC A0 A0 1 8 VCC 1 A0 8 VCC 1 8 A0 VCC 13 A1 2 WP 2 A1 7 WP 3 12 A1 2 7 WP 2 7 NC NC A1 WP 4 11 NC NC A2 3 6 SCL A2 3 6 SCL 3 6 A2 10 SCL 5 NC NC VSS 4 5 SDA 6 9 A2 SCL VSS 4 5 SDA 4 5 VSS SDA 8 7 VSS SDA * 24XX512 is used in this document as a generic part number for the 24AA512/24LC512/24FC512 devices. © 2005 Microchip Technology Inc. DS21754G-page 1 24XX512 24XX512 24XX512 24XX512 24AA512/24LC512/24FC512 1.0 ELECTRICAL CHARACTERISTICS (†) Absolute Maximum Ratings VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins ......................................................................................................................................................≥ 4kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Electrical Characteristics: DC CHARACTERISTICS Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C Param. Sym. Characteristic Min. Max. Units Conditions No. D1 — A0, A1, A2, SCL, SDA —— —— and WP pins: D2 VIH High-level input voltage 0.7 VCC —V— D3 VIL Low-level input voltage — 0.3 VCC V VCC ≥ 2.5V 0.2 VCC V VCC < 2.5V D4 VHYS Hysteresis of Schmitt 0.05 VCC —VVCC ≥ 2.5V (Note) Trigger inputs (SDA, SCL pins) D5 VOL Low-level output voltage — 0.40 V IOL = 3.0 ma @ VCC = 4.5V IOL = 2.1 ma @ VCC = 2.5V D6 ILI Input leakage current — ±1 μAVIN = VSS or VCC, WP = VSS VIN = VSS or VCC, WP = VCC D7 ILO Output leakage current — ±1 μAVOUT = VSS or VCC D8 CIN, Pin capacitance —10 pFVCC = 5.0V (Note) COUT (all inputs/outputs) TA = 25°C, FCLK = 1 MHz D9 ICC Read Operating current — 400 μAVCC = 5.5V, SCL = 400 kHz ICC Write — 5 mA VCC = 5.5V D10 ICCS Standby current — 1 μATA = -40°C to +85°C SCL = SDA = VCC = 5.5V A0, A1, A2, WP = VSS —5 μATA = -40°C to +125°C SCL = SDA = VCC = 5.5V A0, A1, A2, WP = VSS Note: This parameter is periodically sampled and not 100% tested. DS21754G-page 2 © 2005 Microchip Technology Inc. 24AA512/24LC512/24FC512 TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: AC CHARACTERISTICS Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C Param. Sym. Characteristic Min. Max. Units Conditions No. FCLK Clock frequency — 100 kHz 1.8V ≤ VCC < 2.5V 1 — 400 2.5V ≤ VCC ≤ 5.5V — 1000 2.5V ≤ VCC ≤ 5.5V 24FC512 THIGH Clock high time 4000 — ns 1.8V ≤ VCC < 2.5V 2 600 — 2.5V ≤ VCC ≤ 5.5V 500 — 2.5V ≤ VCC ≤ 5.5V 24FC512 TLOW Clock low time 4700 — ns 1.8V ≤ VCC < 2.5V 3 1300 — 2.5V ≤ VCC ≤ 5.5V 500 — 2.5V ≤ VCC ≤ 5.5V 24FC512 TR SDA and SCL rise time (Note 1) — 1000 ns 1.8V ≤ VCC< 2.5V 4 — 300 2.5V ≤ VCC ≤ 5.5V — 300 2.5V ≤ VCC ≤ 5.5V 24FC512 TF SDA and SCL fall time (Note 1) — 300 ns All except, 24FC512 5 — 100 2.5V ≤ VCC ≤ 5.5V 24FC512 6 THD:STA Start condition hold time 4000 — ns 1.8V ≤ VCC < 2.5V 600 — 2.5V ≤ VCC ≤ 5.5V 250 — 2.5V ≤ VCC ≤ 5.5V 24FC512 7 TSU:STA Start condition setup time 4700 — ns 1.8V ≤ VCC < 2.5V 600 — 2.5V ≤ VCC ≤ 5.5V 250 — 2.5V ≤ VCC ≤ 5.5V 24FC512 8 THD:DAT Data input hold time 0 — ns (Note 2) TSU:DAT Data input setup time 250 — ns 1.8V ≤ VCC < 2.5V 9 100 — 2.5V ≤ VCC ≤ 5.5V 100 — 2.5V ≤ VCC ≤ 5.5V 24FC512 TSU:STO Stop condition setup time 4000 — ns 1.8V ≤ VCC < 2.5V 10 600 — 2.5V ≤ VCC ≤ 5.5V 250 — 2.5V ≤ VCC ≤ 5.5V 24FC512 TSU:WP WP setup time 4000 — ns 1.8V ≤ VCC < 2.5V 11 600 — 2.5V ≤ VCC ≤ 5.5V 600 — 2.5V ≤ VCC ≤ 5.5V 24FC512 THD:WP WP hold time 4700 — ns 1.8V ≤ VCC < 2.5V 12 1300 — 2.5V ≤ VCC ≤ 5.5V 1300 — 2.5V ≤ VCC ≤ 5.5V 24FC512 TAA Output valid from clock (Note 2) — 3500 ns 1.8V ≤ VCC < 2.5V 13 — 900 2.5V ≤ VCC ≤ 5.5V — 400 2.5V ≤ VCC ≤ 5.5V 24FC512 TBUF Bus free time: Time the bus 4700 — ns 1.8V ≤ VCC < 2.5V 14 must be free before a new trans- 1300 — 2.5V ≤ VCC ≤ 5.5V mission can start 500 — 2.5V ≤ VCC ≤ 5.5V 24FC512 TSP Input filter spike suppression — 50 ns All except, 24FC512 (Notes 1 and 3) 16 (SDA and SCL pins) TWC Write cycle time (byte or page) — 5 ms — 17 18 — Endurance 1,000,000 — cycles 25°C (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. © 2005 Microchip Technology Inc. DS21754G-page 3 24AA512/24LC512/24FC512 FIGURE 1-1: BUS TIMING DATA 5 4 D4 2 SCL 7 3 10 89 SDA 6 IN 16 14 13 SDA OUT (protected) WP 12 11 (unprotected) DS21754G-page 4 © 2005 Microchip Technology Inc. 24AA512/24LC512/24FC512 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE 14-lead Name PDIP SOIC DFN Function TSSOP A0 1 1 1 1 User Configured Chip Select A1 2 2 2 2 User Configured Chip Select (NC) — — 3, 4, 5 — Not Connected A2 3 3 6 3 User Configured Chip Select SS 4 4 7 4 Ground V SDA 5 5 8 5 Serial Data SCL 6 6 9 6 Serial Clock (NC) — — 10, 11, 12 — Not Connected WP 7 7 13 7 Write-Protect Input VCC 8 8 14 8 +1.8V to 5.5V (24AA512) +2.5V to 5.5V (24LC512) +2.5V to 5.5V (24FC512) 2.1 A0, A1 and A2 Chip Address 2.3 Serial Clock (SCL) Inputs This input is used to synchronize the data transfer from and to the device. The A0, A1 and A2 inputs are used by the 24XX512 for multiple device operations. The logic levels on these inputs are compared with the corresponding bits in the 2.4 Write-Protect (WP) slave address. The chip is selected if the compare is This pin must be connected to either VSS or VCC. If tied true. to VSS, write operations are enabled. If tied to VCC, Up to eight devices may be connected to the same bus write operations are inhibited but read operations are by using different Chip Select bit combinations. These not affected. inputs must be connected to either VCC or VSS. In most applications, the chip address inputs A0, A1 3.0 FUNCTIONAL DESCRIPTION and A2 are hard-wired to logic ‘0’ or logic ‘1’. For applications in which these pins are controlled by a The 24XX512 supports a bidirectional 2-wire bus and microcontroller or other programmable logic device, data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device the chip address pins must be driven to logic ‘0’ or logic ‘1’ before normal device operation can proceed. receiving data as a receiver. The bus must be controlled by a master device which generates the Serial Clock (SCL), controls the bus access and 2.2 Serial Data (SDA) generates the Start and Stop conditions, while the This is a bidirectional pin used to transfer addresses 24XX512 works as a slave. Both master and slave and data into and data out of the device. It is an open- can operate as a transmitter or receiver, but the drain terminal, therefore, the SDA bus requires a pull- master device determines which mode is activated. up resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400kHz and 1MHz). For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. © 2005 Microchip Technology Inc. DS21754G-page 5 24AA512/24LC512/24FC512 4.5 Acknowledge 4.0 BUS CHARACTERISTICS Each receiving device, when addressed, is obliged to The following bus protocol has been defined: generate an Acknowledge signal after the reception of Data transfer may be initiated only when the bus each byte. The master device must generate an extra is not busy. clock pulse which is associated with this Acknowledge During data transfer, the data line must remain bit. See Figure 4-2 for acknowledge timing. stable whenever the clock line is high. Changes in Note: The 24XX512 does not generate any the data line, while the clock line is high, will be Acknowledge bits if an internal programming interpreted as a Start or Stop condition. cycle is in progress. Accordingly, the following bus conditions have been A device that acknowledges must pull down the SDA defined (Figure 4-1). line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of 4.1 Bus Not Busy (A) the acknowledge related clock pulse. Of course, setup Both data and clock lines remain high. and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an Acknowledge bit on the last byte 4.2 Start Data Transfer (B) that has been clocked out of the slave. In this case, the A high-to-low transition of the SDA line while the clock slave (24XX512) will leave the data line high to enable (SCL) is high determines a Start condition. All the master to generate the Stop condition. commands must be preceded by a Start condition. 4.3 Stop Data Transfer (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must end with a Stop condition. 4.4 Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device. DS21754G-page 6 © 2005 Microchip Technology Inc. 24AA512/24LC512/24FC512 FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (D) (D) (C) (A) SCL SDA Start Address or Data Stop Condition Acknowledge Allowed Condition Valid to Change FIGURE 4-2: ACKNOWLEDGE TIMING Acknowledge Bit 1 2 3 4 5 6 7 8 9 123 SCL SDA Data from transmitter Data from transmitter Transmitter must release the SDA line at this point Receiver must release the SDA line allowing the Receiver to pull the SDA line low to at this point so the Transmitter can acknowledge the previous eight bits of data. continue sending data. © 2005 Microchip Technology Inc. DS21754G-page 7 24AA512/24LC512/24FC512 FIGURE 5-1: CONTROL BYTE FORMAT 5.0 DEVICE ADDRESSING A control byte is the first byte received following the Read/Write Bit Start condition from the master device (Figure 5-1). The control byte consists of a 4-bit control code; for the Chip Select 24XX512 this is set as ‘1010’ binary for read and write Control Code Bits operations. The next three bits of the control byte are the Chip Select bits (A2, A1 and A0). The Chip Select S 10 1 0 A2 A1 A0 R/W ACK bits allow the use of up to eight 24XX512 devices on the same bus and are used to select which device is Slave Address accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, Start Bit Acknowledge Bit A1 and A0 pins for the device to respond. These bits are in effect the three Most Significant bits of the word address. 5.1 Contiguous Addressing Across The last bit of the control byte defines the operation to Multiple Devices be performed. When set to a one a read operation is The Chip Select bits A2, A1 and A0 can be used to selected and when set to a zero a write operation is expand the contiguous address space for up to 4 Mbit selected. The next two bytes received define the by adding up to eight 24XX512 devices on the same address of the first data byte (Figure 5-2). Because all bus. In this case, software can use A0 of the control A15…A0 are used, there are no upper address bits that byte as address bit A16; A1 as address bit A17; and A2 are “don’t care”. The upper address bits are transferred as address bit A18. It is not possible to sequentially first, followed by the Less Significant bits. read across device boundaries. Following the Start condition, the 24XX512 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a ‘1010’ code and appro- priate device select bits, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX512 will select a read or write operation. FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS Control Byte Address High Byte Address Low Byte A A A A A A A A A A A A A 1 010 R/W 1 10 2 0 15 14 13 12 11 9 8 7 0 Control Chip Code Select Bits DS21754G-page 8 © 2005 Microchip Technology Inc. 24AA512/24LC512/24FC512 6.3 Write Protection 6.0 WRITE OPERATIONS The WP pin allows the user to write-protect the entire 6.1 Byte Write array (0000-FFFF) when the pin is tied to VCC. If tied to VSS the write protection is disabled. The WP pin is Following the Start condition from the master, the sampled at the Stop bit for every Write command control code (four bits), the Chip Select (three bits) and (Figure 1-1). Toggling the WP pin after the Stop bit will the R/W bit (which is a logic low) are clocked onto the have no effect on the execution of the write cycle. bus by the master transmitter. This indicates to the addressed slave receiver that the address high byte will Note: Page write operations are limited to writing follow after it has generated an Acknowledge bit during bytes within a single physical page, the ninth clock cycle. Therefore, the next byte regardless of the number of bytes transmitted by the master is the high-order byte of the actually being written. Physical page word address and will be written into the Address boundaries start at addresses that are Pointer of the 24XX512. The next byte is the Least integer multiples of the page buffer size (or Significant Address Byte. After receiving another ‘page size’) and end at addresses that are Acknowledge signal from the 24XX512, the master integer multiples of [page size – 1]. If a device will transmit the data word to be written into the Page Write command attempts to write addressed memory location. The 24XX512 acknowl- across a physical page boundary, the edges again and the master generates a Stop result is that the data wraps around to the condition. This initiates the internal write cycle and beginning of the current page (overwriting during this time, the 24XX512 will not generate data previously stored there), instead of Acknowledge signals (Figure6-1). If an attempt is being written to the next page as might be made to write to the array with the WP pin held high, the expected. It is therefore necessary for the device will acknowledge the command, but no write application software to prevent page write cycle will occur, no data will be written and the device operations that would attempt to cross a will immediately accept a new command. After a byte page boundary. Write command, the internal address counter will point to the address location following the one that was just written. 6.2 Page Write The write control byte, word address and the first data byte are transmitted to the 24XX512 in the same way as in a byte write. But instead of generating a Stop condition, the master transmits up to 127 additional bytes, which are temporarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a Stop condition. After receipt of each word, the seven lower Address Pointer bits are inter- nally incremented by one. If the master should transmit more than 128 bytes prior to generating the Stop con- dition, the address counter will roll over and the previ- ously received data will be overwritten. As with the byte write operation, once the Stop condition is received, an internal write cycle will begin (Figure 6-2). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written and the device will immediately accept a new command. © 2005 Microchip Technology Inc. DS21754G-page 9 24AA512/24LC512/24FC512 FIGURE 6-1: BYTE WRITE S Bus Activity T S Control Address Address Master A T Byte High Byte Low Byte Data R O T P A A A SDA Line S 10 10 0 P 2 1 0 A A A A Bus Activity C C C C K K K K FIGURE 6-2: PAGE WRITE S T S Control Address Address Bus Activity A T Byte High Byte Low Byte Data Byte 0 Data Byte 127 R O Master T P A A A SDA Line S 10 1 0 0 P 2 1 0 A A A A A Bus Activity C C C C C K K K K K DS21754G-page 10 © 2005 Microchip Technology Inc. 24AA512/24LC512/24FC512 FIGURE 7-1: ACKNOWLEDGE POLLING 7.0 ACKNOWLEDGE POLLING FLOW Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write Send command has been issued from the master, the device Write Command initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition, followed by the control byte Send Stop for a Write command (R/W = 0). If the device is still Condition to busy with the write cycle, then no ACK will be returned. Initiate Write Cycle If no ACK is returned, then the Start bit and control byte must be re-sent. If the cycle is complete, then the device will return the ACK and the master can then Send Start proceed with the next Read or Write command. See Figure 7-1 for flow diagram. Send Control Byte with R/W = 0 Did Device No Acknowledge (ACK = 0)? Yes Next Operation © 2005 Microchip Technology Inc. DS21754G-page 11 24AA512/24LC512/24FC512 8.3 Sequential Read 8.0 READ OPERATION Sequential reads are initiated in the same way as a Read operations are initiated in the same way as write operations with the exception that the R/W bit of the random read except that after the 24XX512 transmits the first data byte, the master issues an acknowledge control byte is set to ‘1’. There are three basic types of as opposed to the Stop condition used in a random read operations: current address read, random read and sequential read. read. This acknowledge directs the 24XX512 to transmit the next sequentially addressed 8-bit word (Figure 8-3). Following the final byte transmitted to the 8.1 Current Address Read master, the master will NOT generate an acknowledge, The 24XX512 contains an address counter that main- but will generate a Stop condition. To provide tains the address of the last word accessed, internally sequential reads, the 24XX512 contains an internal incremented by ‘1’. Therefore, if the previous read Address Pointer which is incremented by one at the access was to address ‘n’ (n is any legal address), the completion of each operation. This Address Pointer next current address read operation would access data allows the entire memory contents to be serially read from address n + 1. during one operation. The internal Address Pointer will automatically roll over from address FFFF to address Upon receipt of the control byte with R/W bit set to ‘1’, 0000 if the master acknowledges the byte received the 24XX512 issues an acknowledge and transmits the from the array address FFFF. 8-bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the 24XX512 discontinues transmission (Figure 8-1). FIGURE 8-1: CURRENT ADDRESS READ S T S Bus Activity Control Data A T Master Byte Byte R O T P AA A SDA Line S 11 00 1 P 21 0 A N Bus Activity C O K A C K 8.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24XX512 as part of a write operation (R/W bit set to ‘0’). After the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. Then, the master issues the control byte again but with the R/W bit set to a one. The 24XX512 will then issue an acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer but does generate a Stop condition which causes the 24XX512 to discontinue transmission (Figure8-2). After a random Read command, the internal address counter will point to the address location following the one that was just read. DS21754G-page 12 © 2005 Microchip Technology Inc. 24AA512/24LC512/24FC512 FIGURE 8-2: RANDOM READ S S Bus Activity T T S Control Address Address Control Data Master A A T Byte High Byte Low Byte Byte Byte R R O T T P AA A AAA SDA Line S 10 10 0 S 1 010 1 P 21 0 210 N A A A A O Bus Activity C C C C K K K K A C x = “don’t care” bit K FIGURE 8-3: SEQUENTIAL READ S Control Bus Activity T Byte Data (n) Data (n + 1) Data (n + 2) Data (n + x) Master O P P SDA Line A A A A N C C C C O Bus Activity K K K K A C K © 2005 Microchip Technology Inc. DS21754G-page 13 24AA512/24LC512/24FC512 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) Example: 24AA512 XXXXXXXX I/P 017 T/XXXNNN e3 YYWW 0510 8-Lead SOIC (208 mil) Example: 24LC512 XXXXXXXX T/XXXXXX I/SM e3 YYWWNNN 0510017 8-Lead DFN-S Example: 24LC512 XXXXXXX I/MF e3 T/XXXXX 0510 YYWW 017 NNN 14-Lead TSSOP Example: XXXXXXXT 4L512I YYWW 0510 NNN 017 Legend: XX...X Customer-specific information* Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) e3 * This package is Pb-free. The Pb-free JEDEC designator ( ) e3 can be found on the outer packaging for this package. T Temperature Blank Commercial I Industrial E Extended Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. *Standard device marking consists of Microchip part number, year code, week code, and traceability code. For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. DS21754G-page 14 © 2005 Microchip Technology Inc. 24AA512/24LC512/24FC512 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX n Number of Pins 88 p Pitch .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 c Lead Thickness .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 α Mold Draft Angle Top 510 15 5 10 15 β Mold Draft Angle Bottom 510 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 © 2005 Microchip Technology Inc. DS21754G-page 15 24AA512/24LC512/24FC512 8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC) E E1 p D 2 n 1 B α c A2 A φ A1 L β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX n Number of Pins 8 8 p Pitch .050 1.27 Overall Height A .070 .075 .080 1.78 1.97 2.03 Molded Package Thickness A2 .069 .074 .078 1.75 1.88 1.98 Standoff § A1 .002 .005 .010 0.05 0.13 0.25 Overall Width E .300 .313 .325 7.62 7.95 8.26 Molded Package Width E1 .201 .208 .212 5.11 5.28 5.38 Overall Length D .202 .205 .210 5.13 5.21 5.33 Foot Length L .020 .025 .030 0.51 0.64 0.76 φ Foot Angle 04 80 48 c Lead Thickness .008 .009 .010 0.20 0.23 0.25 Lead Width B .014 .017 .020 0.36 0.43 0.51 α Mold Draft Angle Top 0 12 15 0 12 15 β Mold Draft Angle Bottom 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. Drawing No. C04-056 DS21754G-page 16 © 2005 Microchip Technology Inc. 24AA512/24LC512/24FC512 8-Lead Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S) – Saw Singulated © 2005 Microchip Technology Inc. DS21754G-page 17 24AA512/24LC512/24FC512 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 n 1 B α A c φ A1 A2 β L Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX n Number of Pins 14 14 p Pitch .026 0.65 Overall Height A .043 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .193 .197 .201 4.90 5.00 5.10 Foot Length L .020 .024 .028 0.50 0.60 0.70 φ Foot Angle 0 4 8 0 4 8 c Lead Thickness .004 .006 .008 0.09 0.15 0.20 Lead Width B .007 .010 .012 0.19 0.25 0.30 Mold Draft Angle Top α 0 5 10 0 5 10 β Mold Draft Angle Bottom 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 DS21754G-page 18 © 2005 Microchip Technology Inc. 24AA512/24LC512/24FC512 APPENDIX A: REVISION HISTORY Revision D Correction to Section 1.0, Electrical Characteristics. Revision E Correction to Section 1.0., Ambient Temperature Correction to Section 6.2, Page Write Revision F Add E3 (Pb-free) to marking examples. Updated Marking Legend and On-line Support. Revision G Revised Sections 2.1, 2.4 and 6.3. © 2005 Microchip Technology Inc. DS21754G-page 19 24AA512/24LC512/24FC512 NOTES: DS21754G-page 20 © 2005 Microchip Technology Inc. 24AA512/24LC512/24FC512 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to Distributor or Representative customers. Accessible by using your favorite Internet Local Sales Office browser, the web site contains the following Field Application Engineer (FAE) information: Technical Support Product Support – Data sheets and errata, Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help customers. A listing of sales offices and locations isGeneral Technical Support – Frequently Asked included in the back of this document. Questions (FAQ), technical support requests, online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2005 Microchip Technology Inc. DS21754G-page 21 24AA512/24LC512/24FC512 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: Lite 24AA512/24LC512/24FC512rature Number: DS21754G Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21754G-page 22 © 2005 Microchip Technology Inc. 24AA512/24LC512/24FC512 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Examples: PART NO. X /XX X a) 24AA512-I/P: Industrial Temp., Device Temperature Package Lead 1.8V, PDIP package. Range Finish b) 24AA512T-I/SM: Tape and Reel, Industrial Temp., 1.8V, SOIC 2 Device: 24AA512: 512 Kbit 1.8V I C Serial package. EEPROM c) 24AA512-I/ST14: Industrial Temp., 2 24AA512T: 512 Kbit 1.8V I C Serial 1.8V, 14-lead, TSSOP package. EEPROM (Tape and Reel) 2 d) 24AA512-I/MF: Industrial Temp., 24LC512: 512 Kbit 2.5V I C Serial 1.8V, DFN package. EEPROM 2 24LC512T: 512 Kbit 2.5V I C Serial e) 24LC512-E/P: Extended Temp., EEPROM (Tape and Reel) 2.5V, PDIP package. 2 24FC512: 512 Kbit 1 MHz I C Serial f) 24LC512-I/SM: Industrial Temp., EEPROM 2.5V, SOIC package. 2 24FC512T: 512 Kbit 1 MHz I C Serial g) 24LC512T-I/SM: Tape and Reel, EEPROM (Tape and Reel) Industrial Temp., 2.5V, SOIC package. Temperature I= -40°C to +85°C h) 24LC512-I/MF: Industrial Temp., Range: E= -40°C to +125°C 2.5V, DFN package. i) 24FC512-I/P: Industrial Temp., Package: P = Plastic DIP (300 mil body), 8-lead 2.5V, High Speed, PDIP package. SM = Plastic SOIC (208 mil body), 8-lead j) 24FC512-I/SM: Industrial Temp., ST14 = Plastic TSSOP (4.4 mm), 14-lead 2.5V, High Speed, SOIC package. MF = Micro Lead Frame (6x5 mm body), k) 24FC512T-I/SM: Tape and Reel, 8-lead Industrial Temp., 2.5V, High Speed, Lead Finish: Blank= Pb-free – Matte Tin (see Note 1) SOIC package G = Pb-free – Matte Tin only l) 24LC512T-I/SM: Industrial Temp., 2.5V, SOIC package, Tape & Reel, Pb-free m) 24LC512-I/PG: Industrial Temp., 2.5V, PDIP package, Pb-free Note 1: Most products manufactured after January 2005 will have a Matte Tin (Pb-free) finish. Most products manufactured before January 2005 will have a finish of approximately 63% Sn and 37% Pb (Sn/Pb). Please visit www.microchip.com for the latest information on Pb-free conversion, including conversion date codes. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. © 2005 Microchip Technology Inc. DS21754G-page23 24AA512/24LC512/24FC512 NOTES: DS21754G-page24 © 2005 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification cont ained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PRO MATE, PowerSmart, rfPIC, and SmartShunt are MICROCHIP MAKES NO REPRESENTATIONS OR WAR- registered trademarks of Microchip Technology Incorporated RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, in the U.S.A. and other countries. WRITTEN OR ORAL, STATUTORY OR OTHERWISE, AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, RELATED TO THE INFORMATION, INCLUDING BUT NOT PICMASTER, SEEVAL, SmartSensor and The Embedded LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, Control Solutions Company are registered trademarks of MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip Technology Incorporated in the U.S.A. Microchip disclaims all liability arising from this information and its use. Use of Microchip’s products as critical components in Analog-for-the-Digital Age, Application Maestro, dsPICDEM, life support systems is not authorized except with express dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, written approval by Microchip. No licenses are conveyed, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial implicitly or otherwise, under any Microchip intellectual property Programming, ICSP, ICEPIC, Linear Active Thermistor, rights. MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and ® ® procedures are for its PICmicro 8-bit MCUs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2005 Microchip Technology Inc. DS21754G-page 25 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Australia - Sydney India - Bangalore Austria - Weis 2355 West Chandler Blvd. Tel: 61-2-9868-6733 Tel: 91-80-2229-0061 Tel: 43-7242-2244-399 Chandler, AZ 85224-6199 Fax: 61-2-9868-6755 Fax: 91-80-2229-0062 Fax: 43-7242-2244-393 Tel: 480-792-7200 China - Beijing Denmark - Copenhagen India - New Delhi Fax: 480-792-7277 Tel: 86-10-8528-2100 Tel: 45-4450-2828 Tel: 91-11-5160-8631 Technical Support: Fax: 86-10-8528-2104 Fax: 45-4485-2829 Fax: 91-11-5160-8632 http://support.microchip.com China - Chengdu France - Paris India - Pune Web Address: Tel: 86-28-8676-6200 Tel: 33-1-69-53-63-20 Tel: 91-20-2566-1512 www.microchip.com Fax: 86-28-8676-6599 Fax: 33-1-69-30-90-79 Fax: 91-20-2566-1513 Atlanta China - Fuzhou Germany - Munich Japan - Yokohama Alpharetta, GA Tel: 49-89-627-144-0 Tel: 86-591-8750-3506 Tel: 81-45-471- 6166 Tel: 770-640-0034 Fax: 49-89-627-144-44 Fax: 86-591-8750-3521 Fax: 81-45-471-6122 Fax: 770-640-0307 Italy - Milan China - Hong Kong SAR Korea - Gumi Boston Tel: 39-0331-742611 Tel: 852-2401-1200 Tel: 82-54-473-4301 Westborough, MA Fax: 39-0331-466781 Fax: 852-2401-3431 Fax: 82-54-473-4302 Tel: 774-760-0087 Netherlands - Drunen Fax: 774-760-0088 China - Qingdao Korea - Seoul Tel: 31-416-690399 Tel: 86-532-8502-7355 Tel: 82-2-554-7200 Chicago Fax: 31-416-690340 Fax: 86-532-8502-7205 Fax: 82-2-558-5932 or Itasca, IL 82-2-558-5934 Spain - Madrid Tel: 630-285-0071 China - Shanghai Tel: 34-91-352-30-52 Fax: 630-285-0075 Tel: 86-21-5407-5533 Malaysia - Penang Fax: 34-91-352-11-47 Fax: 86-21-5407-5066 Tel: 604-646-8870 Dallas China - Shenyang UK - Wokingham Addison, TX Fax: 604-646-5086 Tel: 86-24-2334-2829 Tel: 44-118-921-5869 Tel: 972-818-7423 Philippines - Manila Fax: 86-24-2334-2393 Fax: 44-118-921-5820 Fax: 972-818-2924 Tel: 632-634-9065 China - Shenzhen Detroit Fax: 632-634-9069 Tel: 86-755-8203-2660 Farmington Hills, MI Singapore Fax: 86-755-8203-1760 Tel: 248-538-2250 Tel: 65-6334-8870 Fax: 248-538-2260 China - Shunde Fax: 65-6334-8850 Tel: 86-757-2839-5507 Kokomo Taiwan - Hsin Chu Kokomo, IN Fax: 86-757-2839-5571 Tel: 886-3-572-9526 Tel: 765-864-8360 China - Wuhan Fax: 886-3-572-6459 Fax: 765-864-8387 Tel: 86-27-5980-5300 Taiwan - Kaohsiung Los Angeles Fax: 86-27-5980-5118 Tel: 886-7-536-4818 Mission Viejo, CA China - Xian Fax: 886-7-536-4803 Tel: 949-462-9523 Tel: 86-29-8833-7250 Taiwan - Taipei Fax: 949-462-9608 Fax: 86-29-8833-7256 Tel: 886-2-2500-6610 San Jose Fax: 886-2-2508-0102 Mountain View, CA Thailand - Bangkok Tel: 650-215-1444 Tel: 66-2-694-1351 Fax: 650-961-0286 Fax: 66-2-694-1350 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 08/24/05 DS21754G-page 26 © 2005 Microchip Technology Inc.