MICRO/SYS MPC920
Specifications
CPLD
Altera EPM7256S. 256 macrocells. 5,000 usable gates. 15ns propagation delay
Environmental
0° - +70°C operating. -25° - +85°C storage. 5%-95% relative humidity, non-condensing
External Connections
40-pin general-purpose header. 34-pin general-purpose header (shares signals with JEDEC socket) 32-pin JEDEC socket (shares signals with 34-pin header) 10-pin JTAG header (interfaces directly with Altera ByteBlasterMV CPLD programming cable)
Mechanical
PC/104 standard. 3.55" (plus I/O region) x 3.775" x .6"
PC/104 Interface
8-bit PC/104 module. 16-bit PC/104 module if MPCOPT16ST installed. All PC/104 signals connect to CPLD. 16 data lines are buffered
Power Requirements
+5V ± 5% at 570mA max
Features
- 32-pin JEDEC socket
- 5V only operation
- Altera EPM7256S CPLD
- Breadboard area
- Buffered data lines
- Interfaces to all PC/104 signals
- PC/104 format
Datasheet
Extracted Text
Universal CPLD Interface for PC/104 MPC920 Features Interfaces to all PC/104 signals Buffered data lines Altera EPM7256S CPLD 5V only operation PC/104 format Breadboard area 32-pin JEDEC socket The MPC920 CPLD board provides an interface ers, a 32-pin JEDEC socket, a 40-pin connector, that can be configured for almost any purpose. and a 34-pin connector. This allows for flexibility Timers, digital I/O, serial-parallel interfaces, state- in I/O configuration. In addition, there is a small machines, and many other custom devices can breadboard area for custom circuitry. be designed into the MPC920 by simply pro- gramming that circuit into the CPLD through the Altera's MAX+PLUS II software (available from JTAG connector. Altera) allows CPLDs to be designed by using schematic capture of high-level description lan- The Altera CPLD connects to all of the signals on guages. the PC/104 bus, four LEDs, four plug-on jump- Software Support Compatible Hardware Mounting/Packaging Altera MAX+PLUS II Altera ByteBlasterMV PC/104 standard Example software included programming cable Chassis mounting Third party synthesis tools Custom interfacing Micro/sys 3730 Park Place, Montrose, CA 91020 (818)244-4600 Fax (818)244-4246 email: info@embeddedsys.com JEDEC Socket P J C/ T CPLD 1 A G 0 4 External Connections: Specifications: � 40-pin general-purpose header � 34-pin general-purpose header (shares Mechanical: signals with JEDEC socket) � PC/104 standard � 32-pin JEDEC socket (shares signals with � 3.55" (plus I/O region) x 3.775" x .6" 34-pin header) � 10-pin JTAG header (interfaces directly Power Requirements: with Altera ByteBlasterMV CPLD program- � +5V ± 5% at 570mA max ming cable) Environmental: Ordering Information: � 0° - +70°C operating � -25° - +85°C storage � 5%-95% relative humidity, non-condensing MPC920 Universal CPLD board MPC920-ET MPC920, extended temp CPLD: � Altera EPM7256S Related Products: � 256 macrocells CA5050 Cable, 34-pin/34-pin headers � 5,000 usable gates CA4025 Cable, 40-pin/40-pin headers � 15ns propagation delay RAM128 128k RAM device FLASH128-5 128k 5V flash PC/104 Interface: MPCOPT16ST Optional 16-bit PC/104 � 8-bit PC/104 module connector added � 16-bit PC/104 module if MPCOPT16ST installed � All PC/104 signals connect to CPLD � 16 data lines are buffered Micro/sys 3730 Park Place, Montrose, CA 91020 (818)244-4600 Fax (818)244-4246 email: info@embeddedsys.com
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