DATASHEET MCJ6 FCN Module Exploit High-Performance FPGAs for Complex Signal and Image Processing ® • FPGA compute nodes fully integrated in a RACE++ VME system Improves performance by a factor of 20 over RISC processors for some algorithms Partition applications between FPGAs and G4 processors for configuration flexibility Lower size, weight, cost, and power consumption FDK and support services significantly reduce development time and risks ® The RACE++ Series MCJ6 FCN board from Mercury Computer Real-Time Reconfiguration for Mode Changes Systems provides a flexible, manageable way to exploit the power of Mercury's FPGA technology adds the versatility of nearly instant field programmable gate arrays (FPGAs) in RACE++ multicomputer reconfiguration. High-speed reconfiguration facilitates dynamic, sys- ® systems. The MCJ6 FCN module is a 6U VME board with two Xilinx tem-level changes in mission and operating mode. An onboard con- ™ Virtex -II Pro P70 FPGAs. Each seven-million gate FPGA is con- figuration manager can load new bitstreams into either FPGA upon nected to the RACE++ switch fabric via an onboard crossbar. user or application command in less than 100 ms. Bitstreams can be obtained over the RACE++ fabric from stored files or off-board Each FPGA is supported by both SRAM and DRAM to maximize Flash, optimally staged by off-board SDRAM. its effectiveness as a compute node. Together, an FPGA and its memory chips are referred to as an FPGA compute node (FCN). Off-the-Shelf IP for RACE++ and Memory Interfaces High-Capacity I/O Connections Through the FPGA Development Kit (FDK), Mercury delivers the MCJ6 FCN modules provide full-duplex fiber-optic and copper MCJ6 FCN module with intellectual property for the RACE++ fab- serial connections for each FCN, as well as LVDS lines for parallel ric interface, memory transfers, and I/O management. Users need I/O, giving each board over 6 GB/s of direct I/O capacity. only incorporate their application-related algorithmic firmware to Delivering I/O directly to the FPGAs allows these devices to per- create complete FPGA bitstreams. Users can create their own form repetitive operations that reduce data volume before passing it FPGA-based solutions with Mercury’s help, or contract Mercury to on to the balance of the system. This feature permits handling of develop the FPGA-resident portion of an application for a complete more I/O without increasing the system processor count. turnkey solution. Partition Applications Easily between FPGAs and PowerPCs MCJ6 FCN boards can be configured in RACE++ systems with ® Switch Fabric other VME boards, including boards carrying PowerPC compute nodes and I/O devices, as well as other MCJ6 FCN boards. Because FPGAs in Mercury systems operate as a seamless element of the FPGA or FPGA or FPGA or FPGA or Sensor Data RACE++ environment, developers can partition their applications PPC/G4 PPC/G4 PPC/G4 PPC/G4 between performance-leveraging segments that run best on the node node node node FPGA and portions that can execute on easier-to-program Sensor Data PowerPC microprocessors. Figure 1. Mercury’s scalable solution www.mc.com FPGA Compute Nodes RACE++ System Connectivity Each 6U VME board contains two fully connected FPGA compute Each FCN has two connections to the RACE++ switch fabric via an nodes. The heart of each FCN is a seven-million gate Xilinx Virtex- onboard RACE++ crossbar. Full connectivity makes MCJ6 FCN II Pro FPGA with its own memory, I/O, and RACE++ fabric con- boards part of a scalable system that can expand to provide as many nections. The 8 MB of QDR II SRAM in each FCN provides low- FPGAs and PowerPC microprocessors as changing applications latency memory with peak access rates of 6.4 GB/s. Larger datasets demand, with minimal application recoding and redeployment can be staged in the 128 MB RLDRAM II of each FCN. High-band- expense. width data transfers are realized through the Mercury-provided When data is required to travel to another board, such as a PowerPC memory controller IP. board, the MCJ6 FCN system leverages the bandwidth, speed, and The two FPGA compute nodes on each board can work together on scalability of the RACE++ switch-fabric communications architec- the same dataset, communicating together over ten 2.5 Gbps serial ture to move data quickly and efficiently. Each FCN has two 267 links. This communication can be extended to multiple boards by MB/s connections to the module's RACE++ crossbar. These ports creating an FPGA communication mesh with the four 2.5 Gbps connect the board to the system-wide fabric, which can connect copper connections to each FPGA available on the front panel. dozens of simultaneous communication paths. Using the RACE++ switch fabric, multiple paths between most Massive I/O at Your Command points in the fabric greatly reduce the chance of blocking or inter- Each FPGA on Mercury's MCJ6 FCN board has six 2.5 Gbps full- ruption. Further, because low latency is often as important, if not duplex fiber-optic interfaces and four 2.5 Gbps full-duplex copper more important, than high bandwidth, each crossbar along the data serial connections. Sensor data can be delivered via fiber directly to transfer path adds only 75 ns to the latency. Once the connection is the FPGAs, where it can undergo data reduction using the repetitive established, each crossbar adds only 15 ns of latency. algorithms particularly suited to deployment on programmable logic devices. This savings in processor and interprocessor bandwidth Application Partitioning reduces system size, cost, and complexity. Algorithms such as FFTs, fast convolutions, and pulse compression Each FCN also has a front-panel parallel I/O interface that supports on incoming data streams can run up to 20 times faster on an FPGA 26 pairs of general-purpose LVDS lines. Designed for application- than a RISC processor. However, algorithms whose functions are defined communications, this interface can be used to support par- data-dependent are not well suited to implementation on an FPGA. allel I/O to sensors or used between boards for direct FPGA-to- Mercury's FPGA solution implements an architecture that can com- FPGA connections. With a cable length of 1 meter, these 26 pairs bine FPGAs and PowerPCs in a RACE++ fabric. Developers can can run at 200 MHz. Cable lengths can be extended up to 10 meters, partition their application across FPGAs and PowerPCs for maxi- but the longer the cable, the slower the data transfer rate. mum effectiveness. Parts of the application that are simple, fixed- On a system-wide level, MCJ6 FCN modules can exchange data with point computations can go on an FPGA, saving space, power, and ™ RACE++ Series MYRIAD I/O devices on other boards via the money. Other parts of the application can go on the PowerPC, RACEway Interlink switch fabric. Third-party I/O daughtercards which is easier to program, so that overall development time is kept can also be accommodated in the RACE++ system. manageable. Serial Serial LVDS I/O LVDS I/O Fiber RX Fiber RX 4x2.5 Gbps 4x2.5 Gbps 26x200 MHz 26x200 MHz 12x2.5 Gbps 12x2.5 Gbps Full-Duplex Full-Duplex 128 MB RLDRAM 128 MB RLDRAM Xilinx Xilinx Virtex-II Virtex-II FPGA FPGA 8 MB SRAM 8 MB SRAM Config Manager RACE++ Crossbar 6U VME Card RACE++ RACE++ Figure 2. MCJ6 FCN board architecture In effect, the intellectual property of the FDK enables each FPGA Scalability compute node to operate as a fully functional RACE++ compute FPGAs in the RACE++ environment become part of a scalable sys- node, capable of reading and writing to local and remote memory tem that can expand to provide as many FPGAs and PowerPC micro- locations across the RACEway switch fabric. This functionality frees processors as changing applications demand, with minimal applica- developers to concentrate on coding “inner loops” for the FPGA tion recoding and redeployment expense. Multiple MCJ6 FCN platform, and provides them with interfaces for connecting their boards can be deployed in a single VME chassis, along with other computational modules with the underlying RACE++ system. See boards carrying I/O devices and RISC processors, communicating Figure 3. via a RACE++ switch fabric with a bisection bandwidth of 2.1 GB/s. To jumpstart the creation of complete application solutions, a 6U VME systems from Mercury can scale to dozens of RISC and Mercury default bitstream is part of the FDK. When loaded into the FPGA nodes, providing ample processing power for the most FPGA, this bitstream enables system software to monitor system demanding image and digital signal processing applications. health through a series of tests, including memory test, DMA test, Developers can create and test algorithms on small laboratory sys- and an I/O loopback test. The Mercury default bitstream can also tems consisting of only a few processors, with the assurance that the serve as an application example and is fully documented. resulting code will move seamlessly to larger deployment platforms. Additionally, as processing requirements change in future program The FDK components are built for easy integration with the leading generations, they can readily resize target platforms with minimal FPGA development tools available, including the Xilinx ISE, impact to their code. ® ® Synplicity Synplify , and Mentor Graphics ModelSim . The Xilinx ™ ChipScope Pro logic analyzer can also be used while developing FPGA Development Software applications for the MCJ6 FCN for improved visibility of FPGA Mercury provides FCN Developer's Kit (FDK) software to simplify operations during debugging. See Figure 4. and accelerate development of FPGA-based applications. The FDK suite of development tools contains off-the-shelf, ready-to-use IP Mercury also provides a complete VHDL simulation environment or components for managing input and output dataflows, memory "harness" that models the FPGA compute node. This environment transfers, and the RACE++ interface in FPGA applications. Also provides a bus functional model (BFM) for RACE++ communica- included is the RACE-on-Chip (RoC) framework, which functions as tions, as well as for SRAM and DRAM attached to the FPGA. The an on-chip communication mechanism between different IP mod- simulation environment enables verification of FPGA applications ules on an FPGA. Users can join IP modules of the FDK with their prior to deployment on final-mission hardware and allows regression own algorithm-specific modules to create a complete FPGA appli- test suites to run with a single command. cation bitstream without reinventing these elements. FPGA Chip FPGA Compute Node (FCN) LVDS I/O Hardware FCN PowerPC CN (LVDS, etc.) Memory Software SFPDP SFPDP User Xilinx FPGA FDK API Application Calls SFPDP to FDK Space DRAM Bridge Modules Config Manager FDK Interfaces Switch Switch DMS Fabric Third party tools required for FDK development Fabric ModelSim Simulator RIB ICR RoC Bitstreams Synplify Xilinx PAR (e.g., MDB) Synthesis Place and Route Platform Memory Controllers Tool Tool Abstraction Layer SRAM DRAM FDK IP User IP Figure 3. Typical FCN-based board Figure 4. FDK IP module architecture www.mc.com Environmental Specifications Specifications Module Specifications Minimum airflow (per slot) 12 CFM FPGA compute nodes (FCNs) 2 Temperature Operating* 0°C to 40°C up to 10,000 ft FPGA processor per FCN Xilinx XC2VP70-6 (inlet air temperature at minimum airflow) SRAM capacity per FCN 8 MB Storage -40°C to +85°C SRAM bandwidth per FCN 3.2 GB/s full-duplex Relative humidity 10-90% (non-condensing) *As altitude increases, air density decreases, hence the cooling effect of a particular DRAM capacity per FCN 128 MB number of CFM decreases. The operating temperature is specified simultaneously with an altitude, because different limits can be achieved by trading among altitude, DRAM bandwidth per FCN 3.2 GB/s temperature, performance, and airflow. Contact Mercury for more information. RACE++ ports per FCN 2 Fiber links per FCN 6 at 2.5 Gbps, full-duplex Copper serial links per FCN 4 at 2.5 Gbps off-board, full-duplex 10 at 2.5 Gbps to other onboard FCN, full-duplex LVDS lines per FCN 26 pairs Electrical/Mechanical Specifications Input voltage 4.75 to 5.25 VDC 3.25 to 3.45 VDC Power 100W max for the board 16A (80W) max at 5 VDC* 17A (56W) max at 3.3 VDC* Dimensions 6U x 160 mm Slot-to-slot spacing 0.8 in *The board does not access both of these maximum values simultaneously. The actual consumption of the module depends on the FPGA application. These num- bers represent the maximum consumptions for each module. RACE++ is a registered trademark, and MYRIAD and Challenges Drive Innovation are trademarks of Mercury Computer Systems, Inc. Other products mentioned may be trademarks or registered trademarks of their respective holders. Mercury Computer Systems, Inc. believes this information is accurate as of its publication date and is not responsible for any inadvertent errors. The information contained herein is subject to change without notice. Copyright © 2006 Mercury Computer Systems, Inc. 712.00E-0606-DS-mcj6fcn Worldwide Locations Mercury Computer Systems has R&D, support and sales locations in France, Germany, Japan, the United Kingdom and the United States. For office locations and contact information, please call the corporate headquarters or visit our Web site at www.mc.com. Corporate Headquarters 199 Riverneck Road Chelmsford, MA 01824-2820 USA • +1 (978) 967-1401 +1 (866) 627-6951 Fax +1 (978) 256-3599 www.mc.com