Preliminary Product Information me me me me meg g g g ga a a a atel tel tel tel tel PC/II+zT 586 Main Street, Glen Williams, Ontario, L7G 3T6 Canada Phone: (905) 873-9988 Fax: (905) 873-4102 Toll free: 1-888-smallpc Website: www.megatel.ca Email: sales@megatel.ca PC/II+zT Features ❏ ZF x86 133MHz Processor, 586-class ❏ 128MB of System SDRAM ❏ 66MHz Front side bus ❏ CRT and Panel Video w/4MB SDRAM ❏ Dual 10Base-T or 100Base-TX Ethernet ❏ 16MB of Flash memory ❏ PC/104-Plus form factor and bus interface ❏ Eight IDE Devices, ATA-4 and ATA-5 ❏ Keyboard, mouse and parallel ports ❏ Dual USB and serial ports From manual IDN0226V2d Specifications Board Form Factor: Dual USB Ports 3.775 x 3.550 inch, PC/104-Plus compliant, FR4 type Integrated controller supports one root hub with two USB ports USB ports signals are pulled to Mass I/O connector Architecture: Supports OpenHCI 1.0a specification PC®/AT, 586-class compatible, x86 32-bit Supports USB 1.1 Compliance Average Bit Rate – 12 Mbps _ 0.25%, or 1.5 Mbps _ 1.5% 586-Class Cpu: On-board termination (IC terminator) 586-Class ZFx86 Low Power S.O.C. 133 MHz Core Frequency (to 33 MHz minimum) Dual 10/100 Ethernets 66 MHz or 33 MHz FPCI (Internal) Bus (1) or (2) Complete Ethernet 10Base-T/100Base-TX Controllers 33 MHz BPCI External (On- & Off-board) bus Your choice – (0), (1), or (2) Ethernet 10/100 Mbps Sub-systems 32-Bit x86 Core Each on-board Ethernet sub-system includes North & South Bridges included Intel GD82559 controller (MAC & PHY) I/O controller included Isolation Transformer Terminators Cache Memory Configuration EEPROM L1 On-Chip Cache Header (10 pins per Ethernet) 8 KB – Unified Code/Data Organization 82559 High-integration Controller supports: High performance write-back or Write-through Master interface on local PCI bus Data cache – Four-way set associative LRU algorithm IEEE 802.3u Auto-negotiation Read Line Size – 16-byte, Write Line Size – 4-byte IEEE 802.3 10BASE-T & 100BASE-TX compatible PHY Read/Write Cache Access – 1 Clock IEEE 803.3x 100BASE-TX Flow Control Software Enable/Disable, Write-back/Write-through Chained memory structure for High Performance TLB Translation Lookaside Full or Half Duplex at both 10 and 100 Mbps Linear to physical translation for Paging 3 KB Transmit FIFO memory TLB Cache – Four-way set associative 32-entry 3 KB Receive FIFO memory Memory Dual Watchdog Timers 8MB, 16MB, 32MB, 64MB or 128MB SDRAM, Soldered Integrated Dual Watchdog Timers 32-Bit, 1 to 8 parts of 8M16 or 4M16 Dual timers, 16-bit (2 Secs) & 8-bit (7.2 ms) Normal Memory Speed – 66 MHz (10 ns) Chained: First timer routable, Second causes unconditional Reset Software Controlled, Multi-mode Flash Array External hardware can Enable/Disable 4-16 MB Flash Array, Soldered BIOS occupies maximum of 256 KB of Flash Array 1284 Parallel Port 1) 1284-compliant ECP (Level 2) Multi-mode port Dual Serial Ports Support for ECP / EPP 1.9 / EPP (Mode 4) / PS2 / SPP / FIFO (1) or (2) Standard 16550A-compatible UARTs Output buffers sink & source 14 mA 16-byte Send/Receive FIFOs Includes Protection Circuit (Printer Powered Up or at higher voltage) Baud rates to 230 Kbps are supported On-board termination (IC terminator) Full EIA-RS232E and CCITT V.28 Transceivers included Output swing ±9V with all Transmitter Outputs loaded with 3K ohms to Ground. PLUS Rev. 25-Oct-2001 Quad ATA/IDE Channels Keyboard, Mouse (4) Channels, IDE/ATA I/O AT-style Keyboard supported (8) Devices supported PS/2 Mouse supported Integrated 2-Channel PCI IDE ATA-4 Bus-Mastering Controller On-board termination for Keyboard & Mouse (IC terminator) ATA-4 Controller Integral to ZFx86 Internal Controller on FS PCI bus (FPCI configured at 33 MHz) Floppy Disk Dual Channels, with shared data path Integrated Floppy Disk Controller – 2.88 MB (formatted) Speed Programmable per Device Compatible to PD765A and 82077SL Architecture Ultra-DMA, Multiword DMA, & PIO modes FDD Support – 3.5" & 5.25", one Device Separate 2-Channel PCI IDE ATA-5 Bus-Mastering Controller Data Transfer Rates – 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps ATA-5 Controller on local PCI bus (2) Data FIFOs, 16-byte Dual channels, with independent data paths Recording Format – FM, MFM Data Transfer Rate – up to 66 MB/sec Formatted Capacities – 720 KB / 1.2 MB / 1.44 MB Burst – Bus master DMA at 133 MB/sec PCI Buffers – 128 Byte DMA Ultra Dma 66, Multiword DMA, & PIO modes (0-4) (7) Standard channels, 32-Bit addressing CRC support (4) 8-Bit Channels, On-board termination (3) 16-Bit Channels Drivers – Available 8237-compatible From CMD – DOS, Windows 95/98, NT 4.0, & 2000 From Microsoft – default IDE drivers available. Timer/Counters (3) Standard timer/counters Video CRT & Flat Panel 8254-compatible Asiliant/Intel 69030 or 69000 HiQVideo Accelerator Input Clock – Standard 1.193 (14.31818_ 12) MHz VGA register set compatibility and I/O accessibility Timer-0 is Available (Legacy uses for Refresh but in ZFx86, its Includes On-Chip SDRAM unused) 4 MB or 2 MB of high-speed SDRAM for video buffer Timer-1 Creates PC Speaker Output Video Memory SDRAM operation at 83 MHz Timer-2 Creates a Timer Interrupt Video Memory SDRAM transfers up to 664 MBytes/sec Supports Analog CRT RGB Video Interface Interrupts Supports 24-Bit Flat Panel Interface (16) Standard interrupts Flexible Panel Interface – TFT/MIM, DSTN, SSTN, EL, Plasma (13) External Supports Mono and Color (4) PCI interrupts can be routed to any PIC IRQ Supports Panel Power On/Off Sequencing Selectable Edge/level type of IRQ Supports VGA, SVGA, XGA, SXGA, UXGA resolutions 8259-compatible (dual, cascaded using master IRQ2). Supports Quarter VGA 32-x240, 320x200 Supports 16:9 Aspect Ratio Panels, 1024x600 Memory & Address Bus Supports HiQColor Technology 32-Bit Data bus Up to 16.7M Colors on STN LCDs and 24-bit active matrix LCDs 32-Bit Address bus 256 Gray Shades Support for Dot Clock to 170 MHz Connectors Support for Flexible Display Modes Power Connector – Single View Mode – up to 1600 x 1200 x 16 bpp at 60 Hz refresh (1) Standard 1x12 Right-Angle header (+5V & +3.3V – Required) Dual Independent Mode – up to 1280 x 1024 x 8 bpp at 60 Hz refresh PC/104-Plus (PCI bus) Connectors – Supports Simultaneous CRT / Flat Panel operation (1) 4x30 2mm pitch Pin and Socket header Supports Graphics Acceleration Stack-through and non stack-through 64-bit Single Cycle BitBLT Engine Board stacking or other arrangements are customer specified Many Features Shroud available Supports panels from popular manufacturers Ethernet Headers – such as Sharp, Optrex, Toshiba, Hitachi, Fujitsu, Samsung, (1) 2x5 Right-Angle header (Single Ethernet), or NEC, Sanyo and others (1) 2x10 Right-Angle header (Dual Ethernets), or Asiliant/Intel/Chips drivers & Option BIOS included Customer specified Mass I/O Connectors – Real-Time Clock, Alarm (1) 5x11 IEC 2mm HM connector, and / or Integral Real-time Clock Controller & Non-volatile Configuration RAM (1) 5x22 IEC 2mm HM connector, and / or Periodic Interrupt Generator – settable from 122 _ s to 500 ms Customer specified Periodic Alarm Interrupt – settable to any time 24 hour period Total grid size – 5x33 2mm 242-byte NVRAM included Support Top Mounting 12 or 24 hour format Support 2mm headers on request (including board stacking headers) Daylight savings time support, Y2KOK. IrDA Header – 2x5 Header IDE Headers – PC Speaker Output (1) or (2) 80-pin FH16-80S Flex connectors Available on Mass I/O connector All connectors except for Power are optional Conditioned output – _ 9v Typical (_ 5v Minimum) Supply Voltage Power Monitoring Dual supplies at +5V 5% and +3.3V 5% Dual 5% monitor – 5V & +3.3V rails Reset hold time – 100 ms Minimum, 180 ms Typical Bios Software Transient voltage immunity 256 KB BIOS, Flash-based RESET is valid above +1V Flash BIOS SECTOR LOCK Protection Asiliant/Intel (Chips) 69030/69000 VGA Driver BIOS included Manual Reset CMD IDE Driver BIOS included Available on Mass I/O Connector Intel Ethernet Driver BIOS included Debounced, generates minimum of 100 ms reset on Low to High AT compatible BIOS and Architecture Initiated by pulling Manual Reset signal line Low (then High) TTL/CMOS-compatible input