MAXIM MAX195BCPE

MAX195 19-0377; Rev 1; 12/97 16-Bit, 85ksps ADC with 10µA Shutdown _______________General Description ____________________________Features The MAX195 is a 16-bit successive-approximation ana-'16 Bits, No Missing Codes log-to-digital converter (ADC) that combines high '90dB SINAD speed, high accuracy, low power consumption, and a '9.4µs Conversion Time 10µA shutdown mode. Internal calibration circuitry cor- rects linearity and offset errors to maintain the full rated'10µA (max) Shutdown Mode performance over the operating temperature range with- 'Built-In Track/Hold out external adjustments. The capacitive-DAC architec- 'AC and DC Specified ture provides an inherent 85ksps track/hold function. 'Unipolar (0V to V ) and Bipolar (-V to V ) REF REF REF The MAX195, with an external reference (up to +5V), Input Range offers a unipolar (0V to V ) or bipolar (-V to V ) REF REF REF pin-selectable input range. Separate analog and digital'Three-State Serial-Data Output supplies minimize digital-noise coupling. 'Small 16-Pin DIP, SO, and Ceramic SB Packages The chip select (CS) input controls the three-state serial- data output. The output can be read either during conver- sion as the bits are determined, or following conversion at ______________Ordering Information up to 5Mbps using the serial clock (SCLK). The end-of- conversion (EOC) output can be used to interrupt a PART TEMP. RANGE PIN-PACKAGE processor, or can be connected directly to the convert MAX195BCPE 0°C to +70°C 16 Plastic DIP input (CONV) for continuous, full-speed conversions. MAX195BCWE 0°C to +70°C 16 Wide SO The MAX195 is available in 16-pin DIP, wide SO, and MAX195ACDE 0°C to +70°C 16 Ceramic SB ceramic sidebraze packages. MAX195BC/D 0°C to +70°C Dice* MAX195BEPE -40°C to +85°C 16 Plastic DIP ________________________Applications MAX195BEWE -40°C to +85°C 16 Wide SO Portable Instruments MAX195AEDE -40°C to +85°C 16 Ceramic SB Audio MAX195AMDE -55°C to +125°C 16 Ceramic SB** Industrial Controls MAX195BMDE -55°C to +125°C 16 Ceramic SB** Robotics * Dice are specified at T = +25°C, DC parameters only. A Multiple Transducer Measurements ** Contact factory for availability and processing to MIL-STD-883. Medical Signal Acquisition ________________Functional Diagram Vibrations Analysis Digital Signal Processing 13 __________________Pin Configuration AIN 4 VDDD MAIN DAC 12 Σ 6 REF DGND 11 VSSD TOP VIEW 16 VDDA 14 AGND BP/UP/SHDN VDDA 1 COMPARATOR 16 CALIBRATION 15 VSSA DACs CLK VSSA 2 15 SCLK AGND 3 14 SAR VDDD MAX195 AIN 4 13 MAX195 2 CLK DOUT REF 5 12 3 5 SCLK DOUT 9 DGND 6 VSSD 11 CONV THREE-STATE BUFFER 1 CONTROL LOGIC EOC RESET 7 10 BP/UP/SHDN 8 7 CS EOC CS 9 CONV 8 10 RESET DIP/Wide SO/Ceramic SB ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. EVALUATION KIT AVAILABLE 16-Bit, 85ksps ADC with 10µA Shutdown ABSOLUTE MAXIMUM RATINGS VDDD to DGND .....................................................................+7V Continuous Power Dissipation (T = +70°C) A VDDA to AGND......................................................................+7V Plastic DIP (derate 10.53mW/°C above +70°C) ............842mW VSSD to DGND.........................................................+0.3V to -6V Wide SO (derate 9.52mW/°C above +70°C)..................762mW VSSA to AGND .........................................................+0.3V to -6V Ceramic SB (derate 10.53mW/°C above +70°C)...........842mW VDDD to VDDA, VSSD to VSSA..........................................±0.3V Operating Temperature Ranges AIN, REF ....................................(VSSA - 0.3V) to (VDDA + 0.3V) MAX195_C_E ........................................................0°C to +70°C AGND to DGND..................................................................±0.3V MAX195_E_E .....................................................-40°C to +85°C Digital Inputs to DGND...............................-0.3V, (VDDA + 0.3V) MAX195_MDE..................................................-55°C to +125°C Digital Outputs to DGND............................-0.3V, (VDDA + 0.3V) Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDDD = VDDA = +5V, VSSD = VSSA = -5V, f = 1.7MHz, V = +5V, T = T to T , unless otherwise noted. Typical CLK REF A MIN MAX values are at T = +25°C.) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ACCURACY (Note 1) Resolution RES 16 Bits MAX195A ±1 Differential Nonlinearity DNL LSB MAX195B ±2 MAX195A ±0.003 Integral Nonlinearity INL %FSR MAX195B ±0.004 MAX195A, V = 4.75V ±3 REF Unipolar/Bipolar Offset Error LSB MAX195B, V = 4.75V ±4 REF Unipolar/Bipolar Offset Tempco 0.4 ppm/°C Unipolar Full-Scale Error V = 4.75V ±0.0075 %FSR REF Bipolar Full-Scale Error V = 4.75V ±0.018 %FSR REF Full-Scale Tempco 0.1 ppm/°C VDDA = 4.75V to 5.25V, V = 4.75V 65 Power-Supply Rejection REF dB Ratio (VDDA and VSSA only) VSSA = -5.25V to -4.75V, V = 4.75V 65 REF ANALOG INPUT Unipolar 0 V REF Input Range V Bipolar -V V REF REF Unipolar 250 Input Capacitance pF Bipolar 125 DYNAMIC PERFORMANCE (f = 85kHz, bipolar range AIN = -5V to +5V, 1kHz) (Note 1) s Signal-to-Noise plus Distortion SINAD T = +25°C 87 90 dB A Ratio (Note 2) Total Harmonic Distortion (up to THD T = +25°C -97 -90 dB A the 5th harmonic) (Note 2) Peak Spurious Noise (Note 2) T = +25°C -90 dB A Conversion Time t 16 (t ) 9.4 µs CONV CLK Clock Frequency f 1.7 MHz CLK (Notes 3, 4) Serial Clock Frequency f 5 MHz SCLK 2 _______________________________________________________________________________________ MAX195 MAX195 16-Bit, 85ksps ADC with 10µA Shutdown ELECTRICAL CHARACTERISTICS (continued) (VDDD = VDDA = +5V, VSSD = VSSA = -5V, f = 1.7MHz, V = +5V, T = T to T , unless otherwise noted. Typical CLK REF A MIN MAX values are at T = +25°C.) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (CLK, CS, CONV, RESET, SCLK, BP/UP/SHDN) CLK, CS, CONV, RESET, SCLK V VDDD = 5.25V 2.4 V IH Input High Voltage CLK, CS, CONV, RESET, SCLK V VDDD = 4.75V 0.8 V IL Input Low Voltage CLK, CS, CONV, RESET, SCLK 10 pF Input Capacitance (Note 3) CLK, CS, CONV, RESET, SCLK Digital inputs = 0 or 5V ±10 µA Input Current BP/UP/SHDN V VDDD - 0.5 V IH Input High Voltage BP/UP/SHDN V 0.5 V IL Input Low Voltage BP/UP/SHDN I BP/UP/SHDN = VDDD 4.0 µA IH Input Current, High BP/UP/SHDN I BP/UP/SHDN = 0V -4.0 µA IL Input Current, Low BP/UP/SHDN V 1.5 VDDD - 1.5 V IM Mid Input Voltage BP/UP/SHDN Voltage, V BP/UP/SHDN = open 2.75 V FLT Floating BP/UP/SHDN Max Allowed BP/UP/SHDN = open -100 +100 nA Leakage, Mid Input DIGITAL OUTPUTS (DOUT, EOC) Output Low Voltage V VDDD = 4.75V, I = 1.6mA 0.4 V OL SINK Output High Voltage V VDDD = 4.75V, I = 1mA VDDD - 0.5 V OH SOURCE DOUT Leakage Current I DOUT = 0 or 5V ±10 µA LKG Output Capacitance (Note 2) 10 pF POWER REQUIREMENTS VDDD 4.75 5.25 V VSSD -5.25 -4.75 V VDDA By supply-rejection test 4.75 5.25 V VSSA By supply-rejection test -5.25 -4.75 V VDDD Supply Current I VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V 2.5 4 mA DDD VSSD Supply Current I VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V 0.9 2 mA SSD VDDA Supply Current I VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V 3.8 5 mA DDA VSSA Supply Current I VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V 3.8 5 mA SSA _______________________________________________________________________________________ 3 16-Bit, 85ksps ADC with 10µA Shutdown ELECTRICAL CHARACTERISTICS (continued) (VDDD = VDDA = +5V, VSSD = VSSA = -5V, f = 1.7MHz, V = +5V, T = T to T , unless otherwise noted. Typical CLK REF A MIN MAX values are at T = +25°C.) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS (cont.) Power Dissipation VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V 80 mW VDDD Shutdown Supply Current VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V, I 1.6 5 µA DDD (Note 5) BP/UP/SHDN = 0V VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V, VSSD Shutdown Supply Current I 0.1 5 µA SSD BP/UP/SHDN = 0V VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V, VDDA Shutdown Supply Current I 0.1 5 µA DDA BP/UP/SHDN = 0V VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V, VSSA Shutdown Supply Current I 0.1 5 µA SSA BP/UP/SHDN = 0V Note 1: Accuracy and dynamic performance tests performed after calibration. Note 2: Guaranteed by design, not tested. Note 3: Tested with 50% duty cycle. Duty cycles from 25% to 75% at 1.7MHz are acceptable. Note 4: See External Clock section. Note 5: Measured in shutdown mode with CLK and SCLK low. TIMING CHARACTERISTICS (VDDD = VDDA = +5V, VSSD = VSSA = -5V, unless otherwise noted.) T = 0°C to T = -40°C to T = -55°C to A A A T = +25°C A PARAMETER SYMBOL CONDITIONS +70°C +85°C +125°C UNITS TYP MIN MAX MIN MAX MIN MAX CONV Pulse Width t 20 30 35 ns CW CONV to CLK Falling t 10 10 10 ns CC1 Synchronization (Note 2) CONV to CLK Rising t 40 40 40 ns CC2 Synchronization (Note 2) Data Access Time t C = 50pF 80 80 90 ns DV L Bus Relinquish Time t C = 10pF 40 40 40 ns DH L CLK to EOC High t C = 50pF 300 300 350 ns CEH L t C = 50pF 300 300 350 ns CLK to EOC Low CEL L CLK to DOUT Valid t C = 50pF 100 350 100 375 100 400 ns CD L SCLK to DOUT Valid t C = 50pF 20 140 20 160 20 160 ns SD L t 75 75 75 ns CS to SCLK Setup Time CSS CS to SCLK Hold Time t -10 -10 -10 ns CSH Acquisition Time t 2.4 2.4 2.4 µs AQ Calibration Time t 14,000 x t 8.2 8.2 8.2 ms CAL CLK t -40 -40 -40 ns RESET to CLK Setup Time RCS RESET to CLK Hold Time t 120 120 120 ns RCH Exiting Start-Up Time (Note 6) t 50 µs SU shutdown Note 6: Settling time required after deasserting shutdown to achieve less than 0.1LSB additional error. 4 _______________________________________________________________________________________ MAX195 MAX195 16-Bit, 85ksps ADC with 10µA Shutdown ______________________________________________________________Pin Description PIN NAME FUNCTION Bipolar/Unipolar/Shutdown Input. Three-state input selects bipolar or unipolar input range, or shutdown. 1 BP/UP/SHDN 0V = shutdown, +5V = unipolar, floating = bipolar. 2 CLK Conversion Clock Input 3 SCLK Serial Clock Input is used to shift data out between conversions. May be asynchronous to CLK. 4 VDDD +5V Digital Power Supply 5 DOUT Serial Data Output, MSB first 6 DGND Digital Ground End-of-Conversion/Calibration Output—normally low. Rises one clock cycle after the beginning of conversion 7 EOC or calibration and falls one clock cycle after the end of either. May be used as an output framing signal. 8 CS Chip-Select Input—active low. Enables the serial interface and the three-state data output (DOUT). Convert-Start Input—active low. Conversion begins on the falling edge after CONV goes low if the input 9 CONV signal has been acquired; otherwise, on the falling clock edge after acquisition. Reset Input. Pulling RESET low places the ADC in an inactive state. Rising edge resets control logic and 10 RESET begins calibration. 11 VSSD -5V Digital Power Supply 12 REF Reference Input, 0 to 5V 13 AIN Analog Input, 0 to V unipolar or ±V bipolar range REF REF 14 AGND Analog Ground 15 VSSA -5V Analog Power Supply 16 VDDA +5V Analog Power Supply disconnected from AIN, trapping a charge proportional _______________Detailed Description to the input voltage on the capacitor array. The MAX195 uses a successive-approximation register The free terminal of the MSB (largest) capacitor is con- (SAR) to convert an analog input to a 16-bit digital nected to the reference (REF), which pulls the common code, which outputs as a serial data stream. The data terminal (connected to the comparator) positive. bits can be read either during the conversion, at the Simultaneously, the free terminals of all other capaci- CLK clock rate, or between conversions asynchronous tors in the array are connected to AGND, which drives with CLK at the SCLK rate (up to 5Mbps). the comparator input negative. If the analog input is The MAX195 includes a capacitive digital-to-analog near V , connecting the MSB’s free terminal to REF REF converter (DAC) that provides an inherent track/hold only pulls the comparator input slightly positive. input. The interface and control logic are designed for However, connecting the remaining capacitor’s free ter- easy connection to most microprocessors (µPs), limiting minals to ground drives the comparator input well the need for external components. In addition to the below ground, so the comparator input is negative, the SAR and DAC, the MAX195 includes a serial interface, a comparator output is low, and the MSB is set high. If sampling comparator used by the SAR, ten calibration the analog input is near ground, the comparator output DACs, and control logic for calibration and conversion. is high and the MSB is low. The DAC consists of an array of 16 capacitors with Following this, the next largest capacitor is disconnect- binary weighted values plus one “dummy LSB” capaci- ed from AGND and connected to REF, and the com- tor (Figure 1). During input acquisition in unipolar parator determines the next bit. This continues until all mode, the array’s common terminal is connected to bits have been determined. For a bipolar input range, AGND and all free terminals are connected to the input the MSB capacitor is connected to REF rather than AIN signal (AIN). After acquisition, the common terminal is during input acquisition, which results in an input range disconnected from AGND and the free terminals are of V to -V . REF REF _______________________________________________________________________________________ 5 16-Bit, 85ksps ADC with 10µA Shutdown MSB LSB DUMMY 32,768C 16,384C 4C 2C C C AIN REF AGND Figure 1. Capacitor DAC Functional Diagram t CAL CLK t RCH t RCS RESET EOC CALIBRATION CALIBRATION BEGINS ENDS MAX195 OPERATION HALTS Figure 2. Initiating Calibration Calibration output and offset the main DAC’s output according to In an ideal DAC, each of the capacitors associated with the value on their digital inputs. During calibration, the correct digital code to compensate for the error in each the data bits would be exactly twice the value of the next smaller capacitor. In practice, this results in a MSB capacitor is determined and stored. Thereafter, range of values too wide to be realized in an economi- the stored code is input to the appropriate calibration DAC whenever the corresponding bit in the main DAC cally feasible size. The capacitor array actually consists is high, compensating for errors in the associated of two arrays, which are capacitively coupled to reduce the LSB array’s effective value. The capacitors in the capacitor. MSB array are production trimmed to reduce errors. The MAX195 calibrates automatically on power-up. To Small variations in the LSB capacitors contribute reduce the effects of noise, each calibration experiment insignificant errors to the 16-bit result. is performed many times and the results are averaged. Calibration requires about 14,000 clock cycles, or Unfortunately, trimming alone does not yield 16-bit per- formance or compensate for changes in performance 8.2ms at the highest clock (CLK) speed (1.7MHz). In due to changes in temperature, supply voltage, and addition to the power-up calibration, bringing RESET low halts MAX195 operation, and bringing it high again other parameters. For this reason, the MAX195 includes initiates a calibration (Figure 2). a calibration DAC for each capacitor in the MSB array. These DACs are capacitively coupled to the main DAC 6 _______________________________________________________________________________________ MAX195 MAX195 16-Bit, 85ksps ADC with 10µA Shutdown t CC1 t CC2 CLK t t CEL CEH EOC * CONV t CW TRACK/HOLD t AQ CONVERSION CONVERSION ENDS BEGINS * THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION Figure 3. Initiating Conversions—At least 3 CLK cycles since end of previous conversion. If the power supplies do not settle within the MAX195’s input (AIN = 0V to V ). Bringing BP/UP/SHDN low REF power-on delay (500ns minimum), power-up calibration places the MAX195 in its 10µA shutdown mode. may begin with supply voltages that differ from the final A logic low on RESET halts MAX195 operation. The ris- values and the converter may not be properly calibrat- ing edge of RESET initiates calibration as described in ed. If so, recalibrate the converter (pulse RESET low) the Calibration section above. before use. For best DC accuracy, calibrate the Begin a conversion by bringing CONV low. After con- MAX195 any time there is a significant change in sup- version begins, additional convert start pulses are ply voltages, temperature, reference voltage, or clock ignored. The convert signal must be synchronized with characteristics (see External Clock section) because CLK. The falling edge of CONV must occur during the these parameters affect the DC offset. If linearity is the period shown in Figures 3 and 4. When CLK is not only concern, much larger changes in these parame- directly controlled by your processor, two methods of ters can be tolerated. ensuring synchronization are to drive CONV from EOC Because the calibration data is stored digitally, there is (continuous conversions) or to gate the conversion-start no need either to perform frequent conversions to main- signal with the conversion clock so that CONV can go tain accuracy or to recalibrate if the MAX195 has been low only while CLK is low (Figure 5). Ensure that the held in shutdown for long periods. However, recalibra- maximum propagation delay through the gate is less tion is recommended if it is likely that ambient tempera- than 40ns. ture or supply voltages have significantly changed The MAX195 automatically ensures four CLK periods since the previous calibration. for track/hold acquisition. If, when CONV is asserted, at Digital Interface least three clock (CLK) cycles have passed since the The digital interface pins consist of BP/UP/SHDN, CLK, end of the previous conversion, a conversion will begin SCLK, EOC, CS, CONV, and RESET. on CLK’s next falling edge and EOC will go high on the following falling CLK edge (Figure 3). If, when convert BP/UP/SHDN is a three-level input. Leave it floating to is asserted, less than three clock cycles have passed, configure the MAX195’s analog input in bipolar mode a conversion will begin on the fourth falling clock edge (AIN = -V to V ) or connect it high for a unipolar REF REF _______________________________________________________________________________________ 7 16-Bit, 85ksps ADC with 10µA Shutdown t CC1 t CC2 CLK t t CEL CEH EOC * CONV t CW t TRACK/HOLD AQ CONVERSION CONVERSION ENDS BEGINS * THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION Figure 4. Initiating Conversions—Less than 3 CLK cycles since end of previous conversion. after the end of the previous conversion and EOC will Output Data The conversion result, clocked out MSB first, is avail- go high on the following CLK falling edge (Figure 4). able on DOUT only when CS is held low. Otherwise, External Clock DOUT is in a high-impedance state. There are two ways The conversion clock (CLK) should have a duty cycle to read the data on DOUT. To read the data bits as they between 25% and 75% at 1.7MHz (the maximum clock are determined (at the CLK clock rate), hold CS low frequency). For lower frequency clocks, ensure the min- during the conversion. To read results between conver- imum high and low times exceed 150ns. The minimum sions, hold CS low and clock SCLK at up to 5MHz. clock rate for accurate conversion is 125Hz for temper- If you read the serial data bits as they are determined, atures up to +70°C or 1kHz at +125°C due to leakage EOC frames the data bits (Figure 6). Conversion begins of the sampling capacitor array. In addition, CLK with the first falling CLK edge, after CONV goes low should not remain high longer than 50ms at tempera- and the input signal has been acquired. Data bits are tures up to +70°C or 500µs at +125°C. If CLK is held shifted out of DOUT on subsequent falling CLK edges. high longer than this, RESET must be pulsed low to initi- Clock data in on CLK’s rising edge or, if the clock ate a recalibration because it is possible that state speed is greater than 1MHz, on the following falling information stored in internal dynamic memory may be edge of CLK to meet the maximum CLK-to-DOUT tim- lost. The MAX195’s clock can be stopped indefinitely if ing specification. See the Operating Modes and it is held low. SPI™/QSPI™ Interfaces section for additional informa- If the frequency, duty cycle, or other aspects of the tion. Reading the serial data during the conversion clock signal’s shape change, the offset created by cou- results in the maximum conversion throughput, pling between CLK and the analog inputs (AIN and because a new conversion can begin immediately after REF) changes. Recalibration corrects for this offset and the input acquisition period following the previous con- restores DC accuracy. version. SPI/QSPI are trademarks of Motorola Corp. 8 _______________________________________________________________________________________ MAX195 MAX195 16-Bit, 85ksps ADC with 10µA Shutdown START MAX195 CONV CLK START CLK CONV SEE DIGITAL INTERFACE SECTION Figure 5. Gating CONV to Synchronize with CLK CS CONV t CW CLK (CASE 1) CLK (CASE 2) t t CEH CEL EOC t t DV CD B15 FROM PREVIOUS DOUT B15 B14 B13 B12 B2 B1 B0 B15 CONVERSION t DH MSB LSB CONVERSION CONVERSION BEGINS ENDS CASE 1: CLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0) CASE 2: CLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1) NOTE: ARROWS ON CLK TRANSITIONS INDICATE LATCHING EDGE Figure 6. Output Data Format, Reading Data During Conversion (Mode 1) If you read the data bits between conversions, you can: Note that the MSB conversion result appears at DOUT after CS goes low, but before the first SCLK pulse. 1) count CLK cycles until the end of the conversion, or Each subsequent SCLK pulse shifts out the next con- 2) poll EOC to determine when the conversion is version bit. The 15th SCLK pulse shifts out the LSB. finished, or Additional clock pulses shift out zeros. 3) generate an interrupt on EOC’s falling edge. _______________________________________________________________________________________ 9 16-Bit, 85ksps ADC with 10µA Shutdown t CONV EOC t CSS CS t CSH SCLK (CASE 1) SCLK (CASE 2) SCLK (CASE 3) DOUT B15 B14 B13 B12 B11 B3 B2 B1 B0 MSB LSB t t t DV SD DH CASE 1: SCLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0) CASE 2: SCLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1) CASE 3: SCLK IDLES HIGH, DATA LATCHED ON FALLING EDGE (CPOL = 1, CPHA = 0) NOTE: ARROWS ON SCLK TRANSITIONS INDICATE LATCHING EDGE Figure 7. Output Data Format, Reading Data Between Conversions (Mode 2) Data is clocked out on SCLK’s falling edge. Clock data in on SCLK’s rising edge or, for clock speeds +5V above 2.5MHz, on the following falling edge to meet -5V the maximum SCLK-to-DOUT timing specification 0.1μF 10μF 0.1μF 10μF (Figure 7). The maximum SCLK speed is 5MHz. See 1 BP/UP/ 16 the Operating Modes and SPI/QSPI Interfaces section VDDA SHDN for additional information. When the conversion clock 15 2 CLK VSSA is near its maximum (1.7MHz), reading the data after CONVERSION 14 3 each conversion (during the acquisition time) results MAX195 CLOCK SCLK AGND ANALOG in lower throughput (about 70ksps max) than reading INPUT 4 13 VDDD AIN the data during conversions, because it takes longer than the minimum input acquisition time (four cycles 5 12 DOUT REF at 1.7MHz) to clock 16 data bits at 5Mbps. After the REFERENCE 6 11 data has been clocked in, leave some time (about DGND VSSD (0V TO VDDA) 1µs) for any coupled noise on AIN to settle before 10 7 EOC RESET beginning the next conversion. 9 8 CS CONV Whichever method is chosen for reading the data, con- versions can be individually initiated by bringing CONV low, or they can occur continuously by connecting EOC to CONV. Figure 8 shows the MAX195 in its simplest operational configuration. Figure 8. MAX195 in the Simplest Operating Configuration 10 ______________________________________________________________________________________ MAX195 MAX195 16-Bit, 85ksps ADC with 10µA Shutdown Table 1. Low-ESR Capacitor Suppliers COMPANY CAPACITOR FACTORY FAX [COUNTRY CODE] USA TELEPHONE 595D series, Sprague 1-603-224-1430 603-224-1961 592D series AVX TPS series 1-207-283-1941 800-282-4975 OS-CON series, Sanyo 81-7-2070-1174 619-661-6835 MVGX series Nichicon PL series 1-708-843-2798 708-843-7500 +5V BRIDGE INSTRUMENTATION AMPLIFIER VDDA MAX195 AIN REF 47μF 0.1μF LOW ESR CERAMIC AGND Figure 9. Ratiometric Measurement Without an Accurate Reference DACs, all of which may be switching between GND and __________Applications Information REF at the conversion clock frequency. The total Reference capacitive load presented can exceed 1000pF and, The MAX195 reference voltage range is 0V to VDDA. unlike the analog input (AIN), REF is sampled continu- When choosing the reference voltage, the MAX195’s ously throughout the conversion. equivalent input noise (40µV in unipolar mode, RMS The first step in choosing a reference circuit is to 80µV in bipolar mode) should be considered. Also, if RMS decide what kind of performance is required. This often V exceeds VDDA, errors will occur due to the internal REF suggests compromises made in the interests of cost protection diodes that will begin to conduct, so use cau- and size. It is possible that a system may not require an tion when using a reference near VDDA (unless V REF accurate reference at all. If a system makes a ratiomet- and VDDA are virtually identical). V must never REF ric measurement such as Figure 9’s bridge circuit, any exceed its absolute maximum rating (VDDA + 0.3V). relatively noise-free voltage that presents a low imped- The MAX195 needs a good reference to achieve its ance at the REF input will serve as a reference. The rated performance. The most important requirement is +5V analog supply suffices if you use a large, low- that the reference must present a low impedance to the impedance bypass capacitor to keep REF stable dur- REF input. This is often achieved by buffering the refer- ing switching of the capacitor arrays. Do not place a ence through an op amp and bypassing the REF input resistance between the +5V supply and the bypass with a large (1µF to 47µF), low-ESR capacitor in parallel capacitor, because it will cause linearity errors due to with a 0.1µF ceramic capacitor. Low-ESR capacitors the dynamic REF input current, which typically ranges are available from the manufacturers listed in Table 1. from 300µA to 400µA. The reference must drive the main conversion DAC Figure 10 shows a more typical scheme that provides capacitors as well as the capacitors in the calibration good AC accuracy. The MAX874’s initial accuracy can ______________________________________________________________________________________ 11 16-Bit, 85ksps ADC with 10µA Shutdown +15V +5V 0.1μF 2 0.1μF 1k 16 V IN VDDA 2k 1N914 8 COMP 0.1μF 2 7 MAX195 1000pF 10Ω MAX874 6 12 REF MAX427 4.096V 10Ω 6 3 V 47μF OUT 0.1μF 4 LOW ESR 0.1μF 1N914 VSSA AGND GND 0.1μF 15 14 4 -15V -5V Figure 10. Typical Reference Circuit for AC Accuracy V ≥ 8V IN 2 IN MAX195 MAX6241 12 6 OUT REF 2.2μF 3 5 10k 2.2μF 0.1μF NR TRIM AGND GND 1μF 4 14 Figure 11. High-Accuracy Reference be improved by trimming, but the drift is too great to of 1ppm/°C (typ). This allows reasonable temperature provide good stability over temperature. The MAX427 changes with less than 1LSB error. While the buffer provides the necessary drive current to stabilize MAX6241’s initial-accuracy specification (0.02%) the REF input quickly after capacitance changes. results in an offset error of about ±14LSB, the reference voltage can be trimmed or the offset can be corrected The reference inaccuracies contribute additional full- in software if absolute DC accuracy is essential. Figure 1 16 scale error. A reference with less than ⁄ total error 2 11’s circuit provides outstanding temperature stability (15 parts per million) over the operating temperature and also provides excellent DC accuracy if the initial range is required to limit the additional error to less error is corrected. than 1LSB. The MAX6241 achieves a drift specification 12 ______________________________________________________________________________________ MAX195 MAX195 16-Bit, 85ksps ADC with 10µA Shutdown +5V +15V VDDA MAX195 10Ω AIN INPUT 1N914 SIGNAL DIODE VSSA CLAMPS -15V -5V Figure 12. Analog Input Protection for Overvoltage or Improper Supply Sequence Input Acquisition and Settling REF and AIN Input Protection The REF and AIN signals should not exceed the Four conversion-clock periods are allocated for acquir- MAX195 supply rails. If this can occur, diode clamp the ing the input signal. At the highest conversion rate, four clock periods is 2.4µs. If more than three clock cycles signal to the supply rails. Use silicon diodes and a 10Ω current-limiting resistor (Figures 10 and 12) or Schottky have occurred since the end of the previous conver- diodes without the resistor. sion, conversion begins on the next falling clock edge after CONV goes low. Otherwise, bringing CONV low When using the current-limiting resistor, place the resis- begins a conversion on the fourth falling clock edge tor between the appropriate input (AIN or REF) and any after the previous conversion. This scheme ensures the bypass capacitor. While this results in AC transients at minimum input acquisition time is four clock periods. the input due to dynamic input currents, the transients settle quickly and do not affect conversion results. Most applications require an input buffer amplifier. If Improperly placing the bypass capacitor directly at the the input signal is multiplexed, the input channel should be switched near the beginning of a conversion, rather input forms an RC lowpass filter with the current-limiting resistor, which averages the dynamic input current and than near the end of or after a conversion (Figure 13). causes linearity errors. This allows time for the input buffer amplifier to respond to a large step change in input signal. The input amplifi- Analog Input er must have a high enough slew rate to complete the The MAX195 uses a capacitive DAC that provides an required output voltage change before the beginning of inherent track/hold function. The input impedance is the acquisition time. typically 30Ω in series with 250pF in unipolar mode and At the beginning of acquisition, the capacitive DAC is 50Ω in series with 125pF in bipolar mode. connected to the amplifier output, causing some output disturbance. Ensure that the sampled voltage has set- Input Range tled to within the required limits before the end of the The analog input range can be either unipolar (0V to acquisition time. If the frequency of interest is low, AIN V ) or bipolar (-V to V ), depending on the REF REF REF can be bypassed with a large enough capacitor to state of the BP/UP/SHDN pin (see Digital Interface sec- charge the capacitive DAC with very little change in tion). The reference range is 0V to VDDA. When choos- voltage (Figure 14). However, for AC use, AIN must be ing the reference voltage, the equivalent MAX195 input driven by a wideband buffer (at least 10MHz), which noise (40µV in unipolar mode, 80µV in bipolar RMS RMS must be stable with the DAC’s capacitive load (in paral- mode) should be considered. lel with any AIN bypass capacitor used) and also must settle quickly (Figure 15 or 16). ______________________________________________________________________________________ 13 16-Bit, 85ksps ADC with 10µA Shutdown A0 A1 IN1 IN2 4-TO-1 MAX195 MUX IN3 AIN OUT IN4 EOC CLK CONVERSION ACQUISITION EOC A0 A1 CHANGE MUX INPUT HERE Figure 13. Change multiplexer input near beginning of conversion to allow time for slewing and settling. 1k +5V +15V 1000pF 0.1μF 1N914 2 7 10Ω 6 AIN MAX400 100Ω 3 IN 4 1N914 1.0μF 0.1μF -15V -5V Figure 14. MAX400 Drives AIN for Low-Frequency Use 14 ______________________________________________________________________________________ MAX195 MAX195 16-Bit, 85ksps ADC with 10µA Shutdown Digital Noise ing. Also, to reduce linearity errors due to finite amplifier Digital noise can easily be coupled to AIN and REF. The gain, use an amplifier circuit with sufficient loop gain at conversion clock (CLK) and other digital signals that are the frequencies of interest (Figures 14, 15, 16). active during input acquisition contribute noise to the con- DC Accuracy version result. If the noise signal is synchronous to the If DC accuracy is important, choose a buffer with an sampling interval, an effective input offset is produced. offset much less than the MAX195’s maximum offset Asynchronous signals produce random noise on the input, (±3LSB = ±366µV for a ±4V input range), or whose whose high-frequency components may be aliased into offset can be trimmed while maintaining good stability the frequency band of interest. Minimize noise by present- over the required temperature range. ing a low impedance (at the frequencies contained in the noise signal) at the inputs. This requires bypassing AIN to Recommended Circuits AGND, or buffering the input with an amplifier that has a Figure 14 shows a good circuit for DC and low-frequen- small-signal bandwidth of several megahertz, or prefer- cy use. The MAX400 has very low offset (10µV) and ably both. AIN has a bandwidth of about 16MHz. drift (0.2µV/°C), and low voltage noise (10nV/ Hz) as √ Offsets resulting from synchronous noise (such as the well. However, its gain-bandwidth product (GBW) is conversion clock) are canceled by the MAX195’s cali- much too low to drive AIN directly, so the analog input bration scheme. However, because the magnitude of is bypassed to present a low impedance at high fre- the offset produced by a synchronous signal depends quencies. The large bypass capacitor is isolated from on the signal’s shape, recalibration may be appropriate the amplifier output by a 100Ω resistor, which provides if the shape or relative timing of the clock or other digi- additional noise filtering. Since the ±15V supplies tal signals change, as might occur if more than one exceed the AIN range, add protection diodes at AIN clock signal or frequency is used. (see REF and AIN Input Protection section). Figure 15 shows a wide-bandwidth amplifier (MAX427) Distortion driving a wideband video buffer, which is capable of Avoid degrading dynamic performance by choosing an driving AIN and a small bypass capacitor (for noise amplifier with distortion much less than the MAX195’s reduction) directly. The video buffer is inside the THD (-97dB, or 0.0014%) at frequencies of interest. If MAX427’s feedback loop, providing good DC accura- the chosen amplifier has insufficient common-mode cy, while the buffer’s low output impedance and high- rejection, which results in degraded THD performance, current capability provide good AC performance. AIN is use the inverting configuration (positive input ground- diode-clamped to the ±5V rails to prevent overvoltage. ed) to eliminate errors from this source. Low tempera- The MAX427’s 15µV maximum offset voltage, 0.8µV/°C ture-coefficient, gain-setting resistors reduce linearity maximum drift, and less than 5nV/ Hz noise specifica- √ errors caused by resistance changes due to self-heat- tions make this an excellent choice for AC/DC use. 1k +5V +15V +15V 100pF 0.1μF 0.1μF 1N914 2 7 1 10Ω 6 2 7 ELANTEC AIN EL2003 MAX427 1k 3 IN 4 4 1N914 0.0033μF 0.1μF 0.1μF -15V -15V -5V Figure 15. AIN Buffer for AC/DC Use ______________________________________________________________________________________ 15 16-Bit, 85ksps ADC with 10µA Shutdown If ±15V supplies are unavailable, Figure 16’s circuit Operating Modes and SPI/QSPI Interfaces works very well with the ±5V analog supplies used by The two basic interface modes are defined according the MAX195. The MAX410 has a minimum ±3.5V com- to whether serial data is received during the conversion mon-mode input range, with a similar output voltage (clocked with CLK, SCLK unused) or in bursts between swing, which allows use of a reference voltage up to conversions (clocked with SCLK). Each mode is pre- 3.5V. The offset voltage (250µV) is about 2LSB. The sented interfaced to a QSPI processor, but is also com- drift (1µV/°C), unity-gain bandwidth (28MHz), and low patible with SPI. voltage noise (2.4nV/√Hz) are appropriate for 16-bit Mode 1 (Simultaneous performance. Conversion and Data Transfer) In this mode, each data bit is read from the MAX195 during the conversion as it is determined. SCLK is 510Ω grounded and CLK is used as both the conversion +5V clock and the serial data clock. Figure 17 shows a QSPI processor connected to the MAX195 for use in this mode and Figure 18 is the associated timing dia- 0.1μF gram. 2 7 22Ω In addition to the standard QSPI interface signals, gen- 6 AIN eral I/O lines are used to monitor EOC and to drive MAX410 3 BP/UP/SHDN and RESET. The two general output pins IN 4 may not be necessary for a given application and, if I/O lines are unavailable, the EOC connection can be omit- 0.01μF 0.1μF ted as well. -5V The EOC signal is monitored during calibration to determine when calibration is finished and before beginning a conversion to ensure the MAX195 is not in Figure 16. ±5V Buffer for AC/DC Use Has ±3.5V Swing mid-conversion, but it is possible for a system to ignore EOC completely. On power-up or after pulsing RESET low, the µP must provide 14,000 CLK cycles to com- plete the calibration sequence (Figure 2). One way to QSPI do this is to toggle CLK and monitor EOC until it goes PCS0 CS low, but it is possible to simply count 14,000 CLK cycles to complete the calibration. Similarly, it is CONV unnecessary to check the status of EOC before begin- ning a conversion if you are sure the last conversion is MAX195 SCK CLK complete. This can be done by ensuring that every conversion consists of at least 20 CLK cycles. MISO DOUT Data is clocked out of the MAX195 on CLK’s falling SCLK edge and can be clocked into the µP on the rising GPT edge or the following falling edge. If you clock data in on the rising edge (SPI/QSPI with CPOL = 0 and CPHA *OC3 BP/UP/SHDN = 0; standard MicroWire™: Hitachi H8), the maximum CLK rate is given by: *IC1 EOC   1 1 *OC2 RESET f = /   CLK(max) 2 t + t   CD SD * THE USE OF THESE SIGNALS ADDS FLEXIBILITY AND FUNCTIONALITY where t is the MAX195’s CLK-to-DOUT valid delay CD BUT IS NOT REQUIRED TO IMPLEMENT THE INTERFACE. and t is the data setup time for your µP. SD Figure 17. MAX195 Connection to QSPI Processor Clocking Data Out During Conversions MicroWire is a trademark of National Semiconductor Corp. 16 ______________________________________________________________________________________ MAX195 MAX195 16-Bit, 85ksps ADC with 10µA Shutdown CS, CONV CLK EOC B15 FROM PREVIOUS B15 B14 B2 B1 B0 B15 DOUT CONVERSION t DH t t DV CD DATA LATCHED: Figure 18. Timing Diagram for Circuit of Figure 17 (Mode 1) If clocking data in on the falling edge (CPOL = 0, CPHA = 1), the maximum CLK rate is given by: 1 f = CLK(max) t + t CD SD QSPI Do not exceed the maximum CLK frequency given in PCS0 CS the Electrical Characteristics table. To clock data in on the falling edge, your processor hold time must not MAX195 SCK SCLK exceed t minimum (100ns). CD While QSPI can provide the required 20 CLK cycles as MISO DOUT two continuous 10-bit transfers, SPI is limited to 8-bit transfers. This means that with SPI, a conversion must OC3 BP/UP/SHDN GPT consist of three 8-bit transfers. Ensure that the pauses between 8-bit operations at your selected clock rate IC1 EOC are short enough to maintain a 20ms or shorter conver- sion time, or the leakage of the capacitive DAC may OC2 RESET cause errors. CONV Complete source code for the Motorola 68HC16 and the MAX195 evaluation kit (EV kit) using this mode is IC3 CLK available with the MAX195 EV kit. 74HC32 Mode 2 (Asynchronous Data Transfer) 1.7MHz This mode uses a conversion clock (CLK) and a serial 1.3μs clock (SCLK). The serial data is clocked out between START conversions, which reduces the maximum throughput for high CLK rates, but may be more convenient for some applications. Figure 19 is a block diagram with a QSPI processor (Motorola 68HC16) connected to the Figure 19. MAX195 Connection to QSPI Processor Clocking MAX195. Figure 20 shows the associated timing dia- Data Out with SCLK Between Conversions gram. Figure 21 gives an assembly language listing for this arrangement. ______________________________________________________________________________________ 17 16-Bit, 85ksps ADC with 10µA Shutdown 588ns CLK START EOC CS 239ns 4.19MHz SCLK DOUT B15 B14 B13 B3 B2 B1 B0 CONVERSION TIME 4μs 1.3μs 9.4μs 17μs* 5.1μs * INTERRUPT LATENCY OF THE PROCESSOR Figure 20. Timing Diagram for Circuit of Figure 19 (Mode 2) An OR gate is used to synchronize the “start” signal to Supplies, Layout, Grounding the asynchronous CLK, as described in the External and Bypassing Clock section. As with Mode 1, the QSPI processor must For best system performance, use printed circuit run CLK during calibration and either count CLK cycles boards with separate analog and digital ground planes. or, as is done here, monitor EOC to determine when cal- Wire-wrap boards are not recommended. The two ibration is complete. Also, EOC is polled by the µP to ground planes should be tied together at the low- determine when a conversion result is available. When impedance power-supply source and at the MAX195 EOC goes low, data is clocked out at the highest QSPI (Figure 22.) If the analog and digital supplies come data rate (4.19Mbps). After the data is transferred, a from the same source, isolate the digital supply from new conversion can be initiated whenever desired. the analog supply with a low-value resistor (10Ω). The timing specification for SCLK-to-DOUT valid (t ) SD Constraints on sequencing the four power supplies are imposes some constraints on the serial interface. At as follows. SCLK rates up to 2.5Mbps, data is clocked out of the • Apply VDDA before VDDD. MAX195 by a falling edge of SCLK and may be • Apply VSSA before VSSD. clocked into the µP by the next rising edge (CPOL = 0, CPHA = 0). For data rates greater than 2.5Mbps (or for • Apply AIN and REF after VDDA and VSSA are present. lower rates, if desired) it is necessary to clock data out • The power supplies should settle within the of the MAX195 on SCLK’s falling edge and to clock it MAX195’s power-on delay (minimum 500ns) or you into the µP on SCLK’s next falling edge (CPOL = 0, should recalibrate the converter (pulse RESET low) CPHA = 1). Also, your processor hold time must not before use. exceed t minimum (20ns). As with CLK in mode 1, SD maximum SCLK rates may not be possible with some interface specifications that are subsets of SPI. 18 ______________________________________________________________________________________ MAX195 MAX195 16-Bit, 85ksps ADC with 10µA Shutdown Figure 21. MAX195 Code Listing for 68HC16 Module and Circuit of Figure 19 ______________________________________________________________________________________ 19 16-Bit, 85ksps ADC with 10µA Shutdown Figure 21. MAX195 Code Listing for 68HC16 Module and Circuit of Figure 19 (continued) 20 ______________________________________________________________________________________ MAX195 MAX195 16-Bit, 85ksps ADC with 10µA Shutdown Figure 21. MAX195 Code Listing for 68HC16 Module and Circuit of Figure 19 (continued) Be sure that digital return currents do not pass through is long enough that the supply voltages or ambient tem- the analog ground and that return-current paths are low perature may have changed. impedance. A 5mA current flowing through a PC board The time required for the converter to “wake up” and ground trace impedance of only 0.05Ω creates an error settle depends heavily on the amount of additional error voltage of about 250µV, or about 2LSBs error with a acceptable. For 0.5LSB additional error, 3.2µs is suffi- ±4V full-scale system. cient settling time and also allows enough time for reac- The board layout should ensure as much as possible quisition of the analog input signal. 50µs settling is that digital and analog signal lines are kept separate. required for less than 0.1LSB error. Figure 23 is a Do not run analog and digital (especially clock) lines graph of theoretical power consumption vs. conver- parallel to one another. If you must cross one with the sions per second for the MAX195 that assumes the other, do so at right angles. conversion clock is 1.7MHz and the converter is shut down as much as possible between conversions. The ADC’s high-speed comparator is sensitive to high- frequency noise on the VDDA and VSSA power sup- Stop CLK before shutting down the MAX195. CLK must plies. Bypass these supplies to the analog ground be stopped without generating short clock pulses. Short plane with 0.1µF in parallel with 1µF or 10µF low-ESR CLK pulses (less than 150ns), or shutting down the capacitors. Keep capacitor leads short for best supply- MAX195 without stopping CLK, may adversely affect the noise rejection. MAX195’s internal calibration data. In applications where CLK is free-running and asynchronous, use the Shutdown circuit of Figure 24 to stop CLK cleanly. The MAX195 may be shut down by pulling BP/UP/ To minimize the time required to settle and perform a SHDN low. In addition to lowering power dissipation to conversion, shut the converter down only after a con- 10µW (100µW max) when the device is not in use, you version is finished and the desired mode (unipolar or can save considerable power by shutting the converter bipolar) has been set. This ensures that the sampling down for short periods between conversions. There is capacitor array is properly connected to the input sig- no need to perform a reset (calibration) after the con- nal. If shut down in mid-conversion, when awakened, verter has been shut down unless the time in shutdown ______________________________________________________________________________________ 21 16-Bit, 85ksps ADC with 10µA Shutdown 10Ω VDDD 100 50μs WAKE-UP DELAY VDDA 10μF 0.01LSB ERROR 5V 10 0.1μF MAX195 20μs WAKE-UP DELAY 0.1μF 0.25LSB ERROR 10μF DGND 1 AGND 10μF 0.1 5V 0.1μF 3.2μs WAKE-UP DELAY 0.1μF 0.5LSB ERROR 10μF VSSA 0.01 1 10 100 1000 10,000 100,000 VSSD CONVERSIONS PER SECOND 10Ω Figure 23. Power Dissipation vs. Conversions/sec When Figure 22. Supply Bypassing and Grounding Shutting the MAX195 Down Between Conversions the MAX195 finishes the old conversion, allows four The theoretical minimum ADC noise is caused by quan- clock (CLK) cycles for input acquisition, then begins tization error and is a direct result of the ADC’s resolu- the new conversion. tion: SNR = (6.02N + 1.76)dB, where N is the number of bits of resolution. A perfect 16-bit ADC can, there- _____________Dynamic Performance fore, do no better than 98dB. An FFT plot of the output High-speed sampling capability, 85ksps throughput, shows the output level in various spectral bands. Figure and wide dynamic range make the MAX195 ideal for 25 shows the result of sampling a pure 1kHz sinusoid at AC applications and signal processing. To support 85ksps with the MAX195. these and other related applications, Fast Fourier By transposing the equation that converts resolution to Transform (FFT) test techniques are used to guarantee SNR, we can, from the measured SNR, determine the the ADC’s dynamic frequency response, distortion, and effective resolution or the “effective number of bits” the noise at the rated throughput. Specifically, this involves ADC provides: N = (SNR - 1.76) / 6.02. Substituting applying a low-distortion sine wave to the ADC input SINAD for SNR in this formula results in a better mea- and recording the digital conversion results for a sure of the ADC’s usefulness. Figure 26 shows the specified time. The data is then analyzed using an FFT effective number of bits as a function of the MAX195’s algorithm, which determines its spectral content. input frequency calculated from the SINAD. Conversion errors are then seen as spectral elements If your intended sample rate is much lower than the other than the fundamental input frequency. MAX195’s maximum of 85ksps, you can improve your Signal-to-Noise Ratio and noise performance by taking more samples than neces- sary (oversampling) and averaging them in software. Effective Number of Bits Figure 27 is a histogram showing 16,384 samples for Signal-to-Noise Ratio (SNR) is the ratio between the the MAX195 without averaging, with an ideal “noiseless RMS amplitude of the fundamental input frequency to conversion,” and with a running average of five sam- the RMS amplitude of all other ADC output signals. The ples. The standard deviation is 0.621LSB without aver- output band is limited to frequencies above DC and aging and 0.382LSB with the running average. If fewer below one-half the ADC sample rate. This usually (but data points are needed, normal averaging (e.g., five not always) includes distortion as well as noise compo- data points averaged to produce one data point) can be nents. For this reason, the ratio is sometimes referred to used instead of a running average, with similar results. as Signal-to-Noise + Distortion (SINAD). 22 ______________________________________________________________________________________ MAX195 POWER DISSIPATION (mW) MAX195-FIG23 MAX195 16-Bit, 85ksps ADC with 10µA Shutdown 1 74HC73 / 2 MAX195 CLOCK SHUTDOWN J CLK Q +5V K BP/UP/SHDN 2 x CLK CK CK (2 x CLK) Q (CLK) J (CLOCK SHUTDOWN) Figure 24. Circuit to Stop Free-Running Asynchronous CLK Even better than oversampling and averaging is over- sampling and digital filtering. Averaging is just a rough (but computationally simple) type of digital filter. Finite impulse response (and other) digital filter algorithms are -10 readily available, and are useful even with slow proces- f = 1kHz IN sors if the data rate is low or the data does not need to -30 f = 85kHz S be processed in real-time. When using averaging, be T = +25°C A -50 sure to average an odd number of samples to avoid small offset errors caused by asymmetrical rounding. -70 Whether simple averaging or more complex digital fil- -90 tering is used, the effect of oversampling is to spread -110 the noise across a wider bandwidth. Digital filtering or averaging then eliminates the portion of this noise that -130 lies above the filter’s passband, leaving less noise in -150 the passband than if oversampling was not used. An 0 5 10 15 20 25 30 35 40 additional benefit of oversampling is that it simplifies FREQUENCY (kHz) the design or choice of an anti-aliasing pre-filter for the input. You can use a filter with a more gradual rolloff, because the sample rate is much higher than the fre- quency of interest. Figure 25. MAX195 FFT Plot ______________________________________________________________________________________ 23 SIGNAL AMPLITUDE (dB) 16-Bit, 85ksps ADC with 10µA Shutdown 16 100 f = 85kHz S f = 85kHz S T = +25°C 95 A T = +25°C A 15 90 14 85 13 80 75 12 70 11 65 10 60 0.1 1 10 100 0.1 1 10 100 FREQUENCY (kHz) FREQUENCY (kHz) Figure 28. Signal-to-Noise + Distortion vs. Frequency Figure 26. Effective Bits vs. Input Frequency This is expressed as follows: 18 2  2 2 2  IDEAL V = +4.5V REF V2 + V3 + V4 + ...+ V 16 N V = +2.25V   CONVERSION AIN THD = 20log UNIPOLAR MODE 14 V1 85ksps 12 NO AVERAGING where V is the fundamental RMS amplitude, and V 1 2 10 through V are the amplitudes of the 2nd through Nth N 8 RUNNING harmonics. The THD specification in the Electrical AVERAGE OF Characteristics includes the 2nd through 5th harmon- 6 5 SAMPLES ics. In the MAX195, this distortion is caused primarily 4 by the changes in on-resistance of the AIN sampling 2 switches with changing input voltage. These resis- tance changes, together with the DAC’s capacitance 0 (which can also vary with input voltage), cause a 8021 8022 8023 8024 8025 8026 8027 varying time delay for AC signals, which causes sig- OUTPUT CODE (HEXADECIMAL) nificant distortion at moderately high frequencies (Figure 28). Figure 27. Histogram of 16,384 Conversions Shows Effects of Noise and Averaging Spurious-Free Dynamic Range Spurious-free dynamic range is the ratio of the funda- mental RMS amplitude to the amplitude of the next Total Harmonic Distortion largest spectral component (in the frequency band If a pure sine wave is input to an ADC, AC integral non- above DC and below one-half the sample rate). linearity (INL) of an ADC’s transfer function results in Usually, this peak occurs at some harmonic of the input harmonics of the input frequency being present in the frequency. However, if the ADC is exceptionally linear, sampled output data. it may occur only at a random peak in the ADC’s noise Total Harmonic Distortion (THD) is the ratio of the RMS floor. sum of all the harmonics (in the frequency band above Transfer Function DC and below one-half the sample rate, but not includ- Figures 29 and 30 show the MAX195’s transfer func- ing the DC component) to the RMS amplitude of the tions. In unipolar mode, the output data is in binary for- fundamental frequency. mat and in bipolar mode it is offset binary. 24 ______________________________________________________________________________________ MAX195 OCCURRENCES OF OUTPUT CODE (THOUSANDS) EFFECTIVE BITS MAX195-26 MAX195 FG27 SINAD (dB) MAX195-28 MAX195 16-Bit, 85ksps ADC with 10µA Shutdown ___________________Chip Topography 11 . . . 111 11 . . . 110 BP/UP/SHDN VSSA 11 . . . 101 CLK VDDA 11 . . . 100 11 . . . 011 SCLK AGND 11 . . . 010 00 . . . 110 00 . . . 101 00 . . . 100 00 . . . 011 AIN 00 . . . 010 REF 00 . . . 001 00 . . . 000 0.273" VDDD 0V V - (1LSB) (6.93mm) REF Figure 29. MAX195 Unipolar Transfer Function DOUT 11 . . . 111 11 . . . 110 DGND VSSD 11 . . . 101 EOC CONV 10 . . . 010 CS RESET 10 . . . 001 0.144" 10 . . . 000 (3.66mm) 01 . . . 111 01 . . . 110 TRANSISTOR COUNT: 7966 00 . . . 010 SUBSTRATE CONNECTED TO VDDA 00 . . . 001 00 . . . 000 -V 0V V - (1LSB) REF REF Figure 30. MAX195 Bipolar Transfer Function ______________________________________________________________________________________ 25 16-Bit, 85ksps ADC with 10µA Shutdown ________________________________________________________Package Information 26 ______________________________________________________________________________________ MAX195 PDIPN.EPS MAX195 16-Bit, 85ksps ADC with 10µA Shutdown ___________________________________________Package Information (continued) ______________________________________________________________________________________ 27 SOICW.EPS 16-Bit, 85ksps ADC with 10µA Shutdown ___________________________________________Package Information (continued) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX195 SBN.EPS