LYRTECH Perseus 601X

UART IPMI JTAG User I/O UART Product sheet FMC to/from FPGA) • MI250 • Mestor interface (debugging ports/control I/Os) • 8× 250 MSPS 14-bit ADCs (contact Lyrtech for availability) • FPGA and IPMI JTAGs Perseus 601X SFP+2 • • LVDS user I/Os (×14), clock (×1) • 2× XFP-compatible SFP+ (contact Lyrtech for • FPGA UART interface (serial RX/TX) [front panel Virtex-6 AMC with FMC site availability) mini-B USB interface on Mestor expander] • ADC550 Mechanical ™ Mid-size AMC for μTCA and AdvancedTCA platforms • 2× 550 MSPS, 12-bit ADCs (contact Lyrtech for • Mid-size AMC availability) ™ Choice of powerful LXT and SXT Virtex-6 FPGAs • Full-size AMC — with optional Mestor expander • ADC512 ™ High-pin-count VITA 57.1 FMC expansion site for I/Os • AMC B+ edge connector • 2× 3 GSPS, 8-bit ADCs (contact Lyrtech for availability) ™ DDR3 SODIMM interface to upgrade system memory IPMI controller • ADC513 • Voltage monitor ™ Supports multiple switch fabrics (PCIe, SRIO, XAUI, GigE) • 4× 1.5 GSPS, 8-bit ADCs (contact Lyrtech for • Geographical address monitor availability) ™ Comprehensive line of software development tools • Temperatures monitors • Power/Reset controller • UART Perseus 601X functional block diagram DDR3 The Perseus 601X advanced mezzanine card Flash memory DDR3 SODIMM QDR2 SRAM QDR2 SRAM MicroBlaze code AMC Standards compliance 64 MB 1 GB (by default) Bank 1: 9 MB Bank 2: 9 MB 128 MB (AMC) is designed around the powerful Purchase information • AdvancedTCA base 3.0 (PICMG 3.0/3.1/3.4/3.5) Virtex-6 FPGA, combining unsurpassed fabric RTM MGT (×4) Lyrtech Incorporated Ports 17–20 • AdvancedMC R2.0 (PICMG AMC.0/AMC.1/AMC.2/ flexibility and a colossal external memory, LVDS I/O (×4) GTX (×8) Ports 12–15 FMC DP[0–7] 2800 Louis-Lumière Street AMC.3/AMC.4) as well as benifiting from multiple high-pin- PCIe/SRIO/XAUI (×4) Ports 8–11 PCIe/SRIO/XAUI (×4) count, modular add-on FMC-based I/O cards. Quebec City, Quebec Ports 4–7 • Support for AdvancedMC R1.0 also available Xilinx Virtex-6 LVDS I/Os (×76) Storage (×1) Port 3 LA[00–33] P-N (full) The Perseus 601X is intended for high- G1P 0A4 CANADA LXT or SXT • μTCA R1.0 HA[00–23] P-N (full) Storage (×1) HB[00–17] P-N Port 2 performance, high-bandwidth, low-latency GigE (×1) • VITA 57.1 FMC HPC Port 1 High-pin- Phone processing applications. The card also takes GigE (×1) count FMC Port 0 FMC clock (×4) Low-jitter • Hot swap clock switch full advantage of the Virtex-6 FPGA’s power, (1) 418-877-4644 Fabric switch Fabric clock • IPMI which, when combined with Lyrtech’s Toll free in the US and Canada: 1-888-922-4644 advanced software development tools, makes 2 I C Testing and development interfaces SMT Module management 2 Fax IPMI (I C) the Perseus 601X perfect for reducing size, jumper controller (MMC) • Mestor interface — FPGA JTAG, IPMI JTAG, mini-B complexity, risks and costs associated to (1) 418-877-7710 TCLKA, B, C, D USB serial port, GPIOs) leading-edge telecommunications, networking, Mestor interface E-mail industrial, defense and medical applications. JTAG interfaces: FPGA/IPMI FPGA JTAG • Test points User I/Os: LVDS ×14, clock ×1 JTAG chain JTAG switch FPGA UART interface (serial TX and RX) On top this, the Perseus 601X’s FMC expansion info@lyrtech.com JTAG • Jumpers JTAG site offers almost endless I/O possibilities. • Software switches Hardware architecture 9 MB QDR2 SRAM banks • USB nd (2 bank under heat sink) Visit us on the Web at www.lyrtech.com. The Perseus 601X is designed around the latest Xilinx • LEDs 1 GB DDR3 SDRAM SODIMM FPGA — the high-performance Virtex-6. The card can Electrical support the LXT and the SXT platform families, which both offer the flexibility and acceptable tradeoffs • AMC 12 V main source, 3.3 V IPMI between high-performance logic and massive digital Power consumption signal processing power. Mestor expander • Total: less than 40 W (with LX240T) troubleshooting interfaces Features • Bias: 9 W (at startup, FPGA not loaded) • Support for AMC R2.0 and R1.0 through onboard • CCE default application loaded, over Linux clock switch 64 MB NOR ash memory MicroBlaze: 12 W (CCE loaded, on stand-by, FPGA containing FPGA images, MicroBlaze boot code, user code • Available GTX base clocks — 100 MHz, 125 MHz, I/Os mapped) 128 MB DDR3 SDRAM 625 MHz (PCIe/GigE/XAUI/SRIO) (MicroBlaze memory) Mid-size AMC FMC modules options • Fabric clock — RX or TX (100 MHz PCIe, default) High-pin-count FMC interface (VITA 57) • ADAC250 • IPMI controller (based on the AVR version of the Pigeon Point AdvancedMC MMC) • 2× 250 MSPS, 14-bit ADC Full-size AMC FMC front panel Lyrtech products are constantly being improved; therefore, Lyrtech Full-size AMC panel shown. Mid-size AMC front panel also available. • FPGA and IPMI JTAGs on the Mestor interface • 2× 1 GSPS, 16-bit DACs reserves itself the right to modify the information herein at any time and without notice. Lyrtech Incorporated. All rights reserved. 2010-05-10 Perseus 601X clock conguration diagram The optional Perseus 601X MBDK allows • Save precious development time using the debugging Software development tools you to easily design high-performance tools part of the MBDK, namely recording/playback AMC The Perseus 601X comes with a comprehensive set of digital signal processing systems within tools and shared-memory GigE/PCIe HIL co- integrated, multilayer software development tools that the card’s FPGA with the MATLAB/ simulation tools. PCIe clock Buer 100 MHz 1:2 offer users a choice of environments — from a base-level MGT Simulink design environment and GigE clock MGT • Configure the Perseus in a snap with its graphical 125 MHz hand-coded design environment to a high-level graphical Fabric clock for PCIe SRIO clock MGT FCLKA (CLK3) extensive DSP IP libraries from Xilinx. 625 MHz FCLKA configuration tools. MGT model-based design environment. IODELAY clock GC 200 MHz MRCC Buer M-LVDS TCLKA (CLK1) TCLKA 1:2 buer For even greater flexibility, System Generator for DSP Draw the maximum out of the Perseus’ streaming DDR3 clock • GC 400 MHz MRCC Buer M-LVDS TCLKC supports MicroBlaze soft processor cores, which allows High-pin- TCLKC CLK0 Buer GC interface between the FPGA and host computer 1:2 buer Xilinx Virtex-6 count FMC 1:2 using high-level abstractions that can be automatically SRCC TCLKB (CLK2) running MATLAB (GigE/PCIe). M-LVDS High-level, optional CLK1 Buer GC TCLKB buer 1:2 software development tools compiled into the FPGA without losing any performance • Further your understanding of the Perseus with its SRCC M-LVDS TCLKD TCLKD Standard Lyrtech CLK2 (BIDIR) GC buer over VHDL designs. Use it with ChipScope Pro to debug software development tools extensive library of demonstrations and applicative CLK3 (BIDIR) GC Optional kit your applications. examples. These features, combined with the capabilities of the Model-based design kit (MBDK) Virtex-6 FPGA, make it simple for designers to harness the Specifications parallel processing power of an FPGA. FPGA Debugging interfaces Xilinx Virtex-6 FPGA Board software development kit (BSDK) The FPGA and IPMI JTAGs are available from the standard • Perseus 6010: LX240T AMC backplane or from the onboard Mestor interface. Lyrtech offers two optional Mestor debugging modes: • Perseus 6011: LX550T (contact Lyrtech for availability) • Perseus 6012: SX315T (contact Lyrtech for availability) Mestor-to-FPGA JTAG adapter Commonly referred to as the BSDK, • Perseus 6013: SX475T (contact Lyrtech for availability) Offers a direct, onboard access to the FPGA’s this kit offers reconfigurable FPGA JTAG chain. Memory components and reference designs, along with • Default 1 GB, 64-bit DDR3 SDRAM SODIMM Mestor expander the infrastructure to • 18 MB QDR2 SRAM (18 bits) — two banks of 9 MB Offers front-panel accesses to the FPGA and implement, simulate, synthesize, validate, IPMI JTAGs, 14 user LVDS I/Os, one clock, and • 64 MB NOR flash memory (16 bits) — for FPGA and deploy complete applications on the card’s an FPGA UART interface (serial RX/TX—Mini-B USB). images, MicroBlaze boot code and user code Virtex-6 FPGA. This development kit takes care of the Note, • 128 MB DDR3 SRAM (8 bits) — for MicroBlaze FPGA tiresome burden of reinventing interface drivers for however, applications the FPGA, freeing you to focus on unique, value-added that using development. AMC connectivity the Mestor The kit includes a complete and fully tested set of Virtex-6 expander, • Two GigE ports (ports 0–1) interfaces to all the Perseus 601X’s peripherals: transforms the Perseus 601X’s form factor into a full-size • Two storage ports (ports 2–3) AMC, thus the expander is supplied with a full-size face • High-speed GTX transceivers • Flexible fat pipes (ports 4–11) PCIe/SRIO/GigE/XAUI plate for the Perseus 601X. • External memory controllers • User LVDS I/Os (ports 12–15) • MicroBlaze instantiation and startup through a Linux • RTM GTXs (ports 17–20) kernel running Lyrtech’s central communication engine • TCLK A/B/C/D support for AMC R2.0/R1.0 through (CCE) server application onboard clock switch • External control through PCIe and GigE • Fabric clock — RX or TX (100 MHz PCIe, default) • APIs and graphical interfaces for remote board management (such as FPGA application deployment, Front panel Processing power parameter control and data streaming) • Mid-size AMC The Virtex-6 family of FPGAs is the high-performance The BSDK also offers: silicon foundation for targeted design platforms. • Board mounted LEDs Consuming 50 % less power and costing 20 % less than • An array of reference designs for quick code • FMC slot the previous generation of FPGAs, the Virtex-6 family is implementation • Full-size AMC built with the right mix • Applicative examples • Mestor expander slot of programmability, • Streamlined debugging tools capable of recording/ • Board mounted LEDs integrated blocks playback from external memory and more for digital signal • FMC slot • An unsurpassed integration to the model-based design processing, memory workflow. Keep reading for details. I/O expansion capabilities and connectivity support — including high-speed The Perseus MBDK edge transceiver capabilities — to satisfy the insatiable demand • High-pin-count VITA 57.1 FMC site • Interface and integrate with the interface libraries for higher bandwidth and higher performance. • 8× GTX transceivers FMC DP[0–7] supplied with the Perseus in no time flat. • 76× LVDS I/O [LA00-33/HA00-23/HB00-17] • Benefit from all-integrated configuration, simulation, • 4× clock (2× FMC to FPGA and 2× bidirectional and code generation advantages of the Perseus’ MBDK. Perseus 601X clock conguration diagram The optional Perseus 601X MBDK allows • Save precious development time using the debugging Software development tools you to easily design high-performance tools part of the MBDK, namely recording/playback AMC The Perseus 601X comes with a comprehensive set of digital signal processing systems within tools and shared-memory GigE/PCIe HIL co- integrated, multilayer software development tools that the card’s FPGA with the MATLAB/ simulation tools. PCIe clock Buer 100 MHz 1:2 offer users a choice of environments — from a base-level MGT Simulink design environment and GigE clock MGT • Configure the Perseus in a snap with its graphical 125 MHz hand-coded design environment to a high-level graphical Fabric clock for PCIe SRIO clock MGT FCLKA (CLK3) extensive DSP IP libraries from Xilinx. 625 MHz FCLKA configuration tools. MGT model-based design environment. IODELAY clock GC 200 MHz MRCC Buer M-LVDS TCLKA (CLK1) TCLKA 1:2 buer For even greater flexibility, System Generator for DSP Draw the maximum out of the Perseus’ streaming DDR3 clock • GC 400 MHz MRCC Buer M-LVDS TCLKC supports MicroBlaze soft processor cores, which allows High-pin- TCLKC CLK0 Buer GC interface between the FPGA and host computer 1:2 buer Xilinx Virtex-6 count FMC 1:2 using high-level abstractions that can be automatically SRCC TCLKB (CLK2) running MATLAB (GigE/PCIe). M-LVDS High-level, optional CLK1 Buer GC TCLKB buer 1:2 software development tools compiled into the FPGA without losing any performance • Further your understanding of the Perseus with its SRCC M-LVDS TCLKD TCLKD Standard Lyrtech CLK2 (BIDIR) GC buer over VHDL designs. Use it with ChipScope Pro to debug software development tools extensive library of demonstrations and applicative CLK3 (BIDIR) GC Optional kit your applications. examples. These features, combined with the capabilities of the Model-based design kit (MBDK) Virtex-6 FPGA, make it simple for designers to harness the Specifications parallel processing power of an FPGA. FPGA Debugging interfaces Xilinx Virtex-6 FPGA Board software development kit (BSDK) The FPGA and IPMI JTAGs are available from the standard • Perseus 6010: LX240T AMC backplane or from the onboard Mestor interface. Lyrtech offers two optional Mestor debugging modes: • Perseus 6011: LX550T • Perseus 6012: SX315T Mestor-to-FPGA JTAG adapter Commonly referred to as the BSDK, • Perseus 6013: SX475T Offers a direct, onboard access to the FPGA’s this kit offers reconfigurable FPGA JTAG chain. Memory components and reference designs, along with • Default 1 GB, 64-bit DDR3 SDRAM SODIMM Mestor expander the infrastructure to • 18 MB QDR2 SRAM (18 bits) — two banks of 9 MB Offers front-panel accesses to the FPGA and implement, simulate, synthesize, validate, IPMI JTAGs, 14 user LVDS I/Os, one clock, and • 64 MB NOR flash memory (16 bits) — for FPGA and deploy complete applications on the card’s an FPGA UART interface (serial RX/TX—Mini-B USB). images, MicroBlaze boot code and user code Virtex-6 FPGA. This development kit takes care of the Note, • 128 MB DDR3 SRAM (8 bits) — for MicroBlaze FPGA tiresome burden of reinventing interface drivers for however, applications the FPGA, freeing you to focus on unique, value-added that using development. AMC connectivity the Mestor The kit includes a complete and fully tested set of Virtex-6 expander, • Two GigE ports (ports 0–1) interfaces to all the Perseus 601X’s peripherals: transforms the Perseus 601X’s form factor into a full-size • Two storage ports (ports 2–3) AMC, thus the expander is supplied with a full-size face • High-speed GTX transceivers • Flexible fat pipes (ports 4–11) PCIe/SRIO/GigE/XAUI plate for the Perseus 601X. • External memory controllers • User LVDS I/Os (ports 12–15) • MicroBlaze instantiation and startup through a Linux • RTM GTXs (ports 17–20) kernel running Lyrtech’s central communication engine • TCLK A/B/C/D support for AMC R2.0/R1.0 through (CCE) server application onboard clock switch • External control through PCIe and GigE • Fabric clock — RX or TX (100 MHz PCIe, default) • APIs and graphical interfaces for remote board management (such as FPGA application deployment, Front panel Processing power parameter control and data streaming) • Mid-size AMC The Virtex-6 family of FPGAs is the high-performance The BSDK also offers: silicon foundation for targeted design platforms. • Board mounted LEDs Consuming 50 % less power and costing 20 % less than • An array of reference designs for quick code • FMC slot the previous generation of FPGAs, the Virtex-6 family is implementation • Full-size AMC built with the right mix • Applicative examples • Mestor expander slot of programmability, • Streamlined debugging tools capable of recording/ • Board mounted LEDs integrated blocks playback from external memory and more for digital signal • FMC slot • An unsurpassed integration to the model-based design processing, memory workflow. Keep reading for details. I/O expansion capabilities and connectivity support — including high-speed The Perseus MBDK edge transceiver capabilities — to satisfy the insatiable demand • High-pin-count VITA 57.1 FMC site • Interface and integrate with the interface libraries for higher bandwidth and higher performance. • 8× GTX transceivers FMC DP[0–7] supplied with the Perseus in no time flat. • 76× LVDS I/O [LA00-33/HA00-23/HB00-17] • Benefit from all-integrated configuration, simulation, • 4× clock (2× FMC to FPGA and 2× bidirectional and code generation advantages of the Perseus’ MBDK. UART IPMI JTAG User I/O UART Product sheet FMC to/from FPGA) • MI250 • Mestor interface (debugging ports/control I/Os) • 8× 250 MSPS 14-bit ADCs (contact Lyrtech for availability) • FPGA and IPMI JTAGs Perseus 601X SFP+2 • • LVDS user I/Os (×14), clock (×1) • 2× XFP-compatible SFP+ (contact Lyrtech for • FPGA UART interface (serial RX/TX) [front panel Virtex-6 AMC with FMC site availability) mini-B USB interface on Mestor expander] • ADC550 Mechanical ™ Mid-size AMC for μTCA and AdvancedTCA platforms • 2× 550 MSPS, 12-bit ADCs (contact Lyrtech for • Mid-size AMC availability) ™ Choice of powerful LXT and SXT Virtex-6 FPGAs • Full-size AMC — with optional Mestor expander • ADC512 ™ High-pin-count VITA 57.1 FMC expansion site for I/Os • AMC B+ edge connector • 2× 3 GSPS, 8-bit ADCs (contact Lyrtech for availability) ™ DDR3 SODIMM interface to upgrade system memory IPMI controller • ADC513 • Voltage monitor ™ Supports multiple switch fabrics (PCIe, SRIO, XAUI, GigE) • 4× 1.5 GSPS, 8-bit ADCs (contact Lyrtech for • Geographical address monitor availability) ™ Comprehensive line of software development tools • Temperatures monitors • Power/Reset controller • UART Perseus 601X functional block diagram DDR3 The Perseus 601X advanced mezzanine card Flash memory DDR3 SODIMM QDR2 SRAM QDR2 SRAM MicroBlaze code AMC Standards compliance 64 MB 1 GB (by default) Bank 1: 9 MB Bank 2: 9 MB 128 MB (AMC) is designed around the powerful Purchase information • AdvancedTCA base 3.0 (PICMG 3.0/3.1/3.4/3.5) Virtex-6 FPGA, combining unsurpassed fabric RTM MGT (×4) Lyrtech Incorporated Ports 17–20 • AdvancedMC R2.0 (PICMG AMC.0/AMC.1/AMC.2/ flexibility and a colossal external memory, LVDS I/O (×4) GTX (×8) Ports 12–15 FMC DP[0–7] 2800 Louis-Lumière Street AMC.3/AMC.4) as well as benifiting from multiple high-pin- PCIe/SRIO/XAUI (×4) Ports 8–11 PCIe/SRIO/XAUI (×4) count, modular add-on FMC-based I/O cards. Quebec City, Quebec Ports 4–7 • Support for AdvancedMC R1.0 also available Xilinx Virtex-6 LVDS I/Os (×76) Storage (×1) Port 3 LA[00–33] P-N (full) The Perseus 601X is intended for high- G1P 0A4 CANADA LXT or SXT • μTCA R1.0 HA[00–23] P-N (full) Storage (×1) HB[00–17] P-N Port 2 performance, high-bandwidth, low-latency GigE (×1) • VITA 57.1 FMC HPC Port 1 High-pin- Phone processing applications. The card also takes GigE (×1) count FMC Port 0 FMC clock (×4) Low-jitter • Hot swap clock switch full advantage of the Virtex-6 FPGA’s power, (1) 418-877-4644 Fabric switch Fabric clock • IPMI which, when combined with Lyrtech’s Toll free in the US and Canada: 1-888-922-4644 advanced software development tools, makes 2 I C Testing and development interfaces SMT Module management 2 Fax IPMI (I C) the Perseus 601X perfect for reducing size, jumper controller (MMC) • Mestor interface — FPGA JTAG, IPMI JTAG, mini-B complexity, risks and costs associated to (1) 418-877-7710 TCLKA, B, C, D USB serial port, GPIOs) leading-edge telecommunications, networking, Mestor interface E-mail industrial, defense and medical applications. JTAG interfaces: FPGA/IPMI FPGA JTAG • Test points User I/Os: LVDS ×14, clock ×1 JTAG chain JTAG switch FPGA UART interface (serial TX and RX) On top this, the Perseus 601X’s FMC expansion info@lyrtech.com JTAG • Jumpers JTAG site offers almost endless I/O possibilities. • Software switches Hardware architecture 9 MB QDR2 SRAM banks • USB nd (2 bank under heat sink) Visit us on the Web at www.lyrtech.com. The Perseus 601X is designed around the latest Xilinx • LEDs 1 GB DDR3 SDRAM SODIMM FPGA — the high-performance Virtex-6. The card can Electrical support the LXT and the SXT platform families, which both offer the flexibility and acceptable tradeoffs • AMC 12 V main source, 3.3 V IPMI between high-performance logic and massive digital Power consumption signal processing power. Mestor expander • Total: less than 40 W (with LX240T) troubleshooting interfaces Features • Bias: 9 W (at startup, FPGA not loaded) • Support for AMC R2.0 and R1.0 through onboard • CCE default application loaded, over Linux clock switch 64 MB NOR ash memory MicroBlaze: 12 W (CCE loaded, on stand-by, FPGA containing FPGA images, MicroBlaze boot code, user code • Available GTX base clocks — 100 MHz, 125 MHz, I/Os mapped) 128 MB DDR3 SDRAM 625 MHz (PCIe/GigE/XAUI/SRIO) (MicroBlaze memory) Mid-size AMC FMC modules options • Fabric clock — RX or TX (100 MHz PCIe, default) High-pin-count FMC interface (VITA 57) • ADAC250 • IPMI controller (based on the AVR version of the Pigeon Point AdvancedMC MMC) • 2× 250 MSPS, 14-bit ADC Full-size AMC FMC front panel Lyrtech products are constantly being improved; therefore, Lyrtech Full-size AMC panel shown. Mid-size AMC front panel also available. • FPGA and IPMI JTAGs on the Mestor interface • 2× 1 GSPS, 16-bit DACs reserves itself the right to modify the information herein at any time and without notice. Lyrtech Incorporated. All rights reserved. 2010-07-12