MACH 1 & 2 Families MACH 1 & 2 FAMILIES 1 FINAL COM’L: -12/15 IND: -18 Lattice Semiconductor MACH120-12/15 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS u68 Pins in PLCC u48 Macrocells u12 ns t Commercial, 18 ns t Industrial PD PD u77 MHz f Commercial CNT u48 I/Os; 4 dedicated inputs; 4 dedicated inputs/clocks u48 Outputs u48 Flip-ţops; 4 clock choices u4 “PALCE26V12” blocks uSpeedLocking™ for guaranteed Ţxed timing uPin-compatible with the MACH221 GENERAL DESCRIPTION ® The MACH120 is a member of the high-performance EE CMOS MACH 1 family. This device has approximately Ţve times the logic macrocell capability of the popular PALCE22V10 without loss of speed. ® The MACH120 consists of four PAL blocks interconnected by a programmable switch matrix. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efŢciently. The MACH120 macrocell provides either registered or combinatorial outputs with programmable polarity. If a registered conŢguration is chosen, the register can be conŢgured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input. Publication# 14129 Rev: J Amendment/0 Issue Date: November 1997 MACH 1 & 2 Families BLOCK DIAGRAM Block B Block A I –I 2 3 I –I I/O –I/O I/O –I/O 6 7 0 11 12 23 12 12 I/O Cells I/O Cells 12 12 4 Macrocells Macrocells OE OE 4 52 x 54 52 x 54 AND Logic Array AND Logic Array and and Logic Allocator Logic Allocator 26 26 Switch Matrix 26 26 52 x 54 52 x 54 AND Logic Array AND Logic Array and and 4 Logic Allocator Logic Allocator OE OE 4 Macrocells Macrocells 12 12 I/O Cells I/O Cells 12 12 I/O –I/O I/O –I/O 36 47 24 35 CLK /I CLK /I , Block D Block C 0 0, 1 1 CLK /I , CLK /I 2 4 3 5 14129J-1 MACH120-12/15 3 CONNECTION DIAGRAM Top View PLCC Block A Block D 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 I/O7 10 60 I/O41 I/O8 11 59 I/O40 12 I/O9 58 I/O39 I/O10 13 57 I/O38 14 I/O11 56 I/O37 15 CLK0/I0 55 I/O36 16 54 I7 CLK1/I1 I2 17 53 GND VCC 18 52 VCC 19 GND 51 I6 I3 20 50 CLK3/I5 I/O12 21 49 CLK2/I4 I/O13 22 48 I/O35 I/O14 23 47 I/O34 I/O15 24 I/O33 46 I/O16 25 45 I/O32 26 I/O17 44 I/O31 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Block C 14129J-2 Block B Note: Pin-compatible with the MACH220 and MACH221. PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output VCC = Supply Voltage 4 MACH120-12/15 GND I/O6 I/O18 GND I/O19 I/O5 I/O20 I/O4 I/O21 I/O3 I/O22 I/O2 I/O23 I/O1 VCC I/O0 GND GND I/O24 VCC I/O25 I/O47 I/O26 I/O46 I/O27 I/O45 I/O28 I/O44 I/O29 I/O43 GND I/O42 I/O30 GND MACH 1 & 2 Families ORDERING INFORMATION Commercial Products Vantis programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH 120 –12 J C FAMILY TYPE OPERATING CONDITIONS MACH = Macro Array CMOS High-Speed C = Commercial (0°C to +70°C) DEVICE NUMBER PACKAGE TYPE J = 68-Pin Plastic Leaded 120 = 48 Macrocells, 68 Pins Chip Carrier (PL 068) SPEED –12 = 12 ns t PD –15 = 15 ns t PD Valid Combinations Valid Combinations The Valid Combinations table lists conŢgurations planned to MACH120-12 be supported in volume for this device. Consult the local Vantis JC sales ofŢce to conŢrm availability of speciŢc valid MACH120-15 combinations and to check on newly released combinations. MACH120-12/15 (Com’l) 5 ORDERING INFORMATION Industrial Products Vantis programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH 120 –18 J I FAMILY TYPE OPERATING CONDITIONS MACH = Macro Array CMOS High-Speed I = Industrial (–40°C to +85°C) PACKAGE TYPE DEVICE NUMBER J = 68-Pin Plastic Leaded 120 = 48 Macrocells, 68 Pins Chip Carrier (PL 068) SPEED –18 = 18 ns t PD Valid Combinations The Valid Combinations table lists conŢgurations planned to Valid Combinations be supported in volume for this device. Consult the local Vantis sales ofŢce to conŢrm availability of speciŢc valid MACH120-18 JI combinations and to check on newly released combinations. 6 MACH120-18 (Ind) MACH 1 & 2 Families FUNCTIONAL DESCRIPTION The MACH120 consists of four PAL blocks connected by a switch matrix. There are 48 I/O pins and 4 dedicated input pins feeding the switch matrix. These signals are distributed to the four PAL blocks for efŢcient design implementation. There are 4 clock pins that can also be used as dedicated inputs. The PAL Blocks Each PAL block in the MACH120 (Figure 1) contains a 48-product-term logic array, a logic allocator, 12 macrocells and 12 I/O cells. The switch matrix feeds each PAL block with 26 inputs. This makes the PAL block look effectively like an independent “PALCE26V12”. There are four additional output enable product terms in each PAL block. For purposes of output enable, the 12 I/O cells are divided into 2 banks of 6 macrocells. Each bank is allocated two of the output enable product terms. An asynchronous reset product term and an asynchronous preset product term are provided for ţip-ţop initialization. All ţip-ţops within the PAL block are initialized together. The Switch Matrix The MACH120 switch matrix is fed by the inputs and feedback signals from the PAL blocks. Each PAL block provides 12 internal feedback signals and 12 I/O feedback signals. The switch matrix distributes these signals back to the PAL blocks in an efŢcient manner that also provides for high performance. The design software automatically conŢgures the switch matrix when Ţtting a design into the device. The Product-Term Array The MACH120 product-term array consists of 48 product terms for logic use, and 6 special-purpose product terms. Four of the special-purpose product terms provide programmable output enable, one provides asynchronous reset, and one provides asynchronous preset. Two of the output enable product terms are used for the Ţrst six I/O cells; the other two control the last six macrocells. The Logic Allocator The logic allocator in the MACH120 takes the 48 logic product terms and allocates them to the 12 macrocells as needed. Each macrocell can be driven by up to 12 product terms. The design software automatically conŢgures the logic allocator when Ţtting the design into the device. Table 1 illustrates which product term clusters are available to each macrocell within a PAL block. Refer to Figure 1 for cluster and macrocell numbers. Table 1. Logic Allocation Available Available Output Macrocell Clusters Output Macrocell Clusters M C , C M C , C , C 0 0 1 6 5 6 7 M C , C , C M C , C , C 1 0 1 2 7 6 7 8 M C , C , C M C , C , C 2 1 2 3 8 7 8 9 M C , C , C M C , C , C 3 2 3 4 9 8 9 10 M C , C , C M C , C , C 4 3 4 5 10 9 10 11 M C , C , C M C , C 5 4 5 6 11 10 11 MACH120-12/15 7 The Macrocell The MACH120 macrocells can be conŢgured as either registered or combinatorial, with programmable polarity. The macrocell provides internal feedback whether conŢgured as registered or combinatorial. The ţip-ţops can be conŢgured as D-type or T-type, allowing for product-term optimization. The ţip-ţops can individually select one of four global clock pins, which are also available as logic inputs. The registers are clocked on the LOW-to-HIGH transition of the clock signal. The ţip-ţops can also be asynchronously initialized with the common asynchronous reset and preset product terms. The I/O Cell The I/O cell in the MACH120 consists of a three-state output buffer. The three-state buffer can be conŢgured in one of three ways: always enabled, always disabled, or controlled by a product term. If product term control is chosen, one of two product terms may be used to provide the control. The two product terms that are available are common to six I/O cells. Within each PAL block, two product terms are available for selection by the Ţrst six three-state outputs; two other product terms are available for selection by the last six three-state outputs. These choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or a three-state output for use in driving a bus. SpeedLocking for Guaranteed Fixed Timing The unique MACH 1 architecture is designed for high performance—a metric that is met in both raw speed, but even more importantly, guaranteed Ţxed speed. Using the design of the central switch matrix, the MACH 120 product offers the SpeedLocking feature, which allows a stable Ţxed pin-to-pin delay, independent of logic paths, routing resources and design reŢts for up to 16 product terms per output. Other non-Vantis CPLDs incur serious timing delays as product terms expand beyond their typical 4 or 5 product term limits. Speed and SpeedLocking combine for continuous, high performance required in today's demanding designs 8 MACH120-12/15 MACH 1 & 2 Families 0 4 8 12 16 20 24 28 32 36 40 43 47 51 Output Enable Output Enable Asynchronous Reset Asynchronous Preset I/O I/O Cell Output Macro M Cell 0 I/O Cell I/O Output Macro M Cell 1 I/O Cell I/O Output Macro M 2 Cell 0 C 0 I/O I/O Cell C Output 1 Macro M 3 Cell C 2 I/O I/O Cell C 3 Output M Macro 4 Cell C 4 I/O C Cell I/O 5 Output Switch Macro M 5 Cell Matrix C 6 I/O C Cell I/O 7 Output Macro M 6 Cell C 8 I/O C 9 Cell I/O Output Macro M 7 Cell C 10 C 11 I/O I/O 47 Cell Output M 8 Macro Cell I/O I/O Cell Output M Macro 9 Cell I/O I/O Cell Output M Macro 10 Cell I/O Cell I/O Output M Macro 11 Cell Output Enable Output Enable 0 4 8 12 16 20 24 28 32 36 40 43 47 51 4 12 12 14129J-3 Figure 1. MACH120 PAL Block MACH120-12/15 9 Logic Allocator CLK ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . -65°C to +150°C Commercial (C) Devices Ambient Temperature Ambient Temperature (T ) A With Power Applied . . . . . . . . . . . . . .-55°C to +125°C Operating in Free Air. . . . . . . . . . . . . . . 0°C to +70°C Device Junction Temperature . . . . . . . . . . . . . +150°C Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . . CC with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V Supply Voltage with Respect to Ground . . . . . . . . . . . . . . -0.5 V to +7.0 V Operating ranges deŢne those limits between which the func- tionality of the device is guaranteed. DC Input Voltage . . . . . . . . . . . -0.5 V to V + 0.5 V CC DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to V + 0.5 V CC Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (T = 0°C to 70°C) . . . . . . . . . . . . . . . . . . . . 200 mA A Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Rat- ings for extended periods may affect device reliability. Pro- gramming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit I = -3.2 mA, V = Min OH CC V Output HIGH Voltage 2.4 V OH V = V or V IN IH IL I = 16 mA, V = Min OL CC V Output LOW Voltage 0.5 V OL V = V or V IN IH IL Guaranteed Input Logical HIGH V Input HIGH Voltage 2.0 V IH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW V Input LOW Voltage 0.8 V IL Voltage for all Inputs (Note 1) I Input HIGH Current V = 5.25 V, V = Max (Note 2) 10mA IH IN CC I Input LOW Current V = 0 V, V = Max (Note 2) -10mA IL IN CC Off-State Output Leakage V = 5.25 V, V = Max OUT CC I 10mA OZH Current HIGH V = V or V (Note 2) IN IH IL Off-State Output Leakage V = 0 V, V = Max OUT CC I -10mA OZL Current LOW V = V or V (Note 2) IN IH IL I Output Short-Circuit Current V = 0.5 V, V = Max (Note 3) -30 -130 mA SC OUT CC V = 5 V, T =25°C, f = 25 MHz CC A I Supply Current (Typical) 85 mA CC (Note 4) Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of I and I (or I and I ). IL OZL IH OZH 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. V = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. OUT 4. Measured with a 12-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded, enabled, and reset. 10 MACH120-12/15 (Com’l) MACH 1 & 2 Families CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit C Input Capacitance V = 2.0 V 6 pF IN IN V = 5.0 V, T = 25°C CC A f = 1 MHz C Output Capacitance V = 2.0 V 8 pF OUT OUT SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) -12 -15 Parameter Symbol Parameter Description Min Max Min Max Unit t Input, I/O, or Feedback to Combinatorial Output 12 15 ns PD D-type 7 10 ns Setup Time from Input, I/O, or t S Feedback to Clock T-type 8 11 ns t Hold Time 0 0 ns H t Clock to Output 8 10 ns CO t LOW 6 6 ns WL CLock Width t HIGH 6 6 ns WH D-type 66.7 50 MHz External Feedback T-type 62.5 47.6 MHz Maximum f Frequency D-type 76.9 66.6 MHz MAX Internal (Note 1) Feedback (f ) CNT T-type 71.4 55.5 MHz No Feedback 83.3 83.3 MHz t Asynchronous Reset to Registered Output 16 20 ns AR t Asynchronous Reset Width (Note 1) 12 15 ns ARW t Asynchronous Reset Recovery Time (Note 1) 8 10 ns ARR t Asynchronous Preset to Registered Output 16 20 ns AP t Asynchronous Preset Width (Note 1) 12 15 ns APW t Asynchronous Preset Recovery Time (Note 1) 8 10 ns APR t Input, I/O, or Feedback to Output Enable 12 15 ns EA t Input, I/O, or Feedback to Output Disable 12 15 ns ER Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modiŢed where frequency may be affected. 2. See Switching Test Circuit, for test conditions. MACH120-12/15 (Com’l) 11 ABSOLUTE MAXIMUM RATINGS INDUSTRIAL OPERATING RANGES Storage Temperature . . . . . . . . . . . . . -65°C to +150°C Industrial (I) Devices Ambient Temperature Ambient Temperature (T ) A With Power Applied . . . . . . . . . . . . . -55°C to +125°C Operating in Free Air. . . . . . . . . . . . . . -40°C to +85°C Device Junction Temperature . . . . . . . . . . . . . +150°C Supply Voltage (V ) CC with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V Supply Voltage with Respect to Ground . . . . . . . . . . . . . . -0.5 V to +7.0 V Operating ranges deŢne those limits between which the func- tionality of the device is guaranteed. DC Input Voltage . . . . . . . . . . . . -0.5 V to V + 0.5 V CC DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to V + 0.5 V CC Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (T = -40°C to +85°C) . . . . . . . . . . . . . . . . . . . 200 mA A Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Rat- ings for extended periods may affect device reliability. Pro- gramming conditions may differ. DC CHARACTERISTICS over INDUSTRIAL operating ranges Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit I = -3.2 mA, V = Min OH CC V Output HIGH Voltage 2.4 V OH V = V or V IN IH IL I = 16 mA, V = Min OL CC V Output LOW Voltage 0.5 V OL V = V or V IN IH IL Guaranteed Input Logical HIGH V Input HIGH Voltage 2.0 V IH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW V Input LOW Voltage 0.8 V IL Voltage for all Inputs (Note 1) I Input HIGH Current V = 5.25 V, V = Max (Note 2) 10mA IH IN CC I Input LOW Current V = 0 V, V = Max (Note 2) -10mA IL IN CC Off-State Output Leakage V = 5.25 V, V = Max OUT CC I 10mA OZH Current HIGH V = V or V (Note 2) IN IH IL Off-State Output Leakage V = 0 V, V = Max OUT CC I -10mA OZL Current LOW V = V or V (Note 2) IN IH IL I Output Short-Circuit Current V = 0.5 V, V = Max (Note 3) -30 -130 mA SC OUT CC I Supply Current (Typical) V = 5 V, T = 25°C, f = 25 MHz (Note 4) 85 mA CC CC A Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of I and I (or I and I ). IL OZL IH OZH 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. V = 0.5 V OUT has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 12-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. 12 MACH120-18 (Ind) MACH 1 & 2 Families CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit C Input Capacitance V = 2.0 V 6 pF IN IN V = 5.0 V, T = 25°C CC A f = 1 MHz C Output Capacitance V = 2.0 V 8 pF OUT OUT SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) -18 Parameter Symbol Parameter Description Min Max Unit t Input, I/O, or Feedback to Combinatorial Output (Note 3) 18 ns PD D-type 12 ns t Setup Time from Input, I/O, or Feedback S T-type 13.5 ns t Hold Time 0 ns H t Clock to Output (Note 3) 12 ns CO t LOW 7.5 ns WL Clock Width t HIGH 7.5 ns WH D-type 40 MHz External Feedback 1/(t + t ) S CO T-type 38 MHz Maximum f Frequency (Note D-type 53 MHz MAX Internal Feedback (f ) 1) CNT T-type 44 MHz No Feedback 1/(t + t ) 66.5 MHz WL WH t Asynchronous Reset to Registered Output 24 ns AR t Asynchronous Reset Width (Note 1) 18 ns ARW t Asynchronous Reset Recovery Time (Note 1) 12 ns ARR t Asynchronous Preset to Registered Output 24 ns AP t Asynchronous Preset Width (Note 1) 18 ns APW t Asynchronous Preset Recovery Time (Note 1) 12 ns APR t Input, I/O, or Feedback to Output Enable (Note 3) 18 ns EA t Input, I/O, or Feedback to Output Disable (Note 3) 18 ns ER Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modiŢed where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 24 outputs switching. MACH120-18 (Ind) 13 TYPICAL CURRENT vs. VOLTAGE (I-V) CHARACTERISTICS V = 5.0 V, T = 25°C CC A IOL (mA) 80 60 40 20 VOL (V) –1.0 –0.8 –0.6 –0.4 –0.2 .2 .4 .6 .8 1.0 –20 –40 –60 –80 14129 Output, LOW IOH (mA) 25 1 2 3 4 5 VOH (V) –3 –2 –1 –25 –50 –75 –100 –125 –150 Output, HIGH 14129J-5 II (mA) 20 VI (V) –2 –1 1 2 3 4 5 –20 –40 –60 –80 –100 Input 14129J-6 14 MACH120-12/15 MACH 1 & 2 Families TYPICAL I CHARACTERISTICS CC V = 5 V, T = 25°C CC A 150 I (mA) CC 125 100 75 50 25 0 0 10 20 30 40 50 60 70 Frequency (MHz) 14129J-7 The selected “typical” pattern is a 12-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register. MACH120-12/15 15 TYPICAL THERMAL CHARACTERISTICS Measured at 25°C ambient. These parameters are not tested. Typ Parameter Symbol Parameter Description PLCC Unit qThermal impedance, junction to case 13 °C/W jc qThermal impedance, junction to ambient 37 °C/W ja 200 lfpm air 33 °C/W 400 lfpm air 30 °C/W qThermal impedance, junction to ambient with air ţow jma 600 lfpm air 28 °C/W 800 lfpm air 25 °C/W Plastic qjc Considerations The data listed for plastic qjc are for reference only and are not recommended for use in calculating junction temperatures. The heat-ţow paths in plastic-encapsulated devices are complex, making the qjc measurement relative to a speciŢc location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, qjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. The thermal measurements are taken with components on a six-layer printed circuit board. SWITCHING WAVEFORMS Input, I/O, or V T Feedback t PD Combinatorial V T Output 14129J-8 Combinatorial Output Input, I/O, or V T Feedback t t S H V T Clock t CO Registered V T Output 14129J-9 Registered Output t WH Clock t WL 14129J-10 Clock Width Notes: 1. V = 1.5 V. T 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. 16 MACH120-12/15 MACH 1 & 2 Families SWITCHING WAVEFORMS t ARW Input, I/O, or V T Feedback t AR Registered V T Output t ARR V T Clock 14129J-11 Asynchronous Reset t APW Input, I/O, V T or Feedback t AP Registered V T Output t APR V T Clock 14129J-12 Asynchronous Preset Input, I/O, or V T Feedback t t ER EA V – 0.5 V OH V Outputs T V + 0.5 V OL 14129J-13 Output Disable/Enable Notes: 1. V = 1.5 V. T 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. MACH120-12/15 17 KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Will be Steady Steady May Will be Change Changing from H to L from H to L May Will be Change Changing from L to H from L to H Don’t Care, Changing, Any Change State Permitted Unknown Does Not Center Apply Line is High- Impedance “Off” State KS000010-PAL SWITCHING TEST CIRCUIT 5 V S 1 R 1 Output Test Point R 2 C L 14129J-14 Commercial SpeciŢcation S C R R Measured Output Value 1 L 1 2 t , t Closed PD CO Z fi H: Open 35 pF 1.5 V t EA Z fi L: Closed 300 W390 W H fi Z: Open H fi Z: V – 0.5 V OH t 5 pF ER L fi Z: Closed L fi Z: V + 0.5 V OL *Switching several outputs simultaneously should be avoided for accurate measurement. 18 MACH120-12/15 MACH 1 & 2 Families F PARAMETERS MAX The parameter f is the maximum clock rate at which the device is guaranteed to operate. Be- MAX cause the ţexibility inherent in programmable logic devices offers a choice of clocked ţip-ţop designs, f is speciŢed for three types of synchronous designs. MAX The Ţrst type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path deŢning the period is the sum of the clock-to-output time and the input setup time for the exter- nal signals (t + t ). The reciprocal, f , is the maximum frequency with external feedback or in S CO MAX conjunction with an equivalent speed device. This f is designated “f external.” MAX MAX The second type of design is a single-chip state machine with internal feedback only. In this case, ţip-ţop inputs are deŢned by the device inputs and ţip-ţop outputs. Under these condi- tions, the period is limited by the internal delay from the ţip-ţop outputs through the internal feedback and logic to the ţip-ţop inputs. This f is designated “f internal”. A simple in- MAX MAX ternal counter is a good example of this type of design; therefore, this parameter is sometimes called “f .” CNT The third type of design is a simple data path application. In this case, input data is presented to the ţip-ţop and clocked through; no feedback is employed. Under these conditions, the pe- riod is limited by the sum of the data setup time and the data hold time (t + t ). However, a S H lower limit for the period of each f type is the minimum clock period (t + t ). Usually, MAX WH WL this minimum clock period determines the period for the third f , designated “f no feed- MAX MAX back.” For devices with input registers, one additional f parameter is speciŢed: f . Because this MAX MAXIR involves no feedback, it is calculated the same way as f no feedback. The minimum period MAX will be limited either by the sum of the setup and hold times (t + t ) or the sum of the clock SIR HIR widths (t + t ). The clock widths are normally the limiting parameters, so that f is WICL WICH MAXIR speciŢed as 1/(t + t ). Note that if both input and output registers are use in the same WICL WICH path, the overall frequency will be limited by t . ICS All frequencies except f internal are calculated from other measured AC parameters. f MAX MAX internal is measured directly. CLK CLK (SECOND CHIP) LOGIC REGISTER LOGIC REGISTER t t t S CO S f Internal (f ) MAX CNT f External 1/(t + t ) MAX s CO CLK CLK LOGIC REGISTER REGISTER LOGIC t S t t SIR HIR f No Feedback; 1/(t + t ) or 1/(t + t ) MAX s H WH WL f ; 1/(t + t ) or 1/(t + t ) MAXIR SIR HIR WICL WICH MACH120-12/15 19 ENDURANCE CHARACTERISTICS The MACH families are manufactured using Vantis’ advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Endurance Characteristics Parameter Symbol Parameter Description Units Test Conditions 10 Years Max Storage Temperature t Min Pattern Data Retention Time DR 20 Years Max Operating Temperature N Max Reprogramming Cycles 100 Cycles Normal Programming Conditions INPUT/OUTPUT EQUIVALENT SCHEMATICS V CC 100 kW V 1 kWCC ESD Protection Input V CC V CC 100 kW 1 kW Preload Feedback Circuitry Input 14129J-15 I/O 20 MACH120-12/15 MACH 1 & 2 Families POWER-UP RESET The MACH devices have been designed with the capability to reset during system power-up. Following power-up, all ţip-ţops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra ţexibility to the designer and is especially valuable in sim- plifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways V can rise CC to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The V rise must be monotonic. CC 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Symbol Parameter Descriptions Max Unit t Power-Up Reset Time 10ms PR t Input or Feedback Setup Time See S Switching t Clock Width LOW WL Characteristics V CC 4 V Power t PR Registered Output t S Clock t WL 14129J-16 Power-Up Reset Waveform MACH120-12/15 21