IT8888F PCI-to-ISA Bridge Chip (Code Name: Golden Gate) Preliminary Specification V0.7.1 Copyright ã 1999 ITE, Inc. This is Preliminary document release. All specifications are subject to change without notice. The material contained in this document supersedes all previous documentation issued for the related products included herein. Please contact ITE, Inc. for the latest document(s). All sales are subject to ITE ’s Standard Terms and Conditions, a copy of which is included in the back of this document. ITE and IT8888F are trademarks of ITE, Inc. Intel and MISA (Moon ISA, 380AB) are claimed as trademarks by Intel Corp. TM PCI is a registered trademark of PCI Special Interest Group. All trademarks are the properties of their respective owners. All specifications are subject to change without notice. Additional copies of this manual or other ITE literature may be obtained from: ITE, Inc. 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Revision History VersionDate Changes from Last Version 0.1 6/15/98 · Initial draft. 0.2 7/10/98 · Implement Dell’s requests. (5V power with 3.3V PCI) (add NOGO pin) · Add Register design notes 0.3 7/17/98 · Final Pin out from Design Engineer · Fix typos. · Enhance feature list 0.4 9/9/98 · Update Register map · Add PCI Configuration registers 0.5 10/6/98 · Convert from IT8888F Advanced information v. 0.4 0.6 11/24/9 · Add AC Characteristics and Waveforms 8 0.7 1/21/99 · Chip Revision (Cfg_08<7:0>=8’h01) · Change Power-On-Strap pins · Change default value of Cfg_50h<24:16, 5> and Cfg_54h<31> to 1 · Change default value of Cfg_70h & Cfg_74h as all zero · Add Cfg_54h<19:16> to report IOCHCK# and I/O byte Enable Error to SERR# · Add Cfg_54h<21> to mask IOCHCK# to SERIRQ encoding · Add Cfg_54h<20> to select pin_133 as NOGO or CLKRUN# · Change Cfg_54h<30> to patch unexpected DREQn de-assertion of PC/PCI DMA · Change Cfg_50h<1> attribute as R/W · Chip Revision (Cfg_08<7:0>=8’h03) 0.7.1 04/23 · In the Retry/Discard Timers, Misc. Control Register table of Cfg_54h, the bit 20 description was changed to: Select the function of pin# 133 to be NOGO or CLKRUN# IT8888F CONTENTS Page 1. Features ................................ ................................ ................................ ................................ ................... 1-1 2. General Description ................................ ................................ ................................ ................................ .... 1 3. Pin Configuration ................................ ................................ ................................ ................................ .... 3-1 4. Pin Description ................................ ................................ ................................ ................................ ........ 4-1 5. Functional Description ................................ ................................ ................................ ............................ 5-0 5.1 PCI Slave Interface ................................ ................................ ................................ ............................ 5-0 5.2 PCI Master Interface ................................ ................................ ................................ ........................... 5-0 5.3 PCI Parity ................................ ................................ ................................ ................................ ........... 5-1 5.4 Positively Decode Spaces ................................ ................................ ................................ .................. 5-1 5.5 Subtractive Decode ................................ ................................ ................................ ............................ 5-1 5.6 PC/PCI DMA (PPDMA) Slave Controller ................................ ................................ ............................. 5-1 5.7 Distributed DMA (DDMA) Slave Controller ................................ ................................ .......................... 5-2 5.8 Type-F DMA Timing ................................ ................................ ................................ ........................... 5-2 5.9 ISA Bus I/O Recovery Time ................................ ................................ ................................ ................ 5-3 5.10ISA Bus Arbiter ................................ ................................ ................................ ................................ ... 5-3 5.11SMB Boot ROM Configuration ................................ ................................ ................................ ............ 5-3 5.12Serialized IRQ ................................ ................................ ................................ ................................ .... 5-5 5.13NOGO and CLKRUN# ................................ ................................ ................................ ........................ 5-5 5.14Optional FLASH ROM Interface ................................ ................................ ................................ .......... 5-6 5.15Testability ................................ ................................ ................................ ................................ ........... 5-6 6. Register Description ................................ ................................ ................................ ................................ 6-1 6.1 Configur ation Register Map ................................ ................................ ................................ ................ 6-1 6.2 Access Configuration Registers ................................ ................................ ................................ .......... 6-2 6.3 Configuration Registers Description ................................ ................................ ................................ .... 6-4 6.3.1Device/Vendor ID Register ................................ ................................ ................................ ........... 6-4 6.3.2Status / Command Register ................................ ................................ ................................ ......... 6-4 6.3.3Class Code/ Revision ID Register ................................ ................................ ................................ 6-6 6.3.4Header Type/ Primary MLT/ Cache Line Size Register ................................ ................................ 6-7 6.3.5Subsystem Devi ce/Vendor ID Register ................................ ................................ ........................ 6-7 6.3.6DDMA Slave Channel_1 Register / DDMA Slave Channel_0 Register ................................ ......... 6-8 6.3.7DDMA Slave Channel_3 Register / DDMA Slave Channel_2 Register ................................ ......... 6-9 6.3.8DDMA Slave Channel_5 Register / DMA Type-F Timing / PPD Register ................................ .... 6-10 6.3.9DDMA Slave Channel_7 Register / DDMA Slave Channel_6 Register ................................ ....... 6-11 6.3.10ROM / ISA Spaces and Timing Control ................................ ................................ ...................... 6-12 6.3.11Retry/Discard Timers, Misc. Control Register ................................ ................................ ............. 6-16 6.3.12Positively Decoded IO_Space_0 Register ................................ ................................ .................. 6-18 6.3.13Positively Decoded IO_Space_1 Register ................................ ................................ .................. 6-19 6.3.14Positively Decoded IO_Space_2 Register ................................ ................................ .................. 6-19 6.3.15Positively Decoded IO_Space_3 Register ................................ ................................ .................. 6-20 6.3.16Positively Decoded IO_Space_4 Register ................................ ................................ .................. 6-20 i IT8888F 6.3.17Positively Decoded IO_Space_5 Register ................................ ................................ .................. 6-21 6.3.18Positively Decoded Memory_Space_0 Register ................................ ................................ ......... 6-22 6.3.19Positively Decoded Memory_Space_1 Register ................................ ................................ ......... 6-22 6.3.20Positively Decoded Memory_Space_2 Register ................................ ................................ ......... 6-23 6.3.21Positively Decoded Memory_Space_3 Register ................................ ................................ ......... 6-23 6.3.22Undefined Register ................................ ................................ ................................ .................... 6-24 6.4 DDMA Slave Registers Description ................................ ................................ ................................ ... 6-25 7. Characteristic ................................ ................................ ................................ ................................ ........... 7-1 7.1 DC Electrical Characteristics ................................ ................................ ................................ ............... 7-1 7.2 AC Characteristics ................................ ................................ ................................ .............................. 7-2 7.3 Waveforms ................................ ................................ ................................ ................................ ......... 7-6 8. Package Information ................................ ................................ ................................ ............................... 8-1 9. Ordering Information ................................ ................................ ................................ ............................... 9-1 FIGURES Page Figure 2 -1 IC Block Diagram ................................ ................................ ................................ ............................. 2-1 Figure 6 -1 PCI C onfiguration Register Structure ................................ ................................ ............................... 6-2 Figure 6 -2 PCI Configuration Access Mechanism #1 ................................ ................................ ........................ 6-3 Figure 7 -1 PCI Bus Interface Timing ................................ ................................ ................................ ................. 7-6 Figure 7 -2 PCI Configuration Write / Read Cycle ................................ ................................ .............................. 7-6 Figure 7 -3 DEVSEL# Decoding Speed ................................ ................................ ................................ .............. 7-7 Figure 7 -4 PCI Memory Read from ISA device when Delayed Transaction is Disabled ................................ ..... 7-7 Figure 7 -5 PCI Memory Read fr om ISA device when Delayed Transaction is Enabled ................................ ...... 7-8 Figure 7 -6 IT8888F Initiated Refresh Cycle ................................ ................................ ................................ ....... 7-9 Figure 7 -7 PCI I/O Read from ISA device ................................ ................................ ................................ ......... 7-9 Figure 7 -8 PCI I/O Wr ite to 8-bit ISA device when Cfg_54<28>=0b ................................ ................................ 7-10 Figure 7 -9 PCI I/O Write to 16-bit ISA device when Cfg_54<28>=1b ................................ .............................. 7-10 Figure 7 -10 PCI Memory Read from 8-bit ISA device ................................ ................................ ..................... 7-11 Figure 7 -11 PCI Memory Read from 16-bit ISA device ................................ ................................ ................... 7-11 Figure 7 -12 PCI Memory Write to 8-bit ISA device ................................ ................................ ......................... 7-12 Figure 7 -13 PCI Memory Write to 16-bit ISA device ................................ ................................ ....................... 7-12 Figure 7 -14 DREQn/DACKn# Coding in PC/PCI DMA function ................................ ................................ ....... 7-13 Figure 7 -15 DMA Read Operation in PC/PCI DMA (Memory Access to PCI with TC) ................................ ...... 7-13 Figure 7 -16 ISA Master Memory Read from PCI in PC /PCI DMA (Retried and Normal Termination) .............. 7-14 Figure 7 -17 DMA Read Operation in DDMA (Memory Access to PCI when DDMA-Concurrent is Disabled.) ... 7-15 Figure 7 -18 DMA Read Operation in DDMA (Memory A ccess to PCI when both Delayed-Transaction and DDMA- Concurrent are Enabled.) ................................ ................................ ................................ ......................... 7-16 Figure 7 -19 DMA Write Operation in DDMA (Memory Access to PCI when both Delayed-Transaction and DDMA- Concurrent are Enabled.) ................................ ................................ ................................ ......................... 7-17 Figure 7 -20 ISA Master Write and Master-Initiated-Refresh Operation in DDMA (Memory Access to PCI when both Delayed-Transaction and DDMA-Concurrent are Enabled.) ................................ .............................. 7-18 Figure 7 -21 Serialized IRQ Coding ................................ ................................ ................................ ................. 7-19 Figure 7 -22 CLKRUN# Operation ................................ ................................ ................................ ................... 7-19 2 Figure 7 -23 SMB Serial E PROM Configuration Programming ................................ ................................ ....... 7-20 2 Figure 7 -24 SMB Serial E PROM Interface Timing ................................ ................................ ......................... 7-20 TABLES Page ii IT8888F Table 4 -1 PCI Bus Interface Signals ................................ ................................ ................................ ................. 4-1 Table 4 -2 ISA Bus Interface Signals ................................ ................................ ................................ ................. 4-3 Table 4 -3 Miscellaneous Signals ................................ ................................ ................................ ....................... 4-6 Table 4 -4 Power Signals ................................ ................................ ................................ ................................ ... 4-6 Table 4 -5 IT8888F Alternative Pin Usage ................................ ................................ ................................ ......... 4-7 Table 4 -6 Power-On-Strap Settings ................................ ................................ ................................ .................. 4-8 Table 6 -1 IT8888F Configuration Register Map ................................ ................................ ................................ .6-1 Table 7 -1. Recommended Operating Conditions ................................ ................................ ............................... 7-1 Table 7 -2 General DC Characteristics ................................ ................................ ................................ ............... 7-1 o o Table 7 -3 DC Electrical Characteristics (T =0C~70C, VCC3=3.0~3.6V, VCC=4.75~5.25V) ......................... 7-2 OPT o o Table 7 -4 AC Characteristics of PCI Interface Timing (VCC=5.0V ± ±5%, VCC3=3.3V ± ±5%,Ta=0 C~70C, C=50 rF) L unit: ns ................................ ................................ ................................ ................................ ....................... 7-2 Table 7 -5 AC Characteristics of ISA Interface Timing (PIO Cycle) (Measured in Design Simulation) unit: 1T=1 PCICLK period ³ ³ 30ns ................................ ................................ ................................ ............................... 7-3 Table 7 -6 AC Characteristics of ISA Interface Timing (DMA Cycle) (Measured in Design Simulation) unit: 1T=1 PCICLK period ³ ³ 30ns ................................ ................................ ................................ ............................... 7-4 Table 7 -7 AC Characteristics of SMB Interface Timing (refer to Figure 7 -23, Measured in Design Simulation) unit: ms................................ ................................ ................................ ................................ .............................. 7-5 iii IT8888F Preliminary V0.7.1 Specification Subject to Change Without Notice ITPM-PN-99034, Cyrus, April 23, 1999 1. Features g PCI Interface g SM Bus - PCI Specification V. 2.1 compliant- Comply with System Management Bus - Supports 32-bit PCI bus & up to 33 MHz PCI Specification R. 1.0 bus frequency- Supports single master mode 2 - Supports PERR# & SERR# Error Reporting- Interface to Serial E PROM - Supports Delayed Transaction g Power-on Serial Bus Configuration - Optional CLKRUN# interface support- Power-on auto configuration through SM bus g Programmable PCI Address Decoders- Patent pending on auto-start and auto-stop scheme- Supports either programmable positive decode or full subtractive decode of PCI g Serial IRQ cycles- Comply with Serialized IRQ Support for PCI - Provides 6 positively decoded I/O blocks & 4 system R6.0 positively decoded memory blocks.- Supports both continuous and quite modes - Optional support ROMCS# fast positive- Auto detect Start Frame width and slot decoder number g PC/PCI DMA Controller- Encodes all ISA IRQs and IOCHCK# - Comply with Intel Mobile PC/PCI DMA R2.2 g Optional FLASH ROM Interface - Supports PPDREQ# and PPDGNT#- Supports up to 1 Mbytes ROM size - Provides software transparent capability- Positively fast decodes F-segments by power- g Distributed DMA Controller on strapping - Comply with Distributed DMA R6.0 g Versatile power-on strapping options - Supports 7 DDMA channels g Supports NOGO function - Optional DDMA-Concurrent PCI bus g Single 33 MHz Clock Input g ISA Interface g +3.3V PCI I/F with +5V tolerant I/O buffers - Supports full ISA compatible functions g +5V ISA I/F and core Power Supply - Supports ISA at ¼ of PCI frequency g Package: 160-pin PQFP - ISA Bus Master supported - Supports 4 ISA slots 2. General Description The IT8888F is a PCI to ISA bridge single function SM bus can provide customer with maximum design device. The IT8888F serves as a bridge between flexibility. The IT8888F also implements the optional the PCI bus and ISA bus. The IT8888F’s 32-bit PCI fast positive decode of F, E, D, C memory bus interface is compliant with PCI Specification segments. This special feature can provide a direct V2.1 and supports both PCI Bus Master & Slave. connection to an FALSH boot ROM. The PCI interface supports both programmable positive and full subtractive decoding schemes. The NOGO function which is also implemented in the IT8888F for enabling or disabling subtractive The IT8888F also integrates two enhanced DMA decode of PCI interface could be a software Slave controllers for achieving PCI DMA cycles: controlled output pin from other host controlled PC/PCI DMA Slave Controller & Distributed DMA devices. The Serial IRQ is also implemented in the Slave Controllers. The device also contains one SM device for sending and receiving ISA IRQs & bus (single master mode) which can be connected IOCHCK#. The device includes an ISA interface 2 to a Serial E PROM for automatic power-on which supports full ISA compatible functions. configuration. ITE’s proprietary (USA & Taiwan patent pending) power-on auto-configuration through The IT8888F is available in 160-pin PQFP package. 1-1 PCI-to-ISA Bridge (Golden Gate) IT8888F PPDREQ# NOGO & PPDGNT# SIRQ PCI Bus IT8888F (PCI to ISA Bridge) Serial PCI PCI PCI IRQ Configuration Slave Master (Slave) Registers Power-On Distributed PC/PCI Configuarion DMA DMA State Machine + 8237 Central Interface Bus CIB Bus SM Bus ISA Bus Data /ROMCS# Arbiter(Master) Control Logic Decoder Serial FLASH ISA Bus 2 EPROM ROM Figure 2-1 IC Block Diagram 2-1 ISA I/F PCI I/F IT8888F 3. Pin Configuration VCC3 1 120 GND C/BE2# 2 119 LA23 FRAME# 3 118 LA22 IRDY# 4 117 LA21 TRDY# 5 116 LA20 DEVSEL# 6 115 SA19 STOP# 7 114 SA18 LOCK# 8 113 SA17 PERR# 9 112 SA16 SERR# 10 111 SD7 PAR 11 110 SD6 C/BE1# 12 109 SD5 IT8888F AD15 13 108 SD4 AD14 14 107 SD3 AD13 15 106 SD2 AD12 16 105 SD1 AD11 17 104 SD0 GND 18 103 SA15 AD10 19 102 SA14 AD9 20 101 GND AD8 21 100 SA13 VCC3 22 99 SA12 PCI-to-ISA Bridge C/BE0# 23 98 SA11 AD7 24 97 SA10 AD6 25 96 SA9 AD5 26 95 SA8 AD4 27 94 SA7 GND 28 93 VCC AD3 29 92 SA6 Golden Gate AD2 30 91 GND AD1 31 90 SA5 (160-pin PQFP) AD0 32 89 SA4 SDATA 33 88 SA3 SCLK 34 87 SA2 RSTDRV 35 86 SA1 DACK7# 36 85 SA0 DACK6# 37 84 SBHE# DACK5# 38 83 MEMR# DACK3# 39 82 MEMW# GND 40 81 VCC 3-1 VCC 41 160 GND DACK2# 42 159 AD16 DACK1# 43 158 AD17 DACK0# 44 157 AD18 DRQ7 45 156 AD19 DRQ6 46 155 AD20 DRQ5 47 154 AD21 DRQ3 48 153 AD22 DRQ2 49 152 AD23 DRQ1 50 151 IDSEL DRQ0 51 150 C/BE3# GND 52 149 AD24 IRQ15 53 148 GND IRQ14/ROMCS#54 147 AD25 IRQ12 55 146 VCC3 IRQ11 56 145 AD26 IRQ10 57 144 AD27 IRQ9 58 143 AD28 IRQ7 59 142 AD29 IRQ6 60 141 AD30 IRQ5 61 140 AD31 IRQ4 62 139 IREQ# IRQ3 63 138 IGNT# TC 64 137 PCICLK REFRESH# 65 136 GND IOCS16# 66 135 PCIRST# MEMCS16# 67 134 SERIRQ IOCHCK# 68 133 NOGO/CLKRUN# GND 69 132 PPDREQ# BCLK 70 131 PPDGNT# IOCHRDY 71 130 VCC3 MASTER# 72 129 SD15 AEN 73 128 SD14 BALE 74 127 SD13 NOWS# 75 126 SD12 SMEMW# 76 125 SD11 SMEMR# 77 124 SD10 IOW# 78 123 SD9 IOR# 79 122 SD8 GND 80 121 VCC IT8888F 4. Pin Description Table 4-1 PCI Bus Interface Signals Pin # Symbol I/O Description Level 140~145, 147, I/O 3.3V AD[31:0] 149, 152~159, 32-bit bi-directional address/data multiplexed lines. AD31 13~17, 19~21, is the MSB and AD0 is the LSB. The direction of these 24~27, 29~32 pins are defined below: Address Phase Outpu t Input Read Data Phase Input Output Write Data Phase Output Input 150, 2, 12, 23 I/OCommand/Byte Enable 3 - 0 #. 3.3V C/BE[3:0]# Multiplexed bus command and byte enables. 6 DEVSEL# I/O #. 3.3V When driven active low, the signal indicates the driving device has decoded its address as the target of the current access. This pin acts as an output pin when the IT8888F (including ISA slave) is the slave of PCI bus cycle transaction. Otherwise, it is an input pin. 5 I/O 3.3V TRDY# This signal indicates that the target of the current data phase of the transaction is ready to be completed. This pin acts as an output pin when the IT8888F (including ISA slave) is the slave of the PCI bus cycle transaction. Otherwise, it is an input pin. 4 IRDY# I/O 3.3V This signal indicates that the initiator is ready to complete the current data phase of the transaction. This pin acts as an output pin when the IT8888F is the bus master of the PCI bus. Otherwise, it is an input pin. 3 FRAME# I/OFRAME #. 3.3V This signal is driven by the initiator to indicate the beginning and duration of a PCI access. 151 IDSEL IInitialization Device Select. 3.3V This signal is used as a chip select during PCI Configuration read / write transactions. 4-1 Initiator Ready #. Target Ready #. Device Select TargetBus MasterPHASE PCI Multiplexed Address / Data 31 - 0. IT8888F Table 4-1 PCI Bus Interface Signals (Continued) Pin # Symbol I/O Description Level 11 PAR I/O 3.3V This signal is used for the even parity check on both AD[31:0] & C/BE[3:0]# lines. The PAR input/output direction follows the AD[31:0] input/output direction. 9 PERR# I/O 3.3V This signal is used for reporting data parity errors during all PCI transactions, except in a Special Cycle. PERR# is an output when it detects a parity error in receiving data as a PCI Target or in reading data as a PCI Master. 10 SERR# I/OD 3.3V This signal is used for reporting address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. (input for IC test only) 8 LOCK# ILock #. 3.3V This signal indicates a Lock Cycle for an atomic operation that may require multiple transactions to complete. 7 I/OStop #. 3.3V STOP# This signal indicates that the current target is requesting the initiator to stop the current transaction. This pin acts as an output pin when the IT8888F (including ISA slave) is the slave of the PCI bus cycle transaction. Otherwise, it is an input pin. 139 IREQ# I/O 3.3V This signal is asserted to request the host bridge to allow the IT8888F to become the PCI bus master. (DDMA) (input for IC test only) 138 IGNT# I 3.3V This signal is asserted from the host bridge allowing the IT8888F to become the PCI bus master. (DDMA) 132 PPDREQ# I/OPC/PCI DMA (PPDMA) Request #. 3.3V This signal is used to encode the ISA DMA request information to the host bridge for PPDMA function. (input for IC test only) 131 PPDGNT# IPC/PCI DMA (PPDMA) Grant #. 3.3V This signal is asserted from the host bridge to send DACKn# information to IT8888F for PPDMA function. 137 I 3.3V PCICLK 135 I.3.3V PCIRST# PCIRST# is used to reset PCI bus devices. 4-2 PCI Bus Reset # 33 MHz PCI Clock. PCI Bus Grant #. PCI Bus Request #. System Error #. Parity Error #. Parity IT8888F Table 4-2 ISA Bus Interface Signals Pin # Symbol I/O Description Level 115~112, 103, SA[19:0] I/O 5V 102, 100~94, SA[19:0] are outputs except during the ISA master 92, 90~85 cycles. 119 - 116LA[23:20] I/O 5V Latchable Address bus LA23 to LA20 are outputs except during the ISA master cycles. 84 I/O, 5V SBHE# P/U 50K This signal indicates that the high byte on the ISA data bus is valid. SBHE# is an output except during the ISA master cycles 129~122, SD[15:0] I/O, 5V P/U 50K 16-bit bi-directional data lines. SD15 is the MSB. 111~104 79 IOR# I/O,.5V P/U 50K Active low output asserted by the CPU or DMA controller to read data or status information from the ISA device. Acts as input when ISA master cycles. 78 I/O,I/O Write #. 5V IOW# P/U 50K Active low output asserted by the CPU or DMA controller to write data or control information to the ISA device. Acts as an input during ISA master cycles. 73 AEN I/O, . 5V P/U 50K This signal is used to indicate DMA accesses. This signal is also used as power-on strapping select. 83 I/O,.5V MEMR# P/U 50K This signal is an output signal for all cycles except when the ISA master controls the bus. 82 MEMW# I/O,Memory Write #.5V P/U 50K This signal is an output signal for all cycles except when the ISA master controls the bus. 4-3 Memory Read # Address Enable I/O Read # ISA Data 15 - 0. System Byte High Enable #. ISA Latch Address 23 - 20. ISA Address 19 - 0. IT8888F Table 4-2 ISA Bus Interface Signals (Continued) Pin # Symbol I/O Description Level 66 IOCS16# I, 5V P/U 50K This signal indicates that the bus size of current ISA I/O slave is 16 bits. 67 MEMCS16# I/O, 5V P/U 50K This signal indicates that the bus size of current ISA memory slave is 16 bits. During DMA/MASTER cycles, MCS16# is asserted low when memory target is on the PCI bus. 75 NOWS# I, 5V P/U 50K This signal is asserted by the ISA slave in order to shorten the ISA cycle. The IT8888F samples NOWS# to escape standard wait states from the PCI when the ISA slaves have completed the transfer. 71 I/O,I/O Channel Ready. 5V IOCHRDY P/U 50K IOCHRDY is used by ISA slaves to insert wait states. During the ISA master cycles, IOCHRDY is asserted low by the IT8888F when the slave is on the PCI bus. 72 MASTER# I, 5V P/U 50K Indicates that a 16-bit ISA master takes control of the ISA bus. 68 IOCHCK# I,I/O Channel Check #. 5V P/U 50K ISA bus error indication 65 REFRESH# I/O, 5V P/U 50K Output to ISA bus when converting system timer ticks into a refresh cycle. Input from ISA master is used to refresh on-board and slot DRAM. 45~51 DRQ[7~ 5, I,DMA Request 7, 6, 5, 3, 2, 1, 0. 5V P/D 50K 3~0] These active high input signals are used to indicate the DMA service request from DMA devices, or the ISA bus control request from the ISA master. 36~39, DACK[7~ 5,I/O,DMA Acknowledge 7, 6, 5, 3, 2, 1, 0 #. 5V P/U 50K 3~0]# Active low outputs to acknowledge the corresponding 42~44 DMA requests. (input for IC test only) 64 TC I/O,Terminal Count.5V P/U 50K This signal is asserted to indicate the end of a DMA transfer. This signal is also used as power-on strapping select. 4-4 System Refresh Control #. 16-bit Master #. No Wait States #. 16-bit Memory Access #. 16-bit I/O Access #. IT8888F Table 4-2 ISA Bus Interface Signals (Continued) Pin # Symbol I/O Description Level 53 IRQ15 I, 5V P/U 50K This pin is the parallel interrupt request line 15. 54 IRQ14/ I/O, 5V ROMCS# P/U 50K The function selection of this pin is determined by ROM decoding related Configuration register settings. Please refer to section 5.14 Optional FLASH ROM Interface. 55 - 63 IRQ[12~9, I, 5V P/U 50K 7~3] These pins are the parallel interrupt request lines. 35 RSTDRV O.5V A high level on this output resets the ISA bus. This signal asynchronously terminates any activity and places the ISA device in the reset state. 77 I/O,.5V SMEMR# P/U 50K This signal is an output signal for access under 1MB; otherwise, tri-state. (input for IC test only) 76 SMEMW# I/O,.5V P/U 50K This signal is an output signal for access under 1MB; otherwise, tri-state. (input for IC test only) 70 BCLK O 5V ISA bus clock equals to ¼ of PCI clock. 74 I/O, 5V BALE P/U 50K This signal is also used as power-on strapping select. 4-5 Buffer Address Latch Enable Bus Clock System Memory Write # System Memory Read # ISA Reset Interrupt Request 12, 11, 10, 9, 7, 6, 5, 4, 3. Interrupt Request 14 /ROM Chip Select # Interrupt Request 15. IT8888F Table 4-3 Miscellaneous Signals Pin # Symbol I/O Description Level 133 NOGO/ I/ONOGO / Clock Run # 5V CLKRUN# The function selection of this pin is determined by Cfg_54h<20>. When acting as NOGO, it is an input from chipset to disable the subtractive decode of the IT8888F; when acting as CLKRUN#, it is an input/output for the IT8888F to request PCICLK to keep running. 134 SERIRQ I/O 5V This is Serialized IRQ for encoding parallel IRQ lines to one pin. 33 SDATA I/O, 5V 2 P/U 50K System Management Bus data for Serial E PROM. 34 I/OD, 5V SCLK P/U 50K System Management Bus clock output for Serial 2 EPROM. (input for IC test only) Table 4-4 Power Signals Pin # Symbol I/O Description Level 1, 22, VCC3 PWR 3.3V 130, 146 Those are connected to 3.3V power supply. 41, 81, VCC PWR 5V 93, 121, 5V power pins. 18, 28, 40, 52, PWRGround pins 0 V GND 69, 80, 91, 101, 120, 136, 148, 160 4-6 ISA Interface and chip core power pins. PCI Interface Power Pins. Serial Bus Clock Serial Bus Data Serial IRQ IT8888F Table 4-5 IT8888F Alternative Pin Usage Pin Signal Pin Signal Pin Signal Pin Signal 1 VCC3 41 VCC 81 VCC 121 VCC 2 C/BE2# 42 DACK2# 82 MEMW# 122 SD8 3 FRAME# 43 DACK1# 83 MEMR# 123 SD9 4 IRDY# 44 DACK0# 84 SBHE# 124 SD10 5 TRDY# 45 DRQ7 85 SA0 125 SD11 6 DEVSEL# 46 DRQ6 86 SA1 126 SD12 7 STOP# 47 DRQ5 87 SA2 127 SD13 8 LOCK# 48 DRQ3 88 SA3 128 SD14 9 PERR# 49 DRQ2 89 SA4 129 SD15 10 SERR# 50 DRQ1 90 SA5 130 VCC3 11 PAR 51 DRQ0 91 GND 131 PPDGNT# 12 C/BE1# 52 GND 92 SA6 132 PPDREQ# 13 AD15 53 IRQ15 93 VCC 133NOGO/CLKRUN# 14 AD14 54 IRQ14/ROMCS# 94 SA7 134 SERIRQ 15 AD13 55 IRQ12 95 SA8 135 PCIRST# 16 AD12 56 IRQ11 96 SA9 136 GND 17 AD11 57 IRQ10 97 SA10 137 PCICLK 18 GND 58 IRQ9 98 SA11 138 IGNT# 19 AD10 59 IRQ7 99 SA12 139 IREQ# 20 AD9 60 IRQ6 100 SA13 140 AD31 21 AD8 61 IRQ5 101 GND 141 AD30 22 VCC3 62 IRQ4 102 SA14 142 AD29 23 C/BE0# 63 IRQ3 103 SA15 143 AD28 24 AD7 64 TC 104 SD0 144 AD27 25 AD6 65 REFRESH# 105 SD1 145 AD26 26 AD5 66 IOCS16# 106 SD2 146 VCC3 27 AD4 67 MEMCS16# 107 SD3 147 AD25 28 GND 68 IOCHCK# 108 SD4 148 GND 29 AD3 69 GND 109 SD5 149 AD24 30 AD2 70 BCLK 110 SD6 150 C/BE3# 31 AD1 71 IOCHRDY 111 SD7 151 IDSEL 32 AD0 72 MASTER# 112 SA16 152 AD23 33 SDATA 73 AEN 113 SA17 153 AD22 34 SCLK 74 BALE 114 SA18 154 AD21 35 RSTDRV 75 NOWS# 115 SA19 155 AD20 36 DACK7# 76 SMEMW# 116 LA20 156 AD19 37 DACK6# 77 SMEMR# 117 LA21 157 AD18 38 DACK5# 78 IOW# 118 LA22 158 AD17 39 DACK3# 79 IOR# 119 LA23 159 AD16 40 GND 80 GND 120 GND 160 GND 4-7 IT8888F Table 4-6 Power-On-Strap Settings Symbol Pin #Jumper Description (P/Up)Reserved for enabling chip test function when PCIRST#=0 AEN 73 P/Down IT8888F Normal Function Fast DEVSEL# timing for F-segment BIOS (both 000FXXXXh and (P/Up) FFFFXXXXh). It will set Cfg_50h<3> BALE 74 P/Down No response or Subtractive Decode for F-segment access Enable SM-bus Boot ROM Configuration. It will set Cfg_50h<4>, (P/Up) but will be auto-cleared when finishing download configure code. TC 64 P/Down Disable SM-bus Boot ROM Configuration 4-8 IT8888F 5. Functional Description The IT8888F provides full ISA interface to hook up on PCI bus, so that the existing legacy ISA devices could be supported in new generation PC chipset architecture without ISA interface. There are some sub-function blocks in the IT8888F as described below: 5.1 PCI Slave Interface The IT8888F PCI Slave interface provides some positively decode space: · IT8888F PCI configuration register spaces – positively decode w/ medium DEVSEL# speed on the Type0 PCI configuration cycle, the access space is described in 6.2 Access Configuration Registers on page 6-2 . · Six I/O positively decode spaces – defined in IT8888F Configuration Registers: Cfg_58h ~ Cfg_6Fh. · Four Memory positively decode spaces – defined in IT8888F Configuration Registers: Cfg_70h ~ Cfg_7Fh. · Optional I/O Port 80 Write Snooping. · Optional F-segment BIOS claim w/ Fast DEVSEL# speed. · ISA Palette decoding (ref: Cfg_50h<7:6>). · DDMA registers spaces. · PC/PCI DMA cycle space: I/O addresses of 0000h / 0004h / 00C0h / 00C4h. The IT8888F supports PCI 2.1 Delayed Transaction feature which can be enabled / disabled by programming Cfg_50h<1>. The benefit of Delayed Transaction is that the PCI bus is still available and can be used by other PCI master, even when there is an ISA PIO cycle in progress behind IT8888F. When Delayed Transaction is enabled, the IT8888F will retry the PCI-to-ISA cycle claimed by IT8888F and latch those address / command / byte-combination, and issues ISA cycle. When the ISA site is not finished, the PCI Slave interface of IT8888F will still retry any PCI cycle. Once the ISA cycle is finished, the PCI Slave interface will wait the same PCI cycle (same address / command / Byte-enable) and terminate it normally with TRDY# asserted. But before that, the other PCI cycle with different address or command or Byte-enable still will be retried. If the original PCI bus master after retried never issue the same cycle within the programmed DISCARD Timer, then the IT8888F will discard that ISA transaction, so that the IT8888F is able to respond to other PCI transactions without locking its ISA bus interface. Please refer to the Cfg_54h<15:8> in 6.3.11, the Retry/Discard Timers of the Misc. Control Register on page 6-16 for the setting of Discard Timer. There is an option to report System Error via asserting SERR#. The IT8888F also supports Exclusive access via LOCK# control. Please refer to PCI Specification Revision 2.1, for more detailed description. 5.2 PCI Master Interface The IT8888F will issue PCI cycle for ISA bus master cycle and DDMA memory cycle if those accesses are forwarded to PCI bus. The Cfg_50h<23:12> define the decoding spaces for IT8888F to decide forwarding the access of ISA bus master or DDMA controller to PCI bus or not. When the accessed space is forwarding to PCI bus, the IT8888F will assert IREQ# to PCI bus arbiter if the DACKn# source is DDMA. Once the IGNT# is asserted by PCI arbiter and the PCI bus is in idle state, the PCI Master I/F of IT8888F will issue non-burst PCI Memory Read/Write cycles or PCI I/O Read/Write cycles (if Cfg_50h<23>=1). In the mean time, the IOCHRDY will be de-asserted to insert wait-state until forwarding cycle is finished on PCI site. When in PC/PCI DMA (PPDMA) cycle, the DACKn# is decoded from PPDGNT#, and the IT8888F will not issue IREQ#. As long as the PPDGNT# and MASTER# signal are asserted and there exist an ISA command 5-0 IT8888F issued by ISA master, then the PCI Master I/F of IT8888F will issue a PCI cycle for ISA master if the accessed space is located on PCI bus. Whenever the PCI Master I/F of IT8888F is retried, it will release PCI bus ownership and re-arbiter and re- issue the same transaction. But if the same retry occurs too many times and exceeds the Retry Timer limitation, then the PCI Master I/F will stop trying and there is an option to report System Error via asserting SERR#. Please refer to Cfg_54h<7:0> in 6.3.11 Retry/Discard Timers, Misc. Control Register on page 6-16 for more detailed Retry Timer setting. 5.3 PCI Parity The IT8888F, like other standard PCI devices, can handle parity error and other errors. Whenever the IT8888F detects address parity error, it is able to assert SERR# if the SERR# reporting mechanism is enabled in PCI Command/Status register. Also when IT8888F acts as a PCI slave, it will check the data parity of writing in data; when IT8888F acts as a PCI master, it will check the data parity of reading back data. Once it detects a data parity error, it can report data parity error and assert PERR# if the PERR# reporting mechanism is enabled in PCI Command/Status register. 5.4 Positively Decode Spaces The six positively decode I/O spaces can be programmed to claim PCI I/O cycle with Fast / Medium / Slow / Subtractive DEVSEL# timing speed. In addition, the ISA I/O aliases can be set to support legacy ISA card with non-fully decoded (only decodes with XA9~0). In other words, when alias is enabled for one I/O space, then the addresses A15~A10 of the PCI access address will be ignored for the enabled I/O space. All I/O spaces are limited under 64KB I/O size. IT8888F only claims I/O access with PCI address A[31:16]=0000h. When programmed to subtractive decoding speed, IT8888F will claim PCI I/O access only when whole chip Subtractive decode function is enabled (Cfg_50h<0>). The four positively decode Memory spaces can also be programmed to claim PCI Memory cycle with Fast / Medium / Slow / Subtractive DEVSEL# timing speed. The memory space is not limited, i.e., even above ISA 16MB size, if it is fall into IT8888F Memory positive decoding spaces, then it will be forwarded to ISA bus with address A31~A24 ignored. So users must carefully claim memory spaces, since the mechanism can support memory relocation. When programmed to subtractive decoding speed, IT8888F will claim PCI Memory access only when whole chip Subtractive decode function is enabled (Cfg_50h<0>), but the claimed space is restricted under memory space base/size setting, not limited to 16MB size. 5.5 Subtractive Decode IT8888F supports subtractive decode. In general, the subtractive decode mechanism of PCI-to-PCI Bridge chip is to respond to all non-claimed space. But for IT8888F, avoiding ISA space wrapped, it only responses to the memory space under 16MB size (ISA only has 24-bit addressing ability) when processing subtractive decode, except when the access space is hit to one of four positively decode memory space with slowest DEVSEL# timing speed. And the IT8888F only responds to unclaimed PCI I/O space under 64KB. 5.6 PC/PCI DMA (PPDMA) Slave Controller The IT8888F, following the “ Mobile PC/PCI DMA Arbitration and Protocols MHPG Architecture Functional Architectures Specification” by Intel Corporation, Revision 2.2, builds a PC/PCI DMA (PPDMA) Slave which supports all 7 ISA DMA channels through a single PPDREQ# / PPDGNT# pair. It provides a very low cost, low pin count mechanism. Please check the waveform for more details. This protocol works as the followings: the IT8888F encodes the DMA channel request information on the PPDREQ# line and decodes the PPDGNT#, which is output from PPDMA Host (in chipset), to assert the DACKn# of the granted DMA channel to ISA bus. The PPDMA protocol supports Single DMA, Demand DMA, but not Block DMA, nor software request DMA 5-1 IT8888F transfers. For PPDMA transfer, the PPDMA Host will separate Memory transaction portion from DMA operation, and issues PCI I/O transaction to PPDMA Slave with PPDGNT# asserted and special address listed below: PCI I/O Address R/W IT8888F Operation 00h R/W Normal DMA operation without TC 04h R/W Normal DMA operation with TC C0h R DMA Verify operation without TC C4h R DMA Verify operation with TC The IT8888F PPDMA slave controller can handle the PCI Retry while it was granted the bus, it continues to hold DACKn# active to ISA bus even when the PPDGNT# is removed. Also when the PCI Master I/F of IT8888F issues cycle for ISA Master and is retried, PPDMA slave would re-send the PPDREQ# to advise PPDMA Host to process Passive Release. 5.7 Distributed DMA (DDMA) Slave Controller The IT8888F integrates two DMA controllers (8237) to build a 7-channel DDMA salve for DDMA function, which comply with Distributed DMA Specification R6.0. There are seven DMA channels in IT8888F. Each channel maps to different ISA DMA channel, i.e. DMA channel 7~5, 3~0. Each channel can be treated as a separate DDMA salve, which has its own DDMA channel base address and can be enabled / disabled separately. To achieve compatibility with ISA, the DDMA channel 7~5 are fixed at 16-bit transfer width; the DDMA channel 3~0 are fixed at 8-bit transfer width. Each channel supports 24 or 32 bits addressing. That is to say, with IT8888F, the system OS or drivers can perform DMA operation to/from anywhere in 4GB-memory space, and is free from the limit of ISA 16MB memory space. When not using the high page register, the system OS or drivers either write 00h or disable high page for dedicated channel. In PC system, the DDMA Host is located in chipset, and it converts the address and data of legacy DMA accesses (including transferring base address, word counter register, mode / command / mask /… registers in I/O port 00h~1Fh, C0h~DFh and page registers in I/O port 8Xh~9Xh). This enables the IT8888F will receive PCI I/O cycles with the address = programming register offset plus pre-configured Base Address of dedicated DDMA slave channel. Please refer to 6.4 DDMA Slave Registers Description on page 6-25 for DDMA Slave Register mapping. For detailed register descriptions of legacy DMA controller, there are numerous manufactures’ data books that describe the functionality. 5.8 Type-F DMA Timing The IT8888F also supports Type F DMA timing. Each DMA channel can be programmed to operate in normal DMA timing or Type-F timing. For normal timing, the DDMA controller issuing I/O and Memory commands or the PPDMA module issuing the DMA I/O command meet the DMA operating timing defined in ISA Specification (IEEE P996 draft). Since the system memory bus is located behind ISA bus in legacy IBM PC/AT architecture, the timing is very loose (slow). But for current PC architecture, the system memory is located on Host bridge chip (or PCI North Bridge), thus DMA cycles can be operated faster to achieve better ISA DMA performance. 5-2 IT8888F 5.9 ISA Bus I/O Recovery Time The recovery time of back to back ISA I/O cycles is 1.5 BCLK (ISA System bus clock). The IT8888F provides different I/O recovery time setting for 8-bit I/O cycles and 16-bit I/O cycles. The configured 8-bit I/O recovery time is inserted after ISA I/F finishes the 8-bit I/O cycle, and the configured 16-bit I/O recovery time is inserted after ISA I/F finishes the 16-bit I/O cycle. No additional recovery time will be inserted due to byte conversion (PCI I/O cycle could be 8/16/24/32 bits, but ISA I/O is only 8/16 bits). 5.10 ISA Bus Arbiter The IT8888F internal ISA arbiter will handle and exclude DDMA cycle, Refresh cycle and PIO cycle from PCI bus to optimize the ISA bus utilization. To achieve PCI/ISA concurrency, there are some technologies to improve system performance: Delayed Transaction, Passive Release and the “DDMA-Concurrent“ in the IT8888F design. In legacy PC architecture, the CPU and PCI bus are held throughout the whole DMA operation even when the DMA access space is onto ISA bus or when the forwarded PCI transaction requires just a few PCI clocks to complete. IT8888F provides one option: DDMA-Concurrent cycle when DDMA operation (Cfg_54h<31>). When enabled, the IT8888F will request PCI bus only when DDMA controller or ISA master issued a transaction to be forwarded to PCI bus, and the IT8888F will release PCI bus after it finished PCI bus cycle, even when the DDMA / ISA master still occupies ISA bus. This is achieved by ISA arbiter, whenever DDMA occupy ISA bus, the PCI Slave will retry all PCI cycles belonging to IT8888F, so that the PCI bus can be used by other PCI transactions. The ISA Bus Refresh timer requests ISA memory REFRESH operation every 15.36 ms which is divided from PCI clocks by 512. The refresh module could be disabled by clearing Cfg_54h<26>. 5.11 SMB Boot ROM Configuration In addition that the IT8888F configuration can be done by PCI Configuration cycles through system chipset, the IT888F also offers an optional configuration method via the System Management Bus (SMB, similar to 2 IC BUS) Boot ROM. As the current version of IT8888F only supports single master mode, users are 2 prohibited to connect the IT8888F SMB interface to other system SMB bus. Only Serial E PROM can be connected, and the preset slave address is 1010000b. 2 st The Serial E PROM Data is grouped by each five bytes into the 1 byte, which serves as an index to indicate which PCI Configuration register is. The other 4 bytes are the 32-bits data will be written to the indexed register. 5-3 IT8888F 2 SMB ROM Data format in Serial E PROM is illustrated below: ROM Address ROM Data IT8888F Operation top 5n Index = AAhStop 5m+4 Data Cfg_50h<31:24> 5m+3 Data Cfg_50h<23:16> 5m+2 Data Cfg_50h<15:8> 5m+1 Data Cfg_50h<7:0> 5m Index = 50hCfg_50h 6 Data Cfg_XXh<7:0> 5 Index = XXhCfg_XXh 4 Data Cfg_??h<31:24> 3 Data Cfg_??h<23:16> 2 Data Cfg_??h<15:8> 1 Data Cfg_??h<7:0> 0 Index = ??hCfg_??h Whether the chip will execute SMB Boot ROM Configuring Sequence or not is determined by one power-on- strap setting. Please refer to the Table 4-6 Power-On-Strap Settings on page 4-8. If SMB boot ROM Configuration is enabled, the IT8888F will then set the SMB_In_Progress status bit (Cfg_50h<4>) on page 6- 2 12 and begin to issue the I C Sequential Read Operation. It writes to PCI Configuration Registers after it has 2 finished reading every five bytes from SM ROM. If it reads an Index value as AA , then it will stop I C hex Sequential Read Operation and clear the SMB_In_Progress status bit. The system BIOS can monitor the status bit to see if SMB is in progress before BIOS can decide to enable some computer system sub- functions. Conversely, if SMB boot ROM Configuration is disabled in power-on-strap setting, the IT8888F will then clear 2 the SMB_In_Progress status bit, and no I C Sequential Read Operation occurs. For instance, if users intend to claim a Memory space of 00F3XXXX (64KB size) and one I/O space of h 02AC ~ 02AD (2byte size) for a special ISA card (or users try to hook up the ISA device to PCI bus), a h h 2 Serial E PROM can be programmed. The resulted data are listed on the next page: 5-4 IT8888F 2 Serial E PROM IT8888F Configuration Register Address Data top ~ XX h B A AA IT8888F SMB I/F Stop h Cfg_64h<31:24> 9 C1 h Medium DEVSEL#, 2Byte size 8 00 Cfg_64h<23:16> = reserved h 7 02 h Cfg_64h<15:0> = 02AC h 6 AC h 5 64 Index 64 => Cfg_64h h h Cfg_7Ch<31:24> 4 A2 h Slow Medium, 64KB size 3 00 h 2 F3 Cfg_7Ch<23:0> = 00F3XXXX h h 1 00 h 0 7C Index 7C => Cfg_7Ch h h In the example above, the IT8888F SMB Configuration block will write the 32-bit data of A200F300 to h 2 Cfg_7Ch when it finishes reading byte 0~4 of Serial E PROM. It will also write the 32-bit data of C10002AC h 2 to Cfg_64h when it finishes reading byte 5~9 of Serial E PROM. After it receives an AA in the ROM position h of 5xN (i.e. address of 5 , 10, 15, .. etc.), the SMB I/F stops fetching more data and clear the d d d SMB_In_Progress status bit. For detailed SMB Configuration operation, please refer to the “IT8888F SMB Configuration Programming Guide”. The SMB Boot Configuring mechanism is patent pending. 5.12 Serialized IRQ The IT8888F builds a Serialized IRQ slave which complies with Serialized IRQ Support for PCI system R6.0. The Serialized IRQ slave provides signal filtering and encoding logic for all ISA IRQ channels (IRQ [15:14, 12:9, 7:3] and IOCHCK#), which also supports both continuous and quite mode, and auto detect Start Frame width and slot number. 5.13 NOGO and CLKRUN# The IT8888F also supports NOGO function, which is MUX-ed with the CLKRUN# signal (selected by Cfg_54h<20>). The NOGO is an input and controlled by chipset to disable the subtractive decode mechanism of the IT8888F, since there is only one subtractive decode device present on PCI bus. For short term, system manufacturers may use GPIO of chipset to control the NOGO pin of the IT8888F to boot up system, but the IT8888F also provides a mechanism to turn on/off the subtractive decode. And it will not be affected by DMA operation, nor by Delayed transaction. 5-5 IT8888F The IT8888F supports CLKRUN# function to reduce system power consumption when no PCI activity in progress. The CLKRUN# function follows the protocol defined in PCI Mobile Design Guide, Revision 1.0. But since the ISA system clock is divided from PCICLK, if some ISA cards still need ISA bus clock all the time, then the user should leave the Cfg_54<27> stay on default value of one. Thus the IT8888F will monitor system CLKRUN# signal and keep PCICLK running; otherwise, the IT8888F will only claim CLKRUN# when ISA Master / DMA requests service or for the DMA service duration, or when the Serialized IRQ module detects the status change on any ISA interrupt requests. 5.14 Optional FLASH ROM Interface The IT8888F provides ROM decoding and write protect. The ROM chip select can be decoded by programming versatile Cfg_50h<31:24> settings through segments C to F under 1MB and the top 1MB of 4GB. The ROM decoding logic provides ROMCS# signal (which is shared with IRQ14 signal, selected by the internal logic, i.e., when the ROM decoding related Configuration register settings are enabled, the pin 54 will be ROMCS# output automatically; otherwise, it will be IRQ14 input). The PCI Slave I/F needs to claim PCI memory space either by configuring four positively decoding spaces or by setting IT8888F in the subtractive decode mode, except in the power-on-strap settings: F-segment setting (BALE). If F-segment is set as positively decode, the IT8888F will only do fast DEVSEL# decoding speed and ROMCS# is generated automatically. Its space is F-segment of both 1MB top and 4GB top. Once the ROM is not on ISA interface, the IT8888F will disable F-segment fast decoding itself. 5.15 Testability The IT8888F provides several test modes, which are aimed for chip testing, not for system testing. Test Mode PCIRST# AEN DRQ1 DRQ0 1 X X X Normal Operation 0 0 X X 0 1 0 0 Tri-State Test 0 1 0 1 NAND Chain Test 0 1 1 0 Reserved 0 1 1 1 Tri-State Test: This test mode tri-states all outputs and bi-directional buffers, including the NAND chain outputs, BCLK and RSTDRV. NAND Chain Test: The IT8888F builds the NAND Chain test mode. This test mode tri-states all outputs and bi-directional buffers, except for BCLK and RSTDRV, and all the other output buffers are configured as inputs in NAND Chain test mode and are included in the NAND chain. The first input of the NAND chain is DACK2#. The NAND chain is routed counter-clockwise around the chip (e.g., DACK2#, DACK1#, DACK0#, DREQ7,…). The BCLK is an intermediate output, and the RSTDRV is the final output. PCIRST#, AEN, DRQ1, DRQ0, BCLK and RSTDRV pins are not included in the NAND chain. This testing method can be used to verify chip package connectivity, V /V DC characteristics. IH IL 5-6 IT8888F 6. Register Description 6.1 Configuration Register Map The IT8888FF PCI header configuration register set complies with Type 00h Configuration Space Header described in the PCI Specification R. 2.1. Table 6-1 IT8888F Configuration Register Map 31 16 15 00 Index Device ID (8888h) Vendor ID (1283h) 00h Status Command 04h Base Class Code (06h) Sub-class code(01/80h) Programming I/F (00h) Revision ID (01h) 08h Reserved (00h)Header Type (00h) Latency Timer (00h) Cache Line Size (00h) 0Ch Reserved 10h~2Bh Subsystem Device ID (0000h) Subsystem Vendor ID (0000h) 2Ch Reserved 30~3Fh DDMA Slave Channel_1 RegisterDDMA Slave Channel_0 Register 40h DDMA Slave Channel_3 RegisterDDMA Slave Channel_2 Register 44h DDMA Slave Channel_5 Register DMA Type F Timing PC/PCI DMA Control 48h DDMA Slave Channel_7 RegisterDDMA Slave Channel_6 Register 4Ch ROMCS# Master/DMA access MTOP, I/O Recovery Timing Control50h Misc. Control Reserved Discard Timer Retry Timer 54h Positively Decoded I/O_Space_0 58h Positively Decoded I/O_Space_1 5Ch Positively Decoded I/O_Space_2 60h Positively Decoded I/O_Space_3 64h Positively Decoded I/O_Space_4 68h Positively Decoded I/O_Space_5 6Ch Positively Decoded Memory_Space_0 70h Positively Decoded Memory_Space_1 74h Positively Decoded Memory_Space_2 78h Positively Decoded Memory_Space_3 7Ch Reserved 80h~FFh 6-1 IT8888F 6.2 Access Configuration Registers The IT8888F will respond to all PCI Bus Configuration cycles when the IDSEL input is asserted high. Address bits 1-0 of the Configuration cycle are both zeros and address bits 10-8 correspond to internal functions. The Type0 configuration address format is as follows: AD31-11 AD10-8 AD7-2 AD1-0 C/BE3-0# Only one Function Select,Register Select, to Configuration Type, Byte Select, to select one asserted to IT8888F only respond select one double- IT8888F only or more byte in selected active to Function = 000b word registerresponse to Type = double-word register IDSEL 00b The configuration registers can be accessed as byte, word (16 bits) or Double-Word (32 bits) quantities or any byte combination. In all of these accesses, only byte enables are used, AD[1:0] is always 00b when accessing the configuration registers. All multi-byte fields use "little-endian" ordering (that is, lower addresses contain the least significant parts of the fields). Registers that are marked “ Reserved ” will be decoded and return zeros when read. All bits defined as “ Reserved ” within IT8888F’s PCI Configuration Registers will be read as zero and will be unaffected by writes, unless specifically documented otherwise. The software can use the PCI Configuration Mechanism One to read or write the IT8888F PCI configuration register space. The PCI Configuration Mechanism One utilizes two 32-bit I/O ports located at addresses 0CF8h and 0CFCh. These two ports are: 1. INDEX Port: 32-bit wide, occupying I/O address 0CF8h through 0CFBh. 2. DATA Port: 32-bit wide, occupying I/O address 0CFCh through 0CFFh. Figure 6-1 PCI Configuration Register Structure Function=7 FCh FDh FEh FFh 08h 09h 0Ah 0Bh Function=1 FCh FDh FEh FFh Function=0 04h 05h 06h 07h FCh FDh FEh FFh INDEX=3Fh 00h 01h 02h 03h 08h 09h 0Ah 0Bh 08h 09h 0Ah 0Bh INDEX=2h 04h 05h 06h 07h 04h 05h 06h 07h INDEX=1h 00h 01h 02h 03h 00h 01h 02h 03h INDEX=0h IDSEL Host Chipset INDEX DATA 0CF8h-0CFBh0CFCh-0CFFh 0 4G PCI I/O Address Space 6-2 IT8888F Accessing any PCI configuration register is a two step process: Step 1: Perform I/O writes of the bus number, physical device number, function number, and register index number to the PCI Configuration Mechanism One INDEX Port. (The mother board chipset will decode the bus number, device number and then generate the IDSEL signal to select the device. The device then decodes the function number to select which bank of register to be accessed and decodes the register index number to select which double-word register will be accessed.) Step 2: Perform an I/O read from or write to the PCI Configuration Mechanism One DATA Port. The PCI Configuration Mechanism One INDEX & Data Port format is illustrated below: Figure 6-2 PCI Configuration Access Mechanism #1 PCI Configuartion Mechanism One INDEX Port Format 31 30 2423 1615 1110 8 7 2 1 0 Device Function Register 1 Reserved Bus Number 0 0 Number Number Index Number (8 bits) (5 bits) (3 bits) (6 bits) PCI Configuration Enable Mechanism Config. One Space Maximum ofMaximum of Maximum of Maximum of 64 Mapping 256 Buses32 Devices 8 Functions Double-word PCI Configuartion Mechanism One DATA Port Format 31 24 23 16 15 8 7 0 (MSB) Byte 3 Byte 2 Byte 1 Byte 0 (LSB) 6-3 IT8888F 6.3 Configuration Registers Description Below is the register description format: Index Value Register Function register r/w Register bits description Default value bitsattribute 6.3.1 Device/Vendor ID Register · Vendor Identification (VID) Register Address Offset: 00h - 01h Default Value: 1283h Access: Read-only Size: 16 bits The Vendor ID Register contains the vendor identification number for ITE. This 16-bit register combined with the Device ID Register uniquely identifies any PCI device. Writes to this register have no effect. Cfg_00h Device/Vendor ID Register <15:0> RO Vendor ID 1283h · Device Identification (DID) Register Address Offset: 02h - 03h Default Value: 8888h Access: Read-o nly Size: 16 bits The Device ID Register contains the device identification number for IT8888F. This 16-bit register along with the Vendor ID Register uniquely identifies any PCI device. Writes to this register have no effect. Cfg_00h Device/Vendor ID Register <31:16>RO Device ID 8888h 6.3.2 Status / Command Register · Command (CMD) Register Address Offset: 04h - 05h Default Value: 0007h Access: Read/Write Size: 16 bits The Command register provides coarse control over the IT8888F’s ability to generate and respond to PCI cycles. 6-4 IT8888F Cfg_04h Status / Command Register <15:10>RO Reserved all zero Fast back-to-back control. IT8888F will not perform FBTB access to the <9> RO 0b target on PCI bus. SERR# drives low enable. A value of 1 enables IT8888F to drive <8> R/W 0b SERR#. A value of 0 disables SERR# signal. <7> RO AD bus stepping. IT8888F does not perform AD stepping. 0b Parity error response. When the bit is 0, IT8888F will ignore any parity <6> R/W 0b error, which is detected on PCI bus interface. <5:3> RO Reserved 000b <2> RO Enable IT8888F to act as a master on primary interface. 1b <1> RO Downstream memory transaction enabling. 1b <0> RO Downstream I/O transaction enabling. 1b · Status (STS) Register Address Offset: 06h - 07h Default Value: 0280h Access: Read Only, Write-1-to-Clear, SMB Load Size: 16 bits The status register is used to record status information for PCI bus related events. Reads to this register behave normally. Some bits with access attribute of W1C (Write-1-to Clear) means when writes to this register with a '1' to the corresponding bit location cause that bit to be reset. Cfg_04h Status / Command Register <31> R/W1CSet by IT8888F whenever it detects a parity error on PCI bus. 0b <30> R/W1CSet by IT8888F whenever it asserts SERR#. 0b Set by IT8888F whenever it, as a PCI bus master, terminates a <29> R/W1C 0b transaction by signaling a Master Abort. Set by IT8888F whenever it, as a master, terminates a transaction by <28> R/W1C 0b receiving a Target Abort. Set by IT8888F whenever it, as a target, terminates a transaction by <27> R/W1C 0b signaling a Target Abort. Medium DEVSEL# timing for IT8888F as a target to respond to an <26:25>R/L 01b access on PCI bus. Set by IT8888F when three conditions are met: 1) asserting PERR# itself or observing PERR# being asserted; 2) IT8888F acts as a bus <24> R/W1C 0b master for the operation in which an error occurs; 3) Cfg_04h<6> is set. <23> RO Fast back-to-back capability (when IT8888F acts as a target). 1b <22:16>RO Reserved all zero 6-5 IT8888F 6.3.3 Class Code/ Revision ID Register · Revision Identification (RID) Register Address Offset: 08h Default Value: 01h Access: Read Only Size: 8bits The Revision ID Register contains the device revision number for IT8888F device. These bits are read- only. Writing to this register has no effect. · Programming Interface (PIF) Register Address Offset: 09h Default Value: 00h Access: Read Only Size: 8bits The Programming interface byte of the Class Code register indicates whether the device supports legacy and/or native mode like IDE interface. · Sub-Class Code (SCC) Register Address Offset: 0Ah Default Value: 01h/80h Access: Read Only Size: 8bits This Register contains the sub-class code for IT8888F. This Sub-Class code is 01h, indicating it is an “ISA Bridge”. These bits are read-only and writes to this register have no effect. · Base Class Code (BCC) Register Address Offset: 0Bh Default Value: 06h Access: Read Only Size: 8bits This Register contains the Base Class Code for IT8888F. This Base Class code is 06h, indicating it is a “Bridge Devices”. These bits are read-only and writes to this register have no effect. Cfg_08h Class Code/ Revision ID Register <31:24>RO Base-Class Code 06h Sub-Class Code. The default RO value depends on the value of Cfg_50h<0>. I.e. if Cfg_50h<0> is one (Subtractive Decode), then the <23:16>RO 80h (or 01h) Cfg_08h<23:16> is RO as 01h (as ISA bridge); otherwise, RO as 80h (as Other bridge device). The default value of Cfg_50h<0> is 0b. <15:8> RO Programming Interface 00h <7:0> RO Revision ID 00h 6-6 IT8888F 6.3.4 Header Type/ Primary MLT/ Cache Line Size Register · Cache Line Size (CLS) Register Address Offset: 0Ch Default Value: 00h Access: Read-only Size: 8bits This register specifies the system cache-line size in the unit of 32-bit words. · Master Latency Timer (MLT) Register Address Offset: 0Dh Default Value: 00h Access: Read-only Size: 8bits This register specifies, in the unit of PCI bus clocks, the value of the 8 most significant bits among the 11-bit Latency Timer for this device when the internal DMA controller is used and the device is a bus master. · Header Type (HTR) Register Address Offset: 0Eh Default Value: 00h Access: Read-only Size: 8bits This register identifies the header layout of the configuration space. These bits are read-only and writes to this register have no effect. Cfg_0Ch Header Type/ Primary MLT/ Cache Line Size Register <31:0> RO Reserved 00000000h 6.3.5 Subsystem Device/Vendor ID Register · Subsystem Vendor Identification (SVID) Register Address Offset: 2Ch - 2Dh Default Value: 0000h Access: Read-only Size: 16bits This value is used to identify the vendor of the subsystem. Subsystem Vendor IDs can be obtained from the PCI-SIG and are used to identify the vendor of the add-in board or subsystem. · Subsystem Device Identification (SDID) Register Address Offset: 2Eh - 2Fh Default Value: 0000h Access: Read-only Size: 16bits This value is used to identify a particular subsystem. This register along with SVID register is used to uniquely identify the add-in board or subsystem where the PCI device resides. Cfg_2Ch Subsystem Device/Vendor ID Register <31:16>R/L Subsystem Device ID 0000h <15:0> R/L Subsystem Vendor ID 0000h 6-7 IT8888F 6.3.6 DDMA Slave Channel_1 Register / DDMA Slave Channel_0 Register · DDMA Slave Channel 0 Register Address Offset: 40h - 41h Default Value: 0000h Access: Read/Write, Read-only Size: 16bits This register is used for DDMA Channel 0 base address assignment, data width status and enable control. Cfg_40h DDMA Slave Channel_1 Register / DDMA Slave Channel_0 Register <15:4>R/W DDMA Slave Channel_0 Base Address A[15:4] 000h DDMA Slave Channel_0 Non-Legacy Extended addressing Enable. If disabled, then the Base Address A[31:24] register of Channel_0 will be <3> R/W 0b always reset to 00h for memory access under 16MB. 0=Disabled, 1=Enabled. DDMA Slave Channel_0 Transfer Data width. <2:1> RO 00b 00=8bits, 01=16bits, 10=32bits, 11=Reserved. <0> R/W DDMA Slave Channel_0 Enable. 0=Disabled, 1=Enabled. 0b · DDMA Slave Channel 1 Register Address Offset: 42h - 43h Default Value: 0000h Access: Read/Write, Read-only Size: 16bits This register is used for DDMA Channel 1 base address assignment, data width status and enable control. Cfg_40h DDMA Slave Channel_1 Register / DDMA Slave Channel_0 Register <31:20>R/W DDMA Slave Channel_1 Base Address A[15:4] 000h DDMA Slave Channel_1 Non-Legacy Extended addressing Enable. If disabled, then the Base Address A[31:24] register of Channel_1 will be <19> R/W 0b always reset to 00h for memory access under 16MB. 0=Disabled, 1=Enabled. DDMA Slave Channel_1 Transfer Data width. <18:17>RO 00b 00=8bits, 01=16bits, 10=32bits, 11=Reserved. <16> R/W DDMA Slave Channel_1 Enable. 0=Disabled, 1=Enabled. 0b 6-8 IT8888F 6.3.7 DDMA Slave Channel_3 Register / DDMA Slave Channel_2 Register · DDMA Slave Channel 2 Register Address Offset: 44h - 45h Default Value: 0000h Access: Read/Write, Read-only Size: 16bits This register is used for DDMA Channel 2 base address assignment, data width status and enable control. Cfg_44h DDMA Slave Channel_3 Register / DDMA Slave Channel_2 Register <15:4>R/W DDMA Slave Channel_2 Base Address A[15:4] 000h DDMA Slave Channel_2 Non-Legacy Extended addressing Enable. If disabled, then the Base Address A[31:24] register of Channel_2 will be <3> R/W 0b always reset to 00h for memory access under 16MB. 0=Disabled, 1=Enabled. DDMA Slave Channel_2 Transfer Data width. <2:1> RO 00b 00=8bits, 01=16bits, 10=32bits, 11=Reserved. <0> R/W DDMA Slave Channel_2 Enable. 0=Disabled, 1=Enabled. 0b · DDMA Slave Channel 3 Register Address Offset: 46h - 47h Default Value: 0000h Access: Read/Write, Read-only Size: 16bits This register is used for DDMA Channel 3 base address assignment, data width status and enable control. Cfg_44h DDMA Slave Channel_3 Register / DDMA Slave Channel_2 Register <31:20>R/W DDMA Slave Channel_3 Base Address A[15:4] 000h DDMA Slave Channel_3 Non-Legacy Extended addressing Enable. If disabled, then the Base Address A[31:24] register of Channel_3 will be <19> R/W 0b always reset to 00h for memory access under 16MB. 0=Disabled, 1=Enabled. DDMA Slave Channel_3 Transfer Data width. <18:17>RO 00b 00=8bits, 01=16bits, 10=32bits, 11=Reserved. <16> R/W DDMA Slave Channel_3 Enable. 0=Disabled, 1=Enabled. 0b 6-9 IT8888F 6.3.8 DDMA Slave Channel_5 Register / DMA Type-F Timing / PPD Register · PPD Register Address Offset: 48h Default Value: FFh Access: Read/Write Size: 8bits This register is used to enable the PC/PCI DMA engine and each channel. Cfg_48h DDMA Slave Channel_5 Register / DMA Type-F Timing / PPD Register <7:5> R/W PPD DREQ Enable bits for Channel_[7:5]. 0= Masked, 1= Enabled. 111b PPD Global Enable bit. <4> R/W 0b: Disable PPDREQ#/PPDGNT# coding 1b 1b: Enable PPDREQ#/PPDGNT# coding <3:0> R/W PPD DREQ Enable bits for Channel_[3:0]. 0=Masked, 1= Enabled. 1111b · DMA Type-F Timing Address Offset: 49h Defaul t Value: 00h Access: Read/Write Size: 8bits This register is used to control DMA Type F timing which applies to both DDMA and PPD. The Type F DMA timing is not ISA compatible timing. Cfg_48h DDMA Slave Channel_5 Register / DMA Type-F Timing / PPD Register Type F DMA Timing Enable for each channel (apply to both DDMA and <15:8>R/W PPD, user should aware that, the Type F DMA Timing is not ISA 00h compatible timing). 0= Disabled, 1=Enabled. · DDMA Slave Channel 5 Register Address Offset: 4Ah – 4Bh Default V alue: 0002h Access: Read/Write, Read-only Size: 16bits This register is used for DDMA Channel 5 base address assignment, data width status and enable control. Cfg_48h DDMA Slave Channel_5 Register / DMA Type-F Timing / PPD Register <31:20>R/W DDMA Slave Channel_5 Base Address A[15:4] 000h DDMA Slave Channel_5 Non-Legacy Extended addressing Enable. If disabled, then the Base Address A[31:24] register of Channel_5 will be <19> R/W 0b always reset to 00h for memory access under 16MB. 0=Disabled, 1=Enabled. DDMA Slave Channel_5 Transfer Data width. <18:17>RO 01b 00=8 bits, 01=16 bits, 10=32 bits, 11=Reserved. <16> R/W DDMA Slave Channel_5 Enable. 0= Disabled, 1=Enabled. 0b 6-10 IT8888F 6.3.9 DDMA Slave Channel_7 Register / DDMA Slave Channel_6 Register · DDMA Slave Channel 6 Register Address Offset: 4Ch – 4Dh Default Value: 0002h Access: Read/Write, Read-only Size: 16bits This register is used for DDMA Channel 6 base address assignment, data width status and enable control. Cfg_4Ch DDMA Slave Channel_7 Register / DDMA Slave Channel_6 Register <15:4>R/W DDMA Slave Channel_6 Base Address A[15:4] 000h DDMA Slave Channel_6 Non-Legacy Extended addressing Enable. If disabled, then the Base Address A[31:24] register of Channel_6 will be <3> R/W 0b always reset to 00h for memory access under 16MB. 0=Disabled, 1=Enabled. DDMA Slave Channel_6 Transfer Data width. <2:1> RO 01b 00=8bits, 01=16bits, 10=32bits, 11=Reserved. DDMA Slave Channel_6 Enable. <0> R/W 0b 0=Disabled, 1=Enabled. · DDMA Slave Channel 7 Register Address Offset: 4Eh – 4Fh Default Value: 0002h Access: Read/Write, Read-only Size: 16bits This register is used for DDMA Channel 7 base address assignment, data width status and enable control. Cfg_4Ch DDMA Slave Channel_7 Register / DDMA Slave Channel_6 Register <31:20>R/W DDMA Slave Channel_7 Base Address A[15:4] 000h DDMA Slave Channel_7 Non-Legacy Extended addressing Enable. If disabled, then the Base Address A[31:24] register of Channel_7 will be <19> R/W 0b always reset to 00h for memory access under 16MB. 0=Disabled, 1=Enabled. DDMA Slave Channel_7 Transfer Data width. <18:17>RO 01b 00=8bits, 01=16bits, 10=32bits, 11=Reserved. <16> R/W DDMA Slave Channel_7 Enable. 0=Disabled, 1=Enabled. 0b 6-11 IT8888F 6.3.10 ROM / ISA Spaces and Timing Control · Timing Control Register Address Offset: 50h Default Value: 001XX000b Access: Read/Write, Read-only Size: 8bits This register is used for PCI Target I/F Response and SMB Boot Configuration. Cfg_50h ISA Spaces and Timing Control Palette Handling. 00b: iWiR. Ignore write, igno re Read access. <7:6> R/W 01b: sWiR. Snoop write, ignore Read access 00b 10b: sW+R. Snoop write, positive decode read access 11b: +W+R. Positive decode write, positive decode read access I/O Port 00000080h Snoop Write (For POST code dump): <5> R/W 1b: Enable Snoop Write to Port 80h 1b 0b: No response or do Subtractive decode for Port 80h SMB_In_Progress, it shows the status of SM Bus Boot ROM being in Power On progress. If TC is Pull/Up, this bit will be set to 1, and the SM-bus Boot <4> RO Strap value ROM Configuration will be initiated. Once finished (get index= AAh), of TC this bit will be cleared automatically. F-Segment BIOS access (of both 000FXXXXh & FFFFXXXXh): Power-On <3> R/W Strap value 1b: Positive decode with Fast DEVSEL# timing for F-segment of BALE 0b: No response or do Subt ractive decode for F-segment Reserved, must be written with 0. For compatible test only. Enable Processing Delayed Transaction in PC/PCI DMA cycle: <2> R/W 1b: Delayed Transaction is enabled in PPDMA cycle if Cfg_50<1> is 0b also enabled 0b: Delayed Transaction is disabled in PPDMA cycle, response as non- Delayed Transaction. Delayed Transaction in PIO cycle: <1> R/W 1b: Delayed Transaction is enabled. 0b 0b: Delayed Transaction is disabled. Non-Claimed PCI cycle until Subtractive DEVSEL# timing: <0> R/W 1b: Responses as a Subtractive decode agent 0b 0b: Still No response (only positive decode pre-defined space) 6-12 IT8888F · Memory Top / IO Recovery Register Address Offset: 51h Default Value: F0h Access: Read/Write Size: 8bits This register is used for system BIOS to set extended memory top in 16MB space (below memory hole) and ISA I/O recovery time between two different PCI I/O accesses (i.e. no additional recovery wait state will be inserted during byte conversion). Cfg_50h ISA Spaces and Timing Control TOP of Memory boundary (Up to Memory Hole) in 1MB ~ 16MB location through PCI bus when DMA or ISA Master access: 0000b: 1M, 0001b: 2M, 0010b: 3M, 0011b: 4M, <15:12>R/W 1111b 0100b: 5M, 0101b: 6M, 0110b: 7M, 0111b: 8M, 1000b: 9M, 1001b: 10M, 1010b: 11M, 1011b: 12M, 1100b: 13M, 1101b: 14M, 1110b: 15M, 1111b: 16M. 16-bit I/O Access Recovery Time <11:10>R/W 00b 00b:3.5 BCLK, 01b:4.5 BCLK, 10b:5.5 BCLK, 11b: 7.5 BCLK 8-bit I/O Access Recovery Time <9:8> R/W 00b 00b:3.5 BCLK, 01b:5.5 BCLK, 10b:7.5 BCLK, 11b:11.5 BCLK 6-13 IT8888F · ISA Space Register Address Offset: 52h Default Value: FFh Access: Read/Write Size: 8bits This register is used for IT8888F to decide whether to forward DDMA or ISA Master cycle to PCI bus. Cfg_50h ISA Spaces and Timing Control KBC Space (0060/2/4/6) location when DMA or ISA Master access: <23> R/W 1b 0b: @ ISA, Disable forwarding. 1b: @ PCI, then issue PCI master cycle. Memory Space of 000EXXXXh location when DMA or ISA Master access: <22> R/W 1b 0b: @ ISA, Disable forwarding. 1b: @ PCI, then issue PCI master cycle. Memory Space of 000D8000h~000DFFFFh location when DMA or ISA Master access: <21> R/W 1b 0b: @ ISA, Disable forwarding. 1b: @ PCI, then issue PCI master cycle. Memory Space of 000D0000h~000D7FFFh location when DMA or ISA Master access: <20> R/W 1b 0b: @ ISA, Disable forwarding. 1b: @ PCI, then issue PCI master cycle. Memory Space of 000C8000h~000CFFFFh location when DMA or ISA Master access: <19> R/W 1b 0b: @ ISA, Disable forwarding. 1b: @ PCI, then issue PCI master cycle. Memory Space of 000C0000h~000C7FFFh (VGA BIOS) location when DMA or ISA Master access: <18> R/W 1b 0b: @ ISA, Disable forwarding. 1b: @ PCI, then issue PCI master cycle. Memory Space of 000A0000h~000BFFFFh (Video Buffer) location when DMA or ISA Master access: <17> R/W 1b 0b: @ ISA, Disable forwarding. 1b: @ PCI, then issue PCI master cycle. Memory Space of 00080000h~0009FFFFh location when DMA or ISA Master access: <16> R/W 1b 0b: @ ISA, Disable forwarding. 1b: @ PCI, then issue PCI master cycle. 6-14 IT8888F · ROM Decoding Register Address Offset: 53h Default Value: 01h Access: Read/Write Size: 8bits This register is used to generate ROM chip select. Cfg_50h ISA Spaces and Timing Control Enable ROMCS# from Memory space FFFEXXXXh (Top E-seg/4GB). <31 > R/W 0b 0b: Excludes FFFEXXXXh; 1b: Includes FFFEXXXXh Enable ROMCS# from Memory space FFF80000h ~ FFFDFFFFh <30 > R/W 0b (Extended 384K of Top 4GB). 0b: Excludes; 1b: Includes Enable ROMCS# from Memory space FFF00000h ~ FFF7FFFFh (1MB <29 > R/W 0b Extended 512K of Top 4GB). 0b: Excludes; 1b: Includes Enable ROMCS# from Memory space 000EXXXXh (E-seg/1MB) <28> R/W 0b 0b: Excludes 000EXXXXh; 1b: Includes 000EXXXXh Enable ROMCS# from Memory space 000DXXXXh (D-seg/1MB) <27> R/W 0b 0b: Excludes 000DXXXXh; 1b: Includes 000DXXXXh Enable ROMCS# from Memory space 000C8000h ~ 000CFFFFh <26> R/W 0b 0b: Excludes 000C8000h ~ 000CFFFFh 1b: Includes 000C8000h ~ 000CFFFFh Enable ROMCS# from Memory space 000C0000h ~ 000C7FFFh <25> R/W 0b 0b: Excludes 000C0000h ~ 000C7FFFh 1b: Includes 000C0000h ~ 000C7FFFh Flash ROM Write Protect (Mask ROMCS# and/or MEMW#) <24> R/W 1b 0b: Enable Write to ROM; 1b: Write-Protect 6-15 IT8888F 6.3.11 Retry/Discard Timers, Misc. Control Register · Retry Timer Control Register Address Offset: 54h Default Value: 3Fh Access: Read/Write, Write-1-to-Clear Size: 8bits This register is used for PCI Master I/F to count Retry control. Cfg_54h Retry/Discard Timers, Misc. Control Register Enable Retry overflow report to SERR#. <7> R/W 0b 0=Disabled, 1=Enabled. Read 1 as the PCI Master interface can not complete its transaction <6> R/W1C 0b within the time (overflow) defined in Cfg_54h<5:0>. Write 1 to clear. Retry Timer. PCI Master interface repeats retried transactions and if the retry counts exceed the Retry Timer value (x 8 times), then the PCI <5:0> R/W Master interface will give up more retry and set status bit 3Fh (Cfg_54h<6>). 00h=not check retry; 01h=8 times; FFh=255*8 times. · Discard Timer Control Register Address Offset: 55h Defaul t Value: 3Fh Access: Read/Write, Write-1-to-Clear Size: 8bits This register is used for PCI Target I/F to count retried time for Discard control. Cfg_54h Retry/Discard Timers, Misc. Control Register Enable Discard overflow report to SERR#. <15> R/W 0b 0=Disabled, 1=Enabled. Read 1 as the PCI Target interface can not receive the same retried <14> R/W1Ctransaction more than the time (overflow) defined in Cfg_54h<13:8>. 0b Write 1 to clear. Discard Timer. If the PCI Master still doesn ’t repeat the same transaction when timer expired (Value x256 PCI clocks) for the PCI <13:8>R/W Target interface that issued the retry cycle, the PCI Target interface will 3Fh then stop waiting and set status bit (Cfg_54h<14>). 00h=never expire; 01h=256T; FFh=255*256T. 6-16 IT8888F · Misc. Control Register Address Offset: 56h – 57h Default Value: 8C00h Access: Read/Write Size: 16bits This register is used for PCI I/F Arbitration for DDMA/PPDMA and test and CLKRUN# function. Cfg_54h Retry/Discard Timers, Misc. Control Register Enable DDMA-Concurrent option <31> R/W 1b 0: Disabled, Hold PCI bus through all DMA cycles 1: Enabled PCI & DMA / ISA-Master Accesses Concurrent. Enable Dummy PPDREQ# message for patching PC/PCI DMA undefined multiple DMA requests underrun/overrun. 0: Disabled, as PC/PCI DMA protocol not supports DMA devices <30> R/W 0b multiple de-asserted simultaneously. 1: Enabled, IT8888F will issue a dummy PPDREQ# message (empty requests) to update the PPDREQ# decoding in core logic chipset. Enable Dummy FRAME# for some chipset arbitration patch when DDMA / ISA Master access with DDMA-Concurrent mode disabled. <29> R/W 0b 0: Disabled, no Dummy FRAME#. 1: Enabled Dummy FRAME# for DDMA Verify and DDMA/ Master non-PCI access. (Available only when Cfg_54h<31>=0). SA[1:0] Toggling of ISA I/O cycles from the same one PCI I/O (due to multiple bytes). But when accessing the internal DDMA I/O ports, the SA[1:0] will be always increased for DMA device driver to program 32- <28> R/W 0b bit Base_Address or 16-bit Word_Count registers): 0: Address Increased as ISA Memory mapped I/O cycles. 1: Address Fixed as the first ISA I/O for the successive I/O. Force PCI clock always running (whenever CLKRUN# sampled high, then drive low output for 2T): <27> R/W 1b 1: Force PCICLK running. 0: Request PCI clock only for ISA master, DDMA and Interrupt. Enable ISA Bus Refresh Timer 1: Enable Processing Refresh every 15.36 ms. (PCI clock will be kept <26> R/W 1b running by asserting CLKRUN#.) 0: Disable Refresh Timer. <25> R/W Reserved for IC test only. Test SMB interface 0b <24> R/W Reserved for IC test only. Test Refresh Address Counter 0b Enable ISA Bus Master to update Flash ROM (when Cfh_50h<24> = 0) 0: Disabled, only PIO (CPU + PCI Master) and DMA cycle can write <23> R/W into ROM with control timing for WE#-Controlled Write Operation. 0b 1: Enabled, and the control timing is used for Flash ROM CE#- Controlled Write Operation 6-17 IT8888F Cfg_54h Retry/Discard Timers, Misc. Control Register Enable PCI Configure write operation to change the content of Subsystem Device/Vendor ID Register (Cfg_2Ch<31:0>). <22> R/W 0b 0: Disabled, only SMB_ROM Configuring can update it. 1: Enabled. It i s generally provided for optional device BIOS to change subsystem ID for its device. Mask IOCHCK# to report to SERIRQ coding <21> R/W 0b 0: Unmasked, IOCHCK# status will be reflected in SERIRQ coding. 1: Masked, IOCHCK# will not be reflected in SERIRQ c oding. Select the function of pin#138 to be NOGO or CLKRUN#: <20> R/W 0b 0=NOGO, 1=CLKRUN#. Enable ISA IOCHCK# report (Cfg_54h<18>) to SERR#. <19> R/W 0b 0=Disabled, 1=Enabled. Read 1 as the ISA IOCHCK# is asserted. This is the inverse state of <18> R/W1C 0b the latched ISA IOCHCK# signal. Write 1 to clear. Enable checking PCI I/O Cycle Byte Lane Error (Cfg_54h<16>) and <17> R/W report to SERR#. 0b 0=Disabled, 1=Enabled. Read 1 as the PCI I/O Cycle Byte Lane Error occurred. Write 1 to <16> R/W1C 0b clear. 6.3.12 Positively Decoded IO_Space_0 Register Address Offset: 58h – 5Bh Default Value: 00000000h Access: Read/Write Size: 32bits This register is used for the configuration and the Positively Decoded I/O Space 0. Cfg_58h Positively Decoded IO_Space_0 IO_Space_0 Enable: <31> R/W 0b 1b: IT8888F will respond to IO_Space_0; 0b: No-response Decoding Speed for IO_Space_0: <30:29>R/W 00b 00b: Subtractive speed 10b: Medium speed 01b: Slow speed 11b: Fast speed Alias Enable for IO_Space_0: <28> R/W 0b 1b: Don’t care A[15:10]; 0b: Fully decode <27> RO Reserved 0b IO_Space_0 Size: <26:24>R/W 000b 000b: 1 bytes 010b: 4 bytes 100b: 16 bytes 110b: 64 bytes 001b: 2 bytes 011b: 8 bytes 101b: 32 bytes 111b: 128 bytes <23:16>RO Reserved 00h <15:0> R/W Base Address of IO_Space_0: A[15:0], with A[31:16]=0000h 0000h 6-18 IT8888F 6.3.13 Positively Decoded IO_Space_1 Register Address Offset: 5Ch – 5Fh Default Value: 00000000h Access: Read/Write Size: 32bits This register used for configuration and the Positively Decoded I/O Space 1. Cfg_5Ch Positively Decoded IO_Space_1 IO_Space_1 Enable: <31> R/W 0b 1b: IT8888F will respond to IO_Space_1; 0b: No-response Decoding Speed for IO_Space_1: <30:29>R/W 00b 00b: Subtractive speed 10b: Medium speed 01b: Slow speed 11b: Fast speed Alias Enable for IO_Space_1: <28> R/W 0b 1b: Don’t care A[15:10]; 0b: Fully decode <27> RO Reserved 0b IO_Space_1 Size: <26:24>R/W 000b 000b: 1 bytes 010b: 4 bytes 100b: 16 bytes 110b: 64 bytes 001b: 2 bytes 011b: 8 bytes 101b: 32 bytes 111b: 128 bytes <23:16>RO Reserved 00h <15:0> R/W Base Address of IO_Space_1: A[15:0], with A[31:16]=0000h 0000h 6.3.14 Positively Decoded IO_Space_2 Register Address Offset: 60h – 63h Default Value: 00000000h Access: Read/Write Size: 32bits This register is used for configuration and the Positively Decoded I/O Space 2. Cfg_60h Positively Decoded IO_Space_2 IO_Space_2 Enable: <31> R/W 0b 1b: IT8888F will respond to IO_Space_2; 0b: No-response Decoding Speed for IO_Space_2: <30:29>R/W 00b 00b: Subtractive speed 10b: Medium speed 01b: Slow speed 11b: Fast speed Alias Enable for IO_Space_2: <28> R/W 0b 1b: Don’t care A[15:10]; 0b: Fully decode <27> RO Reserved 0b IO_Space_2 Size: <26:24>R/W 000b 000b: 1 bytes 010b: 4 bytes 100b: 16 bytes 110b: 64 bytes 001b: 2 bytes 011b: 8 bytes 101b: 32 bytes 111b: 128 bytes <23:16>RO Reserved 00h <15:0> R/W Base Address of IO_Space_2: A[15:0], with A[31:16]=0000h 0000h 6-19 IT8888F 6.3.15 Positively Decoded IO_Space_3 Register Address Offset: 64h – 67h Default Value: 00000000h Access: Read/Write Size: 32bits This register is used for configuration and the Positively Decoded I/O Space 3. Cfg_64h Positively Decoded IO_Space_3 IO_Space_3 Enable: <31> R/W 0b 1b: IT8888F will respond to IO_Space_3; 0b: No-response Decoding Speed for IO_Space_3: <30:29>R/W 00b 00b: Subtractive speed 10b: Medium speed 01b: Slow speed 11b: Fast speed Alias Enable for IO_Space_3: <28> R/W 0b 1b: Don’t care A[15:10]; 0b: Fully decode <27> RO Reserved 0b IO_Space_3 Size: <26:24>R/W 000b 000b: 1 bytes 010b: 4 bytes 100b: 16 bytes 110b : 64 bytes 001b: 2 bytes 011b: 8 bytes 101b: 32 bytes 111b: 128 bytes <23:16>RO Reserved 00h <15:0> R/W Base Address of IO_Space_3: A[15:0], with A[31:16]=0000h 0000h 6.3.16 Positively Decoded IO_Space_4 Register Address Offset: 68h – 6Bh Default Value: 00000000h Access: Read/Write Size: 32bits This register is used for configuring and the Positively Decoded I/O Space 4. Cfg_68h Positively Decoded IO_Space_4 IO_Space_4 Enable: <31> R/W 0b 1b: IT8888F will respond to IO_Space_4; 0b: No-response Decoding Speed for IO_Space_4: <30:29>R/W 00b 00b: Subtractive speed 10b: Medium speed 01b: Slow speed 11b: Fast speed Alias Enable for IO_Space_4: <28> R/W 0b 1b: Don’t care A[15:10]; 0b: Fully decode <27> RO Reserved 0b IO_Space_4 Size: <26:24>R/W 000b 000b: 1 bytes 010b: 4 bytes 100b: 16 bytes 110b: 64 bytes 001b: 2 bytes 011b: 8 bytes 101b: 32 bytes 111b: 128 bytes <23:16>RO Reserved 00h <15:0> R/W Base Address of IO_Space_4: A[15:0], with A[31:16]=0000h 0000h 6-20 IT8888F 6.3.17 Positively Decoded IO_Space_5 Register Address Offset: 6Ch – 6Fh Default Value: 00000000h Access: Read/Write Size: 32bits This register is used for configuration and the Positively Decoded I/O Space 5. Cfg_6Ch Positively Decoded IO_Space_5 IO_Space_5 Enable: <31> R/W 0b 1b: IT8888F will respond to IO_Space_5; 0b: No-response Decoding Speed for IO_Space_5: <30:29>R/W 00b 00b: Subtractive speed 10b: Medium speed 01b: Slow speed 11b: Fast speed Alias Enable for IO_Space_5: <28> R/W 0b 1b: Don’t care A[15:10]; 0b: Fully decode <27> RO Reserved 0b IO_Space_5 Size: <26:24>R/W 000b 000b: 1 bytes 010b: 4 bytes 100b: 16 bytes 110b: 64 bytes 001b: 2 bytes 011b: 8 bytes 101b: 32 bytes 111b: 128 bytes <23:16>RO Reserved 00h <15:0> R/W Base Address of IO_Space_5: A[15:0], with A[31:16]=0000h 0000h 6-21 IT8888F 6.3.18 Positively Decoded Memory_Space_0 Register Address Offset: 70h – 73h Default Value: 00000000h Access: Read/Write Size: 32bits This register is used for configuration and the Positively Decoded Memory Space 0. Cfg_70h Positively Decoded Memory_Space_0 Memory_Space_0 Enable: <31> R/W 0b 1b: IT8888F will respond to Memory_Space_0; 0b: No-response Decoding Speed for Memory_Space_0: <30:29>R/W 00b 00b: Subtractive speed 10b: Medium speed 01b: Slow speed 11b: Fast speed <28:27>RO Reserved 00b Memory_Space_0 Size: <26:24>R/W 000b 000b: 16KB010b: 64KB100b: 256KB110b: 1MB 001b: 32KB011b: 128KB101b: 512KB111b: 2MB High Page Base Address of Memory_Space_0: A[31:24]. IT8888F will <23:16>R/W relocate the access within Memory_Space_0 to ISA bus, but the 00h A[31:24] will be ignored since ISA has SA[23:0] only. Low Base Address of Memory_Space_0: A[23:8]. <15:0> R/W 0000h Bits <15:6> are R/W as A[23:14]; Bits <5:0> are RO as 6’b000000. 6.3.19 Positively Decoded Memory_Space_1 Register Address Offset: 74h – 77h Default Value: 00000000h Access: Read/Write Size: 32bits This register is used for configuration and the Positively Decoded Memory Space 1. Cfg_74h Positively Decoded Memory_Space_1 Memory_Space_1 Enable: <31> R/W 0b 1b: IT8888F will respond to Memory_Space_1; 0b: No-response Decoding Speed for Memory_Space_1: <30:29>R/W 00b 00b: Subtractive speed 10b: Medium speed 01b: Slow speed 11b: Fast speed <28:27>RO Reserved 00b Memory_Space_1 Size: <26:24>R/W 000b 000b: 16KB010b: 64KB100b: 256KB110b: 1 MB 001b: 32KB011b: 128KB101b: 512KB111b: 2MB High Page Base Address of Memory_Space_1: A[31:24]. IT8888F will <23:16>R/W relocate the access within Memory_Space_1 to ISA bus, but the 00h A[31:24] will be ignored since ISA has SA[23:0] only. Low Base Address of Memory_Space_1: A[23:8]. <15:0> R/W 0000h Bits <15:6> are R/W as A[23:14]; Bits <5:0> are RO as 6’b000000. 6-22 IT8888F 6.3.20 Positively Decoded Memory_Space_2 Register Address Offset: 78h – 7Bh Default Value: 00000000h Access: Read/Write Size: 32bits This register is used for configuration and the Positively Decoded Memory Space 2. Cfg_78h Positively Decoded Memory_Space_2 Memory_Space_2 Enable: <31> R/W 0b 1b: IT8888F will respond to Memory_Space_2; 0b: No-response Decoding Speed for Memory_Space_2: <30:29>R/W 00b 00b: Subtractive speed 10b:Medium speed 01b: Slow speed 11b: Fast speed <28:27>RO Reserved 00b Memory_Space_2 Size: <26:24>R/W 000b 000b: 16KB010b: 64KB100b: 256KB110b: 1MB 001b: 32KB011b: 128KB101b: 512KB111b: 2MB High Page Base Address of Memory_Space_2: A[31:24]. IT8888F will <23:16>R/W relocate the access within Memory_Space_2 to ISA bus, but the 00h A[31:24] will be ignored since ISA has SA[23:0] only. Low Base Address of Memory_Space_2: A[23:8]. <15:0> R/W 0000h Bits <15:6> are R/W as A[23:14]; Bits <5:0> are RO as 6’b000000. 6.3.21 Positively Decoded Memory_Space_3 Register Address Offset: 7Ch – 7Fh Default Value: 00000000h Access: Read/Write Size: 32bits This register is used for configuration and the Positively Decoded Memory Space 3. Cfg_7Ch Positively Decoded Memory_Space_3 Memory_Space_3 Enable: <31> R/W 0b 1b: IT8888F will respond to Memory_Space_3; 0b: No-response Decoding Speed for Memory_Space_3: <30:29>R/W 00b 00b: Subtractive speed 10b: Medium speed 01b: Slow speed 11b: Fast speed <28:27>RO Reserved 00b Memory_Space_3 Size: <26:24>R/W 000b 000b: 16KB010b: 64KB100b: 256KB110b: 1MB 001b: 32KB011b: 128KB101b: 512KB111b: 2MB High Page Base Address of Memory_Space_3: A[31:24]. IT8888F will <23:16>R/W relocate the access within Memory_Space_3 to ISA bus, but the 00h A[31:24] will be ignored since ISA has SA[23:0] only. Low Base Address of Memory_Space_3: A[23:8]. <15:0> R/W 0000h Bits <15:6> are R/W as A[23:14]; Bits <5:0> are RO as 6’b000000. 6-23 IT8888F 6.3.22 Undefined Register Address Offset: those not listed above Default Value: 00000000h Access: Read Only Size: 32bits These registers are reserved as read only. Cfg_XXh (else) All other configuration registers in IT8888F <31:0> RO Reserved 00000000h 6-24 IT8888F 6.4 DDMA Slave Registers Description Only one register Base address is dedicated to each DDMA slave channel, and unique 16-byte register spaces are allocated for each DDMA Slave channel. Below is the DDMA slave register description: DDMA Slave R/W Register Name IT8888F Operation Address Channel_N Base Write to 8237_8 or 8237_16 Base address W Transfer Base Address[7:0] Address + 0h register of Channel_N Channel_N Base Read from 8237_8or 8237_16 Current address R Current Transfer Address[7:0] Address + 0h register of Channel_N Channel_N Base Write to 8237_8 or 8237_16 Base address W Transfer Base Address[15:8] 1 Address + 1h register of Channel_N Channel_N Base Read from 8237_8 or 8237_16 Current address R Current Transfer Address[15:8] Address + 1h register of Channel_N Channel_N Base W Transfer Base Address[23:16] Write to Low Page register of Channel_N Address + 2h Channel_N Base R Current Transfer Address[23:16] Read from Low Page register of Channel_N Address + 2h Channel_N Base W Transfer Base Address[31:24] Write to High Page register of Channel_N Address + 3h Channel_N Base R Current Transfer Address[31:24] Read from High Page register of Channel_N Address + 3h Channel_N Base Write to 8237_8 or 8237_16 Base Word Count W Base Word Count[7:0] Address + 4h register of Channel_N Channel_N Base Read from 8237_8 or 8237_16 Current Word R Current Word Count[7:0] Address + 4h Count register of Channel_N Channel_N Base Write to 8237_8 or 8237_16 Base Word Count W Base Word Count[15:8] Address + 5h register of Channel_N Channel_N Base Read from 8237_8 or 8237_16 Current Word R Current Word Count[15:8] Address + 5h Count register of Channel_N Channel_N Base W Base Word Count[23:16] No Operation Address + 6h Channel_N Base R Current Word Count[23:16] Read 00h Address + 6h Channel_N Base N/A Reserved No Operation Address + 7h 1 DDMA Host should handle Byte-Flip-Flop pointer. 6-25 IT8888F DDMA Slave Registers Description (continued) DDMA Slave R/W Register Name IT8888F Operation Address Channel_N Base W Command Write to 8237_8 or 8237_16 Command register Address + 8h Read from 8237_8or 8237_16 Status register Channel_N Base R Status and convert / duplicate data bits, depending on Address + 8h Channel_N information. Channel_N Base W S/W DMA Request Write to 8237_8 or 8237_16 Request register Address + 9h Channel_N Base R Reserved Read Data Undefined Address + 9h Channel_N Base N/A Reserved Ignore Write; Read Data Undefined Address + Ah Channel_N Base W Mode Write to 8237_8 or 8237_16 Mode register Address + Bh Channel_N Base R Reserved Read Data Undefined Address + Bh Channel_N Base N/A Reserved Ignore Write; Read Data Undefined Address + Ch Channel_N Base Write to 8237_8 or 8237_16 Master Clear W Master Clear Address + Dh register Channel_N Base R Reserved Read Data Undefined Address + Dh Channel_N Base N/A Reserved Ignore Write; Read Data Undefined Address + Eh Write to 8237_8 or 8237_16 Single Channel Channel_N Base Mask register w/ shifting data bit<0> to bit<2> W Multi-Channel Mask Address + Fh and converting Channel_N information to bit<1:0> Read from 8237_8or 8237_16 Single Channel Channel_N Base R Multi-Channel Mask Mask register and convert / duplicate data bits, Address + Fh depending on Channel_N information. 6-26 IT8888F 7. Characteristic Absolute Maximum Ratings* *Comments Applied Voltage (V ) -0.3V to 6.0V Stresses above those listed under “Absolute CC Maximum Ratings ” may cause permanent Input Voltage (V ) -0.3V to V +0.3V damage to the device. These are stress ratings I CC only. Functional operation of this device at these or any other conditions above those Output Voltage (V ) -0.3V to V +0.3V O CC indicated in “Recommended Operating o o Conditions ” is not implied and exposure to Storage Temperature (T ) -40C to 125 C STG absolute maximum rating conditions for extended periods may affect device reliability. Table 7-1. Recommended Operating Conditions Symbol Parameter Min. Typical Max. Units VCC3 Power Supply 3.0 3.3 3.6 V VCC Power Supply 4.75 5.0 5.25 V V Input Voltage 0 VCC / VCC3 V IN o T Operating Temperature 0 25 70 OPT C 7.1 DC Electrical Characteristics Table 7-2 General DC Characteristics Symbol Parameter Conditions Min. TypicalMax. Units I Input Low Current no P/D or P/U-1 1 mA IL I Input High Current no P/D or P/U-1 1 IH mA I Tri-state Leakage Current -10 10 mA OZ I Operating Current from VCC source mA CC from VCC3 source I Operating Current mA CC3 C Input Capacitance 3 rF IN C Output Capacitance 3 to 6 OUT rF C Bi-directional buffer Capacitance 3 to 6 rF BID 7-1 IT8888F Table 7-3 DC Electrical Characteristics o o (T =0C~70C, VCC3=3.0~3.6V, VCC=4.75~5.25V) OPT Symbol Parameter ConditionsMin. Typical Max. Units V Input Low Voltage for 5V cell TTL 0.8 V IL V Input Low Voltage for 3.3V cell CMOS 0.3*VCC3 V IL V Schmitt Input Low Voltage TTL 1.10 V IL V Input High Voltage for 5V cell TTL 2.2 V IH V Input High Voltage for 3.3V cell CMOS 0.7*VCC3 V IH V Schmitt Input High Voltage TTL 1.87 V IH V Output Low Voltage for 5V cell 0.4 V OL V Output Low Voltage for 3.3V cell 0.4 V OL V Output High Voltage for 5V cell3.5 V OH V Output High Voltage for 3.3V cell 2.3 V OH 7.2 AC Characteristics Table 7-4 AC Characteristics of PCI Interface Timing o o 2 (VCC=5.0V ±5%, VCC3=3.3V ±5%, T a=0C~70C, C=50 rF) unit: ns L Symbol Parameter Min.Typical Max. Notes t Valid output delay time VALID_PCI t Input setup time SETUP_PCI Input hold time t HOLD_PCI t Float to Active ON_PCI Active to Float t OFF_PCI 2 All the pads loading are based on 50 rF for Typical simulated values. 7-2 IT8888F Table 7-5 AC Characteristics of ISA Interface Timing (PIO Cycle) (Measured in Design Simulation) unit: 1T=1 PCICLK period ³ 30ns In the following parameters, the LA[23:20] signals are replaced by SA[23:20] to simplify descriptions. Symbol Parameter Typical Notes t BCLK frequency £ 8.25MHz (=PCICLK/4) BCLK t BCLK low period ³ 2T1T=1 PCICLK period L_BCLK BCLK high period 2T t H_BCLK t BALE high period in PIO mode 2T H_BALE SA[23:2] valid to BALE de-asserted t ³ 4T OS_LA_BALE 16-bit memory access ³ 4T t SA[23:2] valid to MEMR#/MEMW# asserted OS_LA_M ³ 6T8-bit memory access t SA[23:2] valid to IOR#/IOW# asserted ³ 6T16-/8-bit I/O access OS_LA_IO 2T 16-bit memory access t SA[1:0], SBHE# valid to MEMR#/MEMW# asserted OS_SA_M 4T 8-bit memory access t SA[1:0], SBHE# valid to IOR#/IOW# asserted 4T 16-/8-bit I/O access OS_SA_IO t SA[23:0], SBHE# hold after command de-asserted all PIO access ³ 2T OH_A 8T 16-bit access w/o NOWS# 18T 8-bit access w/o NOWS# t MEMR#/MEMW# low width W_M ³ 4T16-bit access w/ NOWS# 8-bit access w/ NOWS# ³ 6T 6T 16-bit access IOR#/IOW# low width 18T 8-bit access w/o NOWS# t W_IO 8-bit access w/ NOWS# ³ 6T 0T 16-bit memory write t SD[15:0] valid to MEMW#/IOW# asserted OS_SD 2T else t SD[15:0] hold/float after MEMW#/IOW# de-asserted 2T all PIO write access OH_SD t command hold from IOCHRDY ³ 4Tall PIO write access OH_CMD 7-3 IT8888F Table 7-6 AC Characteristics of ISA Interface Timing (DMA Cycle) (Measured in Design Simulation) unit: 1T=1 PCICLK period ³ 30ns In the following parameters, the LA[23:20] signals are replaced by SA[23:20] to simplify descriptions. Symbol Parameter Typical Notes DDMA Mode 0T DACK[7:5]# t AEN asserted to DACKn# asserted DD_AEN_DACK 4T DACK[3:0]# 0T DACK[7:5]# t DACKn# de-asserted to AEN de-asserted DD_DACK_AEN 4T DACK[3:0]# DACKn# asserted to IOR# asserted 6T t DD_DACK_IOR t DACKn# asserted to IOW# asserted 14T DD_DACK_IOW t DACKn# asserted to MEMR#/MEMW# asserted 14T Memory space on ISA DD_DACK_M t Page Address valid to MEMR#/MEMW# asserted 14T SA[23:17/16] DD_PAGE_M t Base Address valid to MEMR#/MEMW# asserted 10T SA[16/15:0] DD_SA_M Address hold after MEMR#/MEMW# de-asserted 4T SA[23:0] t DD_M_SA t IOR#/MEMR# hold after MEMW#/IOW# de-asserted 2T DD_W_R SD[15:0] setup to IOW# de-asserted 8T Memory space on PCI t DD_OS_SD t SD[15:0] hold/float after MEMW#/IOW# de-asserted 4T DD_OH_SD ³ 26TMemory space on PCI t IOR# width DD_W_IOR 30T Memory space on ISA ³ 16TMemory space on PCI t IOW# width DD_W_IOW 24T Memory space on ISA t MEMR# width 26T Memory space on ISA DD_W_MEMR t MEMW# width 20T Memory space on ISA DD_W_MEMW t TC valid to IOR#/IOW# de-asserted22/28T DD_OS_TC t TC hold after IOR#/IOW# de-asserted 4/6T DD_OH_TC 7-4 IT8888F Table 7 -6 AC Characteristics of ISA Interface Timing (DMA Cycle) (continued) (Measured in Design Simulation) unit: 1T=1 PCICLK period ³ 30ns Symbol Parameter Typical Notes PC/PCI DMA Mode t PPDMA I/O cycle start to IOR# asserted ³ 7T PP_SU_IOR t PPDMA I/O cycle start to IOW# assertedNormal/Type-F DMA ³ 13/9T PP_SU_I OW IOR# de-asserted to PPDMA I/O cycle end 6T t PP_HD_IOR DACKn#/AEN hold until PPDGNT# de-asserted t IOW# de-asserted to PPDMA I/O cycle end 8T PP_HD_IOW SD[15:0] setup to IOW# asserted (falling edge) 8/4TNormal/Type-F DMA t PP_OS_SD t SD[15:0] hold/float after IOW# de-asserted 8T PP_OH_SD t IOR# width 26/6TNormal/Type-F DMA PP_W_IOR t IOW# width 18/6TNormal/Type-F DMA PP_W_IOW t TC valid to IOR # de-asserted 28/8TNormal/Type-F DMA PP_OSR_TC t TC valid to IOW# de-asserted 26/10TNormal/Type-F DMA PP_OSW_TC t TC hold after IOR#/IOW# de-asserted 4/6T PP_OH_TC Table 7-7 AC Characteristics of SMB Interface Timing (refer to Figure 7-23 , Measured in Design Simulation) unit: ms Symbol Parameter Typical Notes t SCLK frequency £ 86.8KHz (= PCICLK/384) SCLK t SCLK low period 5.76 ms (= 192 PCI clocks) L_SCLK t SCLK high period 5.76 ms H_SCLK t Start condition setup time 5.76 ms SU_STA Start condition hold time 5.76 t ms HD_STA t Stop condition setup time 5.76 ms SU_STOP SDATA output setup time 2.38 t ms (= 96 PCI clocks) OS_SDATA t SDATA output hold time 2.38 ms OH_SDATA t SDATA input setup time -2.3 ms IS_SDATA t SDATA input hold time -2.3 ms IH_SDATA 7-5 IT8888F 7.3 Waveforms In the following waveforms, the LA[23:20] signals symbol are replaced by SA[23:20] to simplify drawings. PCICLK 1.5V 1.5V Input 1.5V 1.5V t t SETUP HOLD Output 1.5V Delay t VALID t OFF Output Tri-State t ON Figure 7-1 PCI Bus Interface Timing PCI Configuration Write Cycle PCI Configuration Read Cycle PCICLK AD[31:0] 1011b 1010b C/BE[3:0]# FRAME# IRDY# Medium DEVSEL# speed DEVSEL# TRDY# DSC w/ Data STOP# IDSEL Figure 7-2 PCI Configuration Write / Read Cycle 7-6 IT8888F PCICLK Address Data Phase (Read/Write from/to Target) AD[31:0] Command Byte Enable C/BE[3:0]# FRAME# IRDY# DEVSEL# Fast Medium Slow Subtractive Decode Figure 7-3 DEVSEL# Decoding Speed PCICLK XXXXXXXX XXXXFF3D XXXX913D FFE7913D 4AE7913D AD[31:0] P C C/BE[3:0]# 6 0000b I FRAME# A=00E849B0h SD[15:0] to D[15:0] SD[7:0] to D[15:8] SD[15:0] to D[31:16] SD[7:0] to D[31:24] IRDY# B DEVSEL# U S TRDY# example: Positively Decode w/ Slow DEVSEL# timing STOP# T1 T2~6 T1 T2~6 T1 T2~6 T1 T2~5 T6 Ti Ti BCLK SA[23:2, 2'b00] = E849B0h SA[23:2, 2'b00] = E849B0h SA[23:2] I 00b 01b 10b 11b SA[1:0] S BALE A MEMR# Latch SD Latch SD Latch SD Latch SD B ff3D ff91 ffE7 ff4A SD[15:0] U MEMCS16# S IOCHRDY NOWS# Figure 7-4 PCI Memory Read from ISA Device when Delayed Transaction is disabled 7-7 IT8888F PCICLK AD[31:0] P A=00E849B0h A=00E849B0h A=00E849B0h C 6 0000b 6 0000b 6 0000b C/BE[3:0]# other PCI Master access the other PCI Target other PCI Master access the other PCI Target I FRAME# IRDY# B DEVSEL# U Retry other PCI Master access IT8888F (burst) S TRDY# Begin Delay STOP# Continue DelayWaiting Match cycle and End Delay T1 T2~6 T1 T2~6 T1 T2~6 T1 T2~5 T6 Ti Ti BCLK SA[23:2, 2'b00] = E849B0h SA[23:2, 2'b00] = E849B0h SA[23:2] I 00b 01b 10b 11b SA[1:0] S BALE A MEMR# Latch SD Latch SD Latch SD Latch SD B ff3D ff91 ffE7 ff4A SD[15:0] U MEMCS16# S IOCHRDY NOWS# Figure 7-5 PCI Memory Read from ISA Device when Delayed Transaction is enabled 7-8 IT8888F PCICLK 12345678h AD[31:0] P C 3 1101b C/BE[3:0]# I FRAME# A=0000A295h IRDY# B example: Subtractive Decode DEVSEL# U S TRDY# if Delayed Transaction, Retry here after ISA ownership returns to PIO. STOP# SA-bus hold until PIO finished on PCI site T1 T2 T3 T4~6 Ti Ti BCLK SA[23:2, 2'b00] = 0000XYh SA[23:2, 2'b00] = 00A294h SA[23:2] I 01b SA[1:0] S BALE ISA ownership switches to IT8888F initiated Refresh A MEMR# B IOW# U 5656h SD[15:0] S REFRESH# NOWS# Figure 7-6 IT8888F Initiated Refresh Cycle PCI I/O read from 16 bit ISA PCI I/O read from 8 bit ISA SA = 00CA4Bh BE# = 0111b SA = 003545h BE# = 1011b T1 T2 T3 Ti T1 T2 T3 T4 T5 T6 Ti BCLK SA[23:2] SA[1:0] 01b 11b BALE IOR# SD[15:0] IOCS16# IOCHRDY NOWS# Figure 7-7 PCI I/O Read from ISA device 7-9 IT8888F PCI I/O write data=56789ABCh to 8 bit ISA SA = 000142h BE# = 0011b SA = 000143h when Cfg_54<28> = 0b T1 T2 T3 T4 T5 T6 T1 T2 T3 T4 T5 T6 Ti BCLK SA[23:2, 2'b00]=000140h SA[23:2] 10b 11b SA[1:0] BALE IOW# 5678h 5656h SD[15:0] IOCS16# IOCHRDY NOWS# Figure 7-8 PCI I/O Write to 8-bit ISA Device when Cfg_54<28>=0b PCI I/O write 56781234h to 16 bit ISA SA = 00CA48h BE# = 0000b SA = 00CA48h when Cfg_54<28> = 1b T1 T2 T3 T1 T2 T3 Ti Ti Ti Ti Ti BCLK SA[23:2,2'b00]=00CA48h SA[23:2] SA[1:0] 00b BALE IOW# 1234h 5678h SD[15:0] IOCS16# IOCHRDY NOWS# Figure 7-9 PCI I/O Write to 16-bit ISA Device when Cfg_54<28>=1b 7-10 IT8888F PCI memory read from 8 bit ISA SA = 08314Dh SA = 08314Ch BE# = 1100b T1 T2 T3 T4 T5 T6 T1 T2 T3 Ti Ti BCLK SA[23:2,2'b00]=08314Ch SA[23:2] 00b 01b SA[1:0] BALE MEMR# SD[15:0] MEMCS16# IOCHRDY NOWS# NOWS# Figure 7-10 PCI Memory Read from 8-bit ISA Device PCI memory read from 16 bit ISA SA = 08AE42h SA = 08AE40h BE# = 0000b T1 T2 T3 T4 T5 T6 T1 T2 T3 Ti Ti BCLK SA[23:2] SA[23:2,2'b00]=08AE40h SA[1:0] 00b 10b BALE MEMR# SD[15:0] MEMCS16# IOCHRDY NOWS# Figure 7-11 PCI Memory Read from 16-bit ISA Device 7-11 IT8888F PCI memory write 12345678h to 8 bit ISA SA = 08C94Ah SA = 08C949h BE# = 1001b T1 T2 T3 T4 T5 T6 T1 T2 T3 Ti Ti BCLK SA[23:2,2'b00]=08C948h SA[23:2] 01b SA[1:0] 10b BALE MEMW# 5656h 1234h SD[15:0] MEMCS16# IOCHRDY NOWS# NOWS# Figure 7-12 PCI Memory Write to 8-bit ISA Device PCI memory write 12345678h to 16 SA = 085646h bit ISA SA = 085645h BE# = 0001b T1 T2 T3 T1 T2 Ti Ti Ti Ti Ti Ti BCLK SA[23:2] SA[23:2,2'b00]=085644h SA[1:0] 01b 10b BALE MEMW# SD[15:0] 5656h 1234h MEMCS16# IOCHRDY NOWS# NOWS# Figure 7-13 PCI Memory Write to 16-bit ISA Device 7-12 IT8888F STARTCH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 PCICLK STARTCH0 CH1 PPDREQ# STARTBIT0BIT1BIT2 PPDGNT# DREQ7 DREQ0 DACK7# Figure 7-14 DREQn/DACKn# Coding in PC/PCI DMA Function 7 S 0 1 2 3 4 5 6 PPDREQ# 0 1 2 S PPDGNT# PCICLK A=00491238h AD[31:0] C/BE[3:0]# 6 3 FRAME# IRDY# DEVSEL# TRDY# STOP# DREQ7 DACK7# IOW# IOW# minimum 18 (or 6 if TYPE-FDMA) PCI clocks AEN TC Figure 7-15 DMA Read Operation in PC/PCI DMA (Memory Access to PCI with TC) 7-13 IT8888F Resend when retried PPDREQ# Not scaled, both encoding channel 5 PPDGNT# PCICLK AD[31:0] 6 6 C/BE[3:0]# FRAME# IRDY# DEVSEL# TRDY# Retried STOP# DREQ5 DACK5# MEMR# IOCHRDY AEN MASTER# Figure 7-16 ISA Master Memory Read from PCI in PC/PCI DMA (Retried and Normal Termination) 7-14 IT8888F PCICLK AD[31:0] A=00043700h DCBA9876h 6 1101b C/BE[3:0]# P FRAME# C Output when DMA memory space is on PCI bus. I IRDY# DEVSEL# B TRDY# U STOP# S IREQ# When disabling DDMA-Concurrent, the PCI arbiter is required to process a non-Pre-Empty arbitration. IGNT# DREQ3 DACK3# Channel_4 Cascade Channel_4 Cascade I BCLK S BALE A AEN 14 PCI clocks MEMR# B Output when DMA memory space is on ISA bus. U IOW# S SA[23:0] = 043701h next addr. PIO Address SA[23:0] 9898h SD[15:0] 10 PCI clocks TC Figure 7-17 DMA Read Operation in DDMA (Memory Access to PCI when DDMA-Concurrent is disabled.) 7-15 IT8888F PCICLK DCBA9876h AD[31:0] A=00043704h 6 0011b C/BE[3:0]# P FRAME# C I IRDY# DEVSEL# B TRDY# Latch Data U STOP# Retry other access S Retry other access Output when DMA memory space is on PCI bus. IREQ# IGNT# DREQ5 DACK5# I BCLK S BALE A AEN MEMR# B Output when DMA memory space is on ISA bus. U IOW# S SA[23:0] = 043706h next addr. PIO Address SA[23:0] DCBAh SD[15:0] TC Figure 7-18 DMA Read Operation in DDMA (Memory Access to PCI when both Delayed-Transaction and DDMA-Concurrent are enabled.) 7-16 IT8888F PCICLK 294A294Ah AD[31:0] A=0004371Ch 7 1100b C/BE[3:0]# P FRAME# C I IRDY# DEVSEL# B TRDY# U STOP# Retry other access S Retry other access Output when DMA memory space on PCI bus IREQ# IGNT# DREQ6 DACK6# I BCLK S BALE A AEN MEMW# B Output when DMA memory space is on ISA bus. 8 PCI clocks U IOR# S SA[23:0] = 04371Ch next addr. PIO Address SA[23:0] 294Ah SD[15:0] TC Figure 7-19 DMA Write Operation in DDMA (Memory Access to PCI when both Delayed-Transaction and DDMA-Concurrent are enabled.) 7-17 IT8888F PCICLK 31B731B7h AD[31:0] A=002A9568h 7 1100b C/BE[3:0]# P FRAME# C I IRDY# DEVSEL# B TRDY# U STOP# Retry other access Retry other access S Retry other access Output when ISA Master access space is on PCI bus. IREQ# IGNT# DREQ7 If in Master cycle, DACKn# will be stretched (> 13 PCI clocks after DREQn) to meet ISA Spec. DACK7# BCLK BALE I MEMCS16# S A MEMW# MASTER# B SA[23:0] = 2A9568h IT8888F output Refresh Address by Master SA[23:0] U 31B7h SD[15:0] S IOCHRDY Following IBM PC/AT, IT8888F will not assert AEN during the MASTER Refresh. AEN REFRESH# MEMR# If >= 8 PCI clocks, will conduct another Refresh operation. Figure 7-20 ISA Master Write and Master-Initiated-Refresh Operation in DDMA (Memory Access to PCI when both Delayed-Transaction and DDMA-Concurrent are enabled.) 7-18 IT8888F IT8888F will auto-detect Start frame width Stop Frame Start Frame IRQ0 FrameIRQ1 FrameSMI# FrameIRQ3 Frame (Continuous mode) PCICLK P1 P2 P3 R T H1 H2 H3 R T S R T S R T S R T S R T H4 /6/8 SERIRQ IT8888F will auto-detect Quiet/Continuous modes If encoded interrupt is low, IT8888F output low in Sampling- state, then one clock sustain high in Recovery-state. If encoded interrupt is high, IT8888F will not drive. IRQ4~15 IOCHCK# Stop Frame INTA# FrameINTB# FrameINTC# FrameINTD# Frame Frame Frame (Continuous mode) PCICLK S R T S R T S R T S R T S R T S R T P1 P2 P3 R T SERIRQ IT8888F will auto-detect Slot (frame) number After sampling any IRQ status change, IT8888F will assert SERIRQ low for the first T in Start frame to initiate a SERIRQ sequence in Quiet mode. Stop Frame Start Frame IRQ0~4 Frame IRQ5 Frame (Quiet mode) PCICLK P1 P2 R T SL1 H2 H3 R T S R T S R T S H4 /6/8 SERIRQ ISA_IRQ5 Latch any qualified IRQ low to report Each IRQn/IOCHCK# is qualified with three or more continuous sampled low or high; otherwise, it will be filtered out. Figure 7-21 Serialized IRQ Coding Clock Start or Speed Up Maintaining Clock Clock Stop or Slow Down 1 2 3 4 5 1 2 3 4 5 6 7 8 9 10 11 12 PCICLK Driven by Central Resource CLKRUN# Driven by IT8888F until it detects Driven by IT8888F for two PCICLK clocks Driven by Central Resource two rising edges of PCICLK Figure 7-22 CLKRUN# Operation 7-19 IT8888F S S T T A 2 A 2 Serial E PROM Serial E PROM 2 2 2 2 Serial E PROM Serial E PROM Serial E PROM R Serial E PROM R Device Type Page Block Device Type Page Block T W T R Word Address (begin from 0) Data of Address_0 as Index Data of Address_1 as D[7:0] Data of Address_2 as D[15:8] Identifier Address 0 Identifier Address 0 A A A A A A C C C C C C K K K SDATA K K K SCLK Begin SMB Configuring if the Cfg_50h<4>: SMB_In_Progress Enable/Status bit is set S 2 T Serial E PROM O 2 2 2 Serial E PROM Serial E PROM Serial E PROM Data of Address_5xN as index, 2 P Serial E PROM A But if it is AAh, then not ACK Data of Address_4 as D[31:24] Data of Address_5 as Index Data of Address_6 as D[7:0] C Data of Address_3 as D[23:16] K A A A A A C C C C C SDATA K K K K K SCLK SMB Write to Configuration Register Clear SMB_In_Progress Status bit 2 Figure 7-23 SMB Serial E PROM Configuration Programming t H_SCLK t SCLK SCLK t HD_STA t t OH_SDATA IH_SDATA t SU_STOP t L_SCLK t SU_STA Output Input SDATA t t OS_SDATA IS_SDATA 2 Figure 7-24 SMB Serial E PROM Interface Timing 7-20 IT8888F ~~ ~ 8. Package Information PQFP 160L Outline Dimensions unit: inches/mm HD D 160 121 1 120 40 81 41 80 e b GD GD See Detail F y q Seating Plane L L1 Detail F Symbol Dimensions in inch Dimensions in mm A 0.145 Max. 3.68 Max. A1 0.004 Min. 0.10 Min. A2 0.127 ±0.005 3.23 ±0.13 +0.004 +0.10 B 0.012 0.30 -0.002 -0.05 +0.004 +0.10 c 0.006 0.15 -0.002 -0.05 D 1.102 ±0.005 28.00 ±0.13 E 1.102 ±0.005 28.00 ±0.13 e 0.026 ±0.006 0.65 ±0.15 F 0.998 NOM. 25.35 NOM. GD 1.197 NOM. 30.40 NOM. GE 1.197 NOM. 30.40 NOM. HD 1.228 ±0.012 31.20 ±0.30 HE 1.228 ±0.012 31.20 ±0.30 L 0.031 ±0.008 0.80 ±0.20 L1 0.063 ±0.008 1.60 ±0.20 y 0.004 Max. 0.10 Max. q 0°~ 10 ° 0°~10 ° Note: 1.The dimensions D & E don't include resin fins. 2.Dimensions F, G , G are for PC Board surface mount D E pad pitch design reference only. 3.All dim ensions are based on metric system. 8-1 F D A2 E A1 A HE GE c IT8888F 9. Ordering Information Part No. Package IT8888F 160 PQFP 9-1 IT8888F