® IS61LV51216 ISSI 512K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY SEPTEMBER 2005 FEATURES DESCRIPTION The ISSI IS61LV51216 is a high-speed, 8M-bit static RAM • High-speed access time: organized as 525,288 words by 16 bits. It is fabricated using — 8, 10, and 12 ns ISSI's high-performance CMOS technology. This highly reliable CMOS low power operation process coupled with innovative circuit design techniques, Low stand-by power: yields high-performance and low power consumption devices. — Less than 5 mA (typ.) CMOS stand-by When CE is HIGH (deselected), the device assumes a standby TTL compatible interface levels mode at which the power dissipation can be reduced down with Single 3.3V power supply CMOS input levels. Fully static operation: no clock or refresh required Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable Three state outputs (WE) controls both writing and reading of the memory. A data Data control for upper and lower bytes byte allows Upper Byte (UB) and Lower Byte (LB) access. Industrial temperature available The IS61LV51216 is packaged in the JEDEC standard Lead-free available 44-pin TSOP Type II and 48-pin Mini BGA (9mm x 11mm). FUNCTIONAL BLOCK DIAGRAM 512K x 16 A0-A18 DECODER MEMORY ARRAY VDD GND I/O0-I/O7 I/O Lower Byte COLUMN I/O DATA CIRCUIT I/O8-I/O15 Upper Byte CE OE CONTROL WE CIRCUIT UB LB Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1 Rev. C 09/29/05 ® IS61LV51216 ISSI TRUTH TABLE I/O PIN Mode WE WE WE CE CE CE OE OE OE LB LB LB UB UB UB I/O0-I/O7 I/O8-I/O15 VDD Current WE WE CE CE OE OE LB LB UB UB Not Selected X H X X X High-Z High-Z ISB1, ISB2 Output Disabled H L H X X High-Z High-Z ICC X L X H H High-Z High-Z Read H L L L H DOUT High-Z ICC H L L H L High-Z DOUT H LLLL DOUT DOUT Write L L X L H DIN High-Z ICC L L X H L High-Z DIN LL X L L DIN DIN PIN CONFIGURATIONS PIN DESCRIPTIONS 44-Pin TSOP (Type II) A0-A18 Address Inputs I/O0-I/O15 Data Inputs/Outputs A0 1 44 A17 CE Chip Enable Input A1 2 43 A16 A2 3 42 A15 OE Output Enable Input A3 4 41 OE A4 5 40 UB WE Write Enable Input CE 6 39 LB LB Lower-byte Control (I/O0-I/O7) I/O0 7 38 I/O15 I/O1 8 37 I/O14 UB Upper-byte Control (I/O8-I/O15) I/O2 9 36 I/O13 I/O3 10 35 I/O12 NC No Connection VDD 11 34 GND VDD Power GND 12 33 VDD I/O4 13 32 I/O11 GND Ground I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 A18 A5 18 27 A14 A6 19 26 A13 A7 20 25 A12 A8 21 24 A11 A9 22 23 A10 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 09/29/05 ® IS61LV51216 ISSI PIN CONFIGURATIONS 48-Pin mini BGA (9mmx11mm) PIN DESCRIPTIONS 1 A0-A18 Address Inputs 1 2 3 4 5 6 I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input 2 OE Output Enable Input WE Write Enable Input LB OE A0 A1 A2 N/C A LB Lower-byte Control (I/O0-I/O7) 3 I/O UB A3 A4 CE I/O B 8 0 UB Upper-byte Control (I/O8-I/O15) I/O I/O A5 A6 I/O I/O 9 10 1 2 C NC No Connection GND A7 I/O A17 I/O VDD D 11 3 VDD Power 4 I/O GND VDD I/O GND A16 4 E 12 GND Ground I/O14 I/O A14 A15 I/O5 I/O F 13 6 I/O NC A12 A13 WE I/O G 15 7 5 A18 A8 A10 A9 A11 NC H 6 7 (1) 8 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VTERM Terminal Voltage with Respect to GND –0.5 to VDD+0.5 V 9 VDD VDD Related to GND –0.3 to +4.0 V TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W 10 Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect 11 reliability. 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3 Rev. C 09/29/05 ® IS61LV51216 ISSI OPERATING RANGE Range Ambient Temperature VDD Commercial 0°C to +70°C 3.3V +10%, -5% Industrial –40°C to +85°C 3.3V +10%, -5% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 — V VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA — 0.4 V VIH Input HIGH Voltage 2.2 VDD + 0.3 V (1) VIL Input LOW Voltage –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VDD Com. –1 1µA Ind. –5 5 ILO Output Leakage GND ≤ VOUT ≤ VDD Com. –1 1µA Outputs Disabled Ind. –5 5 Notes: 1. VIL (min.) = –2.0V for pulse width less than 10 ns. (1) POWER SUPPLY CHARACTERISTICS (Over Operating Range) -8 -10 -12 Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit ICC VDD Dynamic Operating VDD = Max., Com. — 110 — 100 — 90 mA Supply Current IOUT = 0 mA, f = fMAX Ind. — 120 — 110 — 100 ISB1 TTL Standby Current VDD = Max., Com. — 30 — 30 — 30 mA (TTL Inputs) VIN = VIH or VIL Ind. — 35 — 35 — 35 CE ≥ VIH, f = 0 ISB2 CMOS Standby VDD = Max., Com. — 20 — 20 — 20 mA Current (CMOS Inputs) CE ≥ VDD – 0.2V, Ind. — 25 — 25 — 25 VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 09/29/05 ® IS61LV51216 ISSI (1) CAPACITANCE Symbol Parameter Conditions Max. Unit 1 CIN Input Capacitance VIN = 0V 6 pF COUT Input/Output Capacitance VOUT = 0V 8 pF Note: 2 1. Tested initially and after any design or process changes that may affect these parameters. 3 AC TEST CONDITIONS 4 Parameter Unit Input Pulse Level 0V to 3.0V Input Rise and Fall Times 3 ns 5 Input and Output Timing 1.5V and Reference Level Output Load See Figures 1 and 2 6 AC TEST LOADS 7 319 Ω 3.3V 8 ZO = 50Ω 50Ω 1.5V OUTPUT OUTPUT 30 pF Including 9 jig and 353 Ω scope 5 pF Including jig and scope 10 Figure 1 Figure 2 11 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5 Rev. C 09/29/05 ® IS61LV51216 ISSI (1) READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -8 -10 -12 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit tRC Read Cycle Time 8 — 10 — 12 — ns tAA Address Access Time — 8 — 10 — 12 ns tOHA Output Hold Time 3 — 3 — 3 — ns tACE CE Access Time — 8 — 10 — 12 ns tDOE OE Access Time — 3.5 — 4 — 5 ns (2) tHZOE OE to High-Z Output — 3 — 4 0 5 ns (2) tLZOE OE to Low-Z Output 0 — 0 — 0 — ns (2 tHZCE CE to High-Z Output 0 3 0 4 0 6 ns (2) tLZCE CE to Low-Z Output 3 — 3 — 3 — ns tBA LB, UB Access Time — 3.5 — 4 — 5 ns (2) tHZB LB, UB to High-Z Output 0 3 0 3 0 4 ns (2) tLZB LB, UB to Low-Z Output 0 — 0 — 0 — ns tPU Power Up Time 0 — 0 — 0 — ns tPD Power Down Time — 8 — 10 — 12 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. AC WAVEFORMS (1,2) READ CYCLE NO. 1 (Address Controlled) (CE = OE = VIL, UB or LB = VIL) t RC ADDRESS t AA t OHA t OHA DATA VALID DOUT PREVIOUS DATA VALID READ1.eps 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 09/29/05 ® IS61LV51216 ISSI (1,3) READ CYCLE NO. 2 1 tRC ADDRESS 2 tAA tOHA OE tHZOE tDOE 3 tLZOE CE tACE tHZCE tLZCE 4 LB, UB tBA tHZB tRC tLZB 5 HIGH-Z DOUT DATA VALID ICC 6 VDD 50% 50% tPU tPD Supply ISB Current UB_CEDR2.eps 7 Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 8 3. Address is valid prior to or coincident with CE LOW transition. 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7 Rev. C 09/29/05 ® IS61LV51216 ISSI (1,3) WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -8 -10 -12 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit tWC Write Cycle Time 8 — 10 — 12 — ns tSCE CE to Write End 6.5 — 8 — 8 — ns tAW Address Setup Time 6.5 — 8 — 8 — ns to Write End tHA Address Hold from Write End 0 — 0 — 0 — ns tSA Address Setup Time 0 — 0 — 0 — ns tPWB LB, UB Valid to End of Write 6.5 — 8 — 8 — ns tPWE1 WE Pulse Width 6.5 — 8 — 8 — ns tPWE2 WE Pulse Width (OE = LOW) 8.0 — 10 — 12 — ns tSD Data Setup to Write End 5 — 6 — 6 — ns tHD Data Hold from Write End 0 — 0 — 0 — ns (2) tHZWE WE LOW to High-Z Output — 3.5 — 5 — 6 ns (2) tLZWE WE HIGH to Low-Z Output 2 — 2 — 2 — ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 09/29/05 ® IS61LV51216 ISSI AC WAVEFORMS (1 ) WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) 1 t WC VALID ADDRESS 2 ADDRESS t SA t SCE t HA CE 3 t AW t PWE1 t PWE2 WE t PBW 4 UB, LB t HZWE t LZWE HIGH-Z DATA UNDEFINED DOUT 5 t SD t HD DATAIN VALID DIN UB_CEWR1.eps 6 Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 7 2. WRITE = (CE) [ (LB) = (UB) ] (WE). 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9 Rev. C 09/29/05 ® IS61LV51216 ISSI AC WAVEFORMS (1,2) WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) t WC ADDRESS VALID ADDRESS t HA OE LOW CE t AW t PWE1 WE t SA t PBW UB, LB t HZWE t LZWE HIGH-Z DATA UNDEFINED DOUT t SD t HD DATAIN VALID DIN UB_CEWR2.eps (1) WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) t WC ADDRESS VALID ADDRESS t HA LOW OE CE LOW t AW t PWE2 WE t SA t PBW UB, LB t HZWE t LZWE HIGH-Z DATA UNDEFINED DOUT t SD t HD DATAIN VALID DIN UB_CEWR3.eps 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 09/29/05 ® IS61LV51216 ISSI AC WAVEFORMS (1,3) WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) 1 t WC t WC ADDRESS ADDRESS 1 ADDRESS 2 2 OE t SA CE LOW 3 t HA t HA t SA WE t PBW t PBW UB, LB WORD 1 WORD 2 4 t HZWE t LZWE HIGH-Z DOUT DATA UNDEFINED t HD t HD t SD t SD 5 DATAIN DATAIN DIN VALID VALID UB_CEWR4.eps Notes: 6 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 11 Rev. C 09/29/05 ® IS61LV51216 ISSI ORDERING INFORMATION: Commercial Range: 0°C to +70°C Speed Order Part No. Package (ns) 8 IS61LV51216-8T TSOP (Type II) IS61LV51216-8TL TSOP (Type II), Lead-free IS61LV51216-8M Mini BGA (9mm x 11mm) 10 IS61LV51216-10T TSOP (Type II) IS61LV51216-10M Mini BGA (9mm x 11mm) 12 IS61LV51216-12T TSOP (Type II) Industrial Range: –40°C to +85°C Speed Order Part No. Package (ns) 8 IS61LV51216-8TI TSOP (Type II) IS61LV51216-8MI Mini BGA (9mm x 11mm) 10 IS61LV51216-10TI TSOP (Type II) IS61LV51216-10TLI TSOP (Type II), Lead-free IS61LV51216-10MI Mini BGA (9mm x 11mm) IS61LV51216-10MLI Mini BGA (9mm x 11mm), Lead-free 12 IS61LV51216-12TI TSOP (Type II) 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 09/29/05 ® PACKAGING INFORMATION ISSI Plastic TSOP Package Code: T (Type II) N N/2+1 Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and E E1 should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 1 N/2 D SEATING PLANE A ZD . L α e b C A1 Plastic TSOP (T - Type II) Millimeters Inches Millimeters Inches Millimeters Inches Symbol Min Max Min Max Min Max Min Max Min Max Min Max Ref. Std. No. Leads (N) 32 44 50 A — 1.20 — 0.047 — 1.20 — 0.047 — 1.20 — 0.047 A1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018 C 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 D 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830 E1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 E 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471 e 1.27 BSC 0.050 BSC 0.80 BSC 0.032 BSC 0.80 BSC 0.031 BSC L 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024 ZD 0.95 REF 0.037 REF 0.81 REF 0.032 REF 0.88 REF 0.035 REF α 0° 5° 0° 5° 0° 5° 0° 5° 0° 5° 0° 5° Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 06/18/03 ® PACKAGING INFORMATION ISSI Mini Ball Grid Array Package Code: M (48-pin) Top View Bottom View φ b (48x) 1 2 3 4 5 6 6 5 4 3 2 1 A A e B B C C D D D D1 E E F F G G H H e E E1 Notes: A2 A 1. Controlling dimensions are in millimeters. SEATING PLANE A1 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 01/15/03 ® PACKAGING INFORMATION ISSI Mini Ball Grid Array Package Code: M (48-pin) mBGA - 6mm x 8mm MILLIMETERS INCHES Sym. Min. Typ. Max. Min. Typ. Max. N0. Leads 48 A — — 1.20 .— — 0.047 A1 0.25 — 0.40 0.010 — 0.016 A2 0.60 — — 0.024 — — D 7.90 8.00 8.10 0.311 0.314 0.319 D1 5.60BSC 0.220BSC E 5.90 6.00 6.10 0.232 0.236 0.240 E1 4.00BSC 0.157BSC e 0.80BSC 0.031BSC b 0.40 0.45 0.50 0.016 0.018 0.020 mBGA - 7.2mm x 8.7mm mBGA - 9mm x 11mm MILLIMETERS INCHES MILLIMETERS INCHES Sym. Min. Typ. Max. Min. Typ. Max. Sym. Min. Typ. Max. Min. Typ. Max. N0. N0. Leads 48 Leads 48 A — — 1.20 — — 0.047 A — — 1.20 — — 0.047 A1 0 .24 — 0.30 0.009 — 0.012 A1 0.24 — 0.30 0.009 — 0.012 A2 0.60 — — 0.024 — — A2 0.60 — — 0.024 — — D 8.60 8.70 8.80 0.339 0.343 0.346 D 10.90 11.00 11.10 0.429 0.433 0.437 D1 5.25BSC 0.207BSC D1 5.25BSC 0.207BSC E 7.10 7.20 7.30 0.280 0.283 0.287 E 8.90 9.00 9.10 0.350 0.354 0.358 E1 3.75BSC 0.148BSC E1 3.75BSC 0.148BSC e 0.75BSC 0.030BSC e 0.75BSC 0.030BSC b 0.30 0.35 0.40 0.012 0.014 0.016 b 0.30 0.35 0.40 0.012 0.014 0.016 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 01/15/03