INTERSIL HI7190IB

HI7190 ® Data Sheet June 27, 2006 FN3612.10 24-Bit, High Precision, Sigma Delta A/D Features Converter • 22-Bit Resolution with No Missing Code The Intersil HI7190 is a monolithic instrumentation, sigma • 0.0007% Integral Non-Linearity (Typ) delta A/D converter which operates from ±5V supplies. Both • 20mV to ±2.5V Full Scale Input Ranges the signal and reference inputs are fully differential for maximum flexibility and performance. An internal • Internal PGIA with Gains of 1 to 128 Programmable Gain Instrumentation Amplifier (PGIA) • Serial Data I/O Interface, SPI Compatible provides input gains from 1 to 128 eliminating the need for external pre-amplifiers. The on-demand converter auto- • Differential Analog and Reference Inputs calibrate function is capable of removing offset and gain • Internal or System Calibration errors existing in external and internal circuitry. The on-board user programmable digital filter provides over 120dB of • 120dB Rejection of 60/50Hz Line Noise 60/50Hz noise rejection and allows fine tuning of resolution • Settling Time of 4 Conversions (Max) for a Step Input and conversion speed over a wide dynamic range. The • Pb-Free Plus Anneal Available (RoHS Compliant) HI7190 and HI7191 are functionally the same device, but the HI7190 has tighter linearity specifications. Applications The HI7190 contains a serial I/O port and is compatible with • Process Control and Measurement most synchronous transfer formats including both the Motorola 6805/11 series SPI and Intel 8051 series SSR • Industrial Weight Scales protocols. A sophisticated set of commands gives the user • Part Counting Scales control over calibration, PGIA gain, device selection, standby • Laboratory Instrumentation mode, and several other features. The On-chip Calibration Registers allow the user to read and write calibration data. • Seismic Monitoring • Magnetic Field Monitoring Pinout HI7190 • Additional Reference Literature 20 LD SOIC, PDIP - Technical Brief, TB348 “HI7190/1 Negative Full Scale TOP VIEW Error vs Conversion Frequency” - Application Note, AN9504 “A Brief Intro to Sigma Delta 1 20 MODE SCLK Conversion” SDO 2 19 SYNC - Technical Brief, TB329 “Intersil Sigma Delta Calibration SDIO 3 18 RESET Technique” CS 4 17 OSC 1 - Application Note, AN9505 “Using the HI7190 Evaluation DRDY 5 16 OSC 2 Kit” DGND 6 15 DV DD - Technical Brief, TB331 “Using the HI7190 Serial AV 7 14 AGND SS Interface” V 8 13 AV DD RLO - Application Note, AN9527 “Interfacing HI7190 to a 9 12 V V RHI INHI Microcontroller” V 10 11 V CM INLO - Application Note, AN9532 “Using HI7190 in a Multiplexed System” - Application Note, AN9601 “Using HI7190 with a Single +5V Supply” CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1 1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2005-2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. HI7190 Ordering Information TEMP. PART PART RANGE PKG. NUMBER MARKING (°C) PACKAGE DWG. # HI7190IP HI7190IP -40 to 85 20 Ld PDIP E20.3 HI7190IPZ HI7190IPZ -40 to 85 20 Ld PDIP* E20.3 (Pb-free) HI7190IB HI7190IB -40 to 85 20 Ld SOIC M20.3 HI7190IBZ HI7190IBZ -40 to 85 20 Ld SOIC M20.3 (Note) (Pb-free) HI7190IBZ-T HI7190IBZ -40 to 85 20 Ld SOIC M20.3 (Note) Tape and Reel (Pb-free) HI7190EVAL Evaluation Kit *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Functional Block Diagram V V RHI RLO AV DD REFERENCE INPUTS TRANSDUCER BURN-OUT CURRENT ∑ − Δ MODULATOR PGIA DIGITAL FILTER V INHI ∑ ∑ V ∫∫ 1 INLO 1-BIT D/A V CM CONTROL AND SERIAL INTERFACE UNIT SERIAL INTERFACE UNIT CONTROL REGISTER CLOCK GENERATOR OSC OSC DRDY RESET SYNC CS MODE S SDIO SDO 1 2 CLK FN3612.10 2 June 27, 2006 HI7190 Typical Application Schematic 10MHz 17 16 OSC OSC 15 1 2 13 +5V DV AV DD +5V DD + + 4.7μF 4.7μF 0.1μF 0.1μF 1 SCLK 12 V INPUT + INHI 3 SDIO 11 DATA I/O V INPUT INLO - 10 2 V CM SDO DATA OUT R 1 19 SYNC SYNC 9 +2.5V 4 V RHI CS REFERENCE CS 8 V RLO 5 DRDY DRDY 7 18 AV -5V SS RESET RESET 4.7μF + 20 MODE 0.1μF AGND DGND 14 6 FN3612.10 3 June 27, 2006 HI7190 Absolute Maximum Ratings Thermal Information Supply Voltage Thermal Resistance (Typical, Note 1) θ (°C/W) JA AV to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V DD PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 AV to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V SS SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 DV to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V DD Maximum Junction Temperature DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Analog Input Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . AV to AV SS DD Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C Digital Input, Output and I/O Pins . . . . . . . . . . . . . . DGND to DV DD Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . . 300°C ESD Tolerance (No Damage) (SOIC - Lead Tips Only) Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100V Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1000V Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40° C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. JA Electrical Specifications AV = +5V, AV = -5V, DV = +5V, V = +2.5V, V = AGND = 0V, V = AGND, DD SS DD RHI RLO CM PGIA Gain = 1, OSC = 10MHz, Bipolar Input Range Selected, f = 10Hz IN N PARAMETER TEST CONDITIONS MIN TYP MAX UNITS SYSTEM PERFORMANCE Integral Non-Linearity, INL End Point Line Method (Notes 3, 5, 6) - ±0.0007 ±0.0015 %FS Differential Non-Linearity (Note 2) No Missing codes to 22-Bits LSB Offset Error, V See Table 1 - - - - OS Offset Error Drift V = V (Notes 3, 8) - 1 - μV/°C INHI INLO Full Scale Error, FSE V - V = +2.5V (Notes 3, 5, 8, 10) - - - - INHI INLO Noise, e See Table 1 - - - - N Common Mode Rejection Ratio, CMRR V = 0V, V = V from -2V to +2V - 70 - dB CM INHI INLO Normal Mode 50Hz Rejection Filter Notch = 10Hz, 25Hz, 50Hz (Note 2) 120 - - dB Normal Mode 60Hz Rejection Filter Notch = 10Hz, 30Hz, 60Hz (Note 2) 120 - - dB Step Response Settling Time - 2 4 Conversions ANALOG INPUTS Input Voltage Range Unipolar Mode (Note 9) 0 - V V REF Input Voltage Range Bipolar Mode (Note 9) - V -V V REF REF Common Mode Input Range (Note 2) AV -AV V SS DD Input Leakage Current, I V = AV (Note 2) - - 1.0 nA IN IN DD Input Capacitance, C -5.0 - pF IN Reference Voltage Range, V 2.5 - 5 V REF (V = V - V ) REF RHI RLO Transducer Burn-Out Current, I - 200 - nA BO CALIBRATION LIMITS Positive Full Scale Calibration Limit - - 1.2(V /Gain) - REF Negative Full Scale Calibration Limit - - 1.2(V /Gain) - REF Offset Calibration Limit - - 1.2(V /Gain) - REF Input Span 0.2(V /Gain) - 2.4(V /Gain) - REF REF DIGITAL INPUTS Input Logic High Voltage, V (Note 11) 2.0 - - V IH Input Logic Low Voltage, V -- 0.8 V IL Input Logic Current, I V = 0V, +5V - 1.0 10 μA I IN FN3612.10 4 June 27, 2006 HI7190 Electrical Specifications AV = +5V, AV = -5V, DV = +5V, V = +2.5V, V = AGND = 0V, V = AGND, DD SS DD RHI RLO CM PGIA Gain = 1, OSC = 10MHz, Bipolar Input Range Selected, f = 10Hz (Continued) IN N PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Input Capacitance, C V = 0V - 5.0 - pF IN IN DIGITAL OUTPUTS Output Logic High Voltage, V I = -100μA (Note 7) 2.4 - - V OH OUT Output Logic Low Voltage, V I = 3mA (Note 7) - - 0.4 V OL OUT Output Three-State Leakage Current, V = 0V, +5V (Note 7) -10 1 10 μA OUT I OZ Digital Output Capacitance, C -10 - pF OUT TIMING CHARACTERISTICS SCLK Minimum Cycle Time, t 200 - - ns SCLK SCLK Minimum Pulse Width, t 50 - - ns SCLKPW CS to SCLK Precharge Time, t 50 - - ns PRE DRDY Minimum High Pulse Width (Notes 2, 7) 500 - - ns Data Setup to SCLK Rising Edge (Write), 50 - - ns t DSU Data Hold from SCLK Rising Edge 0- - ns (Write), t DHLD Data Read Access from Instruction Byte (Note 7) - - 40 ns Write, t ACC Read Bit Valid from SCLK Falling Edge, (Note 7) - - 40 ns t DV Last Data Transfer to Data Ready (Note 7) - 35 - ns Inactive, t DRDY RESET Low Pulse Width (Note 2) 100 - - ns SYNC Low Pulse Width (Note 2) 100 - - ns Oscillator Clock Frequency (Note 2) 0.1 - 10 MHz Output Rise/Fall Time (Note 2) - - 30 ns Input Rise/Fall Time (Note 2) - - 1 μs POWER SUPPLY CHARACTERISTICS IAV -- 1.5 mA DD IAV -- 2.0 mA SS IDV SCLK = 4MHz - - 3.0 mA DD Power Dissipation, Active PD SB = ‘0’ - 15 32.5 mW A Power Dissipation, Standby PD SB = ‘1’ - 5 - mW S PSRR (Note 3) - -70 - dB NOTES: 2. Parameter guaranteed by design or characterization, not production tested. 3. Applies to both bipolar and unipolar input ranges. 4. These errors can be removed by re-calibrating at the desired operating temperature. 5. Applies after system calibration. 6. Fully differential input signal source is used. 7. See Load Test Circuit, Figure 4, R1 = 10kΩ, C = 50pF. L 8. 1 LSB = 298nV at 24 bits for a Full Scale Range of 5V. 9. V = V - V REF RHI RLO. 10. These errors are on the order of the output noise shown in Table 1. 11. All inputs except OSC . The OSC input V is 3.5V minimum. 1 1 IH FN3612.10 5 June 27, 2006 HI7190 Timing Diagrams t SCLK t PRE CS t DSU t t SCLKPW SCLKPW SCLK t DHLD SDIO 1ST BIT 2ND BIT FIGURE 1. DATA WRITE TO HI7190 CS SCLK SDIO 1ST BIT 2ND BIT SDO t ACC t DV FIGURE 2. DATA READ FROM HI7190 t DRDY DRDY CS SCLK SDIO 1 5 6 7 8 FIGURE 3. DATA READ FROM HI7190 FN3612.10 6 June 27, 2006 HI7190 Pin Descriptions 20 LEAD DIP, SOIC PIN NAME DESCRIPTION 1 SCLK Serial Interface Clock. Synchronizes serial data transfers. Data is input on the rising edge and output on the falling edge. 2 SDO Serial Data OUT. Serial data is read from this line when using a 3-wire serial protocol such as the Motorola Serial Peripheral Interface. 3 SDIO Serial Data IN or OUT. This line is bidirectional programmable and interfaces directly to the Intel Standard Serial Interface using a 2-wire serial protocol. 4CS Chip Select Input. Used to select the HI7190 for a serial data transfer cycle. This line can be tied to DGND. 5 DRDY An Active Low Interrupt indicating that a new data word is available for reading. 6 DGND Digital Supply Ground. 7AV Negative Analog Power Supply (-5V). SS 8V External Reference Input. Should be negative referenced to V . RLO RHI 9V External Reference Input. Should be positive referenced to V . RHI RLO 10 V Common Mode Input. Should be set to halfway between AV and AV . CM DD SS 11 V Analog Input LO. Negative input of the PGIA. INLO 12 V Analog Input HI. Positive input of the PGIA. The V input is connected to a current source that can be used to check INHI INHI the condition of an external transducer. This current source is controlled via the Control Register. 13 AV Positive Analog Power Supply (+5V). DD 14 AGND Analog Supply Ground. 15 DV Positive Digital Supply (+5V). DD 16 OSC Used to connect a crystal source between OSC and OSC . Leave open otherwise. 2 1 2 17 OSC Oscillator Clock Input for the device. A crystal connected between OSC and OSC will provide a clock to the device, 1 1 2 or an external oscillator can drive OSC . The oscillator frequency should be 10MHz (Typ). 1 18 RESET Active Low Reset Pin. Used to initialize the HI7190 registers, filter and state machines. 19 SYNC Active Low Sync Input. Used to control the synchronization of a number of HI7190s. A logic ‘0’ initializes the converter. 20 MODE Mode Pin. Used to select between Synchronous Self Clocking (Mode = 1) or Synchronous External Clocking (Mode = 0) for the Serial Port. Load Test Circuit V 1 R 1 DUT C (INCLUDES STRAY L CAPACITANCE) FIGURE 4. ESD Test Circuits R R HUMAN BODY 2 1 R 1 C = 100pF ESD CHARGED DEVICE MODEL R = 10MΩ 1 R = 1GΩ DUT 1 R = 1.5kΩ 2 R = 1Ω R 2 V ± 2 ± V C DUT ESD MACHINE MODEL DIELECTRIC C = 200pF ESD R = 10MΩ 1 R = 0Ω 2 FIGURE 5A. FIGURE 5B. FN3612.10 7 June 27, 2006 HI7190 TABLE 1. NOISE PERFORMANCE WITH INPUTS CONNECTED TO ANALOG GROUND P-P NOISE RMS NOISE P-P NOISE RMS NOISE HERTZ SNR ENOB (μV) (μV) HERTZ SNR ENOB (μV) (μV) GAIN = 16 GAIN = 1 10 120.1 19.7 39.8 6.0 10 132.3 21.7 9.8 1.5 25 114.8 18.8 73.4 11.1 25 129.5 21.2 13.6 2.1 30 113.5 18.6 85.1 12.9 30 127.7 20.9 16.6 2.5 50 111.0 18.1 114.4 17.3 50 126.3 20.7 19.5 3.0 60 109.6 17.9 134.0 20.3 60 125.6 20.6 21.2 3.2 100 105.5 17.2 214.8 32.5 100 122.4 20.0 30.7 4.6 250 95.2 15.5 699.1 105.9 250 107.7 17.6 166.7 25.3 500 89.1 14.5 1417.7 214.8 500 98.1 16.0 505.3 76.6 1000 83.5 13.6 2686.0 407.0 1000 85.7 13.9 2101.8 318.5 2000 62.6 10.1 30110.0 4562.1 2000 68.8 11.1 14661.6 2221.4 GAIN = 32 GAIN = 2 10 113.2 18.5 88.8 13.5 10 129.2 21.2 14.0 2.1 25 109.0 17.8 142.7 21.6 25 125.7 20.6 20.9 3.2 30 108.2 17.7 157.4 23.8 30 124.5 20.4 24.1 3.7 50 104.7 17.1 235.8 35.7 50 123.4 20.2 27.3 4.1 60 105.0 17.1 227.8 34.5 60 122.5 20.1 30.3 4.6 100 102.3 16.7 310.5 47.0 100 118.1 19.3 50.0 7.6 250 93.4 15.2 861.1 130.5 250 106.1 17.3 199.5 30.2 500 87.1 14.2 1782.7 270.1 500 96.9 15.8 580.1 87.9 1000 78.2 12.7 4990.4 756.1 1000 84.4 13.7 2435.6 369.0 2000 57.0 9.2 57311.1 8683.5 2000 67.8 11.0 16469.7 2495.4 GAIN = 64 GAIN = 4 10 106.7 17.4 186.2 28.2 10 125.9 20.6 20.5 3.1 25 102.9 16.8 288.4 43.7 25 123.1 20.1 28.4 4.3 30 101.9 16.6 325.8 49.4 30 121.8 19.9 32.8 5.0 50 98.5 16.1 479.8 72.7 50 119.9 19.6 40.9 6.2 60 98.9 16.1 459.8 69.7 60 119.9 19.6 40.9 6.2 100 96.3 15.7 620.2 94.0 100 116.1 19.0 63.2 9.6 250 85.5 13.9 2133.5 323.3 250 105.7 17.3 209.7 31.8 500 78.1 12.7 5025.0 761.4 500 96.6 15.8 597.8 90.6 1000 66.7 10.8 18693.5 2832.3 1000 84.3 13.7 2469.5 374.2 2000 50.5 8.1 120163.0 18206.5 2000 68.2 11.0 15656.1 2372.1 GAIN = 128 GAIN = 8 10 101.1 16.5 356.5 54.0 10 124.7 20.4 23.4 3.5 25 96.0 15.7 638.3 96.7 25 120.6 19.7 37.8 5.7 30 95.2 15.5 704.8 106.8 30 119.2 19.5 44.3 6.7 50 93.2 15.2 882.2 133.7 50 117.5 19.2 53.8 8.2 60 92.2 15.0 996.7 151.0 60 116.8 19.1 58.6 8.9 100 91.4 14.9 1086.6 164.6 100 112.1 18.3 100.0 15.2 250 79.4 12.9 4346.4 658.5 250 101.4 16.5 345.2 52.3 500 71.8 11.6 10439.2 1581.7 500 95.3 15.5 691.1 104.7 1000 60.1 9.7 39923.0 6048.9 1000 83.1 13.5 2838.6 430.1 2000 44.8 7.1 233238.2 35339.1 2000 68.3 11.1 15494.7 2347.7 FN3612.10 8 June 27, 2006 HI7190 noise and, in this case, the output noise tends to decrease Definitions with increasing gain. Integral Non-Linearity, INL, is the maximum deviation of any digital code from a straight line passing through the Since the output noise comes from two sources, the effective endpoints of the transfer function. The endpoints of the resolution of the device (i.e., the ratio of the input full scale to transfer function are zero scale (a point 0.5 LSB below the the output RMS noise) does not remain constant with first code transition 000...000 and 000...001) and full scale (a increasing gain or with increasing bandwidth. It is possible to point 0.5 LSB above the last code transition 111...110 to do post-filtering (such as brick wall filtering) on the data to 111...111). improve the overall resolution for a given -3dB frequency and also to further reduce the output noise. Differential Non-Linearity, DNL, is the deviation from the actual difference between midpoints and the ideal difference Circuit Description between midpoints (1 LSB) for adjacent codes. If this The HI7190 is a monolithic, sigma delta A/D converter which difference is equal to or more negative than 1 LSB, a code operates from ±5V supplies and is intended for will be missed. measurement of wide dynamic range, low frequency signals. Offset Error, V , is the deviation of the first code transition OS It contains a Programmable Gain Instrumentation Amplifier from the ideal input voltage (V - 0.5 LSB). This error can IN (PGIA), sigma delta ADC, digital filter, bidirectional serial port be calibrated to the order of the noise level shown in Table 1. (compatible with many industry standard protocols), clock oscillator, and an on-chip controller. Full Scale Error, FSE, is the deviation of the last code transition from the ideal input full scale voltage The signal and reference inputs are fully differential for (V -+V /Gain - 1.5 LSB). This error can be calibrated IN REF maximum flexibility and performance. Normally V and RHI to the order of the noise level shown in Table 1. V are tied to +2.5V and AGND respectively. This allows RLO for input ranges of 2.5V and 5V when operating in the Input Span, defines the minimum and maximum input unipolar and bipolar modes respectively (assuming the PGIA voltages the device can handle while still calibrating properly is configured for a gain of 1). The internal PGIA provides for gain. input gains from 1 to 128 and eliminates the need for Noise, e , Table 1 shows the peak-to-peak and RMS noise N external pre-amplifiers. This means the device will convert for typical notch and -3dB frequencies. The device signals ranging from 0V to +20mV and 0V to +2.5V when programming was for bipolar input with a V of +2.5V. This REF operating in the unipolar mode or signals in the range of implies the input range is 5V. The analysis was performed on ±20mV to ±2.5V when operating in the bipolar mode. 100 conversions with the peak-to-peak output noise being The input signal is continuously sampled at the input to the the difference between the maximum and minimum readings HI7190 at a clock rate set by the oscillator frequency and the over a rolling 10 conversion window. The equation to convert selected gain. This signal then passes through the sigma the peak-to-peak noise data to ENOB is: delta modulator (which includes the PGIA) and emerges as a ENOB = Log (V /V ) 2 FS NRMS pulse train whose code density contains the analog signal 3 information. The output of the modulator is fed into the sinc where: V = 5V, V = V /CF and FS NRMS NP-P digital low pass filter. The filter output passes into the CF = 6.6 (Empirical Crest Factor) calibration block where offset and gain errors are removed. The calibrated data is then coded (2’s complement, offset The noise from the part comes from two sources, the binary or binary) before being stored in the Data Output quantization noise from the analog-to-digital conversion Register. The Data Output Register update rate is process and device noise. Device noise (or Wideband determined by the first notch frequency of the digital filter. Noise) is independent of gain and essentially flat across the This first notch frequency is programmed into HI7190 via the frequency spectrum. Quantization noise is ratiometric to Control Register and has a range of 10Hz to 1.953kHz which input full scale (and hence gain) and its frequency response corresponds to -3dB frequencies of 2.62Hz and 512Hz is shaped by the modulator. respectively. Looking at Table 1, as the cutoff frequency increases the Output data coding on the HI7190 is programmable via the output noise increases. This is due to more of the Control Register. When operating in bipolar mode, data quantization noise of the part coming through to the output output can be either 2’s complement or offset binary. In and, hence, the output noise increases with increasing -3dB unipolar mode output is binary. frequencies. For the lower notch settings, the output noise is dominated by the device noise and, hence, altering the gain The DRDY signal is used to alert the user that new output has little effect on the output noise. At higher notch data is available. Converted data is read via the HI7190 frequencies, the quantization noise dominates the output serial I/O port which is compatible with most synchronous transfer formats including both the Motorola 6805/11 series FN3612.10 9 June 27, 2006 HI7190 SPI and Intel 8051 series SSR protocols. Data Integrity is If the device is written to the conversion mode, a new always maintained at the HI7190 output port. This means calibration is NOT performed (A new calibration is that if a data read of conversion N is begun but not finished recommended any time data is written to the Control before the next conversion (conversion N + 1) is complete, Register.). In either case, DRDY goes low when valid data is the DRDY line remains active (low) and the data being read available at the output. is not overwritten. If a single data byte is written to byte 0 of the Control The HI7190 provides many calibration modes that can be Register, the device assumes the gain has NOT been initiated at any time by writing to the Control Register. The changed. It is up to the user to re-calibrate the device if the device can perform system calibration where external gain is changed in this manner. For this reason it is components are included with the HI7190 in the calibration recommended that the entire Control Register be written loop or self-calibration where only the HI7190 itself is in the when changing the gain of the device. This ensures that the calibration loop. The On-chip Calibration Registers are part is re-calibrated (if in a calibration mode) before the read/write registers which allow the user to read calibration DRDY output goes low indicating that valid data is available. coefficients as well as write previously determined The calibration registers can be read via the serial interface calibration coefficients. at any time. However, care must be taken when writing data to the calibration registers. If the HI7190 is internally Circuit Operation updating any calibration register the user can not write to The analog and digital supplies and grounds are separate that calibration register. See the Operational Modes section on the HI7190 to minimize digital noise coupling into the for details on which calibration registers are updated for the analog circuitry. Nominal supply voltages are AV = +5V, DD various modes. DV = +5V, and AV = -5V. If the same supply is used DD SS Since access to the calibration registers is asynchronous to the for AV and DV it is imperative that the supply is DD DD conversion process the user is cautioned that new calibration separately decoupled to the AV and DV pins on the DD DD data may not be used on the very next set of “valid” data after a HI7190. Separate analog and digital ground planes should calibration register write. It is guaranteed that the new data will be maintained on the system board and the grounds should take effect on the second set of output data. Non-calibrated be tied together back at the power supply. data can be obtained from the device by writing 000000 (h) to When the HI7190 is powered up it needs to be reset by the Offset Calibration Register, 800000 (h) to the Positive Full pulling the RESET line low. The reset sets the internal Scale Calibration Register, and 800000 (h) to the Negative Full registers of the HI7190 as shown in Table 2 and puts the part Scale Calibration Register. This sets the offset correction factor in the bipolar mode with a gain of 1 and offset binary coding. to 0 and the positive and negative gain slope factors to 1. The filter notch of the digital filter is set at 30Hz while the I/O If several HI7190s share a system master clock the SYNC is set up for bidirectional I/O (data is read and written on the pin can be used to synchronize their operation. A common SDIO line and SDO is three-stated), descending byte order, SYNC input to multiple devices will synchronize operation and MSB first data format. A self calibration is performed such that all output registers are updated simultaneously. Of before the device begins converting. DRDY goes low when course the SYNC pin would normally be activated only after valid data is available at the output. each HI7190 has been calibrated or has had calibration TABLE 2. REGISTER RESET VALUES coefficients written to it. REGISTER VALUE (HEX) The SYNC pin can also be used to control the HI7190 when Data Output Register XXXX (Undefined) an external multiplexer is used with a single HI7190. The SYNC pin in this application can be used to guarantee a Control Register 28B300 maximum settling time of 3 conversion periods when Offset Calibration Register Self Calibration Value switching channels on the multiplexer. Positive Full Scale Calibration Register Self Calibration Value Analog Section Description Negative Full Scale Calibration Register Self Calibration Value Figure 6 shows a simplified block diagram of the analog modulator front end of a sigma delta A/D Converter. The The configuration of the HI7190 is changed by writing new input signal V comes into a summing junction (the PGIA in setup data to the Control Register. Whenever data is written IN this case) where the previous modulator output is subtracted to byte 2 and/or byte 1 of the Control Register the part from it. The resulting signal is then integrated and the output assumes that a critical setup parameter is being changed of the integrator goes into the comparator. The output of the which means that DRDY goes high and the device is re- comparator is then fed back via a 1-bit DAC to the summing synchronized. If the configuration is changed such that the device is in any one of the calibration modes, a new calibration is performed before normal conversions continue. FN3612.10 10 June 27, 2006 HI7190 junction. The feedback loop forces the average of the fed Programmable Gain Instrumentation Amplifier back signal to be equal to the input signal V . IN The Programmable Gain Instrumentation Amplifier allows the user to directly interface low level sensors and bridges directly PGIA INTEGRATOR COMPARATOR to the HI7190. The PGIA has 4 selectable gain options of 1, 2, + 4, 8 which are implemented by multiple sampling of the input V ∑ ∫ + IN - - signal. Input signals can be gained up further to 16, 32, 64 or 128. These higher gains are implemented in the digital section DAC of the design to maintain a high signal to noise ratio through V RHI the front end amplifiers. The gain is digitally programmable in the Control Register via the serial interface. For optimum V RLO PGIA performance the V pin should be tied to the mid point CM FIGURE 6. SIMPLE MODULATOR BLOCK DIAGRAM of the analog supplies. Differential Reference Input Analog Inputs The reference inputs of the of the HI7190, V and V , The analog input on the HI7190 is a fully differential input RHI RLO provide a differential reference input capability. The nominal with programmable gain capabilities. The input accepts both differential voltage (V = V - V ) is +2.5V and the unipolar and bipolar input signals and gains range from 1 to REF RHI RLO common mode voltage cab be anywhere between AV and 128. The common mode range of this input is from AV to SS SS AV . Larger values of V can be used without AV provided that the absolute value of the analog input DD REF DD degradation in performance with the maximum reference voltage lies within the power supplies. The input impedance voltage being V = +5V. Smaller values of V can also of the HI7190 is dependent upon the modulator input REF REF be used but performance will be degraded since the LSB sampling rate and the sampling rate varies with the selected size is reduced. PGIA gain. Table 3 shows the sampling rates and input impedances for the different gain settings of the HI7190. The full scale range of the HI7190 is defined as: Note that this table is valid only for a 10MHz master clock. If FSR = 2 x V /GAIN BIPOLAR REF the input clock frequency is changed, then the input impedance will change accordingly. The equation used to FSR = V /GAIN UNIPOLAR REF calculate the input impedance is: and V must always be greater than V for proper RHI RLO Z = 1/(C x f ), IN IN S operation of the device. where C is the nominal input capacitance (8pF) and f is in S The reference inputs provide a high impedance dynamic the modulator sampling rate. load similar to the analog inputs and the effective input TABLE 3. EFFECTIVE INPUT IMPEDANCE vs GAIN impedance for the reference inputs can be calculated in the same manner as it is for the analog input impedance. The SAMPLING RATE INPUT IMPEDANCE only difference in the calculation is that C for the reference GAIN (kHz) (MΩ) IN inputs is 10.67pF. Therefore, the input impedance range for 1 78.125 1.6 the reference inputs is from 149kΩ in a gain of 8 or higher 2 156.25 0.8 mode to 833kΩ in the gain of 1 mode. 4 312.5 0.4 V Input CM 8, 16, 32, 64, 128 625 0.2 The voltage at the V input is the voltage that the internal CM analog circuitry is referenced to and should always be tied to Bipolar/Unipolar Input Ranges the midpoint of the AV and AV supplies. This point DD SS provides a common mode input voltage for the internal The input on the HI7190 can accept either unipolar or bipolar operational amplifiers and must be driven from a low noise, input voltages. Bipolar or unipolar options are chosen by low impedance source if it is not tied to analog ground. programming the B/U bit of the Control Register. Failure to do so will result in degraded HI7190 performance. Programming the part for either unipolar or bipolar operation It is recommended that V be tied to analog ground when does not change the input signal conditioning. CM operating off of AV = +5V and AV = -5V supplies. DD SS The inputs are differential, and as a result are referenced to the V also determines the headroom at the upper and lower voltage on the V input. For example, if V is +1.25V CM INLO INLO ends of the power supplies which is limited by the common and the HI7190 is configured for unipolar operation with a gain mode input range where the internal operational amplifiers of 1 and a V of +2.5V, the input voltage range on the V REF INHI remain in the linear, high gain region of operation. The input is +1.25V to +3.75V. If V is +1.25V and the HI7190 is INLO HI7190 is designed to have a range of AV +1.8V < V < configured for bipolar mode with gain of 1 and a V of +2.5V, SS CM REF the analog input range on the V input is -1.25V to +3.75V. INHI FN3612.10 11 June 27, 2006 HI7190 AV - 1.8V. Exceeding this range on the V pin will the conversion. It can not, however, remove noise present DD CM compromise the device performance. on the analog signal prior to the ADC (which an analog filter can). Transducer Burn-Out Current Source One problem with the modulator/digital filter combination is The V input of the HI7190 contains a 500nA (Typ) current INHI that excursions outside the full scale range of the device source which can be turned on/off via the Control Register. could cause the modulator and digital filter to saturate. This This current source can be used in checking whether a device has headroom built in to the modulator and digital transducer has burnt-out or become open before attempting filter which tolerates signal deviations up to 33% outside of to take measurements on that channel. When the current the full scale range of the device. If noise spikes can drive source is turned on an additional offset will be created the input signal outside of this extended range, it is indicating the presence of a transducer. The current source is recommended that an input analog filter is used or the controlled by the BO bit (Bit 4) in the Control Register and is overall input signal level is reduced. disabled on power up. See Figure 7 for an applications circuit. Low Pass Decimation Filter HI7190 3 The digital low-pass filter is a Hogenauer (sinc ) decimating AV DD filter. This filter was chosen because it is a cost effective low pass decimating filter that minimizes the need for internal RATIOMETRIC CURRENT multipliers and extensive storage and is most effective when CONFIGURATION SOURCE used with high sampling or oversampling rates. Figure 9 LOAD CELL shows the frequency characteristics of the filter where f is C V RHI the -3dB frequency of the input signal and f is the N V RLO programmed notch frequency. The analog modulator sends a one bit data stream to the filter at a rate of that is V INHI determined by: f = f /128 MODULATOR OSC f = 78.125kHz for f = 10MHz. V INLO MODULATOR OSC The filter then converts the serial modulator data into 40-bit AV SS words for processing by the Hogenauer filter. The data is decimated in the filter at a rate determined by the CODE FIGURE 7. BURN-OUT CURRENT SOURCE CIRCUIT word FP10-FP0 (programed by the user into the Control Register) and the external clock rate. The equation is: Digital Section Description f = f /(512 x CODE). NOTCH OSC A block diagram of the digital section of the HI7190 is shown The Control Register has 11 bits that select the filter cutoff in Figure 8. This section includes a low pass decimation frequency and the first notch of the filter. The output data filter, conversion controller, calibration logic, serial interface, update rate is equal to the notch frequency. The notch and clock generator. frequency sets the Nyquist sampling rate of the device while the -3dB point of the filter determines the frequency MODULATOR CLOCK OSC 2 CLOCK spectrum of interest (f ). The FP bits have a usable range of S GENERATOR OSC 1 10 through 2047 where 10 yields a 1.953kHz Nyquist rate. The Hogenauer filter contains alias components that reflect SDO CALIBRATION around the notch frequency. If the spectrum of the frequency SERIAL I/O DIGITAL AND CONTROL SDIO FILTER of interest reaches the alias component, the data has been SCLK aliased and therefore undersampled. CS DRDY Filter Characteristics Please note: We have recently discovered a performance anomaly with the HI7190. The problem SYNC RESET occurs when the digital code for the notch filter is programmed within certain frequencies. We believe the FIGURE 8. DIGITAL SECTION BLOCK DIAGRAM error is caused by the calibration logic and the digital notch code NOT the absolute frequency. The error is Digital Filtering seen when the user applies mid-scale (0V input, Bipolar One advantage of digital filtering is that it occurs after the mode). With this input, the expected digital output conversion process and can remove noise introduced during FN3612.10 12 June 27, 2006 MODULATOR OUTPUT HI7190 should be mid-scale (800000 ). Instead, there is a small clock frequency and gain, determines the allotted time for the h probability, of an erroneous negative full scale (000000 ) input capacitor to charge. The addition of external components h output. Refer to Technical Brief TB348 for complete may cause the charge time of the capacitor to increase beyond details. the allotted time. The result of the input not settling to the proper value is a system gain error which can be eliminated by system The FP10 to FP0 bits programmed into the Control Register calibration of the HI7190. determine the cutoff (or notch) frequency of the digital filter. The allowable code range is 00A . This corresponds to a Clocking/Oscillators H maximum and minimum cutoff frequency of 1.953kHz and The master clock into the HI7190 can be supplied by either a 10Hz, respectively when operating at a clock frequency of crystal connected between the OSC and OSC pins as 1 2 10MHz. If a 1MHz clock is used then the maximum and shown in Figure 10A or a CMOS compatible clock signal minimum cutoff frequencies become 195.3kHz and 1Hz, connected to the OSC pin as shown in Figure 10B. The 1 3 respectively. A plot of the (sinx/x) digital filter characteristics input sampling frequency, modulator sampling frequency, is shown in Figure 9. This filter provides greater than 120dB filter -3dB frequency, output update rate, and calibration time of 50Hz or 60Hz rejection. Changing the clock frequency or are all directly related to the master clock frequency, f . OSC the programming of the FP bits does not change the shape For example, if a 1MHz clock is used instead of a 10MHz of the filter characteristics, it merely shifts the notch clock, what is normally a 10Hz conversion rate becomes a frequency. This low pass digital filter at the output of the 1Hz conversion rate. Lowering the clock frequency will also converter has an accompanying settling time for step inputs lower the amount of current drawn from the power supplies. just as a low pass analog filter does. New data takes Please note that the HI7190 specifications are written for a between 3 and 4 conversion periods to settle and update on 10MHz clock only. the serial port with a conversion period t being equal to CONV 1/f . N 10MHz 17 16 0 ALIAS BAND OSC OSC 1 2 f ±f N C HI7190 -20 -40 FIGURE 10A. -60 10MHz NO -80 CONNECTION -100 17 16 -120 OSC OSC 1 2 HI7190 f f 2f 3f 4f C N N N N FREQUENCY (Hz) FIGURE 10B. FIGURE 9. LOW PASS FILTER FREQUENCY CHARACTERISTICS FIGURE 10. OSCILLATOR CONFIGURATIONS Input Filtering The digital filter does not provide rejection at integer Operational Modes multiples of the modulator sampling frequency. This implies The HI7190 contains several operational modes including that there are frequency bands where noise passes to the calibration modes for cancelling offset and gain errors of output without attenuation. For most cases this is not a both internal and external circuitry. A calibration routine problem because the high oversampling rate and noise should be initiated whenever there is a change in the shaping characteristics of the modulator cause this noise to ambient operating temperature or supply voltage. Calibration become a small portion of the broadband noise which is should also be initiated if there is a change in the gain, filter filtered. However, if an anti-alias filter is necessary a single notch, bipolar, or unipolar input range. Non-calibrated data pole RC filter is usually sufficient. can be obtained from the device by writing 000000 to the If an input filter is used the user must be careful that the source Offset Calibration Register, 800000 (h) to the Positive Full impedance of the filter is low enough not to cause gain errors in Scale Calibration Register, and 800000 (h) to the Negative the system. The DC input impedance at the inputs is > 1GΩ but Full Scale Calibration Register. This sets the offset it is a dynamic load that changes with clock frequency and correction factor to 0 and both the positive and negative gain selected gain. The input sample rate, also dependent upon slope factors to 1. FN3612.10 13 June 27, 2006 AMPLITUDE (dB) HI7190 The HI7190 offers several different modes of Self-Calibration HI7190 then takes 3 conversion cycles to sample the data and System Calibration. For calibration to occur, the on-chip and update the Positive Full Scale Calibration Register. Next microcontroller must convert the modulator output for three the polarity of the reference voltage across the modulator different input conditions - “zero-scale,” “positive full scale,” input terminals is reversed and after 3 conversion cycles the and “negative full scale”. With these readings, the HI7190 Negative Full Scale Calibration Register is updated. The can null any offset errors and calculate the gain slope factor values stored in the Positive and Negative Full Scale for the transfer function of the converter. It is imperative that Calibration Registers correct for any internal gain errors in the zero-scale calibration be performed before either of the the A/D transfer function. After 3 more conversion cycles the gain calibrations. However, the order of the gain calibrations DRDY line will activate signaling that the calibration is is not important. complete and valid data is present in the Data Output Register. The calibration modes are user selectable in the Control Register by using the MD bits (MD2-MD0) as shown in System Offset Calibration Mode Table 4. DRDY will go low indicating that the calibration is The System Offset Calibration Mode is a single step process complete and there is valid data at the output. that allows the user to lump offset errors of external circuitry and the internal errors of the HI7190 together and null them TABLE 4. HI7190 OPERATIONAL MODES out. This mode will convert the external differential signal MD2 MD1 MD0 OPERATIONAL MODE applied to the V inputs and then store that value in the IN Offset Calibration Register. The user must apply the zero 0 0 0 Conversion point or offset voltage to the HI7190 analog inputs and allow 0 0 1 Self Calibration (Gain of 1 only) the signal to settle before selecting this mode. After 4 0 1 0 System Offset Calibration conversion periods the DRDY line will activate signaling that the calibration is complete and valid data is present in the 0 1 1 System Positive Full Scale Calibration Data Output Register. 1 0 0 System Negative Full Scale Calibration System Positive Full Scale Calibration Mode 1 0 1 System Offset/Internal Gain Calibration (Gain of 1 only) The System Positive Full Scale Calibration Mode is a single step process that allows the user to lump gain errors of 1 1 0 System Gain Calibration external circuitry and the internal errors of the HI7190 111 Reserved together and null them out. This mode will convert the external differential signal applied to the V inputs and IN Conversion Mode stores the converted value in the Positive Full Scale For Conversion Mode operation the HI7190 converts the Calibration Register. The user must apply the +Full Scale differential voltage between V and V . From INHI INLO voltage to the HI7190 analog inputs and allow the signal to switching into this mode it takes 3 conversion periods (3 x settle before selecting this mode. After 4 conversion periods 1/f ) for DRDY to go low and new data to be valid. No N the DRDY line will activate signaling the calibration is calibration coefficients are generated when operating in complete and valid data is present in the Data Output Conversion Mode as data is calibrated using the existing Register. calibration coefficients. System Negative Full Scale Calibration Mode Self-Calibration Mode The System Negative Full Scale Calibration Mode is a Please note: Self-calibration is only valid when operating in a single-step process that allows the user to lump gain errors gain of one. In addition, the offset and gain errors are not of external circuitry and the internal errors of the HI7190 reduced as with the full system calibration. together and null them out. This mode will convert the The Self-Calibration Mode is a three step process that external differential signal applied to the V inputs and IN updates the Offset Calibration Register, the Positive Full stores the converted value in the Negative Full Scale Scale Calibration Register, and the Negative Full Scale Calibration Register. The user must apply the -Full Scale Calibration Register. In this mode an internal offset voltage to the HI7190 analog inputs and allow the signal to calibration is done by disconnecting the external inputs and settle before selecting this mode. After 4 conversion periods shorting the inputs of the PGIA together. After 3 conversion the DRDY line will activate signaling the calibration is periods the Offset Calibration Register is updated with the complete and valid data is present in the Data Output value that corrects any internal offset errors. Register. After the offset calibration is completed, the Positive and Negative Full Scale Calibration Registers are updated. The inputs V and V are disconnected and the external INHI INLO reference is applied across the modulator inputs. The FN3612.10 14 June 27, 2006 HI7190 /GAIN, the offset must be less than 1 x System Offset/Internal Gain Calibration Mode value of 0.2 x V REF V /GAIN. In bipolar mode the span is equidistant around Please note: System Offset/Internal Gain is only valid when REF the voltage used for the zero scale point. For this mode the operating in a gain of one. In addition, the offset and gain errors offset plus half the span cannot exceed 1.2 x V /GAIN. If are not reduced as with the full system calibration. REF the span is at ±0.2 x V /GAIN, then the offset can not be REF The System Offset/Internal Gain Calibration Mode is a single greater than ±2 x V /GAIN. REF step process that updates the Offset Calibration Register, Serial Interface the Positive Full Scale Calibration Register, and the Negative Full Scale Calibration Register. First the external The HI7190 has a flexible, synchronous serial communication differential signal applied to the V inputs is converted and port to allow easy interfacing to many industry standard IN that value is stored in the Offset Calibration Register. The microcontrollers and microprocessors. The serial I/O is user must apply the zero point or offset voltage to the compatible with most synchronous transfer formats, including HI7190 analog inputs and allow the signal to settle before both the Motorola 6805/11 SPI and Intel 8051 SSR protocols. selecting this mode. The Serial Interface is a flexible 2-wire or 3-wire hardware interface where the HI7190 can be configured to read and After this is completed the Positive and Negative Full Scale write on a single bidirectional line (SDIO) or configured for Calibration Registers are updated. The inputs V and V INHI INLO writing on SDIO and reading on the SDO line. are disconnected and the external reference is switched in. The HI7190 then takes 3 conversion cycles to sample the data and The interface is byte organized with each register byte update the Positive Full Scale Calibration Register. Next the having a specific address and single or multiple byte polarity of the reference voltage across the V and V transfers are supported. In addition, the interface allows INHI INLO terminals is reversed and after 3 conversion cycles the flexibility as to the byte and bit access order. That is, the user Negative Full Calibration Register is updated. The values can specify MSB/LSB first bit positioning and can access stored in the Positive and Negative Full Scale Calibration bytes in ascending/descending order from any byte position. Registers correct for any internal gain errors in the A/D transfer The serial interface allows the user to communicate with 5 function. After 3 more conversion cycles, the DRDY line will registers that control the operation of the device. activate signaling that the calibration is complete and valid data is present in the Data Output Register. Data Output Register - a 24-bit, read only register containing the conversion results. System Gain Calibration Mode Control Register - a 24-bit, read/write register containing The Gain Calibration Mode is a single step process that the setup and operating modes of the device. updates the Positive and Negative Full Scale Calibration Registers. This mode will convert the external differential Offset Calibration Register - a 24-bit, read/write register signal applied to the V inputs and then store that value in IN used for calibrating the zero point of the converter or system. the Negative Full Scale Calibration Register. Then the Positive Full Scale Calibration Register - a 24-bit, polarity of the input is reversed internally and another read/write register used for calibrating the Positive Full Scale conversion is performed. This conversion result is written to point of the converter or system. the Positive Full Scale Calibration Register. The user must apply the +Full Scale voltage to the HI7190 analog inputs Negative Full Scale Calibration Register - a 24-bit, and allow the signal to settle before selecting this mode. read/write register used for calibrating the Negative Full After 1 more conversion period the DRDY line will activate Scale point of the converter or system. signaling the calibration is complete and valid data is present Two clock modes are supported. The HI7190 can accept the in the data output register. serial interface clock (SCLK) as an input from the system or Reserved generate the SCLK signal as an output. If the MODE pin is This mode is not used in the HI7190 and should not be logic low the HI7190 is in external clocking mode and the selected. There is no internal detection logic to keep this SCLK pin is configured as an input. In this mode the user condition from being selected and care should be taken not supplies the serial interface clock and all interface timing to assert this bit combination. specifications are synchronous to this input. If the MODE pin is logic high the HI7190 is in self-clocking mode and the Offset and Span Limits SCLK pin is configured as an output. In self-clocking mode, There are limits to the amount of offset and gain which can SCLK runs at F = OSC /8 and stalls high at byte SCLK 1 be adjusted out for the HI7190. For both bipolar and unipolar boundaries. SCLK does NOT have the capability to stall low modes the minimum and maximum input spans are in this mode. All interface timing specifications are 0.2 x V /GAIN and 1.2 x V /GAIN respectively. REF REF synchronous to the SCLK output. In the unipolar mode the offset plus the span cannot exceed Normal operation in self-clocking mode is as follows (See the 1.2 x V /GAIN limit. So, if the span is at its minimum REF Figure 12): CS is sampled low on falling OSC edges. The 1 FN3612.10 15 June 27, 2006 HI7190 first SCLK transition output is delayed 29 OSC cycles from case of CS inactive during the clock stall time it takes 1 OSC 1 1 the next rising OSC . SCLK transitions eight times and then cycle plus prop delay (Max) for the outputs to be disabled. 1 stalls high for 28 OSC cycles. After this stall period is 1 I/O Port Pin Descriptions completed SCLK will again transition eight times and stall The serial I/O port is a bidirectional port which is used to high. This sequence will repeat continuously while CS is read the data register and read or write the control register active. and calibration registers. The port contains two data lines, a The extra OSC cycle required when coming out of the CS 1 synchronous clock, and a status flag. Figure 11 shows a inactive state is a one clock cycle latency required to diagram of the serial interface lines. properly sample the CS input. Note that the normal stall at byte boundaries is 28 OSC cycles thus giving a SCLK rising DATA OUT SDO 1 to rising edge stall period of 32 OSC cycles. BIDIRECTIONAL DATA SDIO 1 PORT CLOCK SCLK HI7190 The affects of CS on the I/O are different for self-clocking CHIP SELECT CS mode (MODE = 1) than for external mode (MODE = 0). For DEVICE STATUS DRDY external clocking mode CS inactive disables the I/O state CLOCK MODE MODE machine, effectively freezing the state of the I/O cycle. That FIGURE 11. HI7190 SERIAL INTERFACE is, an I/O cycle can be interrupted using chip select and the HI7190 will continue with that I/O cycle when re-enabled via SDO - Serial Data out. Data is read from this line using those CS. SCLK can continue toggling while CS is inactive. If CS protocols with separate lines for transmitting and receiving goes inactive during an I/O cycle, it is up to the user to data. An example of such a standard is the Motorola Serial ensure that the state of SCLK is identical when reactivating Peripheral Interface (SPI) using the 68HC05 and 68HC11 CS as to what it was when CS went inactive. For read family of microcontrollers, or other similar processors. In the operations in external clocking mode, the output will go case of using bidirectional data transfer on SDIO, SDO does three-state immediately upon deactivation of CS. not output data and is set in a high impedance state. For self-clocking mode (MODE = 1), the affects of CS are SDIO - Serial Data in or out. Data is always written to the different. If CS transitions high (inactive) during the period device on this line. However, this line can be used as a when data is being transferred (any non stall time) the HI7190 bidirectional data line. This is done by properly setting up the will complete the data transfer to the byte boundary. That is, Control Register. Bidirectional data transfer on this line can once SCLK begins the eight transition sequence, it will always be used with Intel standard serial interfaces (SSR, Mode 0) complete the eight cycles. If CS remains inactive after the byte in MCS51 and MCS96 family of microcontrollers, or other has been transferred it will be sampled and SCLK will remain similar processors. stalled high indefinitely. If CS has returned to active low before SCLK - Serial clock. The serial clock pin is used to the data byte transfer period is completed the HI7190 acts as synchronize data to and from the HI7190 and to run the port if CS was active during the entire transfer period. state machines. In Synchronous External Clock Mode, SCLK It is important to realize that the user can interrupt a data is configured as an input, is supplied by the user, and can transfer on byte boundaries. That is, if the Instruction run up to a 5MHz rate. In Synchronous Self Clocking Mode, Register calls for a 3 byte transfer and CS is inactive after SCLK is configured as an output and runs at OSC /8. 1 only one byte has been transferred, the HI7190, when CS - Chip select. This signal is an active low input that allows reactivated, will continue with the remaining two bytes before more than one device on the same serial communication lines. looking for the next Instruction Register write cycle. The SDO and SDIO will go to a high impedance state when this Note that the outputs will NOT go three-state immediately upon signal is high. If driven high during any communication cycle, CS inactive for read operations in self-clocking mode. In the that cycle will be suspended until CS reactivation. Chip select case of CS going inactive during a read cycle the outputs can be tied low in systems that maintain control of SCLK. remain driving until after the last data bit is transferred. In the 29 33 37 41 89 45 121 125 OSC 1 CS SCLK FIGURE 12. SCLK OUTPUT IN SELF-CLOCKING MODE FN3612.10 16 June 27, 2006 HI7190 DRDY - Data Ready. This is an output status flag from the The second combination is to set both the BD and MSB bits device to signal that the Data Output Register has been to 1. This sets up the interface for ascending byte order and updated with the new conversion result. DRDY is useful as an LSB first format. When this combination is used the user edge or level sensitive interrupt signal to a microprocessor or should always write the Instruction Register such that the microcontroller. DRDY low indicates that new data is available starting byte is the least significant byte address. For at the Data Output Register. DRDY will return high upon example, read three bytes of DR starting with the least completion of a complete Data Output Register read cycle. significant byte. The first byte read will be the least significant in LSB to MSB format. The next byte will be the MODE - Mode. This input is used to select between next greater significant (recall ascending byte order) again in Synchronous Self Clocking Mode (‘1’) or the Synchronous LSB to MSB order. The last byte will be the next greater External Clocking Mode (‘0’). When this pin is tied to V the DD significant byte in LSB to MSB order. The entire word was serial port is configured in the Synchronous Self Clocking read MSB to LSB format. mode where the synchronous shift clock (SCLK) for the serial port is generated by the HI7190 and has a frequency of After completion of each communication cycle, The HI7190 OSC /8. When the pin is tied to DGND the serial port is interface enters a standby mode while waiting to receive a 1 configured for the Synchronous External Clocking Mode new instruction byte. where the synchronous shift clock for the serial port is generated by an external device up to a maximum frequency CS of 5MHz. DATA DATA DATA INSTRUCTION BYTE BYTE 1 BYTE 2 BYTE 3 Programming the Serial Interface SDIO It is useful to think of the HI7190 interface in terms of INSTRUCTION communication cycles. Each communication cycle happens DATA TRANSFER CYCLE in 2 phases. The first phase of every communication cycle is the writing of an instruction byte. The second phase is FIGURE 13A. 2-WIRE, 3-BYTE READ OR WRITE TRANSFER the data transfer as described by the instruction byte. It is important to note that phase 2 of the communication cycle can be a single byte or a multi-byte transfer of data. For example, the 3-byte Data Output Register can be read CS using one multi-byte communication cycle rather than three single-byte communication cycles. It is up to the user to INSTRUCTION BYTE maintain synchronism with respect to data transfers. If the SDIO system processor “gets lost” the only way to recover is to DATA DATA DATA reset the HI7190. Figures 13A and 13B show both a 2-wire INSTRUCTION BYTE 1 BYTE 2 BYTE 3 CYCLE and a 3-wire data transfer. SDO Several formats are available for reading from and writing to DATA TRANSFER the HI7190 registers in both the 2-wire and 3-wire protocols. A portion of these formats is controlled by the CR<2:1> (BD FIGURE 13B. 3-WIRE, 3-BYTE READ TRANSFER and MSB) bits which control the byte direction and bit order Instruction Byte Phase of a data transfer respectively. These two bits can be written in any combination but only the two most useful will be The instruction byte phase initiates a data transfer discussed here. sequence. The processor writes an 8-bit byte (Instruction Byte) to the Instruction Register. The instruction byte informs The first combination is to reset both the BD and MSB bits the HI7190 about the Data transfer phase activities and (BD = 0, MSB = 0). This sets up the interface for descending includes the following information: byte order and MSB first format. When this combination is used the user should always write the Instruction Register • Read or Write cycle such that the starting byte is the most significant byte • Number of Bytes to be transferred address. For example, read three bytes of DR starting with • Which register and starting byte to be accessed the most significant byte. The first byte read will be the most significant in MSB to LSB format. The next byte will be the Data Transfer Phase next least significant (recall descending byte order) again in In the data transfer phase, data transfer takes place as set MSB to LSB order. The last byte will be the next lesser by the Instruction Register contents. See Write Operation significant byte in MSB to LSB order. The entire word was and Read Operation sections for detailed descriptions. read MSB to LSB format. FN3612.10 17 June 27, 2006 HI7190 TABLE 6. INTERNAL DATA ACCESS DECODE STARTING Instruction Register BYTE (Continued) The Instruction Register is an 8-bit register which is used FSC A3A2A1A0 DESCRIPTION during a communications cycle for setting up read/write operations. 1 1100 Negative Full Scale Cal Register, Byte 0 INSTRUCTION REGISTER 1 1101 Negative Full Scale Cal Register, Byte 1 MSB 654321 LSB 1 1110 Negative Full Scale Cal Register, Byte 2 R/W MB1 MB0 FSC A3 A2 A1 A0 Write Operation R/W - Bit 7 of the Instruction Register determines whether a Data can be written to the Control Register, Offset read or write operation will be done following the instruction Calibration Register, Positive Full Scale Calibration Register, byte load. 0 = READ, 1 = WRITE. and the Negative Full Scale Calibration Register. Write operations are done using the SDIO, CS and SCLK lines MB1, MB0 - Bits 6 and 5 of the Instruction Register only, as all data is written into the HI7190 via the SDIO line determine the number of bytes that will be accessed even when using the 3-wire configuration. Figures 14 and 15 following the instruction byte load. See Table 5 for the show typical write timing diagrams. number of bytes to transfer in the transfer cycle. The communication cycle is started by asserting the CS line TABLE 5. MULTIPLE BYTE ACCESS BITS low and starting the clock from its idle state. To assert a write MB1 MB0 DESCRIPTION cycle, during the instruction phase of the communication 0 0 Transfer 1 Byte cycle, the Instruction Byte should be set to a write transfer (R/W = 1). 0 1 Transfer 2 Bytes 1 0 Transfer 3 Bytes When writing to the serial port, data is latched into the HI7190 on the rising edge of SCLK. Data can then be 1 1 Transfer 4 Bytes changed on the falling edge of SCLK. Data can also be changed on the rising edge of SCLK due to the 0ns hold time FSC - Bit 4 is used to determine whether a Positive Full Scale required on the data. This is useful in pipelined applications Calibration Register I/O transfer (FSC = 0) or a Negative Full where the data is latched on the rising edge of the clock. Scale Calibration Register I/O transfer (FSC = 1) is being performed (see Table 6). Read Operation - 3-Wire Transfer Data can be read from the Data Output Register, Control A3, A2, A1, A0 - Bits 3 and 2 (A3 and A2) of the Instruction Register, Offset Calibration Register, Positive Full Scale Register determine which internal register will be accessed Calibration Register, and the Negative Full Scale Calibration while bits 1 and 0 (A1 and A0) determine which byte of that Register. When configured in 3-wire transfer mode, read register will be accessed first. See Table 6 for the address operations are done using the SDIO, SDO, CS and SCLK decode. lines. All data is read via the SDO line. Figures 16 and 17 show typical 3-wire read timing diagrams. TABLE 6. INTERNAL DATA ACCESS DECODE STARTING BYTE The communication cycle is started by asserting the CS line and starting the clock from its idle state. To assert a read FSC A3A2A1A0 DESCRIPTION cycle, during the instruction phase of the communication X 0000 Data Output Register, Byte 0 cycle, the Instruction Byte should be set to a read transfer X 0001 Data Output Register, Byte 1 (R/W = 0). X 0010 Data Output Register, Byte 2 When reading the serial port, data is driven out of the HI7190 X 0100 Control Register, Byte 0 on the falling edge of SCLK. Data can be registered externally on the next rising edge of SCLK. X 0101 Control Register, Byte 1 Read Operation - 2-Wire Transfer X 0110 Control Register, Byte 2 Data can be read from the Data Output Register, Control X 1000 Offset Cal Register, Byte 0 Register, Offset Calibration Register, Positive Full Scale X 1001 Offset Cal Register, Byte 1 Calibration Register, and the Negative Full Scale Calibration X 1010 Offset Cal Register, Byte 2 Register. When configured in two-wire transfer mode, read operations are done using the SDIO, CS and SCLK lines. All 0 1100 Positive Full Scale Cal Register, Byte 0 data is read via the SDIO line. Figures 18 and 19 show 0 1101 Positive Full Scale Cal Register, Byte 1 typical 2-wire read timing diagrams. 0 1110 Positive Full Scale Cal Register, Byte 2 FN3612.10 18 June 27, 2006 HI7190 The communication cycle is started by asserting the CS line BYTE 2 and starting the clock from its idle state. To assert a read cycle, MSB 22212019181716 during the instruction phase of the communication cycle, the D23 D22 D21 D20 D19 D18 D17 D16 Instruction Byte should be set to a read transfer (R/W = 0). When reading the serial port, data is driven out of the HI7190 on the falling edge of SCLK. Data can be registered BYTE 1 externally on the next rising edge of SCLK. 15 14 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 D9 D8 Detailed Register Descriptions Data Output Register BYTE 0 The Data Output Register contains 24 bits of converted data. This register is a read only register. 7654321 LSB D7 D6 D5 D4 D3 D2 D1 D0 IR WRITE PHASE DATA TRANSFER PHASE - TWO-BYTE WRITE CS SCLK I0 I1 I2 I3 I4 I5 I6 I7 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 SDIO SDO THREE-STATE THREE-STATE FIGURE 14. DATA WRITE CYCLE, SCLK IDLE LOW IR WRITE PHASE DATA TRANSFER PHASE - TWO-BYTE WRITE CS SCLK B15 I0 I1 I2 I3 I4 I5 I6 I7 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 SDIO SDO THREE-STATE THREE-STATE FIGURE 15. DATA WRITE CYCLE, SCLK IDLE HIGH IR WRITE PHASE DATA TRANSFER PHASE - TWO-BYTE READ CS SCLK SDIO I0 I1 I2 I3 I4 I5 I6 I7 B15 B8 B9 B10 B11 B12 B13 B14 B0 B1 B2 B3 B4 B5 B6 B7 SDO FIGURE 16. DATA READ CYCLE, 3-WIRE CONFIGURATION, SCLK IDLE LOW FN3612.10 19 June 27, 2006 HI7190 IR WRITE PHASE DATA TRANSFER PHASE - TWO-BYTE READ CS SCLK I0 I1 I2 I3 I4 I5 I6 I7 SDIO B15 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 SDO FIGURE 17. DATA READ CYCLE, 3-WIRE CONFIGURATION, SCLK IDLE HIGH IR WRITE PHASE DATA TRANSFER PHASE - TWO-BYTE READ CS SCLK B15 SDIO I0 I1 I2 I3 I4 I5 I6 I7 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 SDO THREE-STATE THREE-STATE FIGURE 18. DATA READ CYCLE, 2-WIRE CONFIGURATION, SCLK IDLE LOW IR WRITE PHASE DATA TRANSFER PHASE - TWO-BYTE READ CS SCLK B15 I0 I1 I2 I3 I4 I5 I6 I7 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 SDIO SDO THREE-STATE THREE-STATE FIGURE 19. DATA READ CYCLE, 2-WIRE CONFIGURATION, SCLK IDLE HIGH DC - Bit 23 is the Data Coding Bit used to select between Control Register two’s complementary and offset binary data coding. When The Control Register contains 24-bits to control the various this bit is set (DC = 1) the data in the Data Output Register sections of the HI7190. This register is a read/write will be two’s complement. When cleared (DC = 0) this data register. will be offset binary. When operating in the unipolar mode BYTE 2 the output data is available in straight binary only (the DC bit is ignored). This bit is cleared after a RESET is applied to the MSB 22212019181716 part. DC FP10 FP9 FP8 FP7 FP6 FP5 FP4 FP10 through FP0 - Bits 22 through 12 are the Filter programming bits that determine the frequency response of BYTE 1 the digital filter. These bits determine the filter cutoff frequency, the position of the first notch and the data rate of 15 14 13 12 11 10 9 8 the HI7190. The first notch of the filter is equal to the FP3 FP2 FP1 FP0 MD2 MD1 MD0 B/U decimation rate and can be determined by the formula: f = f /(512 x CODE) NOTCH OSC BYTE 0 where CODE is the decimal equivalent of the value in FP10 7654321 LSB through FP0. The values that can be programmed into these bits are 10 to 2047 decimal, which allows a conversion rate G2 G1 G0 BO SB BD MSB SDL range of 9.54Hz to 1.953kHz when using a 10MHz clock. FN3612.10 20 June 27, 2006 HI7190 Changing the filter notch frequency, as well as the selected can be used to detect the presence of an external gain, impacts resolution. The output data rate (or effective connection to V . This bit is cleared after a RESET is INHI conversion time) for the device is equal to the frequency applied to the part. selected for the first notch to the filter. For example, if the SB - Bit 3 is the Standby Mode enable bit used to put the first notch of the filter is selected at 50Hz then a new word is HI7190 in a lower power/standby mode. When this bit is set available at a 50Hz rate or every 20ms. If the first notch is at (SB = 1) the filter nodes are halted, the DRDY line is set high 1kHz a new word is available every 1ms. and the modulator clock is disabled. When this bit is cleared The settling-time of the converter to a full scale step input the HI7190 begins operation as described by the contents of change is between 3 and 4 times the data rate. For example, the Control Register. For example, if the Control Register is with the first filter notch at 50Hz, the worst case settling time programmed for Self Calibration Mode and a notch to a full scale step input change is 80ms. If the first notch is frequency to 10Hz, the HI7190 will perform the self 1kHz, the settling time to a full scale input step is 4ms calibration before providing the data at the 10Hz rate. This maximum. bit is cleared after a RESET is applied to the part. The -3dB frequency is determined by the programmed first BD - Bit 2 is the Byte Direction bit used to select the multi- notch frequency according to the relationship: byte access ordering. The bit determines the either ascending or descending order access for the multi-byte f = 0.262 x f . -3dB NOTCH registers. When set (BD = 1) the user can access multi-byte MD2 through MD0 - Bits 11 through 9 are the Operational registers in ascending byte order and when cleared (BD = 0) Modes of the converter. See Table 4 for the Operational the multi-byte registers are accessed in descending byte Modes description. After a RESET is applied to the part order. This bit is cleared after a RESET is applied to the part. these bits are set to the self calibration mode. MSB - Bit 1 is used to select whether a serial data transfer is B/U - Bit 8 is the Bipolar/Unipolar select bit. When this bit is MSB or LSB first. This bit allows the user to change the set the HI7190 is configured for bipolar operation. When this order that data can be transmitted or received by the bit is reset the part is in unipolar mode. This bit is set after a HI7190. When this bit is cleared (MSB = 0) the MSB is the RESET is applied to the part. first bit in a serial data transfer. If set (MSB = 1), the LSB is the first bit transferred in the serial data stream. This bit is G2 through G0 - Bits 7 through 5 select the gain of the input cleared after a RESET is applied to the part. analog signal. The gain is accomplished through a programmable gain instrumentation amplifier that gains up SDL - Bit 0 is the Serial Data Line control bit. This bit selects incoming signals from 1 to 8. This is achieved by using a the transfer protocol of the serial interface. When this bit is switched capacitor voltage multiplier network preceding the cleared (SDL = 0), both read and write data transfers are modulator. The higher gains (i.e., 16 to 128) are achieved done using the SDIO line. When set (SDL = 1), write through a combination of a PGIA gain of 8 and a digital transfers are done on the SDIO line and read transfers are multiply after the digital filter (see Table 7). The gain will done on the SDO line. This bit is cleared after a RESET is affect noise and Signal to Noise Ratio of the conversion. applied to the part. These bits are cleared to a gain of 1 (G2, G1, G0 = 000) after Reading the Data Output Register a RESET is applied to the part. The HI7190 generates an active low interrupt (DRDY) TABLE 7. GAIN SELECT BITS indicating valid conversion results are available for reading. At this time the Data Output Register contains the latest G2 G1 G0 GAIN GAIN ACHIEVED conversion result available from the HI7190. Data integrity is 0 0 0 1 PGIA = 1, Filter Multiply = 1 maintained at the serial output port but it is possible to miss 0 0 1 2 PGIA = 2, Filter Multiply = 1 a conversion result if the Data Output Register is not read within a given period of time. Maintaining data integrity 0 1 0 4 PGIA = 4, Filter Multiply = 1 means that if a Data Output Register read of conversion N is 0 1 1 8 PGIA = 8, Filter Multiply = 1 begun but not finished before the next conversion 1 0 0 16 PGIA = 8, Filter Multiply = 2 (conversion N + 1) is complete, the DRDY line remains active low and the data being read is not overwritten. 1 0 1 32 PGIA = 8, Filter Multiply = 4 1 1 0 64 PGIA = 8, Filter Multiply = 8 In addition to the Data Output Register, the HI7190 has a one conversion result storage buffer. No conversion results 1 1 1 128 PGIA = 8, Filter Multiply = 16 will be lost if the following constraints are met. BO - Bit 4 is the Transducer Burn-Out Current source enable 1) A Data Output Register read cycle is started for a given bit. When this bit is set (BO = 1) the burn-out current source conversion (conversion X) 1/f - (128*1/f ) after DRDY N OSC connected to V internally is enabled. This current source initially goes active low. Failure to start the read cycle may INHI FN3612.10 21 June 27, 2006 HI7190 result in conversion X + 1 data overwriting conversion X Positive Full Scale Calibration Register results. For example, with f = 10MHz, f = 2kHz, the OSC N The Positive Full Scale Calibration Register is a 24-bit 6 read cycle must start within 1/2000 - 128(1/10 ) = 487μs register containing the Positive Full Scale correction after DRDY went low. coefficient. This coefficient is used to determine the positive gain slope factor. This register is indeterminate on power-up 2) The Data Output Register read cycle for conversion X but will contain a Self Calibration correction coefficient after must be completed within 2(1/f )-1440(1/f ) after DRDY N OSC a RESET has been applied. initially goes active low. If the read cycle for conversion X is not complete within this time the results of conversion X + 1 BYTE 2 are lost and results from conversion X + 2 are now stored in MSB 22212019181716 the data output word buffer. P23 P22 P21P20 P19P18 P17P16 Completing the Data Output Register read cycle inactivates the DRDY interrupt. If the one word data output buffer is full when this read is complete this data will be immediately BYTE 1 transferred to the Data Output Register and a new DRDY 15 14 13 12 11 10 9 8 interrupt will be issued after the minimum DRDY pulse high time is met. P15 P14 P13 P12 P11 P10 P9 P8 Writing the Control Register If data is written to byte 2 and/or byte 1 of the Control BYTE 0 Register the DRDY output is taken high and the device re- 7654321 LSB calibrates if written to a calibration mode. This action is taken P7 P6 P5 P4 P3 P2 P1 P0 because it is assumed that by writing byte 2 or byte 1 that the user either reprogrammed the filter or changed modes of Negative Full Scale Calibration Register the part. However, if a single data byte is written to byte 0, it The Negative Full Scale Calibration Register is a 24-bit is assumed that the gain has NOT been changed. It is up to register containing the Negative Full Scale correction the user to re-calibrate the HI7190 after the gain has been coefficient. This coefficient is used to determine the negative changed by this method. It is recommended that the entire gain slope factor. This register is indeterminate on power-up Control Register be written to when changing the selected but will contain a Self Calibration correction coefficient after gain. This ensures that the part is re-calibrated before the a RESET has been applied. DRDY signal goes low indicating valid data is available. BYTE 2 Offset Calibration Register MSB 22212019181716 The Offset Calibration Register is a 24-bit register containing the offset correction factor. This register is indeterminate on N23 N22 N21 N20 N19 N18 N17 N16 power-up but will contain a Self Calibration correction value after a RESET has been applied. BYTE 1 BYTE 2 15 14 13 12 11 10 9 8 MSB 22212019181716 N15 N14 N13 N12 N11 N10 N9 N8 O23 O22 O21 O20 O19 O18 O17 O16 BYTE 0 BYTE 1 7654321 LSB 15 14 13 12 11 10 9 8 N7 N6 N5 N4 N3 N2 N1 N0 O15 O14 O13 O12 O11 O10 O9 O8 BYTE 0 7654321 LSB O7 O6 O5 O4 O3 O2 O1 O0 The Offset Calibration Register holds the value that corrects the filter output data to all 0’s when the analog input is 0V. FN3612.10 22 June 27, 2006 HI7190 SUBSTRATE POTENTIAL (POWERED UP) Die Characteristics AV SS DIE DIMENSIONS PASSIVATION 3550μm x 6340μm Type: Sandwich METALLIZATION Thickness:Nitride 8kÅ Type: AlSiCu USG 1kÅ Thickness:Metal 2, 16kÅ Metal 1, 6kÅ Metallization Mask Layout HI7190 OSC CS 1 DRDY OSC 2 DGND DV DD AV SS AGND FN3612.10 23 June 27, 2006 SDIO V RLO V RHI SDO V CM SCLK MODE V INLO SYNC V INHI AV DD RESET HI7190 Dual-In-Line Plastic Packages (PDIP) N E20.3 (JEDEC MS-001-AD ISSUE D) E1 20 LEAD DUAL-IN-LINE PLASTIC PACKAGE INDEX 12 3 N/2 AREA INCHES MILLIMETERS -B- SYMBOL MIN MAX MIN MAX NOTES -A- A- 0.210 - 5.33 4 D E A1 0.015 - 0.39 -4 BASE PLANE A2 A A2 0.115 0.195 2.93 4.95 - -C- SEATING B 0.014 0.022 0.356 0.558 - PLANE L C L B1 0.045 0.070 1.55 1.77 8 D1 e A1 A D1 C 0.008 0.014 0.204 0.355 - e B1 e C C B D 0.980 1.060 24.89 26.9 5 e B 0.010 (0.25) M C A BS D1 0.005 - 0.13 -5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English e 0.100 BSC 2.54 BSC - and Metric dimensions, the inch dimensions control. e 0.300 BSC 7.62 BSC 6 A 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. e - 0.430 - 10.92 7 B 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 L 0.115 0.150 2.93 3.81 4 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in N20 20 9 JEDEC seating plane gauge GS-3. Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). e 6. E and are measured with the leads constrained to be perpen- A -C- dicular to datum . 7. e and e are measured at the lead tips with the leads uncon- B C strained. e must be zero or greater. C 8. B1 maximum dimensions do not include dambar protrusions. Dam- bar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN3612.10 24 June 27, 2006 HI7190 Small Outline Plastic Packages (SOIC) M20.3 (JEDEC MS-013-AC ISSUE C) N 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX 0.25(0.010) M B M H AREA INCHES MILLIMETERS E SYMBOL MIN MAX MIN MAX NOTES -B- A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - 12 3 L B 0.014 0.019 0.35 0.49 9 SEATING PLANE C 0.0091 0.0125 0.23 0.32 - -A- D 0.4961 0.5118 12.60 13.00 3 A h x 45° D E 0.2914 0.2992 7.40 7.60 4 -C- e 0.050 BSC 1.27 BSC - α H 0.394 0.419 10.00 10.65 - e A1 C h 0.010 0.029 0.25 0.75 5 B 0.10(0.004) L 0.016 0.050 0.40 1.27 6 M M S 0.25(0.010) C A B N20 20 7 α 0° 8° 0° 8° - NOTES: Rev. 2 6/05 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN3612.10 25 June 27, 2006