INTERSIL HI5812JIB

HI5812 ® Data Sheet March 31, 2005 FN3214.6 CMOS 20 Microsecond, 12-Bit, Sampling Features A/D Converter with Internal Track and • Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 20µs Hold Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 50 kSPS The HI5812 is a fast, low power, 12-bit, successive Built-In Track and Hold approximation analog-to-digital converter. It can operate from a single 3V to 6V supply and typically draws just 1.9mA Guaranteed No Missing Codes Over Temperature when operating at 5V. The HI5812 features a built-in track Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . .+5V and hold. The conversion time is as low as 20µs with a 5V supply.Maximum Power Consumption. . . . . . . . . . . . . . . . 25mW Internal or External Clock The twelve data outputs feature full high speed CMOS three-state bus driver capability, and are latched and held • Pb-Free Available (RoHS Compliant) through a full conversion cycle. The output is user selectable, i.e., 12-bit, 8-bit (MSBs), and/or 4-bit (LSBs). A Applications data ready flag, and conversion-start input complete the Remote Low Power Data Acquisition Systems digital interface. Digital Audio An internal clock is provided and is available as an output. The clock may also be over-driven by an external source.DSP Modems General Purpose DSP Front End Ordering Information µP Controlled Measurement System INL (LSB) TEMP. PART (MAX OVER RANGE PKG. Professional Audio Positioner/Fader o NUMBER TEMP.) ( C) PACKAGE DWG. # Pinout HI5812JIP ±1.5 -40 to 85 24 Ld PDIP E24.3 HI5812 HI5812JIPZ ±1.5 -40 to 85 24 Ld PDIP* E24.3 (PDIP, SOIC) (See Note) (Pb-free) TOP VIEW HI5812JIB ±1.5 -40 to 85 24 Ld SOIC M24.3 DRDY 1 24 V DD (LSB) D0 2 23 OEL HI5812JIBZ ±1.5 -40 to 85 24 Ld SOIC M24.3 D1 3 22 CLK (See Note) (Pb-free) 21 STRT D2 4 HI5812KIB ±1.0 -40 to 85 24 Ld SOIC M24.3 D3 5 20 V - REF D4 6 19 V + REF HI5812KIBZ ±1.0 -40 to 85 24 Ld SOIC M24.3 D5 7 18 V (See Note) (Pb-free) IN D6 8 17 V + AA *Pb-free PDIPs can be used for through hole wave solder D7 9 16 V - AA processing only. They are not intended for use in Reflow solder D8 10 15 OEM processing applications. NOTE: Intersil Pb-free products employ special Pb-free material D9 11 14 D11 (MSB) sets; molding compounds/die attach materials and 100% matte tin V 12 13 D10 SS plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2001, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HI5812 Functional Block Diagram STRT V DD TO INTERNAL LOGIC V SS V IN CLOCK CLK CONTROL + TIMING DRDY 32C OEM V + REF 16C D11 (MSB) 8C 50Ω SUBSTRATE D10 4C D9 2C V + AA C D8 V - 32C AA 64C D7 63 16C 12-BIT 12-BIT EDGE SUCCESSIVE D6 TRIGGERED APPROXIMATION 8C “D” LATCHES REGISTER D5 4C 2C D4 C P1 D3 C D2 D1 V - REF D0 (LSB) OEL 2 HI5812 Absolute Maximum Ratings Thermal Information o Supply Voltage Thermal Resistance (Typical, Note 1) θ ( C/W) JA V to V . . . . . . . . . . . . . . . . . . . . (V -0.5V) < V < +6.5V DD SS SS DD PDIP Package*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 V + to V - . . . . . . . . . . . . . . . . . . . (V -0.5V) to (V +6.5V) AA AA SS SS SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 V + to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V AA DD Maximum Junction Temperature o Analog and Reference Inputs Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 C ο o V , V +, V - . . . . . . . . (V -0.3V) < V < (V +0.3V) IN REF REF SS INA DD Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C o Digital I/O Pins . . . . . . . . . . . . . . . (V -0.3V) < V < (V +0.3V) SS I/O DD Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . .300 C (SOIC - Lead Tips Only) Operating Conditions *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing o o Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. JA Electrical Specifications V = V + = 5V, V + = +4.608V, V = V - = V - = GND, CLK = External 750kHz, DD AA REF SS AA REF Unless Otherwise Specified o o o 25 C -40 C TO 85 C PARAMETER TEST CONDITIONS MIN TYP MAX MIN MAX UNITS ACCURACY Resolution 12 - - 12 - Bits Integral Linearity Error, INL J-- ±1.5 - ±1.5 LSB (End Point) K-- ±1.0 - ±1.0 LSB Differential Linearity Error, DNL J - - ±2.0 - ±2.0 LSB K-- ±1.0 - ±1.0 LSB Gain Error, FSE J-- ±3.0 - ±3.0 LSB (Adjustable to Zero) K-- ±2.5 - ±2.5 LSB Offset Error, V J-- ±2.0 - ±2.0 LSB OS (Adjustable to Zero) K-- ±1.0 - ±1.0 LSB Power Supply Rejection, PSRR V = 4V - - REF Offset Error PSRR V = V + = 5V ±5% ±0.1 ±0.5 ±0.5 LSB DD AA Gain Error PSRR V = V + = 5V ±5% ±0.1 ±0.5 ±0.5 LSB DD AA DYNAMIC CHARACTERISTICS Signal to Noise Ratio, SINAD Jf = Internal Clock, f = 1kHz - 68.8 -- - dB S IN RMS Signal f = 750kHz, f = 1kHz 69.2 dB S IN RMS Noise + Distortion Kf = Internal Clock, f = 1kHz - 71.0 -- - dB S IN f = 750kHz, f = 1kHz 71.5 dB S IN Signal to Noise Ratio, SNR Jf = Internal Clock, f = 1kHz - 70.5 -- - dB S IN RMS Signal f = 750kHz, f = 1kHz 71.1 dB S IN RMS Noise Kf = Internal Clock, f = 1kHz - 71.5 -- - dB S IN f = 750kHz, f = 1kHz 72.1 dB S IN Total Harmonic Distortion, THD J f = Internal Clock, f = 1kHz - -73.9 -- - dBc S IN f = 750kHz, f = 1kHz -73.8 dBc S IN Kf = Internal Clock, f = 1kHz - -80.3 -- - dBc S IN f = 750kHz, f = 1kHz -79.0 dBc S IN 3 HI5812 Electrical Specifications V = V + = 5V, V + = +4.608V, V = V - = V - = GND, CLK = External 750kHz, DD AA REF SS AA REF Unless Otherwise Specified (Continued) o o o 25 C -40 C TO 85 C PARAMETER TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Spurious Free Dynamic Range, Jf =Internal Clock, f = 1kHz - -75.4 -- - dB S IN SFDR f = 750kHz, f = 1kHz -75.1 dB S IN Kf = Internal Clock, f = 1kHz - -80.9 -- - dB S IN f = 750kHz, f = 1kHz -79.6 dB S IN ANALOG INPUT Input Current, Dynamic At V = V +, 0V - ±50 ±100 - ±100 µA IN REF Input Current, Static Conversion Stopped - ±0.4 ±10 - ±10 µA Input Bandwidth -3dB - 1 - - - MHz Reference Input Current - 160 - - - µA Input Series Resistance, R In Series with Input C - 420 - - - W S SAMPLE Input Capacitance, C During Sample State - 380 - - - pF SAMPLE Input Capacitance, C During Hold State - 20 - - - pF HOLD DIGITAL INPUTS OEL, OEM, STRT High-Level Input Voltage, V 2.4 - - 2.4 - V IH Low-Level Input Voltage, V - - 0.8 - 0.8 V IL Input Leakage Current, I Except CLK, V = 0V, 5V - - ±10 - ±10 µA IL IN Input Capacitance, C -10- - - pF IN DIGITAL OUTPUTS High-Level Output Voltage, V I = -400µA4.6--4.6 - V OH SOURCE Low-Level Output Voltage, V I = 1.6mA - - 0.4 - 0.4 V OL SINK Three-State Leakage, I Except DRDY, V = 0V, 5V - - ±10 - ±10 µA OZ OUT Output Capacitance, C Except DRDY - 20 - - - pF OUT CLOCK High-Level Output Voltage, V I = -100µA (Note 2) 4 - - 4 - V OH SOURCE Low-Level Output Voltage, V I = 100µA (Note 2) - - 1 - 1 V OL SINK Input Current CLK Only, V = 0V, 5V - - ±5- ±5mA IN TIMING Conversion Time (t + t ) 20 - - 20 - µs CONV ACQ (Includes Acquisition Time) Clock Frequency Internal Clock, (CLK = Open) 200 300 400 150 500 kHz External CLK (Note 2) 0.05 2 1.5 0.05 1.5 MHz Clock Pulse Width, t , t External CLK (Note 2) 100 - - 100 - ns LOW HIGH Aperture Delay, t APR (Note 2) - 35 50 - 70 ns D Clock to Data Ready Delay, t DRDY (Note 2) - 105 150 - 180 ns D1 Clock to Data Ready Delay, t DRDY (Note 2) - 100 160 - 195 ns D2 Start Removal Time, t STRT (Note 2) 75 30 - 75 - ns R Start Setup Time, t STRT (Note 2) 85 60 - 100 - ns SU Start Pulse Width, t STRT (Note 2) 10 4 - 15 - ns W Start to Data Ready Delay, t DRDY (Note 2) - 65 105 - 120 ns D3 4 HI5812 Electrical Specifications V = V + = 5V, V + = +4.608V, V = V - = V - = GND, CLK = External 750kHz, DD AA REF SS AA REF Unless Otherwise Specified (Continued) o o o 25 C -40 C TO 85 C PARAMETER TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Clock Delay from Start, t STRT (Note 2) - 60 - - - ns D Output Enable Delay, t (Note 2) - 20 30 - 50 ns EN Output Disabled Delay, t (Note 2) - 80 95 - 120 ns DIS POWER SUPPLY CHARACTERISTICS Supply Current, I + I -1.9 5 - 8 mA DD AA NOTE: 2. Parameter guaranteed by design or characterization, not production tested. Timing Diagrams 5 - 14 1 2 3 4 15 1 2 3 CLK (EXTERNAL OR INTERNAL) t t DRDY LOW D1 t HIGH STRT t DRDY D2 DRDY D0 - D11 DATA N - 1 DATA N HOLD N V IN TRACK N TRACK N + 1 OEL = OEM = V SS FIGURE 1. CONTINUOUS CONVERSION MODE 5 HI5812 Timing Diagrams (Continued) 2 15 1 2 2 3 4 5 CLK (EXTERNAL) t STRT t STRT SU R t STRT W STRT t DRDY D3 DRDY HOLD HOLD TRACK V IN FIGURE 2. SINGLE SHOT MODE EXTERNAL CLOCK 15 1 2 3 4 5 CLK (INTERNAL) t STRT R t STRT D t STRT W STRT DON’T CARE t DRDY D3 DRDY HOLD HOLD TRACK V IN FIGURE 3. SINGLE SHOT MODE INTERNAL CLOCK 6 HI5812 Timing Diagrams (Continued) OEL OR OEM t t DIS EN 1.6mA 90% 50% D0 - D3 OR D4 - D11 HIGH IMPEDANCE TO +2.1V TO HIGH OUTPUT 50pF PIN HIGH IMPEDANCE 50% TO LOW 10% -1.6mA FIGURE 4A. FIGURE 4B. FIGURE 4. OUTPUT ENABLE/DISABLE TIMING DIAGRAM 1.6mA +2.1V 50pF -400µA FIGURE 5. GENERAL TIMING LOAD CIRCUIT 7 HI5812 Typical Performance Curves 1.0 1.5 V = V + = 5V A. CLK = INTERNAL DD AA V = V + = 5V, V + = 4.608V DD AA REF B. CLK = 750kHz V + = 4.608V REF C. CLK = 1MHz C 0.75 1 C B 0.5 A 0.5 A 0.25 A. CLK = INTERNAL B. CLK = 750kHz C. CLK = 1MHz B 0 0 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -20 0 20 40 60 80 100 120 140 -40 o o TEMPERATURE ( C) TEMPERATURE ( C) FIGURE 6. INL vs TEMPERATURE FIGURE 7. OFFSET VOLTAGE vs TEMPERATURE 1.0 2 o C V = V + = 5V, T = 25 C V = V + = 5V, V + = 4.608V DD AA A DD AA REF CLK = 750kHz 0.75 1.5 B FSE 0.5 1 A DNL 0.25 0.5 INL A. CLK = INTERNAL B. CLK = 750kHz V C. CLK = 1MHz OS 0 0 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 -60 -20 0 20 40 60 80 100 120 140 -40 o REFERENCE VOLTAGE, V (V) REF TEMPERATURE ( C) FIGURE 8. DNL vs TEMPERATURE FIGURE 9. ACCURACY vs REFERENCE VOLTAGE 2 0.5 A. CLK = INTERNAL V = V + = 5V, DD AA V = V + = 5V ±5% DD AA B. CLK = 750kHz V + = 4.608V REF CLK = 750kHz C. CLK = 1MHz 1.5 V + = 4.0V REF 0.375 C 1 0.25 B 0.5 0.125 PSRR V OS A PSRR FSE 0 0 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -20 0 20 40 60 80 100 120 140 -40 o o TEMPERATURE ( C) TEMPERATURE ( C) FIGURE 10. FULL SCALE ERROR vs TEMPERATURE FIGURE 11. POWER SUPPLY REJECTION vs TEMPERATURE 8 INL ERROR (LSBs) DNL ERROR (LSBs) FS ERROR (LSBs) PSRR (LSBs) V ERROR (LSBs) OS ERROR (LSBs) HI5812 Typical Performance Curves (Continued) 8 INPUT FREQUENCY = 1kHz 0.0 V = V + = 5V, V + = 4.608V DD AA REF SAMPLING RATE = 50kHz -10.0 7 SNR = 72.1dB -20.0 SINAD = 71.4dB -30.0 6 EFFECTIVE BITS = 11.5 -40.0 THD = -79.1dBc 5 -50.0 PEAK NOISE = -80.9dB -60.0 SFDR = -80.9dB 4 -70.0 -80.0 3 INTERNAL CLOCK -90.0 -100.0 2 -110.0 -120.0 1 -130.0 0 -140.0 -60 -40 -20 0 20 40 60 80 100 120 140 0 500 1000 1500 2000 o FREQUENCY BINS TEMPERATURE ( C) FIGURE 12. SUPPLY CURRENT vs TEMPERATURE FIGURE 13. FFT SPECTRUM 500 12 V = V + = 5V, V + = 4.608V DD AA REF 450 11 400 10 350 B V = V + = 5V DD AA 300 V + = 4.608V REF 9 o T = 25 C A 250 A. CLK = INTERNAL C B. CLK = 750kHz 8 200 C. CLK = 1MHz A 7 150 -60 -20 0 20 40 60 80 100 120 140 -40 0.1 1 10 100 o TEMPERATURE ( C) INPUT FREQUENCY (kHz) FIGURE 14. INTERNAL CLOCK FREQUENCY vs TEMPERATURE FIGURE 15. EFFECTIVE BITS vs INPUT FREQUENCY 75 -80 70 B -70 65 C V = V + = 5V DD AA V = V + = 5V V + = 4.608V DD AA REF o V + = 4.608V A REF T = 25 C A 60 o T = 25 C A -60 A. CLK =INTERNAL B A. CLK = INTERNAL B. CLK = 750kHz 55 B. CLK = 750kHz C. CLK = 1MHz C. CLK = 1MHz C A -50 50 0.1 1 10 100 0.1 1 10 100 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) FIGURE 16. TOTAL HARMONIC DISTORTION vs INPUT FIGURE 17. SIGNAL NOISE RATIO vs INPUT FREQUENCY FREQUENCY 9 THD (dBc) INTERNAL CLOCK FREQUENCY (kHz) SUPPLY CURRENT, I (mA) DD SNR (dBc) ENOB (BITS) AMPLITUDE (dB) HI5812 connected to the V + terminal; and the remaining REF TABLE 1. PIN DESCRIPTIONS capacitors to V -. The capacitor-common node, after the REF charges balance out, will indicate whether the input was PIN NO. NAME DESCRIPTION 1 above / of (V + - V -). At the end of the fourth 1 DRDY Output flag signifying new data is available. 2 REF REF period, the comparator output is stored and the MSB Goes high at end of clock period 15. Goes low when new conversion is started. capacitor is either left connected to V + (if the comparator REF was high) or returned to V -. This allows the next 2 D0 Bit 0 (Least Significant Bit, LSB). REF 3 1 comparison to be at either / or / of (V + - V -). 3D1 Bit 1. 4 4 REF REF 4D2 Bit 2. At the end of periods 5 through 14, capacitors representing D10 through D1 are tested, the result stored, and each 5D3 Bit 3. capacitor either left at V + or at V -. 6D4 Bit 4. REF REF 7D5 Bit 5. At the end of the 15th period, when the LSB (D0) capacitor is tested, (D0) and all the previous results are shifted to the 8D6 Bit 6. output registers and drivers. The capacitors are reconnected 9D7 Bit 7. to the input, the comparator returns to the balance state, and 10 D8 Bit 8. the data-ready output goes active. The conversion cycle is 11 D9 Bit 9. now complete. 12 V Digital Ground (0V). SS Analog Input 13 D10 Bit 10. The analog input pin is a predominately capacitive load that 14 D11 Bit 11 (Most Significant Bit, MSB). changes between the track and hold periods of the 15 OEM Three-State Enable for D4-D11. Active low input. conversion cycle. During hold, clock period 4 through 15, the 16 V - Analog Ground, (0V). AA input loading is leakage and stray capacitance, typically less 17 V + Analog Positive Supply. (+5V) (See text.) AA than 5µA and 20pF. 18 V Analog Input. IN At the start of input tracking, clock period 1, some charge is 19 V + Reference Voltage Positive Input, sets 4095 REF dumped back to the input pin. The input source must have code end of input range. low enough impedance to dissipate the current spike by the 20 V - Reference Voltage Negative Input, sets 0 code REF end of the tracking period as shown in Figure 18. The end of input range. amount of charge is dependent on supply and input 21 STRT Start Conversion Input Active Low, recognized voltages. The average current is also proportional to clock after end of clock period 15. frequency. 22 CLK CLK Input or Output. Conversion functions are synchronized to positive going edge. (See text.) 23 OEL Three-State Enable for D0 D3. Active Low Input. 20mA 24 V Digital Positive Supply (+5V). DD I IN 10mA Theory of Operation 0mA HI5812 is a CMOS 12-Bit Analog-to-Digital Converter that uses capacitor-charge balancing to successively approximate CLK the analog input. A binarily weighted capacitor network forms 5V the A/D heart of the device. See the block diagram for the 0V HI5812. 5V DRDY The capacitor network has a common node which is 0V connected to a comparator. The second terminal of each 200ns/DIV. capacitor is individually switchable to the input, V + or REF CONDITIONS: V = V + = 5.0V, V + = 4.608V, V -. DD AA REF REF o V = 4.608V, CLK = 750kHz, T = 25 C IN A During the first three clock periods of a conversion cycle, the FIGURE 18. TYPICAL ANALOG INPUT CURRENT switchable end of every capacitor is connected to the input and the comparator is being auto-balanced at the capacitor As long as these current spikes settle completely by end of common node. the signal acquisition period, converter accuracy will be During the fourth period, all capacitors are disconnected preserved. The analog input is tracked for 3 clock cycles. from the input; the one representing the MSB (D11) is With an external clock of 750kHz the track period is 4µs. 10 HI5812 A simplified analog input model is presented in Figure 19. The HI5812 is specified with a 4.608V reference, however, it During tracking, the A/D input (V ) typically appears as a will operate with a reference down to 3V having a slight IN 380pF capacitor being charged through a 420Ω internal degradation in performance. A typical graph of accuracy vs switch resistance. The time constant is 160ns. To charge this reference voltage is presented. capacitor from an external “zero Ω” source to 0.5 LSB Full Scale and Offset Adjustment (1/8192), the charging time must be at least 9 time constants In many applications the accuracy of the HI5812 would be or 1.4µs. The maximum source impedance (R Max) SOURCE sufficient without any adjustments. In applications where for a 4µs acquisition time settling to within 0.5LSB is 750Ω. accuracy is of utmost importance full scale and offset errors If the clock frequency was slower, or the converter was not may be adjusted to zero. restarted immediately (causing a longer sample time), a The V + and V - pins reference the two ends of the higher source impedance could be tolerated. REF REF analog input range and may be used for offset and full scale adjustments. In a typical system the V - might be REF V IN returned to a clean ground, and the offset adjustment done R ≈ 420Ω SW on an input amplifier. V + would then be adjusted to null REF C ≈ 380pF SAMPLE out the full scale error. When this is not possible, the V - REF R SOURCE input can be adjusted to null the offset error, however, V - –t REF ACQ --- ----- ----- ----- ------ ----- ----- ------ ----- ----- ------ ----- - R = – R must be well decoupled. SOURCE(MAX) SW –() N1 + C In[] 2 SAMPLE Full scale and offset error can also be adjusted to zero in the FIGURE 19. ANALOG INPUT MODEL IN TRACK MODE signal conditioning amplifier driving the analog input (V ). IN Control Signal Reference Input The HI5812 may be synchronized from an external source by using the STRT (Start Conversion) input to initiate The reference input V + should be driven from a low REF conversion, or if STRT is tied low, may be allowed to free impedance source and be well decoupled. run. Each conversion cycle takes 15 clock periods. As shown in Figure 20, current spikes are generated on the The input is tracked from clock period 1 through period 3, reference pin during each bit test of the successive then disconnected as the successive approximation takes approximation part of the conversion cycle as the charge- place. After the start of the next period 1 (specified by t balancing capacitors are switched between V - and D REF data), the output is updated. V + (clock periods 5 - 14). These current spikes must REF settle completely during each bit test of the conversion to not The DRDY (Data Ready) status output goes high (specified degrade the accuracy of the converter. Therefore V + and REF by t DRDY) after the start of clock period 1, and returns low D1 V - should be well bypassed. Reference input V - is REF REF (specified by t DRDY) after the start of clock period 2. D2 normally connected directly to the analog ground plane. If The 12 data bits are available in parallel on three-state bus V - is biased for nulling the converters offset it must be REF driver outputs. When low, the OEM input enables the most stable during the conversion cycle. significant byte (D4 through D11) while the OEL input enables the four least significant bits (D0 - D3). t and t EN DIS 20mA specify the output enable and disable times. I If the output data is to be latched externally, either the trailing REF+ 10mA edge of data ready or the next falling edge of the clock after 0mA data ready goes high can be used. When STRT input is used to initiate conversions, operation is 5V slightly different depending on whether an internal or CLK external clock is used. 0V Figure 3 illustrates operation with an internal clock. If the 5V DRDY STRT signal is removed (at least t STRT) before clock R 0V period 1, and is not reapplied during that period, the clock 2µs/DIV. will shut off after entering period 2. The input will continue to CONDITIONS: V = V + = 5.0V, V + = 4.608V, track and the DRDY output will remain high during this time. DD AA REF o V = 2.3V, CLK = 750kHz, T = 25 C IN A A low signal applied to STRT (at least t STRT wide) can W FIGURE 20. TYPICAL REFERENCE INPUT CURRENT now initiate a new conversion. The STRT signal (after a delay of (t STRT)) causes the clock to restart. D 11 HI5812 Depending on how long the clock was shut off, the low Power Supplies and Grounding portion of clock period 2 may be longer than during the V and V are the digital supply pins: they power all DD SS remaining cycles. internal logic and the output drivers. Because the output drivers can cause fast current spikes in the V and V The input will continue to track until the end of period 3, the DD SS lines, V should have a low impedance path to digital same as when free running. SS ground and V should be well bypassed. DD Figure 2 illustrates the same operation as above but with an Except for V +, which is a substrate connection to V , all external clock. If STRT is removed (at least t STRT) before AA DD R pins have protection diodes connected to V and V . clock period 2, a low signal applied to STRT will drop the DD SS Input transients above V or below V will get steered to DRDY flag as before, and with the first positive-going clock DD SS the digital supplies. edge that meets the (t STRT) setup time, the converter will SU continue with clock period 3. The V + and V - terminals supply the charge-balancing AA AA comparator only. Because the comparator is autobalanced Clock between conversions, it has good low-frequency supply The HI5812 can operate either from its internal clock or from rejection. It does not reject well at high frequencies however; one externally supplied. The CLK pin functions either as the V - should be returned to a clean analog ground and V + AA AA clock output or input. All converter functions are should be RC decoupled from the digital supply as shown in synchronized with the rising edge of the clock signal. Figure 22. Figure 21 shows the configuration of the internal clock. The There is approximately 50Ω of substrate impedance clock output drive is low power: if used as an output, it between V and V +. This can be used, for example, as DD AA should not have more than 1 CMOS gate load applied, and part of a low-pass RC filter to attenuate switching supply stray wiring capacitance should be kept to a minimum. noise. A 10µF capacitor from V + to ground would AA The internal clock will shut down if the A/D is not restarted attenuate 30kHz noise by approximately 40dB. Note that after a conversion. The clock could also be shut down with back-to-back diodes should be placed from V to V + to DD AA an open collector driver applied to the CLK pin. This should handle supply to capacitor turn-on or turn-off current spikes. only be done during the sample portion (the first three clock Dynamic Performance periods) of a conversion cycle, and might be useful for using Fast Fourier Transform (FFT) techniques are used to the device as a digital sample and hold. evaluate the dynamic performance of the A/D. A low If an external clock is supplied to the CLK pin, it must have distortion sine wave is applied to the input of the A/D sufficient drive to overcome the internal clock source. The converter. The input is sampled by the A/D and its output external clock can be shut off, but again, only during the stored in RAM. The data is than transformed into the sample portion of a conversion cycle. At other times, it must frequency domain with a 4096 point FFT and analyzed to be above the minimum frequency shown in the evaluate the converters dynamic performance such as SNR specifications. In the above two cases, a further restriction and THD. See typical performance characteristics. applies in that the clock should not be shut off during the Signal-To-Noise Ratio third sample period for more than 1ms. This might cause an internal charge-pump voltage to decay. The signal to noise ratio (SNR) is the measured RMS signal to RMS sum of noise at a specified input and sampling If the internal or external clock was shut off during the frequency. The noise is the RMS sum of all except the conversion time (clock cycles 4 through 15) of the A/D, the fundamental and the first five harmonic signals. The SNR is output might be invalid due to balancing capacitor droop. dependent on the number of quantization levels used in the An external clock must also meet the minimum t and converter. The theoretical SNR for an N-bit converter with no LOW t times shown in the specifications. A violation may differential or integral linearity error is: SNR = (6.02N + 1.76) HIGH cause an internal miscount and invalidate the results. dB. For an ideal 12-bit converter the SNR is 74dB. Differential and integral linearity errors will degrade SNR. INTERNAL Sinewave Signal Power ENABLE SNR = 10 Log Total Noise Power CLOCK CLK OPTIONAL Signal-To-Noise + Distortion Ratio EXTERNAL CLOCK 100kΩ SINAD is the measured RMS signal to RMS sum of noise 18pF plus harmonic power and is expressed by the following: Sinewave Signal Power FIGURE 21. INTERNAL CLOCK CIRCUITRY SINAD = 10 Log Noise + Harmonic Power (2nd - 6th) 12 HI5812 the fundamental RMS signal for a specified input and Effective Number of Bits sampling frequency. The effective number of bits (ENOB) is derived from the SINAD data; Total Harmonic Power (2nd - 6th Harmonic) THD = 10 Log SINAD - 1.76 Sinewave Signal Power ENOB = 6.02 Spurious-Free Dynamic Range The spurious-free dynamic range (SFDR) is the ratio of the Total Harmonic Distortion fundamental RMS amplitude to the RMS amplitude of the The total harmonic distortion (THD) is the ratio of the RMS next largest spur or spectral component. If the harmonics are sum of the second through sixth harmonic components to buried in the noise floor it is the largest peak. Sinewave Signal Power SFDR = 10 Log Highest Spurious Signal Power TABLE 2. CODE TABLE BINARY OUTPUT CODE INPUT VOLTAGE† V = 4.608V MSB LSB REF+ CODE V = 0.0V DECIMAL REF- D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION (V) COUNT Full Scale (FS) 4.6069 4095 1 1 1 1 1 1 1 1 1 1 1 1 FS - 1 LSB 4.6058 4094 1 1 1 1 1 1 1 1 1 1 1 0 3 / FS 3.4560 3072 1 1 0 0 0 0 0 0 0 0 0 0 4 1 / FS 2.3040 2048 1 0 0 0 0 0 0 0 0 0 0 0 2 1 / FS 1.1520 1024 0 1 0 0 0 0 0 0 0 0 0 0 4 1 LSB 0.001125 1 0 0 0 0 0 0 0 0 0 0 0 1 Zero 0 0 0 0 0 0 0 0 0 0 0 0 0 0 † The voltages listed above represent the ideal lower transition of each output code shown as a function of the reference voltage. +5V 0.1µF 4.7µF 10µF 0.1µF 0.01µF V+V AA DD D11 . . OUTPUT . DATA D0 V REF V REF+ 0.001µF 4.7µF 0.1µF DRDY OEM OEL ANALOG V IN INPUT STRT CLK 750kHz CLOCK V V V REF- AA- SS FIGURE 22. GROUND AND SUPPLY DECOUPLING 13 HI5812 Die Characteristics DIE DIMENSIONS: PASSIVATION: 3200µm x 3940µm Type: PSG Thickness: 13kÅ ±2.5kÅ METALLIZATION: WORST CASE CURRENT DENSITY: Type: AlSi 5 2 Thickness: 11kÅ ±1kÅ 1.84 x 10 A/cm Metallization Mask Layout HI5812 D0 D1 (LSB) DRDY V OEL DD CLK D2 STRT D3 V - REF D4 D5 V + D6 REF D7 V IN D8 V + AA V - AA D9 V D10 D11 OEM SS (MSB) 14 HI5812 Dual-In-Line Plastic Packages (PDIP) E24.3 (JEDEC MS-001-AF ISSUE D) N 24 LEAD NARROW BODY DUAL-IN-LINE PLASTIC E1 PACKAGE INDEX 12 3 N/2 AREA INCHES MILLIMETERS -B- SYMBOL MIN MAX MIN MAX NOTES -A- A - 0.210 - 5.33 4 D E A1 0.015 - 0.39 - 4 BASE PLANE A2 A A2 0.115 0.195 2.93 4.95 - -C- SEATING B 0.014 0.022 0.356 0.558 - PLANE L C L B1 0.045 0.070 1.15 1.77 8 D1 e A1 A D1 C 0.008 0.014 0.204 0.355 - e B1 e C C B D 1.230 1.280 31.24 32.51 5 e B 0.010 (0.25) M C A BS D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and E1 0.240 0.280 6.10 7.11 5 Metric dimensions, the inch dimensions control. e 0.100 BSC 2.54 BSC - 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. e 0.300 BSC 7.62 BSC 6 A 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of e - 0.430 - 10.92 7 Publication No. 95. B 4. Dimensions A, A1 and L are measured with the package seated in L 0.115 0.150 2.93 3.81 4 JEDEC seating plane gauge GS-3. N24 24 9 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Rev. 0 12/93 Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and e are measured with the leads constrained to be perpendic- A ular to datum -C- . 7. e and e are measured at the lead tips with the leads unconstrained. B C e must be zero or greater. C 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 15 HI5812 Small Outline Plastic Packages (SOIC) M24.3 (JEDEC MS-013-AD ISSUE C) N 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX 0.25(0.010) M B M H AREA INCHES MILLIMETERS E SYMBOL MIN MAX MIN MAX NOTES -B- A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - 12 3 L B 0.013 0.020 0.33 0.51 9 SEATING PLANE C 0.0091 0.0125 0.23 0.32 - -A- o D 0.5985 0.6141 15.20 15.60 3 A h x 45 D E 0.2914 0.2992 7.40 7.60 4 -C- e 0.05 BSC 1.27 BSC - αµ H 0.394 0.419 10.00 10.65 - e A1 C h 0.010 0.029 0.25 0.75 5 B 0.10(0.004) L 0.016 0.050 0.40 1.27 6 0.25(0.010) M C A M BS N24 24 7 o o o o 0 8 0 8 - NOTES: α 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Rev. 0 12/93 Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16