EL4093 ® Data Sheet January 1996, Rev B FN7159 300MHz DC-Restored Video Amplifier Features The EL4093 is a complete DC- • High accuracy DC restoration for video restored video amplifier subsystem, • Low supply current of 9.5mA typ. featuring low power consumption and • 300MHz bandwidth high slew rate. It contains a current feedback amplifier and a sample and hold amplifier designed to stabilize video • 1500V/µs slew rate performance. When the HOLD logic input is low, the sample • 0.04% differential gain and 0.02° differential phase into and hold may be used as a general purpose op amp to null 150Ω for NTSC the DC offset of the video amplifier. When the HOLD input goes high the sample and hold stores the correction voltage • 1.5mV max. restored DC offset on the hold capacitor to maintain DC correction during the • Sample and hold amplifier with fast enable and low subsequent video scan line. leakage The sample and hold amplifier contains a current output • TTL-compatible HOLD logic input stage that greatly simplifies its connection to the video amplifier. Its high output impedance also helps to preserve Applications video linearity at low supply voltages. For ease of interfacing, • Input amplifier in video equipment the HOLD input is TTL-compatible. This device has an operational temperature of -40°C to +85°C and is packaged • Restoration amplifier in video mixers in plastic 16-pin DIP and 16-pin SOIC. Ordering Information Pinout PART NUMBER TEMP. RANGE PACKAGE PKG. NO. EL4093 EL4093CN -40°C to +85°C 16-Pin PDIP MDP0031 (16-PIN PDIP, SO) EL4093CS -40°C to +85°C 16-Pin SOIC MDP0027 TOP VIEW Demo Board A demo PCB is available for this product. Request “EL4093 Demo Board.” CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. OBSOLETE PRODUCT NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc EL4093 Absolute Maximum Ratings (T = 25°C) A V V+ to V- Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 12.6V I S/H amplifier output current . . . . . . . . . . . . . . . . . . . . ±10mA S OUT2 V Voltage at HOLD input I Maximum current into other pins. . . . . . . . . . . . . . . . . . ±6mA HOLD IN (DGND-0.7) to (DGND+5.5V) P Maximum Power Dissipation. . . . . . . . . . . . . . . . See Curves D V Voltage at any other input . . . . . . . . . . . . . . . . . . . . . V+ to V- T Operating Ambient Temperature Range . . . . .-40°C to +85°C IN A ΔV Difference between Sample and Hold inputs . . . . . . . . . .±8V T Operating Junction Temperature. . . . . . . . . . . . . . . . . . 150°C IN J I Video amplifier output current . . . . . . . . . . . . . . . . . . . ±30mA T Storage Temperature Range. . . . . . . . . . . . .-65°C to +150°C OUT1 ST CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T = T = T J C A Open-Loop DC Electrical Specifications Power supplies at ±5V, T = 25°C A Sample and Hold PARAMETER DESCRIPTION MIN TYP MAX UNITS I Total Supply current in HOLD mode 9.5 11.5 mA S,HOLD I Total Supply current in SAMPLE mode 8.5 10.5 mA S,SAMPLE Video Amplifier Section (Not Restored) PARAMETER DESCRIPTION MIN TYP MAX UNITS V Input Offset Voltage 10 110 mV OS I + Non-Inverting Input Bias Current 10 25 µA B I - Inverting Input Bias Current 15 50 µA B R Transimpedance, V = ±2.5V, R = 150Ω 150 400 kΩ OL OUT L V Output Voltage Swing, R = 150Ω ±3 ±3.5 V O L I Output Short-Circuit Current 60 100 mA SC Open-Loop DC Electrical Specifications Power supplies at ±5V, T = 25°C A Sample and Hold Section PARAMETER DESCRIPTION MIN TYP MAX UNITS V Input Offset Voltage 0.5 1.5 mV OS TCV Average Offset Voltage Drift 6 µV/°C OS I Input Bias Current 12 µA B I Input Offset Current 10 200 nA OS TCI Average Offset Current Drift 0.1 nA/°C OS V Common Mode Input Range ±2.5 ±2.8 V CM g Transconductance (R = 500Ω)515 A/V M L CMRR Common Mode Rejection Ratio (V -2.5V to +2.5V) 70 90 dB CM V HOLD Logic Input Low (referenced to Digital GND) 0.8 V IL V HOLD Logic Input High (referenced to Digital GND) 2.0 V IH V Digital GND Reference Voltage (V-) (V+) - 4.0 V GND I Hold Mode Droop Current 10 70 nA DROOP I Charge Current Available to C ±5.5 ±8.5 mA CHARGE HOLD V Output Voltage Swing (R = 10kΩ)±3±3.5 V O L I Output Current Swing (R = 0Ω) ±4.5 ±5.5 mA O L 2 EL4093 Closed-Loop AC Electrical Specifications Power supplies at ±5V, T = 25°C, R = R = 750Ω, R = 150Ω, C = 5pF, C - A F G L L IN (parasitic) = 1.8pF Video Amplifier Section PARAMETER DESCRIPTION MIN TYP MAX UNITS BW, -3dB -3dB Small-Signal Bandwidth 300 MHz BW, ±0.1dB 0.1dB Flatness Bandwidth 50 MHz Peaking Frequency Response Peaking 0 dB SR Slew rate, V between -2V and +2V 1500 V/µs OUT dG Differential Gain Error, Voffset between -714mV and +714mV 0.04 % dθ Differential Phase Error, Voffset between -714mV and +714mV 0.02 ° Closed-Loop AC Electrical Specifications Power supplies at ±5V, T = 25°C, R = R = 750Ω, R = 150Ω, C = 5pF, A F G L L C =2.2nF HOLD Sample and Hold Section PARAMETER DESCRIPTION MIN TYP MAX UNITS ΔI Change in Sample to Hold Output Current Due to Hold Step 0.1 µA STEP ΔT Sample to Hold Delay Time 15 ns SH ΔT Hold to Sample Delay Time 40 ns HS T Settling Time to 1% (DC Restored Amplifier Output) Video Amplifier Input 2.2 µs AC from 0 to 1V Typical Application 3 EL4093 Typical Performance Curves Non-inverting Frequency Frequency Response Non-inverting Frequency Response (Phase) for Various R L Response (Gain) Inverting Frequency Inverting Frequency Frequency Response Response (Gain) Response (Phase) for Various C L Frequency Response for 3dB Bandwidth vs Frequency Response Various R and R Temperature (Video Amp) F G for Various C IN 4 EL4093 Typical Performance Curves (Continued) Peaking vs Temperature Output Voltage 2nd and 3rd Harmonic (Video Amp) Swing vs Frequency Distortion vs Frequency Voltage and Current Supply Current Noise vs Frequency vs Temperature Input Offset Voltage vs Die Temperature Input Bias Current vs Transimpedance vs (Video Amp, 3 Sample) Temperature (Video Amp) Temperature (Video Amp) 5 EL4093 Typical Performance Curves (Continued) Input Offset Voltage Input Bias Current vs vs Die Temperature Die Temperature Transconductance vs (Sample & Hold, 3 Samples) (Sample & Hold) Temperature (Sample & Hold) Transconductance vs Die Temperature Output Current Swing vs (Sample & Hold) Temperature (Sample & Hold) Droop Current Charge Current vs vs Temperature Temperature Hold Step (ΔI ) OUT (Sample & Hold) (Sample & Hold) vs Temperature 6 EL4093 Typical Performance Curves (Continued) Differential Gain and Differential Gain and Phase vs DC Input Phase vs DC Input Slew Rate vs Die Voltage at 3.58MHz Voltage at 3.58MHz Temperature (Video Amp) Small-Signal Step Response Large-Signal Step Response Settling Time vs Maximum Power Dissipation Maximum Power Dissipation Settling Accuracy vs Ambient Temperature, vs Ambient Temperature, (Video Amp) 16-Pin PDIP Package 16-Pin SO Package The connection between the CFA and sample & hold (the Applications Information Autozero interface) has been greatly simplified. The output Product Description of the sample & hold is a high impedance current source, The EL4093 is a high speed DC-restore system containing a allowing direct connection to the CFA inverting input for current feedback amplifier (CFA) and a sample & hold (S/H) autozero purposes. In addition, special circuitry within the amplifier. The CFA offers a wide 3dB bandwidth of 300MHz sample & hold provides a charge current of 8.5mA in sample and a slew rate of 1500V/µs, making it ideal for high speed mode, resulting in a sample hold current ratio (ratio of video applications such as SVGA. The CFA’s excellent charging current to droop current) of approx. 1,000,000. differential gain and phase at 3.58MHz also makes it suitable Theory of Operation for NTSC applications. Drawing only 9.5mA on ±5V supplies, In video applications, DC restoration moves the backporch the EL4093 serves as an excellent choice for those or black level to a fixed DC reference. The EL4093 uses a applications requiring both low power and high bandwidth. CFA in feedback with a sample & hold to provide DC 7 EL4093 restoration. Figure 1 shows how the two are connected to be well bypassed to reduce the risk of oscillation. In the provide this function; the S/H compares the output of the EL4093 there are two sets of supply pins: V+1/V-1 provide CFA to a DC reference, and any difference between them power for the CFA, and V+2/V-2 are for the S/H amplifier. causes an output current from the S/H. This “autozero” Good performance can be achieved using only one set of current is fed to the CFA inverting input, the effect of which is bypass capacitors, although they must be close to the to move the CFA output towards the reference voltage. This V+1/V-1 pins since that is where the high frequency currents autozero mechanism settles when the CFA output is one flow. The combination of a 4.7µF tantalum capacitor in V away from the reference (the V here refers to the parallel with a 0.01µF capacitor has been shown to work OS OS S/H offset voltage). well. Chip capacitors are recommended for the 0.01µF bypass to minimize lead inductance. For good AC performance, parasitic capacitance should be kept to a minimum, especially at the CFA inverting input. Ground plane construction should be used, but it should be removed from the area near the inverting input to minimize any stray capacitance at that node. Chip resistors are recommended for R and R , and use of sockets should be F G avoided if possible. Sockets add parasitic inductance and capacitance which will result in some additional peaking and overshoot. If the CFA is configured for non-inverting gain, then one should also pay attention to the trace leading to the +input. The inductance of a long trace (> 3’) can form a resonant network with the amplifier input, resulting in high frequency FIGURE 1. oscillations around 700MHz. In such cases a 50Ω–100Ω The autozero mechanism is typically active for only a short series resistor placed close to the +input would isolate this period of each video line. Figure 2 shows a NTSC video inductance and damp out the resonance. signal along with the EL4581 back porch output. The back Capacitance at the Inverting Input porch signal is used to drive the HOLD input of the EL4093, and we see that the EL4093 is in sample mode for only Any manufacturer’s high-speed voltage or current feedback 3.5µs of each line. It is during this time that the autozero amplifier can be affected by stray capacitance at the mechanism attempts to drive the CFA output towards the inverting input. For inverting gains this parasitic capacitance reference voltage, at the same time putting a correction has little effect because the inverting input is a virtual voltage onto the hold capacitor C . During the rest of ground, but for non-inverting gains this capacitance (in HOLD the line (60µs) the EL4093 is in hold mode, but DC conjunction with the feedback and gain resistors) creates a correction is maintained by the voltage on C . pole in the feedback path of the amplifier. This pole, if low HOLD enough in frequency, has the same destabilizing effect as a zero in the forward open-loop response. Hence it is important to minimize the stray capacitance at this node by removing the nearby ground plane. In addition, since the S/H output connects to this node, it is important to minimize the trace capacitance. Good practice here would be to connect the two pins with a short trace directly underneath the chip. Feedback Resistor Values The EL4093 has been optimized for a gain of +2 with R =750Ω. This value of feedback resistor gives a 3dB F bandwidth of 300MHz at a gain of +2 driving a 150Ω load. FIGURE 2. Since the amplifier inside the EL4093 uses current mode feedback, it is possible to change the value of R to adjust F Power Supply Bypassing and Printed Circuit the bandwidth. Shown in the table below are optimum Board Layout feedback resistor values for different closed loop gains. As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended. Lead lengths should be as short as possible. The power supply pins must 8 EL4093 can come from the S/H output. Since the maximum that I AZ be is 5.5mA, we can solve for V using the following: DC GAIN OPTIMUM RF BW (MHz) PEAKING (dB) V DC ⎛⎞ 5.5mA 2 I = ± = --------------- AZ ⎝⎠ 750Ω +1 910 314 0.2 and see that V = ±2V. This range can easily DC +2 750 300 0 accommodate most video signals. +5 470 294 0.2 As another example, consider the case where we are -1 680 300 0 restoring to a reference voltage of +0.75V. Using the same reasoning as above, a current I = (V - 0.75V)/R must RF DC F Autozero Interface flow through R , and a current I = V /R must go into F RG DC G R . Again, our boundary condition is that I + I The autozero interface refers to the connection between the G RF RG ≤ ±5.5mA, and we can solve for the allowable V values S/H output and the CFA inverting input. This interface has DC using the following: been greatly simplified compared to that of the EL2090, in that the S/H output is a high impedance current source. The V – 0.75V V DC DC S/H output can be connected directly to the inverting input, ±5.5mA= ---------------------------------- + --------------- 750Ω 750Ω and its high impedance greatly reduces the interaction between the sample & hold and the gain setting resistors. Hence V must be between +2.4V to -1.7V. This example DC Another virtue of this interface is better gain linearity as the illustrates that when the reference changes, the autozero autozero current changes. For example, at an autozero range also changes. In general, the user should determine current of 0mA the output impedance is about 5MΩ, the autozero range for his/her application, and ensure that dropping to 1MΩ as the autozero current increases to 3mA. the input signal is within this range during the autozero Using R = R = 750Ω, the closed loop gain changes only F G period. by 0.025% in this interval. Autozero Loop Bandwidth Autozero Range The gain-bandwidth product (GBWP) of the autozero loop is The autozero range is defined as the difference between the determined by the size of the hold capacitor, the value of R , F input DC level and the reference voltage to restore to. The and the transconductances (gm’s) of the S/H amplifier. To size of this range is a function of the gain setting resistors begin, the S/H amplifier is modeled as in Figure 4. First, the used and the S/H output current swing. For a gain of +2 the input stage transconductance is represented by gm1, with optimum feedback resistor is 750Ω, and the available S/H the compensation capacitor given by C . This stage’s HOLD output current is ±5.5mA minimum. To determine the GBWP is thus gm1/(2π • C ) = 1/(2π • (350Ω)(2.2nF)) = HOLD autozero range for this case, we refer to Figure 3 below. 207kHz. Next, since the S/H has a current output, its output stage can be modeled as a transconductance gm2, in this case having a value of 1/(500Ω). The current from gm2 then flows through the I to V converter made up of the CFA and R to produce a voltage gain. Thus the GBWP of the overall F loop is given by: gm1 = () × GBWP --------------------------------- gm2 R F 2π× C HOLD FIGURE 3. Suppose that the input DC level is +V , and that the DC reference voltage is 0V. We know that in feedback, the following two conditions will exist on the CFA: first, its output will be equal to 0V (due to autozero), and second, its V - IN voltage is equal to the V + voltage (i.e. V - = +V ). So IN IN DC we have a potential difference of +V across both R and DC F R , resulting in a current I = I = V /750Ω that must G RF RG DC flow into each of them. This current I = (I + I ) must AZ RF RG 9 EL4093 FIGURE 4. With R = 750Ω, a GBWP of 310kHz is obtained. Note the hold capacitor voltage, which in turn produces a similar F however that this is the small signal GBWP. As mentioned effect at the CFA output. The Droop Rate at the CFA output earlier, the sample and hold has special boost circuits built in can be found using the equation below: which provides ±8.5mA of charge current during full slew. I DROOP These boost circuits turn on when the S/H input differential Droop = ----------------------() gm2× R F C HOLD voltage exceeds ±50mV. When the boosters are turned on, gm1 greatly increases and the circuit becomes nonlinear. Thus some stability issues are associated with the boosters, Assuming R = 750Ω and C = 2.2nF, the drift in the F HOLD and they will be addressed in a later section. CFA output due to droop current is about 7µV/µs. Recall that in NTSC applications, there is about 60µs between autozero Charge Injection and Hold Step periods. Thus there is 7µV/µs(60µs) = 0.4mV, or less than Charge injection refers to the charge transferred to the hold 0.1 IRE, of drift over each NTSC scan line. This drift is capacitor when switching to the HOLD mode. The charge negligible in most applications. should ideally be 0, but due to stray capacitive coupling and Choice of Hold Capacitor other effects, is typically 0.1pC in the EL4093. This charge changes the hold capacitor voltage by ΔV = ΔQ/C , and The EL4093 has been designed to work with a hold HOLD this ΔV is multiplied by the output stage transconductance capacitor of 2.2nF. With this value of C , the droop rate HOLD (gm2) to produce a change in S/H output current. This last and hold step are negligibly small for most applications. In quantity is listed as the spec ΔI , and is calculated using addition, with the special boost circuits inside the S/H, fast STEP the following: acquisition is possible even using a hold capacitor of this size. Figure 5 shows the input and output of the DC-restored ΔQ ⎛⎞ ΔI = -------------------- × gm2 amplifier while the S/H is in sample mode. Applying a +1V SEP ⎝⎠ C HOLD step to the non-inverting input of the CFA, the output of the CFA jumps to +2V. The S/H, however, then tries to autozero For C = 2.2nF and gm2 = 1/(500Ω), ΔI has a the system by driving the CFA output back to the reference HOLD STEP typical value of 100nA. This change in S/H output current voltage. Since the input differential across the S/H is initially flows through R , shifting the CFA output voltage. However, +2V, the boost circuits turn on and supply 8.5mA of charge F as we shall soon see, this shift is negligible. Assuming current to the hold capacitor. The boost circuit remains on R =750Ω, ΔI is impressed across R to give until the CFA output has come to within 50mV of the F STEP F (750Ω)(100nA) = 0.08mV of change at the CFA output. reference. Note that this event took only 320ns; settling to within 1% of the final value takes another 2µs. Thus for a 1V Droop Rate input step, acquisition takes only one to two NTSC scan When the S/H amplifier is in HOLD mode, there is a small lines. current that leaks from the switch into the hold capacitor. This quantity is termed the droop current, and is typically 10nA in the EL4093. This droop current produces a ramp in 10 EL4093 A remedy for this situation is to attenuate the colorburst before applying it to the S/H input. Figure 6 below shows a 3.58MHz chroma trap which would notch out the colorburst while preserving the video DC level. FIGURE 5. AUTOZERO MECHANISM RESTORES AMPLIFIER OUTPUT TO GROUND AFTER +1V STEP AT INPUT A natural question arises as to whether there are other FIGURE 6. COLORBURST TRAP FOR NTSC C values that can be used. In one direction, increasing HOLD APPLICATIONS C will further reduce the droop and hold step, but HOLD One may be tempted to use a RC lowpass filter to suppress lengthen the acquisition time. Since the droop and hold step the colorburst, as shown in Figure 7 below. This technique, are already small to begin with, there is no apparent however, poses several problems. First, to obtain enough advantage to increasing C . HOLD attenuation, we need to set the pole frequency 10 to 20 times lower than 3.58MHz. This pole, being close to the auto In the other direction, decreasing C would increase the HOLD zero loop pole, would destabilize the system and cause the droop and hold step but shorten the acquisition time. There loop to oscillate. is, however, a caveat to reducing C : too small a C HOLD HOLD would cause the autozero loop to oscillate. The reason is that when the S/H boost circuit turns on, the input stage gm increases drastically and the circuit becomes nonlinear. A sufficiently large C must be used to suppress the non- HOLD linearity and force the loop to settle. For example, it has been found that a C of 470pF results in 1V HOLD P-P oscillation around 10MHz at the CFA output. The minimum recommended value for C is 2.2nF. With HOLD this value the loop remains stable over the entire operating temperature range (-40°C to +85°C). The greatest instability occurs at low temperatures, where we observe from the performance curves that the S/H gm’s, and hence the FIGURE 7. CAUTION: LOWPASS FILTER DOES GBWP, are at their maximum. If the operating range is NOT WORK IN NTSC APPLICATIONS restricted to room temperature or above, then 1.5nF is Although we can cancel this pole by introducing a zero, the sufficient to keep the loop stable. At this value of C the HOLD RC network introduces a time delay between the CFA output acquisition time reduces to about 1.5µs. and the S/H input. This has undesirable effects in some Video Performance and Application NTSC applications, as Figure 8 illustrates. There is only Although the EL4093 is intended for high speed video 0.6µs from the rising edge of sync to the colorburst. If we are applications such as SVGA, it also offers excellent autozeroing over the back porch, the autozero period would performance for NTSC, with 0.04% dG and 0.02° dP at begin somewhere in this 0.6µs interval. Since the edge of 3.58MHz. Some application considerations, however, are sync is now delayed by the RC network, autozero begins required for handling NTSC signals. before the video back porch reaches its final value. Consequently, the autozero loop performs a correction on Referring back to Figure 2, recall that typically, the autozero every line and never settles. interval lies in the back porch portion of video containing the colorburst pulse. When the S/H compares the video to the reference voltage during this period, the colorburst (40 IRE ) triggers the S/H boost circuit and prevents the P-P autozero loop from settling. 11 EL4093 FIGURE 8. LOWPASS FILTER DELAYS INPUT TO SAMPLE AND HOLD If the video does not contain any AC components during the where: autozero level (e.g. RGB video), then the above networks V = Supply Voltage S are not needed and the CFA output can be connected directly to the S/H input. I = Maximum Supply Current of Amplifier SMAX Power Dissipation V = Maximum Output Voltage of Application OUTMAX The EL4093 current feedback amplifier has an absolute R = Load Resistance L maximum of ±30mA output current drive. This is slightly For the EL4093, the maximum supply current is 11.5mA on more than the current required to drive ±2V into 75Ω. To see V = ±5V. Assume that in the worst case, the CFA output S how much the junction temperature is raised in this worst swings ±2V into 75Ω. Since the S/H has a current output, we case, we refer to the equations below: assume that it is at maximum current swing (±5.5mA) but at T = T + (θ • PD ) JMAX MAX JA MAX a mid-rail output voltage (0V). With the above assumptions, PD for the EL4093 is 223mW, and using the thermal MAX where: resistance of a narrow SO package (120°C/W), this yields a T = Maximum Ambient Temperature MAX temperature increase of 27°C. Since the maximum ambient temperature is 85°C, the resulting junction temperature of θ = Thermal Resistance of the Package JA 112°C is still below the maximum. PD = Maximum Power Dissipation of the CFA and S/H MAX Please note that this in addition to metal migration problems. amplifier in the Package PD for either the CFA or the S/H amplifier can be MAX calculated as follows: PD = (2•V •I ) + (V - V ) • MAX S SMAX S OUTMAX (V /R ) OUTMAX L All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. 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