® Intel StrataFlash Embedded Memory (P30) 1-Gbit P30 Family Datasheet Product Features ■ High performance ■ Security — 85/88 ns initial access — One-Time Programmable Registers: • 64 unique factory device identifier bits — 40 MHz with zero wait states, 20 ns clock-to- • 64 user-programmable OTP bits data output synchronous-burst read mode • Additional 2048 user-programmable OTP bits — 25 ns asynchronous-page read mode — Selectable OTP Space in Main Array: — 4-, 8-, 16-, and continuous-word burst mode • 4x32KB parameter blocks + 3x128KB main — Buffered Enhanced Factory Programming blocks (top or bottom configuration) (BEFP) at 5 µs/byte (Typ) — Absolute write protection: V = V PP SS — 1.8 V buffered programming at 7 µs/byte (Typ) — Power-transition erase/program lockout ■ Architecture — Individual zero-latency block locking — Multi-Level Cell Technology: Highest Density — Individual block lock-down at Lowest Cost ■ Software — Asymmetrically-blocked architecture — 20 µs (Typ) program suspend — Four 32-KByte parameter blocks: top or — 20 µs (Typ) erase suspend bottom configuration ® —Intel Flash Data Integrator optimized — 128-KByte main blocks — Basic Command Set and Extended Command ■ Voltage and Power Set compatible —V (core) voltage: 1.7 V – 2.0 V CC — Common Flash Interface capable —V (I/O) voltage: 1.7 V – 3.6 V CCQ ■ Density and Packaging — Standby current: 55 µA (Typ) for 256-Mbit — 64/128/256-Mbit densities in 56-Lead TSOP — 4-Word synchronous read current: package 13 mA (Typ) at 40 MHz — 64/128/256/512-Mbit densities in 64-Ball ■ Quality and Reliability Intel® Easy BGA package — Operating temperature: –40 °C to +85 °C • 1-Gbit in SCSP is –30 °C to +85 °C — 64/128/256/512-Mbit and 1-Gbit densities in Intel® QUAD+ SCSP — Minimum 100,000 erase cycles per block — 16-bit wide data bus — ETOX™ VIII process technology (130 nm) ® The Intel StrataFlash Embedded Memory (P30) product is the latest generation of Intel ® StrataFlash memory devices. Offered in 64-Mbit up through 1-Gbit densities, the P30 device brings reliable, two-bit-per-cell storage technology to the embedded flash market segment. Benefits include more density in less space, high-speed interface, lowest cost-per-bit NOR device, and support for code and data storage. Features include high-performance synchronous- burst read mode, fast asynchronous access times, low power, flexible security options, and three industry standard package choices. ® The P30 product family is manufactured using Intel 130 nm ETOX™ VIII process technology. Order Number: 306666, Revision: 001 April 2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information. StrataFlash® Embedded Memory (P30) Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © 2005, Intel Corporation * Other names and brands may be claimed as the property of others. ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 2 Order Number: 306666, Revision: 001 1-Gbit P30 Family Contents 1.0 Introduction ...............................................................................................................................7 1.1 Nomenclature .......................................................................................................................7 1.2 Acronyms..............................................................................................................................7 1.3 Conventions..........................................................................................................................8 2.0 Functional Overview ..............................................................................................................9 3.0 Package Information ............................................................................................................10 3.1 56-Lead TSOP Package.....................................................................................................10 3.2 64-Ball Easy BGA Package ................................................................................................12 3.3 QUAD+ SCSP Packages....................................................................................................13 4.0 Ballout and Signal Descriptions......................................................................................17 4.1 Signal Ballout......................................................................................................................17 4.2 Signal Descriptions .............................................................................................................20 4.3 SCSP Configurations..........................................................................................................22 4.4 Memory Maps .....................................................................................................................24 5.0 Maximum Ratings and Operating Conditions ...........................................................29 5.1 Absolute Maximum Ratings ................................................................................................29 5.2 Operating Conditions ..........................................................................................................30 6.0 Electrical Specifications .....................................................................................................31 6.1 DC Current Characteristics.................................................................................................31 6.2 DC Voltage Characteristics.................................................................................................32 7.0 AC Characteristics ................................................................................................................33 7.1 AC Test Conditions.............................................................................................................33 7.2 Capacitance........................................................................................................................34 7.3 AC Read Specifications ......................................................................................................35 7.4 AC Write Specifications ......................................................................................................41 7.5 Program and Erase Characteristics....................................................................................45 8.0 Power and Reset Specifications .....................................................................................46 8.1 Power Up and Down...........................................................................................................46 8.2 Reset Specifications ...........................................................................................................46 8.3 Power Supply Decoupling...................................................................................................47 9.0 Device Operations.................................................................................................................48 9.1 Bus Operations ...................................................................................................................48 9.1.1 Reads ....................................................................................................................48 9.1.2 Writes.....................................................................................................................49 9.1.3 Output Disable .......................................................................................................49 9.1.4 Standby..................................................................................................................49 9.1.5 Reset .....................................................................................................................49 9.2 Device Commands .............................................................................................................50 9.3 Command Definitions .........................................................................................................51 ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 3 1-Gbit P30 Family 10.0 Read Operations.................................................................................................................... 53 10.1 Asynchronous Page-Mode Read........................................................................................53 10.2 Synchronous Burst-Mode Read.......................................................................................... 53 10.3 Read Configuration Register .............................................................................................. 54 10.3.1 Read Mode ............................................................................................................55 10.3.2 Latency Count........................................................................................................ 55 10.3.3 WAIT Polarity......................................................................................................... 57 10.3.4 Data Hold............................................................................................................... 58 10.3.5 WAIT Delay............................................................................................................59 10.3.6 Burst Sequence ..................................................................................................... 59 10.3.7 Clock Edge ............................................................................................................59 10.3.8 Burst Wrap.............................................................................................................59 10.3.9 Burst Length .......................................................................................................... 60 11.0 Programming Operations ..................................................................................................61 11.1 Word Programming.............................................................................................................61 11.1.1 Factory Word Programming................................................................................... 62 11.2 Buffered Programming........................................................................................................62 11.3 Buffered Enhanced Factory Programming ......................................................................... 63 11.3.1 BEFP Requirements and Considerations.............................................................. 64 11.3.2 BEFP Setup Phase................................................................................................ 64 11.3.3 BEFP Program/Verify Phase ................................................................................. 64 11.3.4 BEFP Exit Phase ................................................................................................... 65 11.4 Program Suspend............................................................................................................... 65 11.5 Program Resume................................................................................................................ 66 11.6 Program Protection.............................................................................................................66 12.0 Erase Operations................................................................................................................... 67 12.1 Block Erase......................................................................................................................... 67 12.2 Erase Suspend ................................................................................................................... 67 12.3 Erase Resume.................................................................................................................... 68 12.4 Erase Protection ................................................................................................................. 68 13.0 Security Modes.......................................................................................................................69 13.1 Block Locking...................................................................................................................... 69 13.1.1 Lock Block .............................................................................................................69 13.1.2 Unlock Block.......................................................................................................... 69 13.1.3 Lock-Down Block................................................................................................... 69 13.1.4 Block Lock Status ..................................................................................................70 13.1.5 Block Locking During Suspend.............................................................................. 70 13.2 Selectable One-Time Programmable Blocks...................................................................... 71 13.3 Protection Registers ........................................................................................................... 72 13.3.1 Reading the Protection Registers.......................................................................... 73 13.3.2 Programming the Protection Registers..................................................................73 13.3.3 Locking the Protection Registers........................................................................... 74 14.0 Special Read States .............................................................................................................75 14.1 Read Status Register.......................................................................................................... 75 14.1.1 Clear Status Register............................................................................................. 76 14.2 Read Device Identifier ........................................................................................................ 76 ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 4 Order Number: 306666, Revision: 001 1-Gbit P30 Family 14.3 CFI Query ...........................................................................................................................77 Appendix A Write State Machine..........................................................................................78 Appendix B Flowcharts............................................................................................................85 Appendix C Common Flash Interface ................................................................................93 Appendix D Additional Information...................................................................................100 Appendix E Ordering Information for Discrete Products ........................................101 Appendix F Ordering Information for SCSP Products..............................................102 ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 5 1-Gbit P30 Family Revision History Revision Date Revision Description April 2005 -001 Initial Release ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 6 Order Number: 306666, Revision: 001 1-Gbit P30 Family 1.0 Introduction This document provides information about the Intel StrataFlash® Embedded Memory (P30) device and describes its features, operation, and specifications. 1.1 Nomenclature 1.8 V : V (core) voltage range of 1.7 V – 2.0 V CC 3.0 V : V (I/O) voltage range of 1.7 V – 3.6 V CCQ 9.0 V : V voltage range of 8.5 V – 9.5 V PP Block : A group of bits, bytes,1-Gbit P30 Family or words within the flash memory array that erase simultaneously when the Erase command is issued to the device. The 1-Gbit P30 Family has two block sizes: 32-KByte and 128-KByte. Main block : An array block that is usually used to store code and/or data. Main blocks are larger than parameter blocks. Parameter block : An array block that is usually used to store frequently changing data or small system parameters that traditionally would be stored in EEPROM. Top parameter device : A device with its parameter blocks located at the highest physical address of its memory map. Bottom parameter device : A device with its parameter blocks located at the lowest physical address of its memory map. 1.2 Acronyms BEFP : Buffer Enhanced Factory Programming CUI : Command User Interface MLC : Multi-Level Cell OTP : One-Time Programmable PLR : Protection Lock Register PR : Protection Register RCR : Read Configuration Register ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 7 1-Gbit P30 Family RFU : Reserved for Future Use SR : Status Register WSM : Write State Machine 1.3 Conventions VCC : Signal or voltage connection V : Signal or voltage level CC 0x : Hexadecimal number prefix 0b : Binary number prefix SR[4] : Denotes an individual register bit. A[15:0] : Denotes a group of similarly named signals, such as address or data bus. A5 : Denotes one element of a signal group membership, such as an individual address bit. Bit : Binary unit Byte : Eight bits Word : Two bytes, or sixteen bits Kbit : 1024 bits KByte : 1024 bytes KWord : 1024 words Mbit : 1,048,576 bits MByte : 1,048,576 bytes MWord : 1,048,576 words ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 8 Order Number: 306666, Revision: 001 1-Gbit P30 Family 2.0 Functional Overview This section provides an overview of the features and capabilities of the 1-Gbit P30 Family device. The P30 family provides density upgrades from 64-Mbit through 1-Gbit. This family of devices provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage. Upon initial power up or return from reset, the device defaults to asynchronous page-mode read. Configuring the Read Configuration Register enables synchronous burst-mode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides an easy CPU-to-flash memory synchronization. In addition to the enhanced architecture and interface, the device incorporates technology that enables fast factory program and erase operations. Designed for low-voltage systems, the 1-Gbit P30 Family supports read operations with V at 1.8 V, and erase and program operations with CC V at 1.8 V or 9.0 V. Buffered Enhanced Factory Programming (BEFP) provides the fastest flash PP array programming performance with V at 9.0 V, which increases factory throughput. With V PP PP at 1.8 V, VCC and VPP can be tied together for a simple, ultra low power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when V ≤ PP V . PPLK A Command User Interface (CUI) is the interface between the system processor and all internal operations of the device. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase and program. A Status Register indicates erase or program completion and any errors that may have occurred. An industry-standard command sequence invokes program and erase automation. Each erase operation erases one block. The Erase Suspend feature allows system software to pause an erase cycle to read or program data in another block. Program Suspend allows system software to pause programming to read other locations. Data is programmed in word increments (16 bits). The 1-Gbit P30 Family’s protection register allows unique flash device identification that can be used to increase system security. The individual Block Lock feature provides zero-latency block locking and unlocking. In addition, the P30 device also has four pre-defined spaces in the main array that can be configured as One-Time Programmable (OTP). ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 9 1-Gbit P30 Family 3.0 Package Information 3.1 56-Lead TSOP Package Figure 1. TSOP Mechanical Specifications Z A 2 See Note 2 See Notes 1 and 3 Pin 1 e See Detail B E Y D A 1 1 D Seating Plane See Detail A A Detail A Detail B C 0 b L [231369-90] Table 1. TSOP Package Dimensions (Sheet 1 of 2) Millimeters Inches Product Information Sym Min Nom Max Min Nom Max Package Height A - - 1.200 - - 0.047 Standoff A 0.050 - - 0.002 - - 1 Package Body Thickness A 0.965 0.995 1.025 0.038 0.039 0.040 2 Lead Width b 0.100 0.150 0.200 0.004 0.006 0.008 Lead Thickness c 0.100 0.150 0.200 0.004 0.006 0.008 Package Body Length D 18.200 18.400 18.600 0.717 0.724 0.732 1 Package Body Width E 13.800 14.000 14.200 0.543 0.551 0.559 Lead Pitch e - 0.500 - - 0.0197 - ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 10 Order Number: 306666, Revision: 001 1-Gbit P30 Family Table 1. TSOP Package Dimensions (Sheet 2 of 2) Millimeters Inches Product Information Sym Min Nom Max Min Nom Max Terminal Dimension D 19.800 20.00 20.200 0.780 0.787 0.795 Lead Tip Length L 0.500 0.600 0.700 0.020 0.024 0.028 Lead Count N - 56 - - 56 - Lead Tip Angle ∅ 0° 3° 5° 0° 3° 5° Seating Plane Coplanarity Y - - 0.100 - - 0.004 Lead to Package Offset Z 0.150 0.250 0.350 0.006 0.010 0.014 ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 11 1-Gbit P30 Family 3.2 64-Ball Easy BGA Package Figure 2. Easy BGA Mechanical Specifications Ball A1 Ball A1 Corner Corner D S1 1 2 3 4 5 6 7 8 87 6 5 4 3 2 1 S2 A A B B C C D D b E E E F F G G e H H Top View - Ball side down Bottom View - Ball Side Up A1 A2 A Seating Y Plane Note: Drawing not to scale Table 2. Easy BGA Package Dimensions Millimeters Inches Product Information Symbol Notes Min Nom Max Min Nom Max Package Height (64/128/256-Mbit) A - - 1.200 - - 0.0472 Package Height (512-Mbit) A - - 1.300 - - 0.0512 Ball Height (64/128/256-Mbit) A1 0.250 - - 0.0098 - - Ball Height (512-Mbit) A1 0.240 - - 0.0094 - - Package Body Thickness (64/128/256-Mbit) A2 - 0.780 - - 0.0307 - Package Body Thickness (512-Mbit) A2 - 0.910 - - 0.0358 - Ball (Lead) Width b 0.330 0.430 0.530 0.0130 0.0169 0.0209 Package Body Width D 9.900 10.000 10.100 0.3898 0.3937 0.3976 1 Package Body Length E 12.900 13.000 13.100 0.5079 0.5118 0.5157 1 Pitch [e] - 1.000 - - 0.0394 - Ball (Lead) Count N - 64 - - 64 - Seating Plane Coplanarity Y - - 0.100 - - 0.0039 Corner to Ball A1 Distance Along D S1 1.400 1.500 1.600 0.0551 0.0591 0.0630 1 Corner to Ball A1 Distance Along E S2 2.900 3.000 3.100 0.1142 0.1181 0.1220 1 Note: Daisy Chain Evaluation Unit information is at Intel® Flash Memory Packaging Technology http://developer.intel.com/ design/flash/packtech. ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 12 Order Number: 306666, Revision: 001 1-Gbit P30 Family 3.3 QUAD+ SCSP Packages Figure 3. 64/128-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x10x1.2 mm) A1 Index S 1 Mark 123 4 567 8 8 7 6 5 4 3 2 1 S 2 A A B B C C D D E E F F D e G G H H J J K K L L M M b E Top View - Ball Bottom View - Ball Up Down A 2 A A 1 Y Drawing not to scale. Millimeters Inches Dimensions Symbol Min Nom Max Min Nom Max Package Height A - - 1.200 - - 0.0472 Ball Height A1 0.200 - - 0.0079 - - Package Body Thickness A2 - 0.860 - - 0.0339 - Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 Package Body Width D 9.900 10.000 10.100 0.3898 0.3937 0.3976 Package Body Length E 7.900 8.000 8.100 0.3110 0.3150 0.3189 Pitch e - 0.800 - - 0.0315 - Ball (Lead) Count N - 88 - - 88 - Seating Plane Coplanarity Y - - 0.100 - - 0.0039 Corner to Ball A1 Distance Along E S1 1.100 1.200 1.300 0.0433 0.0472 0.0512 2 Corner to Ball A1 Distance Along D S 0.500 0.600 0.700 0.0197 0.0236 0.0276 ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 13 1-Gbit P30 Family Figure 4. 256-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.0 mm) A 1 Index S1 Mark 12 34 56 78 8 7 6 5 4 3 2 1 S2 A A B B C C D D E E F F D e G G H H J J K K L L M M b E Bottom View - Ball Up Top View - Ball Down A2 A1 A Y Drawing not to scale. Note: Dimensions A1, A2, and b are preliminary Millimeters Inches Dimensions Symbol Min Nom Max Min Nom Max Package Height A - - 1.000 - - 0.0394 Ball Height A1 0.117 - - 0.0046 - - Package Body Thickness A2 - 0.740 - - 0.0291 - Ball (Lead) Width b 0.300 0.350 0.400 0.0118 0.0138 0.0157 Package Body Length D 10.900 11.00 11.100 0.4291 0.4331 0.4370 Package Body Width E 7.900 8.00 8.100 0.3110 0.3150 0.3189 Pitch e - 0.80 - - 0.0315 - Ball (Lead) Count N - 88 - - 88 - Seating Plane Coplanarity Y - - 0.100 - - 0.0039 Corner to Ball A1 Distance Along E S1 1.100 1.200 1.300 0.0433 0.0472 0.0512 Corner to Ball A1 Distance Along D S2 1.000 1.100 1.200 0.0394 0.0433 0.0472 ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 14 Order Number: 306666, Revision: 001 1-Gbit P30 Family Figure 5. 512-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.2 mm) S1 A 1 Index Mark 12 34 5 6 7 8 8 7 6 5 4 3 2 1 S2 A A B B C C D D E E F F D e G G H H J J K K L L M M b E Top View - Ball Down Bottom View - Ball Up A2 A1 A Y Drawing not to scale. Millimeters Inches Dimensions Symbol Min Nom Max Min Nom Max Package Height A - - 1.200 - - 0.0472 Ball Height A1 0.200 - - 0.0079 - - Package Body Thickness A2 - 0.860 - - 0.0339 - Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 Package Body Length D 10.900 11.000 11.100 0.4291 0.4331 0.4370 Package Body Width E 7.900 8.000 8.100 0.3110 0.3150 0.3189 Pitch e - 0.800 - - 0.0315 - Ball (Lead) Count N - 88 - - 88 - Seating Plane Coplanarity Y - - 0.100 - - 0.0039 Corner to Ball A1 Distance Along E S1 1.100 1.200 1.300 0.0433 0.0472 0.0512 Corner to Ball A1 Distance Along D S2 1.000 1.100 1.200 0.0394 0.0433 0.0472 ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 15 1-Gbit P30 Family Figure 6. 1-Gbit, 88-ball (80 active) QUAD+ SCSP Specifications (11x11x1.4 mm) A1 Index S1 Mark 12 3456 78 8 7 6 5 4 3 2 1 S2 A A B B C C D D E E F F D e G G H H J J K K L L M M b E Bottom View - Ball Up Top View - Ball Down A2 A1 A Y Drawing not to scale. Millimeters Inches Dimens ions Symbol Min Nom Max Min Nom Max Package Height A - - 1.400 - - 0.0551 Ball Height A1 0.200 - - 0.0079 - - Package Body Thickness A2 - 1.070 - - 0.0421 - Ball (Lead) W idth b 0.325 0.375 0.425 0.0128 0.0148 0.0167 Package Body Length D 10.900 11.000 11.100 0.4291 0.4331 0.4370 Package Body W idth E 10.900 11.000 11.100 0.4291 0.4331 0.4370 Pitch e - 0.800 - - 0.0315 - Ball (Lead) Count N - 88 - - 88 - Seating Plane Coplanarity Y - - 0.100 - - 0.0039 Corner to Ball A1 Distance Along E S1 2.600 2.700 2.800 0.1024 0.1063 0.1102 Corner to Ball A1 Distance Along D S2 1.000 1.100 1.200 0.0394 0.0433 0.0472 ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 16 Order Number: 306666, Revision: 001 1-Gbit P30 Family 4.0 Ballout and Signal Descriptions 4.1 Signal Ballout Figure 7. 56-Lead TSOP Pinout (64/128/256-Mbit) 1 56 WAIT A16 55 A17 A15 2 54 DQ15 3 A14 53 DQ7 4 A13 52 DQ14 5 A12 6 51 DQ6 A11 50 DQ13 7 A10 49 DQ5 8 A9 48 DQ12 9 A23 10 47 DQ4 A22 11 46 ADV# A21 Intel StrataFlash® 45 CLK 12 VSS Embedded Memory (P30) 44 RST# 13 VCC 43 VPP 14 WE# 56-Lead TSOP Pinout 15 42 DQ11 WP# 14 mm x 20 mm 41 DQ3 16 A20 40 DQ10 17 A19 Top View 39 DQ2 18 A18 19 38 VCCQ A8 20 37 DQ9 A7 36 DQ1 21 A6 35 DQ8 22 A5 34 DQ0 23 A4 24 33 VCC A3 32 OE# 25 A2 31 VSS 26 A24 30 CE# 27 RFU 29 A1 28 VSS Notes: 1. A1 is the least significant address bit. 2. A23 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC). 3. A24 is valid for 256-Mbit densities and above; otherwise, it is a no connect (NC). ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 17 1-Gbit P30 Family Figure 8. 64-Ball Easy BGA Ballout (64/128/256/512-Mbit) 5 8 8 5 1 23 4 67 7 6 4 3 2 1 A A A1 A6 A8 VPP A13 VCC A18 A22 A22 A18 VCC A13 VPP A8 A6 A1 B B A2 VSS A9 CE# A14 A25 A19 RFU RFU A19 A25 A14 CE# A9 VSS A2 C C A3 A7 A10 A12 A15 WP# A20 A21 A21 A20 WP# A15 A12 A10 A7 A3 D D A4 A5 A11 RST# VCCQ VCCQ A16 A17 A17 A16 VCCQ VCCQ RST# A11 A5 A4 E E DQ8 DQ1 DQ9 DQ3 DQ4 CLK DQ15 RFU RFU DQ15 CLK DQ4 DQ3 DQ9 DQ1 DQ8 F F RFU DQ0 DQ10 DQ11 DQ12 ADV# WAIT OE# OE# WAIT ADV# DQ12 DQ11 DQ10 DQ0 RFU G G A23 RFU DQ2 VCCQ DQ5 DQ6 DQ14 WE# WE# DQ14 DQ6 DQ5 VCCQ DQ2 RFU A23 H H RFU VSS VCC VSS DQ13 VSS DQ7 A24 A24 DQ7 VSS DQ13 VSS VCC VSS RFU Easy BGA Easy BGA Top View- Ball side down Bottom View- Ball side up Notes: 1. A1 is the least significant address bit. 2. A23 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC). 3. A24 is valid for 256-Mbit densities and above; otherwise, it is a no connect (NC). 4. A25 is valid for 512-Mbit densities; otherwise, it is a no connect (NC). ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 18 Order Number: 306666, Revision: 001 1-Gbit P30 Family Figure 9. 88-Ball (80-Active Ball) QUAD+ SCSP Ballout Pin 1 123 456 78 A DU DU Depop Depop Depop Depop DU DU A B A4 A18 A19 VSS VCC VCC A21 A11 B C A5 RFUA23 VSS RFU CLKA22 A12 C D A3 A17 A24 VPP RFU RFU A9 A13 D E A2 A7 RFU WP# ADV# A20 A10 A15 E F A1 A6 RFU RST# WE# A8 A14 A16 F G A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT F2-CE# G H RFU DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 F2-OE# H J RFU F1-OE# DQ9 DQ11 DQ4 DQ6 DQ15 VCCQ J K F1-CE# RFU RFU RFU RFU VCC VCCQ RFU K L VSS VSS VCCQ VCC VSS VSS VSS VSS L M DU DU Depop Depop Depop Depop DU DU M 123 456 78 ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 19 1-Gbit P30 Family 4.2 Signal Descriptions This section has signal descriptions for the various P30 packages. Table 3. TSOP and Easy BGA Signal Descriptions (Sheet 1 of 2) Symbol Type Name and Function ADDRESS INPUTS: Device address inputs. 64-Mbit: A[22:1]; 128-Mbit: A[23:1]; 256-Mbit: A[24:1]; 512-Mbit: A[25:1]. A[MAX:1] Input See Table 5 on page 22 and Figure 10 on page 23 for 512-Mbit addressing. DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during Input/ DQ[15:0] memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls Output float when the CE# or OE# are deasserted. Data is internally latched during writes. ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. ADV# Input In asynchronous mode, the address is latched when ADV# going high or continuously flows through if ADV# is held low. WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through. FLASH CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the associated flash die is deselected, power is reduced to standby levels, data and CE# Input WAIT outputs are placed in high-Z state. WARNING: All chip enables must be high when device is not in use. CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the CLK Input next valid CLK edge with ADV# low, whichever occurs first. WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS. OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read OE# Input cycles. OE# high places the data outputs and WAIT in High-Z. RESET: Active low input. RST# resets internal automation and inhibits write operations. This RST# Input provides data protection during power transitions. RST# high enables normal operation. Exit from reset places the device in asynchronous read array mode. WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration Register bit 10 (RCR[10], WT) determines its polarity when asserted. WAIT’s active output is V or OL V when CE# and OE# are V . WAIT is high-Z if CE# or OE# is V . OH IL IH WAIT Output • In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and valid data when deasserted. • In asynchronous page mode, and all write modes, WAIT is deasserted. WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched WE# Input on the rising edge of WE#. WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock- WP# Input down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function enabling blocks to be erased or programmed using software commands. Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory contents cannot be altered when V ≤ V . Block erase and program at invalid V voltages PP PPLK PP should not be attempted. Set V = V for in-system program and erase operations. To accommodate resistor or diode drops PP CC Power/ VPP from the system supply, the V level of V can be as low as V min. V must remain above V IH PP PPL PP PPL Input min to perform in-system flash modification. VPP may be 0 V during read operations. V can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 PPH cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of this pin at 9 V may reduce block cycling capability. Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when VCC Power V ≤ V . Operations at invalid V voltages should not be attempted. CC LKO CC ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 20 Order Number: 306666, Revision: 001 1-Gbit P30 Family Table 3. TSOP and Easy BGA Signal Descriptions (Sheet 2 of 2) Symbol Type Name and Function VCCQ Power Output Power Supply: Output-driver source voltage. VSS Power Ground: Connect to system ground. Do not float any VSS connection. Reserved for Future Use: Reserved by Intel for future device functionality and enhancement. These RFU — should be treated in the same way as a Do Not Use (DU) signal. DU — Do Not Use: Do not connect to any other signal, or power supply; must be left floating. NC — No Connect: No internal connection; can be driven or floated. Table 4. QUAD+ SCSP Signal Descriptions (Sheet 1 of 2) Symbol Type Name and Function ADDRESS INPUTS: Device address inputs. 64-Mbit: A[21:0]; 128-Mbit: A[22:0]; 256-Mbit: A[23:0]; 512-Mbit: A[24:0]. A[MAX:0] Input See Table 6 on page 22, Figure 11 on page 23, and Figure 12 on page 23 for 512-Mbit and 1-Gbit addressing. DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during Input/ DQ[15:0] memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls Output float when the CE# or OE# are deasserted. Data is internally latched during writes. ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. ADV# Input In asynchronous mode, the address is latched when ADV# going high or continuously flows through if ADV# is held low. WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through. FLASH CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the associated flash die is deselected, power is reduced to standby levels, data and F1-CE# Input WAIT outputs are placed in high-Z state. F2-CE# See Table 6 on page 22 for CE# assignment definitions. WARNING: All chip enables must be high when device is not in use. CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the CLK Input next valid CLK edge with ADV# low, whichever occurs first. WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS. OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read F1-OE# cycles. OE# high places the data outputs and WAIT in High-Z. Input F2-OE# F1-OE# and F2-OE# should be tied together for all densities. RESET: Active low input. RST# resets internal automation and inhibits write operations. This RST# Input provides data protection during power transitions. RST# high enables normal operation. Exit from reset places the device in asynchronous read array mode. WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration Register bit 10 (RCR[10], WT) determines its polarity when asserted. WAIT’s active output is V or OL V when CE# and OE# are V . WAIT is high-Z if CE# or OE# is V . OH IL IH WAIT Output • In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and valid data when deasserted. • In asynchronous page mode, and all write modes, WAIT is deasserted. WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched WE# Input on the rising edge of WE#. ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 21 1-Gbit P30 Family Table 4. QUAD+ SCSP Signal Descriptions (Sheet 2 of 2) Symbol Type Name and Function WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock- WP# Input down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function enabling blocks to be erased or programmed using software commands. Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory contents cannot be altered when V ≤ V . Block erase and program at invalid V voltages PP PPLK PP should not be attempted. Set V = V for in-system program and erase operations. To accommodate resistor or diode drops PP CC Power/ VPP from the system supply, the V level of V can be as low as V min. V must remain above V IH PP PPL PP PPL lnput min to perform in-system flash modification. VPP may be 0 V during read operations. V can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 PPH cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of this pin at 9 V may reduce block cycling capability. Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when VCC Power V ≤ V . Operations at invalid V voltages should not be attempted. CC LKO CC VCCQ Power Output Power Supply: Output-driver source voltage. VSS Power Ground: Connect to system ground. Do not float any VSS connection. Reserved for Future Use: Reserved by Intel for future device functionality and enhancement. These RFU — should be treated in the same way as a Do Not Use (DU) signal. DU — Do Not Use: Do not connect to any other signal, or power supply; must be left floating. NC — No Connect: No internal connection; can be driven or floated. 4.3 SCSP Configurations Table 5. Stacked Easy BGA Chip Select Logic Selected Flash Selected Flash Stack Combination Die #1 Die #2 1-die F1-CE# - 2-die F1-CE# + A25 (V ) F1-CE# + A25 (V ) IL IH Table 6. QUAD+ SCSP Chip Select Logic Stack Selected Flash Selected Flash Selected Flash Selected Flash Combination Die #1 Die #2 Die #3 Die #4 1-die F1-CE# - - - 2-die F1-CE# + A24 (V ) F1-CE# + A24 (V)- - IL IH 4-die F1-CE# + A24 (V ) F1-CE# + A24 (V ) F2-CE# + A24 (V ) F2-CE# + A24 (V ) IL IH IL IH ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 22 Order Number: 306666, Revision: 001 1-Gbit P30 Family Figure 10. 512-Mbit Easy BGA Device Block Diagram Easy BGA 2-Die (512-Mbit) Device Configuration F1-CE# Flash Die #1 RST# WP# (256-Mbit) VCC OE# VPP WE# VCCQ CLK VSS ADV# Flash Die #2 (256-Mbit) DQ[15:0] A[MAX:1] WAIT Figure 11. 512-Mbit QUAD+ SCSP Device Block Diagram QUAD+ 2-Die (512-Mbit) Device Configuration F1-CE# Flash Die #1 WP# RST# (256-Mbit) OE# VCC WE# VPP CLK VCCQ ADV# VSS Flash Die #2 (256-Mbit) A[MAX:0] DQ[15:0] WAIT Figure 12. 1-Gbit QUAD+ SCSP Device Block Diagram QUAD+ 4-Die (1-Gbit) Device Configuration F1-CE# F2-CE# Flash Die #1 Flash Die #3 WP# (256-Mbit) (256-Mbit) RST# OE# VCC WE# VPP CLK VCCQ ADV# VSS Flash Die #2 Flash Die #4 (256-Mbit) (256-Mbit) A[MAX:0] DQ[15:0] WAIT ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 23 1-Gbit P30 Family 4.4 Memory Maps Table 7 through Table 10 show the P30 memory maps. See Section 11.0, “Programming Operations” on page 61 for Programming Region information. Table 7. Discrete Top Parameter Memory Maps (all packages) Programming Size Programming Size Blk 256-Mbit Blk 128-Mbit Blk 64-Mbit Region # (KB) Region # (KB) 32 258 FFC000 - FFFFFF 130 7FC000 - 7FFFFF 32 66 3FC000 - 3FFFFF 32 255 FF0000 - FF3FFF 127 7F0000 - FF3FFF 32 63 3F0000 - 3F3FFF 15 7 128 254 FE0000 - FEFFFF 126 7E0000 - 7EFFFF 128 62 3E0000 - 3EFFFF 128 240 F00000 - F0FFFF 120 780000 - 78FFFF 128 56 380000 - 38FFFF 128 239 EF0000 - EFFFFF 119 770000 - 77FFFF 128 55 370000 - 37FFFF 14 6 128 224 E00000 - E0FFFF 112 700000 - 70FFFF 128 48 300000 - 30FFFF 128 223 DF0000 - DFFFFF 111 6F0000 - 6FFFFF 128 47 2F0000 - 2FFFFF 13 5 128 208 D00000 - D0FFFF 104 680000 - 68FFFF 128 40 280000 - 28FFFF 128 207 CF0000 - CFFFFF 103 670000 - 67FFFF 128 39 270000 - 27FFFF 12 4 128 192 C00000 - C0FFFF 96 600000 - 60FFFF 128 32 200000 - 20FFFF 128 191 BF0000 - BFFFFF 95 5F0000 - 5FFFFF 128 31 1F0000 - 1FFFFF 11 3 128 176 B00000 - B0FFFF 88 580000 - 58FFFF 128 24 180000 - 18FFFF 128 175 AF0000 - AFFFFF 87 570000 - 57FFFF 128 23 170000 - 17FFFF 10 2 128 160 A0000 - A0FFFF 80 500000 - 50FFFF 128 16 100000 - 10FFFF 128 159 9F0000 - 9FFFFF 79 4F0000 - 4FFFFF 128 15 0F0000 - 0FFFFF 9 1 128 144 900000 - 90FFFF 72 480000 - 48FFFF 128 8 080000 - 08FFFF 128 143 8F0000 - 8FFFFF 71 470000 - 47FFFF 128 7 070000 - 07FFFF 8 0 128 128 800000 - 80FFFF 64 400000 - 40FFFF 128 0 000000 - 00FFFF 128 127 7F0000 - 7FFFFF 63 3F0000 - 3FFFFF 7 128 112 700000 - 70FFFF 56 380000 - 38FFFF ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 24 Order Number: 306666, Revision: 001 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1-Gbit P30 Family Table 7. Discrete Top Parameter Memory Maps (all packages) Programming Size Programming Size Blk 256-Mbit Blk 128-Mbit Blk 64-Mbit Region # (KB) Region # (KB) 128 111 6F0000 - 6FFFFF 55 370000 - 37FFFF 6 128 96 600000 - 60FFFF 48 300000 - 30FFFF 128 95 5F0000 - 5FFFFF 47 2F0000 - 2FFFFF 5 128 80 500000 - 50FFFF 39 280000 - 28FFFF 128 79 4F0000 - 4FFFFF 38 270000 - 27FFFF 4 128 64 400000 - 40FFFF 32 200000 - 20FFFF 128 63 3F0000 - 3FFFFF 31 1F0000 - 1FFFFF 3 128 48 300000 - 30FFFF 24 180000 - 18FFFF 128 47 2F0000 - 2FFFFF 23 170000 - 17FFFF 2 128 32 200000 - 20FFFF 16 100000 - 10FFFF 128 31 1F0000 - 1FFFFF 15 0F0000 - 0FFFFF 1 128 16 100000 - 10FFFF 8 080000 - 08FFFF 128 15 0F0000 - 0FFFFF 7 070000 - 07FFFF 0 128 0 000000 - 00FFFF 0 000000 - 00FFFF Table 8. Discrete Bottom Parameter Memory Maps (all packages) Programming Size Programming Size Blk 256-Mbit Blk 128-Mbit Blk 64-Mbit Region (KB) Region (KB) 128 258 FF0000 - FFFFFF 130 7F0000 - 7FFFFF 128 62 3F0000 - 3FFFFF 15 7 128 243 F00000 - F0FFFF 123 780000 - 78FFFF 128 56 380000 - 38FFFF 128 242 EF0000 - EFFFFF 122 770000 - 77FFFF 128 55 370000 - 37FFFF 14 6 128 227 E00000 - E0FFFF 115 700000 - 70FFFF 128 48 300000 - 30FFFF 128 226 DF0000 - DFFFFF 114 6F0000 - 6FFFFF 128 47 2F0000 - 2FFFFF 13 5 128 211 D00000 - D0FFFF 107 680000 - 68FFFF 128 40 280000 - 28FFFF ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 25 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1-Gbit P30 Family Table 8. Discrete Bottom Parameter Memory Maps (all packages) Programming Size Programming Size Blk 256-Mbit Blk 128-Mbit Blk 64-Mbit Region (KB) Region (KB) 128 210 CF0000 - CFFFFF 106 670000 - 67FFFF 128 39 270000 - 27FFFF 12 4 128 195 C00000 - C0FFFF 99 600000 - 60FFFF 128 32 200000 - 20FFFF 128 194 BF0000 - BFFFFF 98 5F0000 - 5FFFFF 128 31 1F0000 - 1FFFFF 11 3 128 179 B00000 - B0FFFF 91 580000 - 58FFFF 128 24 180000 - 18FFFF 128 178 AF0000 - AFFFFF 90 570000 - 57FFFF 128 23 170000 - 17FFFF 10 2 128 163 A0000 - A0FFFF 83 500000 - 50FFFF 128 16 100000 - 10FFFF 128 162 9F0000 - 9FFFFF 82 4F0000 - 4FFFFF 128 15 0F0000 - 0FFFFF 9 1 128 147 900000 - 90FFFF 75 480000 - 48FFFF 128 8 080000 - 08FFFF 128 146 8F0000 - 8FFFFF 74 470000 - 47FFFF 128 10 070000 - 07FFFF 8 128 131 800000 - 80FFFF 67 400000 - 40FFFF 128 4 010000 - 01FFFF 0 128 130 7F0000 - 7FFFFF 66 3F0000 - 3FFFFF 32 3 00C000 - 00FFFF 7 128 115 700000 - 70FFFF 59 380000 - 38FFFF 32 0 000000 - 003FFF 128 114 6F0000 - 6FFFFF 58 370000 - 37FFFF 6 128 99 600000 - 60FFFF 51 300000 - 30FFFF 128 98 5F0000 - 5FFFFF 50 2F0000 - 2FFFFF 5 128 83 500000 - 50FFFF 43 280000 - 28FFFF 128 82 4F0000 - 4FFFFF 42 270000 - 27FFFF 4 128 67 400000 - 40FFFF 35 200000 - 20FFFF 128 66 3F0000 - 3FFFFF 34 1F0000 - 1FFFFF 3 128 51 300000 - 30FFFF 27 180000 - 18FFFF 128 50 2F0000 - 2FFFFF 26 170000 - 17FFFF 2 128 35 200000 - 20FFFF 19 100000 - 10FFFF 128 34 1F0000 - 1FFFFF 18 0F0000 - 0FFFFF 1 128 19 100000 - 10FFFF 11 080000 - 08FFFF ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 26 Order Number: 306666, Revision: 001 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1-Gbit P30 Family Table 8. Discrete Bottom Parameter Memory Maps (all packages) Programming Size Programming Size Blk 256-Mbit Blk 128-Mbit Blk 64-Mbit Region (KB) Region (KB) 128 18 0F0000 - 0FFFFF 10 070000 - 07FFFF 128 4 010000 - 01FFFF 4 010000 - 01FFFF 0 32 3 00C000 - 00FFFF 3 00C000 - 00FFFF 32 0 000000 - 03FFFF 0 000000 - 00FFFF Table 9. 512-Mbit Memory Map (Easy BGA and QUAD+ SCSP) 512-Mbit Flash (2x256-Mbit w/ 1CE) Flash Die # Die Stack Config. Size (KB) Blk Address Range 32 258 FFC000 - FFFFFF 32 255 FF0000 - FF3FFF Flash Die #2 2 (Top Parameter) 128 254 FE0000 - FEFFFF 128 0 000000 - 00FFFF 128 258 FF0000 - FFFFFF 128 4 010000 - 01FFFF Flash Die #1 (Bottom 1 Parameter) 32 3 00C000 - 00FFFF 32 0 000000 - 003FFF Note: Refer to 256-Mbit Memory Map (Table 7 and Table 8) for Programming Region Information. ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 27 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1-Gbit P30 Family Table 10. 1-Gbit Memory Map (QUAD+ SCSP only) 1-Gbit Flash (4x256-Mbit w/ 2CE) Flash Die # Die Stack Config. Size (KB) Blk Address Range 32 258 FFC000 - FFFFFF 32 255 FF0000 - FF3FFF Flash Die #4 4 (Top Parameter) 128 254 FE0000 - FEFFFF 128 0 000000 - 00FFFF 128 258 FF0000 - FFFFFF 128 5 020000 - 02FFFF Flash Die #3 3 (Bottom Parameter) 32 3 00C000 - 00FFFF 32 0 000000 - 003FFF 32 258 FFC000 - FFFFFF 32 255 FF0000 - FF3FFF Flash Die #2 2 (Top Parameter) 128 254 FE0000 - FEFFFF 128 0 000000 - 00FFFF 128 258 FF0000 - FFFFFF 128 4 010000 - 01FFFF Flash Die #1 1 (Bottom Parameter) 32 3 00C000 - 00FFFF 32 0 000000 - 003FFF Note: Refer to 256-Mbit Memory Map (Table 7 and Table 8) for Programming Region Information. ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 28 Order Number: 306666, Revision: 001 1-Gbit P30 Family 5.0 Maximum Ratings and Operating Conditions 5.1 Absolute Maximum Ratings Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Parameter Maximum Rating Notes Temperature under bias –40 °C to +85 °C 1 Storage temperature –65 °C to +125 °C Voltage on any signal (except VCC, VPP) –0.5 V to +4.1 V 2 VPP voltage –0.2 V to +10 V 2,3,4 VCC voltage –0.2 V to +2.5 V 2 VCCQ voltage –0.2 V to +4.1 V 2 Output short circuit current 100 mA 5 Notes: 1. Temperature for 1-Gbit SCSP is –30 °C to +85 °C. 2. Voltages shown are specified with respect to V . Minimum DC voltage is –0.5 V on input/output SS signals and –0.2 V on V , V , and V . During transitions, this level may undershoot to –2.0 V for CC CCQ PP periods < 20 ns. Maximum DC voltage on V is V + 0.5 V, which, during transitions, may CC CC overshoot to V + 2.0 V for periods < 20 ns. Maximum DC voltage on input/output signals and V CC CCQ is V + 0.5 V, which, during transitions, may overshoot to V + 2.0 V for periods < 20 ns. CCQ CCQ 3. Maximum DC voltage on V may overshoot to +11.5 V for periods < 20 ns. PP 4. Program/erase voltage is typically 1.7 V – 2.0 V. 9.0 V can be applied for 80 hours maximum total, to any blocks for 1000 cycles maximum. 9.0 V program/erase voltage may reduce block cycling capability. 5. Output shorted for no more than one second. No more than one output shorted at a time. ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 29 1-Gbit P30 Family 5.2 Operating Conditions Note: Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. Table 11. Operating Conditions Symbol Parameter Min Max Units Notes T Operating Temperature –40 +85 °C 1,2 C V VCC Supply Voltage 1.7 2.0 CC CMOS inputs 1.7 3.6 V I/O Supply Voltage CCQ TTL inputs 2.4 3.6 V V V Voltage Supply (Logic Level) 0.9 3.6 PPL PP V Factory word programming V 8.5 9.5 PPH PP t Maximum VPP Hours V = V -80 Hours PPH PP PPH 3 Main and Parameter Blocks V = V 100,000 - PP CC Block Erase Main Blocks V = V -1000 Cycles PP PPH Cycles Parameter Blocks V = V -2500 PP PPH NOTES: 1. T = Case Temperature C 2. Temperature for 1-Gbit SCSP is –30 °C to +85 °C. 3. In typical operation, the VPP program voltage is V . VPP can be connected to 8.5 V – 9.5 V for 80 PPL hours. ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 30 Order Number: 306666, Revision: 001 1-Gbit P30 Family 6.0 Electrical Specifications 6.1 DC Current Characteristics Table 12. DC Current Characteristics (Sheet 1 of 2) CMOS TTL Inputs Inputs (V = CCQ (V = CCQ Sym Parameter 2.4 V - 3.6 V) Unit Test Conditions Notes 1.7 V - 3.6 V) Typ Max Typ Max V = V Max CC CC I Input Load Current - ±1 - ±2 µA V = V Max LI CCQ CCQ V = V or V IN CCQ SS 1 Output V = V Max CC CC I Leakage DQ[15:0], WAIT - ±1 - ±10 µA V = V Max LO CCQ CCQ Current V = V or V IN CCQ SS 64-Mbit 203520 35 V = V Max CC CC 128-Mbit 30 75 30 75 V = V Max CCQ CCQ I , V Standby, CCS CC CE# = V CCQ 256-Mbit 55 115 55 200 µA 1,2 RST# = V (for I ) I Power Down CCQ CCS CCD RST# = V (for I ) 512-Mbit 110 230 110 400 SS CCD WP# = V IH 1-Gbit 220 460 220 800 Asynchronous Single- 1-Word 14 16 14 16 mA Word f = 5 MHz (1 CLK) Read Page-Mode Read 4-Word 910 9 10 mA V = V Max CC CC Average f = 13 MHz (5 CLK) Read CE# = V V IL CC I 1 13 17 n/a n/a mA BL = 4W CCR Read OE# = V IH Current 15 19 n/a n/a mA BL = 8W Inputs: V or V Synchronous Burst IL IH f = 40 MHz 17 21 n/a n/a mA BL = 16W 21 26 n/a n/a mA BL = Cont. 36 51 36 51 V = V , pgm/ers in progress 1,3,4,7 I V Program Current, PP PPL CCW, CC mA I V Erase Current 26 33 26 33 V = V , pgm/ers in progress 1,3,5,7 CCE CC PP PPH 64-Mbit 203520 35 V Program 128-Mbit 30 75 30 75 CC I Suspend Current, CCWS, CE# = V ; suspend in CCQ 256-Mbit 55 115 55 200 µA 1,3,6 progress I V Erase CCES CC Suspend Current 512-Mbit 110 230 110 400 1-Gbit 220 460 220 800 I V Standby Current, PPS, PP I V Program Suspend Current, 0.2 5 0.2 5 µA V = V , suspend in progress 1,3 PPWS, PP PP PPL I V Erase Suspend Current PPES PP I V Read 2 15 2 15 µA V ≤ V 1,3 PPR PP PP CC ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 31 1-Gbit P30 Family Table 12. DC Current Characteristics (Sheet 2 of 2) CMOS TTL Inputs Inputs (V = CCQ (V = CCQ 2.4 V - 3.6 V) Sym Parameter Unit Test Conditions Notes 1.7 V - 3.6 V) Typ Max Typ Max 0.05 0.10 0.05 0.10 V = V program in progress PP PPL, I V Program Current mA PPW PP 8228 22 V = V program in progress PP PPH, 0.05 0.10 0.05 0.10 V = V erase in progress PP PPL, I V Erase Current mA PPE PP 8228 22 V = V erase in progress PP PPH, Notes: 1. All currents are RMS unless noted. Typical values at typical V , T = +25 °C. CC C 2. I is the average current measured over any 5 ms time interval 5 µs after CE# is deasserted. CCS 3. Sampled, not 100% tested. 4. V read + program current is the sum of V read and V program currents. CC CC CC 5. V read + erase current is the sum of V read and V erase currents. CC CC CC 6. I is specified with the device deselected. If device is read while in erase suspend, current is I plus I . CCES CCES CCR 7. I , I measured over typical or max times specified in Section 7.5, “Program and Erase Characteristics” on CCW CCE page 45. 6.2 DC Voltage Characteristics Table 13. DC Voltage Characteristics (1) CMOS Inputs TTL Inputs (V = 1.7 V - 3.6 V) (V = 2.4 V - 3.6 V) CCQ CCQ Sym Parameter Unit Test Condition Notes Min Max Min Max V Input Low Voltage 0 0.4 0 0.6 V IL 2 V Input High Voltage V – 0.4 V 2.0 V V IH CCQ CCQ CCQ V = V Min CC CC V Output Low Voltage - 0.1 - 0.1 V V = V Min OL CCQ CCQ I = 100 µA OL V = V Min CC CC V Output High Voltage V – 0.1 - V – 0.1 - V V = V Min OH CCQ CCQ CCQ CCQ I = –100 µA OH V V Lock-Out Voltage - 0.4 - 0.4 V 3 PPLK PP V V Lock Voltage 1.0 - 1.0 - V LKO CC V V Lock Voltage 0.9 - 0.9 - V LKOQ CCQ NOTES: 1. Synchronous read mode is not supported with TTL inputs. 2. V can undershoot to –0.4 V and V can overshoot to V + 0.4 V for durations of 20 ns or less. IL IH CCQ 3. V ≤ V inhibits erase and program operations. Do not use V and V outside their valid ranges. PP PPLK PPL PPH ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 32 Order Number: 306666, Revision: 001 1-Gbit P30 Family 7.0 AC Characteristics 7.1 AC Test Conditions Figure 13. AC Input/Output Reference Waveform V CCQ Input V /2 Test Points V /2 Output CCQ CCQ 0V Note: AC test inputs are driven at V for Logic "1" and 0.0 V for Logic "0." Input/output timing begins/ends CCQ at V /2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed occurs at V = V Min. CCQ CC CC Figure 14. Transient Equivalent Testing Load Circuit Device Out Under Test C L NOTES: 1. See the following table for component values. 2. Test configuration component value for worst case speed conditions. 3. C includes jig capacitance L . Table 14. Test configuration component value for worst case speed conditions Test Configuration C (pF) L V Min Standard Test 30 CCQ Figure 15. Clock Input AC Waveform R201 V IH CLK [C] V IL R202 R203 ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 33 1-Gbit P30 Family 7.2 Capacitance Table 15. Capacitance Symbol Parameter Signals Min Typ Max Unit Condition Note Address, Data, Typ temp = 25 °C, CE#, WE#, OE#, C Input Capacitance 26 7 pF Max temp = 85 °C, IN RST#, CLK, 1,2,3 V = V = (0 V - 1.95 V), CC CCQ ADV#, WP# Discrete silicon die C Output Capacitance Data, WAIT 2 4 5 pF OUT NOTES: 1. Capacitance values are for a single die; for 2-die and 4-die stacks multiple the above values by the number of die in the stack. 2. Sampled, not 100% tested. 3. Silicon die capacitance only, add 1 pF for discrete packages. ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 34 Order Number: 306666, Revision: 001 1-Gbit P30 Family 7.3 AC Read Specifications Table 16. AC Read Specifications for 64/128-Mbit Densities (Sheet 1 of 2) Num Symbol Parameter Min Max Unit Notes Asynchronous Specifications R1 t Read cycle time 85 - ns AVAV R2 t Address to output valid - 85 ns AVQV R3 t CE# low to output valid - 85 ns ELQV R4 t OE# low to output valid - 25 ns 1,2 GLQV R5 t RST# high to output valid - 150 ns 1 PHQV R6 t CE# low to output in low-Z 0 - ns 1,3 ELQX R7 t OE# low to output in low-Z 0 - ns 1,2,3 GLQX R8 t CE# high to output in high-Z - 24 ns EHQZ R9 t OE# high to output in high-Z - 24 ns 1,3 GHQZ R10 t Output hold from first occurring address, CE#, or OE# change 0 - ns OH R11 t CE# pulse width high 20 - ns EHEL 1 R12 t CE# low to WAIT valid - 17 ns ELTV R13 t CE# high to WAIT high-Z - 20 ns 1,3 EHTZ R15 t OE# low to WAIT valid - 17 ns 1 GLTV R16 t OE# low to WAIT in low-Z 0 - ns GLTX 1,3 R17 t OE# high to WAIT in high-Z - 20 ns GHTZ Latching Specifications R101 t Address setup to ADV# high 10 - ns AVVH R102 t CE# low to ADV# high 10 - ns ELVH R103 t ADV# low to output valid - 85 ns 1 VLQV R104 t ADV# pulse width low 10 - ns VLVH R105 t ADV# pulse width high 10 - ns VHVL R106 t Address hold from ADV# high 9 - ns 1,4 VHAX R108 t Page address access - 25 ns APA 1 R111 t RST# high to ADV# high 30 - ns phvh Clock Specifications R200 f CLK frequency - 40 MHz CLK R201 t CLK period 25 - ns CLK 1,3,6 R202 t CLK high/low time 5 - ns CH/CL R203 t CLK fall/rise time - 3 ns FCLK/RCLK Synchronous Specifications R301 t Address setup to CLK 9 - ns AVCH/L R302 t ADV# low setup to CLK 9 - ns VLCH/L 1 R303 t CE# low setup to CLK 9 - ns ELCH/L R304 t / t CLK to output valid - 20 ns CHQV CLQV ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 35 1-Gbit P30 Family Table 16. AC Read Specifications for 64/128-Mbit Densities (Sheet 2 of 2) Num Symbol Parameter Min Max Unit Notes R305 t Output hold from CLK 3 - ns 1,5 CHQX R306 t Address hold from CLK 10 - ns 1,4,5 CHAX R307 t CLK to WAIT valid - 20 ns 1,5 CHTV R311 t CLK Valid to ADV# Setup 3 - ns 1 CHVL R312 t WAIT Hold from CLK 3 - ns 1,5 CHTX NOTES: 1. See Figure 13, “AC Input/Output Reference Waveform” on page 33 for timing measurements and max allowable input slew rate. 2. OE# may be delayed by up to t – t after CE#’s falling edge without impact to t . ELQV GLQV ELQV 3. Sampled, not 100% tested. 4. Address hold in synchronous burst mode is t or t , whichever timing specification is satisfied first. CHAX VHAX 5. Applies only to subsequent synchronous reads. 6. See your local Intel representative for designs requiring higher than 40 MHz synchronous operation. Table 17. AC Read Specifications for 256/512-Mbit and 1-Gbit Densities (Sheet 1 of 2) Num Symbol Parameter Speed Min Max Unit Notes Asynchronous Specifications Vcc = 1.8 V – 2.0 V 85 - R1 t Read cycle time ns AVAV Vcc = 1.7 V – 2.0 V 88 - Vcc = 1.8 V – 2.0 V -85 R2 t Address to output valid ns AVQV Vcc = 1.7 V – 2.0 V -88 Vcc = 1.8 V – 2.0 V -85 R3 t CE# low to output valid ns ELQV Vcc = 1.7 V – 2.0 V -88 R4 t OE# low to output valid - 25 ns 1,2 GLQV R5 t RST# high to output valid - 150 ns 1 PHQV R6 t CE# low to output in low-Z 0 - ns 1,3 ELQX R7 t OE# low to output in low-Z 0 - ns 1,2,3 GLQX R8 t CE# high to output in high-Z - 24 ns EHQZ R9 t OE# high to output in high-Z - 24 ns 1,3 GHQZ R10 t Output hold from first occurring address, CE#, or OE# change 0 - ns OH R11 t CE# pulse width high 20 - ns EHEL 1 R12 t CE# low to WAIT valid - 17 ns ELTV R13 t CE# high to WAIT high-Z - 20 ns 1,3 EHTZ R15 t OE# low to WAIT valid - 17 ns 1 GLTV R16 t OE# low to WAIT in low-Z 0 - ns GLTX 1,3 R17 t OE# high to WAIT in high-Z - 20 ns GHTZ Latching Specifications ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 36 Order Number: 306666, Revision: 001 1-Gbit P30 Family Table 17. AC Read Specifications for 256/512-Mbit and 1-Gbit Densities (Sheet 2 of 2) Num Symbol Parameter Speed Min Max Unit Notes R101 t Address setup to ADV# high 10 - ns AVVH R102 t CE# low to ADV# high 10 - ns ELVH Vcc = 1.8 V – 2.0 V -85 R103 t ADV# low to output valid ns 1 VLQV Vcc = 1.7 V – 2.0 V -88 R104 t ADV# pulse width low 10 - ns VLVH R105 t ADV# pulse width high 10 - ns VHVL R106 t Address hold from ADV# high 9 - ns 1,4 VHAX R108 t Page address access - 25 ns APA 1 R111 t RST# high to ADV# high 30 - ns phvh Clock Specifications R200 f CLK frequency - 40 MHz CLK R201 t CLK period 25 - ns CLK 1,3,6 R202 t CLK high/low time 5 - ns CH/CL R203 t CLK fall/rise time - 3 ns FCLK/RCLK Synchronous Specifications R301 t Address setup to CLK 9 - ns AVCH/L R302 t ADV# low setup to CLK 9 - ns VLCH/L 1 R303 t CE# low setup to CLK 9 - ns ELCH/L R304 t / t CLK to output valid - 20 ns CHQV CLQV R305 t Output hold from CLK 3 - ns 1,5 CHQX R306 t Address hold from CLK 10 - ns 1,4,5 CHAX R307 t CLK to WAIT valid - 20 ns 1,5 CHTV R311 t CLK Valid to ADV# Setup 3 - ns 1 CHVL R312 t WAIT Hold from CLK 3 - ns 1,5 CHTX NOTES: 1. See Figure 13, “AC Input/Output Reference Waveform” on page 33 for timing measurements and max allowable input slew rate. 2. OE# may be delayed by up to t – t after CE#’s falling edge without impact to t . ELQV GLQV ELQV 3. Sampled, not 100% tested. 4. Address hold in synchronous burst mode is t or t , whichever timing specification is satisfied first. CHAX VHAX 5. Applies only to subsequent synchronous reads. 6. See your local Intel representative for designs requiring higher than 40 MHz synchronous operation. ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 37 1-Gbit P30 Family Figure 16. Asynchronous Single-Word Read (ADV# Low) R1 R1 R2 Address [A] ADV# R3 R8 CE# [E} R4 R9 OE# [G] R15 R17 WAIT [T] R7 R6 Data [D/Q] R5 RST# [P] Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low). Figure 17. Asynchronous Single-Word Read (ADV# Latch) R1 R2 Address [A] A[1:0][A] R101 R1 R10 05 5 R106 ADV# R3 R8 CE# [E} R4 R9 OE# [G] R15 R17 WAIT [T] R7 R6 R10 Data [D/Q] Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low). ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 38 Order Number: 306666, Revision: 001 1-Gbit P30 Family Figure 18. Asynchronous Page-Mode Read Timing R1 R1 R2 A[Max:2] [A] A[1:0] R101 R R105 105 R106 ADV# R3 R8 CE# [E] R4 R10 OE# [G] R15 R17 WAIT [T] R7 R9 R108 DATA [D/Q] Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low). Figure 19. Synchronous Single-Word Array or Non-array Read Timing R301 R306 CLK [C] R2 Address [A] R101 R106 R1 R10 05 5 R R104 104 ADV# [V] R303 R102 R3 R8 CE# [E] R7 R9 OE# [G] R15 R307 R312 R17 WAIT [T] R4 R304 R305 Data [D/Q] 1. WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data. 2. This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by CE# deassertion after the first word in the burst. ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 39 1-Gbit P30 Family Figure 20. Continuous Burst Read, showing an Output Delay Timing R301 R302 R306 R304 R304 R304 CLK [C] R2 R101 Address [A] R106 R1 R10 05 5 ADV# [V] R303 R102 R3 CE# [E] OE# [G] R15 R307 R312 WAIT [T] R304 R4 R7 R305 R305 R305 R305 Data [D/Q] Notes: 1. WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data. 2. At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is not 4-word boundary aligned. ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 40 Order Number: 306666, Revision: 001 1-Gbit P30 Family Figure 21. Synchronous Burst-Mode Four-Word Read Timing y R302 R301 R306 CLK [C] R2 R101 Address [A] A R R105 105 R106 R102 ADV# [V] R303 R3 R8 CE# [E] R9 OE# [G] R15 R17 R307 WAIT [T] R4 R304 R7 R304 R305 R10 Data [D/Q] Q0 Q1 Q2 Q3 Note: WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and deasserted during valid data (RCR[10] = 0, Wait asserted low). 7.4 AC Write Specifications Table 18. AC Write Specifications (Sheet 1 of 2) Num Symbol Parameter Min Max Units Notes W1 t RST# high recovery to WE# low 150 - ns 1,2,3 PHWL W2 t CE# setup to WE# low 0 - ns 1,2,3 ELWL W3 t WE# write pulse width low 50 - ns 1,2,4 WLWH W4 t Data setup to WE# high 50 - ns DVWH W5 t Address setup to WE# high 50 - ns AVWH W6 t CE# hold from WE# high 0 - ns 1,2 WHEH W7 t Data hold from WE# high 0 - ns WHDX W8 t Address hold from WE# high 0 - ns WHAX W9 t WE# pulse width high 20 - ns 1,2,5 WHWL W10 t V setup to WE# high 200 - ns VPWH PP 1,2,3,7 W11 t V hold from Status read 0 - ns QVVL PP W12 t WP# hold from Status read 0 - ns QVBL 1,2,3,7 W13 t WP# setup to WE# high 200 - ns BHWH ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 41 1-Gbit P30 Family Table 18. AC Write Specifications (Sheet 2 of 2) Num Symbol Parameter Min Max Units Notes W14 t WE# high to OE# low 0 - ns 1,2,9 WHGL 1,2,3,6,1 W16 t WE# high to read valid t + 35 - ns WHQV AVQV 0 Write to Asynchronous Read Specifications W18 t WE# high to Address valid 0 - ns 1,2,3,6,8 WHAV Write to Synchronous Read Specifications W19 t WE# high to Clock valid 19 - ns WHCH/L 1,2,3,6,1 0 W20 t WE# high to ADV# high 19 - ns WHVH Write Specifications with Clock Active W21 t ADV# high to WE# low - 20 ns VHWL 1,2,3,11 W22 t Clock high to WE# low - 20 ns CHWL Notes: 1. Write timing characteristics during erase suspend are the same as write-only operations. 2. A write operation can be terminated with either CE# or WE#. 3. Sampled, not 100% tested. 4. Write pulse width low (t or t ) is defined from CE# or WE# low (whichever occurs last) to WLWH ELEH CE# or WE# high (whichever occurs first). Hence, t = t = t = t . WLWH ELEH WLEH ELWH 5. Write pulse width high (t or t ) is defined from CE# or WE# high (whichever occurs first) to WHWL EHEL CE# or WE# low (whichever occurs last). Hence, t = t = t = t ). WHWL EHEL WHEL EHWL 6. t or t must be met when transitioning from a write cycle to a synchronous burst read. WHVH WHCH/L 7. V and WP# should be at a valid level until erase or program success is determined. PP 8. This specification is only applicable when transitioning from a write cycle to an asynchronous read. See spec W19 and W20 for synchronous read. 9. When doing a Read Status operation following any command that alters the Status Register, W14 is 20 ns. 10. Add 10 ns if the write operations results in a RCR or block lock status change, for the subsequent read operation to reflect this change. 11. These specs are required only when the device is in a synchronous mode and clock is active during address setup phase. Figure 22. Write-to-Write Timing W5 W8 W5 W8 Address [A] W2 W6 W2 W6 CE# [E} W3 W3 W9 W9 W3 W3 WE# [W] OE# [G] W4 W7 W4 W7 Data [D/Q] W1 RST# [P] ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 42 Order Number: 306666, Revision: 001 1-Gbit P30 Family Figure 23. Asynchronous Read-to-Write Timing R1 R1 R2 W5 W8 Address [A] R3 R8 CE# [E} R4 R9 OE# [G] W2 W3 W3 W6 WE# [W] R15 R17 WAIT [T] R7 W7 R6 R10 W4 Data [D/Q] Q D R5 RST# [P] Note: WAIT deasserted during asynchronous read and during write. WAIT High-Z during write per OE# deasserted. Figure 24. Write-to-Asynchronous Read Timing W5 W8 R1 R1 Address [A] ADV# [V] W2 W6 R10 CE# [E} W3 W3 W18 WE# [W] W14 OE# [G] R15 R17 WAIT [T] R4 R2 R8 W4 W7 R3 R9 Data [D/Q] D Q W1 RST# [P] ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 43 1-Gbit P30 Family Figure 25. Synchronous Read-to-Write Timing Latency Count R301 R302 R306 CLK [C] R2 W5 R101 W18 Address [A] R1 R10 05 5 R106 R102 R1 R10 04 4 ADV# [V] R303 R1 R11 1 R3 R13 W6 CE# [E] R4 R8 OE# [G] W21 W21 W22 W22 W8 W15 W2 W3 W3 W9 W9 WE# R16 R307 R312 WAIT [T] R304 R7 R305 W7 Q D D Data [D/Q] Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0, Wait asserted low). Clock is ignored during write operation. Figure 26. Write-to-Synchronous Read Timing R302 R301 R2 CLK W5 W8 R306 Address [A] R106 R1 R10 04 4 ADV# W6 R303 W2 R1 R11 1 CE# [E} W18 W19 W3 W3 W20 WE# [W] R4 OE# [G] R15 R307 WAIT [T] W7 R304 R305 W4 R3 R304 Data [D/Q] D Q Q W1 RST# [P] Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0, Wait asserted low). ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 44 Order Number: 306666, Revision: 001 1-Gbit P30 Family 7.5 Program and Erase Characteristics V V PPL PPH Num Symbol Parameter Units Notes Min Typ Max Min Typ Max Conventional Word Programming Single word - 90 200 - 85 190 Program W200 t µs 1 PROG/W Time Single cell - 30 60 - 30 60 Buffered Programming W200 t Single word - 90 200 - 85 190 Program PROG/W µs 1 Time W251 t 32-word buffer - 440 880 - 340 680 BUFF Buffered Enhanced Factory Programming W451 t Single word n/a n/a n/a - 10 - 1,2 BEFP/W Program µs t BEFP/ W452 BEFP Setup n/a n/a n/a 5 - - 1 Setup Erasing and Suspending W500 t 32-KByte Parameter - 0.4 2.5 - 0.4 2.5 ERS/PB Erase Time s W501 t 128-KByte Main - 1.2 4.0 - 1.0 4.0 ERS/MB 1 W600 t Program suspend - 20 25 - 20 25 Suspend SUSP/P µs Latency W601 t Erase suspend - 20 25 - 20 25 SUSP/E Notes: 1. Typical values measured at T = +25 °C and nominal voltages. Performance numbers are valid for all C speed versions. Excludes system overhead. Sampled, but not 100% tested. 2. Averaged over entire device. ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 45 1-Gbit P30 Family 8.0 Power and Reset Specifications 8.1 Power Up and Down Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; If VCCQ and/or VPP are not connected to the VCC supply, then V should attain V before CC CCMIN applying V and V . Device inputs should not be driven before supply voltage equals V . CCQ PP CCMIN Power supply transitions should only occur when RST# is low. This protects the device from accidental programming or erasure during power transitions. 8.2 Reset Specifications Asserting RST# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization may not occur. This is because the flash memory may be providing status information, instead of array data as expected. Connect RST# to the same active low reset signal used for CPU initialization. Also, because the device is disabled when RST# is asserted, it ignores its control inputs during power-up/down. Invalid bus conditions are masked, providing a level of memory protection. Num Symbol Parameter Min Max Unit Notes P1 t RST# pulse width low 100 - ns 1,2,3,4 PLPH RST# low to device reset during erase - 25 1,3,4,7 P2 t PLRH RST# low to device reset during program - 25 µs 1,3,4,7 P3 t V Power valid to RST# de-assertion (high) 60 - 1,4,5,6 VCCPH CC Notes: 1. These specifications are valid for all device versions (packages and speeds). 2. The device may reset if t is < t MIN, but this is not guaranteed. PLPH PLPH 3. Not applicable if RST# is tied to Vcc. 4. Sampled, but not 100% tested. 5. If RST# is tied to the V supply, device will not be ready until t after V ≥ V . CC VCCPH CC CCMIN 6. If RST# is tied to any supply/signal with V voltage levels, the RST# input voltage must not exceed CCQ V until V ≥ V . CC CC CCMIN 7. Reset completes within t if RST# is asserted while no erase or program operation is executing. PLPH ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 46 Order Number: 306666, Revision: 001 1-Gbit P30 Family Figure 27. Reset Operation Waveforms P1 R5 V IH (A) Reset during RST# [P] read mode V IL Abort P2 R5 Complete (B) Reset during V IH RST# [P] program or block erase V IL P1 ≤ P2 Abort P2 R5 Complete (C) Reset during V IH RST# [P] program or block erase V IL P1 ≥ P2 P3 V CC (D) VCC Power-up to V CC RST# high 0V 8.3 Power Supply Decoupling Flash memory devices require careful power supply de-coupling. Three basic power supply current considerations are: 1) standby current levels; 2) active current levels; and 3) transient peaks produced when CE# and OE# are asserted and deasserted. When the device is accessed, many internal conditions change. Circuits within the device enable charge-pumps, and internal logic states change at high speed. All of these internal activities produce transient signals. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and correct de-coupling capacitor selection suppress transient voltage peaks. ® Because Intel Multi-Level Cell (MLC) flash memory devices draw their power from VCC, VPP, and VCCQ, each power connection should have a 0.1 µF ceramic capacitor to ground. High- frequency, inherently low-inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices used in the system, a 4.7 µF electrolytic capacitor should be placed between power and ground close to the devices. The bulk capacitor is meant to overcome voltage droop caused by PCB trace inductance. ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 47 1-Gbit P30 Family 9.0 Device Operations This section provides an overview of device operations. The system CPU provides control of all in- system read, write, and erase operations of the device via the system bus. The on-chip Write State Machine (WSM) manages all block-erase and word-program algorithms. Device commands are written to the Command User Interface (CUI) to control all flash memory device operations. The CUI does not occupy an addressable memory location; it is the mechanism through which the flash device is controlled. 9.1 Bus Operations CE# low and RST# high enable device read operations. The device internally decodes upper address inputs to determine the accessed block. ADV# low opens the internal address latches. OE# low activates the outputs and gates selected data onto the I/O bus. In asynchronous mode, the address is latched when ADV# goes high or continuously flows through if ADV# is held low. In synchronous mode, the address is latched by the first of either the rising ADV# edge or the next valid CLK edge with ADV# low (WE# and RST# must be V ; CE# must IH be V ). IL Bus cycles to/from the P30 device conform to standard microprocessor bus operations. Table 19 summarizes the bus operations and the logic levels that must be applied to the device control signal inputs. Table 19. Bus Operations Summary Bus Operation RST# CLK ADV# CE# OE# WE# WAIT DQ[15:0] Notes Asynchronous V X L L L H Deasserted Output IH Read Synchronous V Running L L L H Driven Output IH Write V X L L H L High-Z Input 1 IH Output Disable V X X L H H High-Z High-Z 2 IH Standby V X X H X X High-Z High-Z 2 IH Reset V X X X X X High-Z High-Z 2,3 IL Notes: 1. Refer to the Table 20, “Command Bus Cycles” on page 50 for valid DQ[15:0] during a write operation. 2. X = Don’t Care (H or L). 3. RST# must be at V ± 0.2 V to meet the maximum specified power-down current. SS 9.1.1 Reads To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are asserted. CE# is the device-select control. When asserted, it enables the flash memory device. OE# is the data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus. See Section 10.0, “Read Operations” on page 53 for details on the available read modes, and see Section 14.0, “Special Read States” on page 75 for details regarding the available read states. ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 48 Order Number: 306666, Revision: 001 1-Gbit P30 Family 9.1.2 Writes To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deasserted. During a write operation, address and data are latched on the rising edge of WE# or CE#, whichever occurs first. Table 20, “Command Bus Cycles” on page 50 shows the bus cycle sequence for each of the supported device commands, while Table 21, “Command Codes and Definitions” on page 51 describes each command. See Section 7.0, “AC Characteristics” on page 33 for signal-timing details. Note: Write operations with invalid V and/or V voltages can produce spurious results and should not CC PP be attempted. 9.1.3 Output Disable When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-impedance (High-Z) state, WAIT is also placed in High-Z. 9.1.4 Standby When CE# is deasserted the device is deselected and placed in standby, substantially reducing power consumption. In standby, the data outputs are placed in High-Z, independent of the level placed on OE#. Standby current, I , is the average current measured over any 5 ms time interval, CCS 5 µs after CE# is deasserted. During standby, average current is measured over the same time interval 5 µs after CE# is deasserted. When the device is deselected (while CE# is deasserted) during a program or erase operation, it continues to consume active power until the program or erase operation is completed. 9.1.5 Reset As with any automated device, it is important to assert RST# when the system is reset. When the system comes out of reset, the system processor attempts to read from the flash memory if it is the system boot device. If a CPU reset occurs with no flash memory reset, improper CPU initialization may occur because the flash memory may be providing status information rather than array data. Flash memory devices from Intel allow proper CPU initialization following a system reset through the use of the RST# input. RST# should be controlled by the same low-true reset signal that resets the system CPU. After initial power-up or reset, the device defaults to asynchronous Read Array, and the Status Register is set to 0x80. Asserting RST# de-energizes all internal circuits, and places the output drivers in High-Z. When RST# is asserted, the device shuts down the operation in progress, a process which takes a minimum amount of time to complete. When RST# has been deasserted, the device is reset to asynchronous Read Array state. Note: If RST# is asserted during a program or erase operation, the operation is terminated and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, because the data may have been only partially written or erased. When returning from a reset (RST# deasserted), a minimum wait is required before the initial read access outputs valid data. Also, a minimum delay is required after a reset before a write cycle can be initiated. After this wake-up interval passes, normal operation is restored. See Section 7.0, “AC Characteristics” on page 33 for details about signal-timing. ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 49 1-Gbit P30 Family 9.2 Device Commands Device operations are initiated by writing specific device commands to the Command User Interface (CUI). See Table 20, “Command Bus Cycles” on page 50. Several commands are used to modify array data including Word Program and Block Erase commands. Writing either command to the CUI initiates a sequence of internally-timed functions that culminate in the completion of the requested task. However, the operation can be aborted by either asserting RST# or by issuing an appropriate suspend command. Table 20. Command Bus Cycles (Sheet 1 of 2) First Bus Cycle Second Bus Cycle Bus Mode Command Cycles (1) (2) (1) (2) Oper Addr Data Oper Addr Data Read Array 1 Write DBA 0xFF - - - Read Device Identifier ≥ 2 Write DBA 0x90 Read DBA + IA ID Read CFI Query ≥ 2 Write DBA 0x98 Read DBA + QA QD Read Status Register 2 Write DBA 0x70 Read DBA SRD Clear Status Register 1 Write DBA 0x50 - - - 0x40/ Word Program 2 Write WA Write WA WD 0x10 (3) Program Buffered Program > 2 Write WA 0xE8 Write WA N - 1 Buffered Enhanced Factory > 2 Write WA 0x80 Write WA 0xD0 (4) Program (BEFP) Erase Block Erase 2 Write BA 0x20 Write BA 0xD0 Program/Erase Suspend 1 Write DBA 0xB0 - - - Suspend Program/Erase Resume 1 Write DBA 0xD0 - - - Lock Block 2 Write BA 0x60 Write BA 0x01 Block Locking/ Unlock Block 2 Write BA 0x60 Write BA 0xD0 Unlocking Lock-down Block 2 Write BA 0x60 Write BA 0x2F ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 50 Order Number: 306666, Revision: 001 1-Gbit P30 Family Table 20. Command Bus Cycles (Sheet 2 of 2) First Bus Cycle Second Bus Cycle Bus Mode Command Cycles (1) (2) (1) (2) Oper Addr Data Oper Addr Data Program Protection Register 2 Write PRA 0xC0 Write PRA PD Protection Program Lock Register 2 Write LRA 0xC0 Write LRA LRD Program Read Configuration Configuration 2 Write RCD 0x60 Write RCD 0x03 Register Notes: 1. First command cycle address should be the same as the operation’s target address. DBA = Device Base Address (NOTE: needed for 2 or more die stacks) IA = Identification code address offset. QA = CFI Query address offset. WA = Word address of memory location to be written. BA = Address within the block. PRA = Protection Register address. LRA = Lock Register address. RCD = Read Configuration Register data on A[15:0]. 2. ID = Identifier data. QD = Query data on DQ[15:0]. SRD = Status Register data. WD = Word data. N = Word count of data to be loaded into the write buffer. PD = Protection Register data. LRD = Lock Register data. 3. The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This is followed by up to 32 words of data.Then the confirm command (0xD0) is issued, triggering the array programming operation. 4. The confirm command (0xD0) is followed by the buffer data. 9.3 Command Definitions Valid device command codes and descriptions are shown in Table 21. Table 21. Command Codes and Definitions (Sheet 1 of 2) Mode Code Device Mode Description 0xFF Read Array Places the device in Read Array mode. Array data is output on DQ[15:0]. Places the device in Read Status Register mode. The device enters this mode 0x70 Read Status Register after a program or erase command is issued. Status Register data is output on DQ[7:0]. Read Device ID Places device in Read Device Identifier mode. Subsequent reads output Read 0x90 or Configuration manufacturer/device codes, Configuration Register data, Block Lock status, or Register Protection Register data on DQ[15:0]. Places the device in Read Query mode. Subsequent reads output Common 0x98 Read Query Flash Interface information on DQ[7:0]. The WSM can only set Status Register error bits. The Clear Status Register 0x50 Clear Status Register command is used to clear the SR error bits. First cycle of a 2-cycle programming command; prepares the CUI for a write operation. On the next write cycle, the address and data are latched and the WSM executes the programming algorithm at the addressed location. During program operations, the device responds only to Read Status Register and Write 0x40 Word Program Setup Program Suspend commands. CE# or OE# must be toggled to update the Status Register in asynchronous read. CE# or ADV# must be toggled to update the Status Register Data for synchronous Non-array reads. The Read Array command must be issued to read array data after programming has finished. ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 51 1-Gbit P30 Family Table 21. Command Codes and Definitions (Sheet 2 of 2) Mode Code Device Mode Description Alternate Word 0x10 Equivalent to the Word Program Setup command, 0x40. Program Setup This command loads a variable number of words up to the buffer size of 32 0xE8 Buffered Program words onto the program buffer. The confirm command is Issued after the data streaming for writing into the Buffered Program 0xD0 buffer is done. This instructs the WSM to perform the Buffered Program Confirm Write algorithm, writing the data from the buffer to the flash memory array. First cycle of a 2-cycle command; initiates Buffered Enhanced Factory Program mode (BEFP). The CUI then waits for the BEFP Confirm command, 0x80 BEFP Setup 0xD0, that initiates the BEFP algorithm. All other commands are ignored when BEFP mode begins. If the previous command was BEFP Setup (0x80), the CUI latches the address 0xD0 BEFP Confirm and data, and prepares the device for BEFP mode. First cycle of a 2-cycle command; prepares the CUI for a block-erase operation. The WSM performs the erase algorithm on the block addressed by 0x20 Block Erase Setup the Erase Confirm command. If the next command is not the Erase Confirm (0xD0) command, the CUI sets Status Register bits SR[4] and SR[5], and places the device in read status register mode. Erase If the first command was Block Erase Setup (0x20), the CUI latches the address and data, and the WSM erases the addressed block. During block- erase operations, the device responds only to Read Status Register and Erase 0xD0 Block Erase Confirm Suspend commands. CE# or OE# must be toggled to update the Status Register in asynchronous read. CE# or ADV# must be toggled to update the Status Register Data for synchronous Non-array reads This command issued to any device address initiates a suspend of the currently-executing program or block erase operation. The Status Register Program or Erase indicates successful suspend operation by setting either SR[2] (program 0xB0 Suspend suspended) or SR[6] (erase suspended), along with SR[7] (ready). The Write Suspend State Machine remains in the suspend mode regardless of control signal states (except for RST# asserted). This command issued to any device address resumes the suspended program 0xD0 Suspend Resume or block-erase operation. First cycle of a 2-cycle command; prepares the CUI for block lock configuration changes. If the next command is not Block Lock (0x01), Block Unlock (0xD0), 0x60 Lock Block Setup or Block Lock-Down (0x2F), the CUI sets Status Register bits SR[4] and SR[5], indicating a command sequence error. If the previous command was Block Lock Setup (0x60), the addressed block is 0x01 Lock Block Block Locking/ locked. Unlocking If the previous command was Block Lock Setup (0x60), the addressed block is 0xD0 Unlock Block unlocked. If the addressed block is in a lock-down state, the operation has no effect. If the previous command was Block Lock Setup (0x60), the addressed block is 0x2F Lock-Down Block locked down. First cycle of a 2-cycle command; prepares the device for a Protection Register Program Protection Protection 0xC0 or Lock Register program operation. The second cycle latches the register Register Setup address and data, and starts the programming algorithm First cycle of a 2-cycle command; prepares the CUI for device read Read Configuration configuration. If the Set Read Configuration Register command (0x03) is not 0x60 Register Setup the next command, the CUI sets Status Register bits SR[4] and SR[5], indicating a command sequence error. Configuration If the previous command was Read Configuration Register Setup (0x60), the Read Configuration CUI latches the address and writes A[15:0] to the Read Configuration Register. 0x03 Register Following a Configure Read Configuration Register command, subsequent read operations access array data. ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 52 Order Number: 306666, Revision: 001 1-Gbit P30 Family 10.0 Read Operations The device supports two read modes: asynchronous page mode and synchronous burst mode. Asynchronous page mode is the default read mode after device power-up or a reset. The Read Configuration Register must be configured to enable synchronous burst reads of the flash memory array (see Section 10.3, “Read Configuration Register” on page 54). The device can be in any of four read states: Read Array, Read Identifier, Read Status or Read Query. Upon power-up, or after a reset, the device defaults to Read Array. To change the read state, the appropriate read command must be written to the device (see Section 9.2, “Device Commands” on page 50). See Section 14.0, “Special Read States” on page 75 for details regarding Read Status, Read ID, and CFI Query modes. The following sections describe read-mode operations in detail. 10.1 Asynchronous Page-Mode Read Following a device power-up or reset, asynchronous page mode is the default read mode and the device is set to Read Array. However, to perform array reads after any other device operation (e.g. write operation), the Read Array command must be issued in order to read from the flash memory array. Note: Asynchronous page-mode reads can only be performed when Read Configuration Register bit RCR[15] is set (see Section 10.3, “Read Configuration Register” on page 54). To perform an asynchronous page-mode read, an address is driven onto the Address bus, and CE# and ADV# are asserted. WE# and RST# must already have been deasserted. WAIT is deasserted during asynchronous page mode. ADV# can be driven high to latch the address, or it must be held low throughout the read cycle. CLK is not used for asynchronous page-mode reads, and is ignored. If only asynchronous reads are to be performed, CLK should be tied to a valid V level, WAIT IH signal can be floated and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an initial access time t delay. (see Section 7.0, “AC Characteristics” on page 33). AVQV In asynchronous page mode, four data words are “sensed” simultaneously from the flash memory array and loaded into an internal page buffer. The buffer word corresponding to the initial address on the Address bus is driven onto DQ[15:0] after the initial access delay. The lowest two address bits determine which word of the 4-word page is output from the data buffer at any given time. 10.2 Synchronous Burst-Mode Read To perform a synchronous burst- read, an initial address is driven onto the Address bus, and CE# and ADV# are asserted. WE# and RST# must already have been deasserted. ADV# is asserted, and then deasserted to latch the address. Alternately, ADV# can remain asserted throughout the burst access, in which case the address is latched on the next valid CLK edge while ADV# is asserted. During synchronous array and non-array read modes, the first word is output from the data buffer on the next valid CLK edge after the initial access latency delay (see Section 10.3.2, “Latency Count” on page 55). Subsequent data is output on valid CLK edges following a minimum delay. ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 53 1-Gbit P30 Family However, for a synchronous non-array read, the same word of data will be output on successive clock edges until the burst length requirements are satisfied. Refer to the following waveforms for more detailed information: • Figure 19, “Synchronous Single-Word Array or Non-array Read Timing” on page 39 • Figure 20, “Continuous Burst Read, showing an Output Delay Timing” on page 40 • Figure 21, “Synchronous Burst-Mode Four-Word Read Timing” on page 41 10.3 Read Configuration Register The Read Configuration Register (RCR) is used to select the read mode (synchronous or asynchronous), and it defines the synchronous burst characteristics of the device. To modify RCR settings, use the Configure Read Configuration Register command (see Section 9.2, “Device Commands” on page 50). RCR contents can be examined using the Read Device Identifier command, and then reading from offset 0x05 (see Section 14.2, “Read Device Identifier” on page 76). The RCR is shown in Table 22. The following sections describe each RCR bit. Table 22. Read Configuration Register Description (Sheet 1 of 2) Read Configuration Register (RCR) Data WAIT Burst Read WAIT Burst CLK RES Latency Count RES RES Burst Length Mode Polarity Seq Edge Hold Delay Wrap RM R LC[2:0] WP DH WD BS CE R R BW BL[2:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Description 15 Read Mode (RM) 0 = Synchronous burst-mode read 1 = Asynchronous page-mode read (default) 14 Reserved (R) Reserved bits should be cleared (0) 13:11 Latency Count (LC[2:0]) 010 =Code 2 011 =Code 3 100 =Code 4 101 =Code 5 110 =Code 6 111 =Code 7 (default) (Other bit settings are reserved) 10 Wait Polarity (WP) 0 =WAIT signal is active low 1 =WAIT signal is active high (default) 9 Data Hold (DH) 0 =Data held for a 1-clock data cycle 1 =Data held for a 2-clock data cycle (default) 8 Wait Delay (WD) 0 =WAIT deasserted with valid data 1 =WAIT deasserted one data cycle before valid data (default) 7 Burst Sequence (BS) 0 =Reserved 1 =Linear (default) 6 Clock Edge (CE) 0 = Falling edge 1 = Rising edge (default) 5:4 Reserved (R) Reserved bits should be cleared (0) ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 54 Order Number: 306666, Revision: 001 1-Gbit P30 Family Table 22. Read Configuration Register Description (Sheet 2 of 2) 3 Burst Wrap (BW) 0 =Wrap; Burst accesses wrap within burst length set by BL[2:0] 1 =No Wrap; Burst accesses do not wrap within burst length (default) 2:0 Burst Length (BL[2:0]) 001 =4-word burst 010 =8-word burst 011 =16-word burst 111 =Continuous-word burst (default) (Other bit settings are reserved) Note: Latency Code 2, Data Hold for a 2-clock data cycle (DH = 1) WAIT must be deasserted with valid data (WD = 0). Latency Code 2, Data Hold for a 2-cock data cycle (DH=1) WAIT deasserted one data cycle before valid data (WD = 1) combination is not supported. 10.3.1 Read Mode The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode operation for the device. When the RM bit is set, asynchronous page mode is selected (default). When RM is cleared, synchronous burst mode is selected. 10.3.2 Latency Count The Latency Count bits, LC[2:0], tell the device how many clock cycles must elapse from the rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the first data word is to be driven onto DQ[15:0]. The input clock frequency is used to determine this value. Figure 28 shows the data output latency for the different settings of LC[2:0]. Synchronous burst with a Latency Count setting of Code 4 will result in zero WAIT state; however, a Latency Count setting of Code 5 will cause 1 WAIT state (Code 6 will cause 2 WAIT states, and Code 7 will cause 3 WAIT states) after every four words, regardless of whether a 16-word boundary is crossed. If RCR[9] (Data Hold) bit is set (data hold of two clocks) this WAIT condition will not occur because enough clocks elapse during each burst cycle to eliminate subsequent WAIT states. Refer to Table 23, “LC and Frequency Support” on page 56 for Latency Code Settings. ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 55 1-Gbit P30 Family Figure 28. First-Access Latency Count CLK [C] Valid Address [A] A ddress ADV# [V] Code 0 (Reserved) Valid Valid Valid Valid Valid Valid Valid Va lid DQ [D/Q] Ou tp u t O u tput O u tput Ou tp u t Ou tp u t O u tput Ou tp u t Ou tp u t 15-0 Code 1 Valid Valid Valid Valid Valid Valid Va lid (R eserved DQ [D/Q] O u tput O u tput Ou tp u t Ou tp u t O u tput Ou tp u t Ou tp u t 15-0 Code 2 Valid Valid Valid Valid Valid Va lid DQ [D/Q] O u tput Ou tp u t Ou tp u t O u tput Ou tp u t Ou tp u t 15-0 Code 3 Valid Valid Valid Valid Va lid DQ [D/Q] Ou tp u t Ou tp u t O u tput Ou tp u t Ou tp u t 15-0 Code 4 Valid Valid Valid Va lid DQ [D/Q] Ou tp u t O u tput Ou tp u t Ou tp u t 15-0 Code 5 Valid Valid Va lid DQ [D/Q] O u tput Ou tp u t Ou tp u t 15-0 Code 6 Valid Va lid DQ [D/Q] Ou tp u t Ou tp u t 15-0 Code 7 Va lid DQ [D/Q] Ou tp u t 15-0 Table 23. LC and Frequency Support Latency Count Settings Frequency Support (MHz) 2 ≤ 27 3 ≤ 40 See Figure 29, “Example Latency Count Setting using Code 3. ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 56 Order Number: 306666, Revision: 001 1-Gbit P30 Family Figure 29. Example Latency Count Setting using Code 3 t Data 01 2 34 CLK CE# ADV# Address A[MAX:0] Code 3 High-Z Data D[15:0] R103 10.3.3 WAIT Polarity The WAIT Polarity bit (WP), RCR[10] determines the asserted level (V or V ) of WAIT. OH OL When WP is set, WAIT is asserted high (default). When WP is cleared, WAIT is asserted low. WAIT changes state on valid clock edges during active bus cycles (CE# asserted, OE# asserted, RST# deasserted). 10.3.3.1 WAIT Signal Function The WAIT signal indicates data valid when the device is operating in synchronous mode (RCR[15]=0). The WAIT signal is only “deasserted” when data is valid on the bus. When the device is operating in synchronous non-array read mode, such as read status, read ID, or read query. The WAIT signal is also “deasserted” when data is valid on the bus. WAIT behavior during synchronous non-array reads at the end of word line works correctly only on the first data access. When the device is operating in asynchronous page mode, asynchronous single word read mode, and all write operations, WAIT is set to a deasserted state as determined by RCR[10]. See Figure 17, “Asynchronous Single-Word Read (ADV# Latch)” on page 38, and Figure 18, “Asynchronous Page-Mode Read Timing” on page 39. ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 57 1-Gbit P30 Family Table 24. WAIT Functionality Table Condition WAIT Notes CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’ High-Z 1 CE# =’0’, OE# = ‘0’ Active 1 Synchronous Array Reads Active 1 Synchronous Non-Array Reads Active 1 All Asynchronous Reads Deasserted 1 All Writes High-Z 1,2 Notes: 1. Active: WAIT is asserted until data becomes valid, then deasserts 2. When OE# = V during writes, WAIT = High-Z IH 10.3.4 Data Hold For burst read operations, the Data Hold (DH) bit determines whether the data output remains valid on DQ[15:0] for one or two clock cycles. This period of time is called the “data cycle”. When DH is set, output data is held for two clocks (default). When DH is cleared, output data is held for one clock (see Figure 30). The processor’s data setup time and the flash memory’s clock-to-data output delay should be considered when determining whether to hold output data for one or two clocks. A method for determining the Data Hold configuration is shown below: To set the device at one clock data hold for subsequent reads, the following condition must be satisfied: t (ns) + t (ns) ≤ One CLK Period (ns) CHQV DATA t = Data set up to Clock (defined by CPU) DATA For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming t = 20 ns and t = 4 ns. Applying these values to the formula above: CHQV DATA 20 ns + 4 ns ≤ 25 ns The equation is satisfied and data will be available at every clock period with data hold setting at one clock. If t (ns) + t (ns) > One CLK Period (ns), data hold setting of 2 clock periods CHQV DATA must be used. Figure 30. Data Hold Timing CLK [C] 1 CLK Valid Valid Valid D[15:0] [Q] Output Output Output Data Hold 2 CLK Valid Valid D[15:0] [Q] Output Output Data Hold ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 58 Order Number: 306666, Revision: 001 … … … … … … … … … … … … … … … … … … 1-Gbit P30 Family 10.3.5 WAIT Delay The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during synchronous burst reads. WAIT can be asserted either during or one data cycle before valid data is output on DQ[15:0]. When WD is set, WAIT is deasserted one data cycle before valid data (default). When WD is cleared, WAIT is deasserted during valid data. 10.3.6 Burst Sequence The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst sequence is supported. Table 25 shows the synchronous burst sequence for all burst lengths, as well as the effect of the Burst Wrap (BW) setting. Table 25. Burst Sequence Word Ordering Burst Addressing Sequence (DEC) Start Burst Wrap Addr. (RCR[3]) 4-Word Burst 8-Word Burst 16-Word Burst Continuous Burst (DEC) (BL[2:0] = 0b001) (BL[2:0] = 0b010) (BL[2:0] = 0b011) (BL[2:0] = 0b111) 0 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4…14-15 0-1-2-3-4-5-6-… 1 0 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5…15-0 1-2-3-4-5-6-7-… 2 0 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6…15-0-1 2-3-4-5-6-7-8-… 3 0 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7…15-0-1-2 3-4-5-6-7-8-9-… 40 4-5-6-7-0-1-2-3 4-5-6-7-8…15-0-1-2-3 4-5-6-7-8-9-10… 50 5-6-7-0-1-2-3-4 5-6-7-8-9…15-0-1-2-3-4 5-6-7-8-9-10-11… 60 6-7-0-1-2-3-4-5 6-7-8-9-10…15-0-1-2-3-4-5 6-7-8-9-10-11-12-… 70 7-0-1-2-3-4-5-6 7-8-9-10…15-0-1-2-3-4-5-6 7-8-9-10-11-12-13… 14 0 14-15-0-1-2…12-13 14-15-16-17-18-19-20-… 15 0 15-0-1-2-3…13-14 15-16-17-18-19-20-21-… 0 1 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4…14-15 0-1-2-3-4-5-6-… 1 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5…15-16 1-2-3-4-5-6-7-… 2 1 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6…16-17 2-3-4-5-6-7-8-… 3 1 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7…17-18 3-4-5-6-7-8-9-… 41 4-5-6-7-8-9-10-11 4-5-6-7-8…18-19 4-5-6-7-8-9-10… 51 5-6-7-8-9-10-11-12 5-6-7-8-9…19-20 5-6-7-8-9-10-11… 61 6-7-8-9-10-11-12-13 6-7-8-9-10…20-21 6-7-8-9-10-11-12-… 71 7-8-9-10-11-12-13-14 7-8-9-10-11…21-22 7-8-9-10-11-12-13… 14 1 14-15-16-17-18…28-29 14-15-16-17-18-19-20-… 15 1 15-16-17-18-19…29-30 15-16-17-18-19-20-21-… 10.3.7 Clock Edge The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK. This clock edge is used at the start of a burst cycle, to output synchronous data, and to assert/deassert WAIT. 10.3.8 Burst Wrap The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length accesses wrap within the selected word-length boundaries or cross word-length boundaries. When BW is set, burst wrapping does not occur (default). When BW is cleared, burst wrapping occurs. When performing synchronous burst reads with BW set (no wrap), an output delay may occur when the burst sequence crosses its first device-row (16-word) boundary. If the burst sequence’s start address is 4-word aligned, then no delay occurs. If the start address is at the end of a 4-word ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 59 1-Gbit P30 Family boundary, the worst case output delay is one clock cycle less than the first access Latency Count. This delay can take place only once, and doesn’t occur if the burst sequence does not cross a device-row boundary. WAIT informs the system of this delay when it occurs. 10.3.9 Burst Length The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word. Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see Table 25, “Burst Sequence Word Ordering” on page 59). When a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the “burstable” address space. ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 60 Order Number: 306666, Revision: 001 1-Gbit P30 Family 11.0 Programming Operations The device supports three programming methods: Word Programming (40h/10h), Buffered Programming (E8h, D0h), and Buffered Enhanced Factory Programming (80h, D0h). See Section 9.0, “Device Operations” on page 48 for details on the various programming commands issued to the device. The following sections describe device programming in detail. Successful programming requires the addressed block to be unlocked. If the block is locked down, WP# must be deasserted and the block must be unlocked before attempting to program the block. Attempting to program a locked block causes a program error (SR[4] and SR[1] set) and termination of the operation. See Section 13.0, “Security Modes” on page 69 for details on locking and unlocking blocks. The Intel StrataFlash® Embedded Memory (P30) is segmented into multiple Programming Regions. Programming Regions are made up of 8 or 16 blocks depending on the density. The 64- and 128-Mbit devices have 8 blocks per Programming Region, while the 256-Mbit has 16 blocks in each Programming Region (see Table 26). See Section 4.4, “Memory Maps” on page 24 for address ranges of each Programming Region per density. Table 26. Programming Regions per Device Number of blocks per Number of Programming Device Density Programming Region Regions per Device 64-Mbit 8 blocks 8 128-Mbit 8 blocks 16 256-Mbit 16 blocks 16 512-Mbit 16 blocks 32 1-Gbit 16 blocks 64 Execute in Place (XIP) is defined as the ability to execute code directly from the flash memory. XIP applications must partition the memory such that code and data are in separate programming regions (see Table 26, “Programming Regions per Device” on page 61). Each Programming Region should contain only code or data, and not both. The following terms define the difference between code and data. System designs must use these definitions when partitioning their code and data for the P30 device. Code : Execution code ran out of the flash device on a continuous basis in the system. Data : Information periodically programmed into the flash device and read back (e.g. execution code shadowed and executed in RAM, pictures, log files, etc.). 11.1 Word Programming Word programming operations are initiated by writing the Word Program Setup command to the device (see Section 9.0, “Device Operations” on page 48). This is followed by a second write to the device with the address and data to be programmed. The device outputs Status Register data when read. See Figure 40, “Word Program Flowchart” on page 85. V must be above V , and within PP PPLK the specified V min/max values (nominally 1.8 V). PPL ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 61 1-Gbit P30 Family During programming, the Write State Machine (WSM) executes a sequence of internally-timed events that program the desired data bits at the addressed location, and verifies that the bits are sufficiently programmed. Programming the flash memory array changes “ones” to “zeros”. Memory array bits that are zeros can be changed to ones only by erasing the block (see Section 12.0, “Erase Operations” on page 67). The Status Register can be examined for programming progress and errors by reading at any address. The device remains in the Read Status Register state until another command is written to the device. Status Register bit SR[7] indicates the programming status while the sequence executes. Commands that can be issued to the device during programming are Program Suspend, Read Status Register, Read Device Identifier, CFI Query, and Read Array (this returns unknown data). When programming has finished, Status Register bit SR[4] (when set) indicates a programming failure. If SR[3] is set, the WSM could not perform the word programming operation because V PP was outside of its acceptable limits. If SR[1] is set, the word programming operation attempted to program a locked block, causing the operation to abort. Before issuing a new command, the Status Register contents should be examined and then cleared using the Clear Status Register command. Any valid command can follow, when word programming has completed. 11.1.1 Factory Word Programming Factory word programming is similar to word programming in that it uses the same commands and programming algorithms. However, factory word programming enhances the programming performance with V = V . This can enable faster programming times during OEM PP PPH manufacturing processes. Factory word programming is not intended for extended use. See Section 5.2, “Operating Conditions” on page 30 for limitations when V = V . PP PPH Note: When V = V , the device draws programming current from the V supply. If V is driven PP PPL CC PP by a logic signal, V must remain above V MIN to program the device. When V = V , PPL PPL PP PPH the device draws programming current from the V supply. Figure 31, “Example VPP Supply PP Connections” on page 66 shows examples of device power supply configurations. 11.2 Buffered Programming The device features a 32-word buffer to enable optimum programming performance. For Buffered Programming, data is first written to an on-chip write buffer. Then the buffer data is programmed into the flash memory array in buffer-size increments. This can improve system programming performance significantly over non-buffered programming. When the Buffered Programming Setup command is issued (see Section 9.2, “Device Commands” on page 50), Status Register information is updated and reflects the availability of the buffer. SR[7] indicates buffer availability: if set, the buffer is available; if cleared, the buffer is not available. To retry, issue the Buffered Programming Setup command again, and re-check SR[7]. When SR[7] is set, the buffer is ready for loading. (see Figure 42, “Buffer Program Flowchart” on page 87). On the next write, a word count is written to the device at the buffer address. This tells the device how many data words will be written to the buffer, up to the maximum size of the buffer. ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 62 Order Number: 306666, Revision: 001 1-Gbit P30 Family On the next write, a device start address is given along with the first data to be written to the flash memory array. Subsequent writes provide additional device addresses and data. All data addresses must lie within the start address plus the word count. Optimum programming performance and lower power usage are obtained by aligning the starting address at the beginning of a 32-word boundary (A[4:0] = 0x00). Crossing a 32-word boundary during programming will double the total programming time. After the last data is written to the buffer, the Buffered Programming Confirm command must be issued to the original block address. The WSM begins to program buffer contents to the flash memory array. If a command other than the Buffered Programming Confirm command is written to the device, a command sequence error occurs and Status Register bits SR[7,5,4] are set. If an error occurs while writing to the array, the device stops programming, and Status Register bits SR[7,4] are set, indicating a programming failure. When Buffered Programming has completed, additional buffer writes can be initiated by issuing another Buffered Programming Setup command and repeating the buffered program sequence. Buffered programming may be performed with V = V or V (see Section 5.2, “Operating PP PPL PPH Conditions” on page 30 for limitations when operating the device with V = V ). PP PPH If an attempt is made to program past an erase-block boundary using the Buffered Program command, the device aborts the operation. This generates a command sequence error, and Status Register bits SR[5,4] are set. If Buffered programming is attempted while V is below V , Status Register bits SR[4,3] are PP PPLK set. If any errors are detected that have set Status Register bits, the Status Register should be cleared using the Clear Status Register command. 11.3 Buffered Enhanced Factory Programming Buffered Enhanced Factory Programing (BEFP) speeds up Multi-Level Cell (MLC) flash programming. The enhanced programming algorithm used in BEFP eliminates traditional programming elements that drive up overhead in device programmer systems. BEFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 43, “BEFP Flowchart” on page 88). It uses a write buffer to spread MLC program performance across 32 data words. Verification occurs in the same phase as programming to accurately program the flash memory cell to the correct bit state. A single two-cycle command sequence programs the entire block of data. This enhancement eliminates three write cycles per buffer: two commands and the word count for each set of 32 data words. Host programmer bus cycles fill the device’s write buffer followed by a status check. SR[0] indicates when data from the buffer has been programmed into sequential flash memory array locations. Following the buffer-to-flash array programming sequence, the Write State Machine (WSM) increments internal addressing to automatically select the next 32-word array boundary. This aspect of BEFP saves host programming equipment the address-bus setup overhead. With adequate continuity testing, programming equipment can rely on the WSM’s internal verification to ensure that the device has programmed properly. This eliminates the external post- program verification and its associated overhead. ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 63 1-Gbit P30 Family 11.3.1 BEFP Requirements and Considerations BEFP requirements: • Case temperature: T = 25 °C ± 5 °C C • V within specified operating range CC • VPP driven to V PPH • Target block unlocked before issuing the BEFP Setup and Confirm commands • The first-word address (WA0) for the block to be programmed must be held constant from the setup phase through all data streaming into the target block, until transition to the exit phase is desired 1 • WA0 must align with the start of an array buffer boundary BEFP considerations: 2 • For optimum performance, cycling must be limited below 100 erase cycles per block 3 • BEFP programs one block at a time; all buffer data must fall within a single block • BEFP cannot be suspended 4 • Programming to the flash memory array can occur only when the buffer is full NOTES: 1. Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start point is A[4:0] = 0x00. 2. Some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work properly. 3. If the internal address counter increments beyond the block's maximum address, addressing wraps around to the beginning of the block. 4. If the number of words is less than 32, remaining locations must be filled with 0xFFFF. 11.3.2 BEFP Setup Phase After receiving the BEFP Setup and Confirm command sequence, Status Register bit SR[7] (Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup. A delay before checking SR[7] is required to allow the WSM enough time to perform all of its setups and checks (Block-Lock status, V level, etc.). If an error is detected, SR[4] is set and BEFP operation PP terminates. If the block was found to be locked, SR[1] is also set. SR[3] is set if the error occurred due to an incorrect V level. PP Note: Reading from the device after the BEFP Setup and Confirm command sequence outputs Status Register data. Do not issue the Read Status Register command; it will be interpreted as data to be loaded into the buffer. 11.3.3 BEFP Program/Verify Phase After the BEFP Setup Phase has completed, the host programming system must check SR[7,0] to determine the availability of the write buffer for data streaming. SR[7] cleared indicates the device is busy and the BEFP program/verify phase is activated. SR[0] indicates the write buffer is available. ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 64 Order Number: 306666, Revision: 001 1-Gbit P30 Family Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data programming to the array. For BEFP, the count value for buffer loading is always the maximum buffer size of 32 words. During the buffer-loading sequence, data is stored to sequential buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory array starts as soon as the buffer is full. If the number of words is less than 32, the remaining buffer locations must be filled with 0xFFFF. Caution: The buffer must be completely filled for programming to occur. Supplying an address outside of the current block's range during a buffer-fill sequence causes the algorithm to exit immediately. Any data previously loaded into the buffer during the fill cycle is not programmed into the array. The starting address for data entry must be buffer size aligned, if not the BEFP algorithm will be aborted and the program fails and (SR[4]) flag will be set. Data words from the write buffer are directed to sequential memory locations in the flash memory array; programming continues from where the previous buffer sequence ended. The host programming system must poll SR[0] to determine when the buffer program sequence completes. SR[0] cleared indicates that all buffer data has been transferred to the flash array; SR[0] set indicates that the buffer is not available yet for the next fill cycle. The host system may check full status for errors at any time, but it is only necessary on a block basis after BEFP exit. After the buffer fill cycle, no write cycles should be issued to the device until SR[0] = 0 and the device is ready for the next buffer fill. Note: Any spurious writes are ignored after a buffer fill operation and when internal program is proceeding. The host programming system continues the BEFP algorithm by providing the next group of data words to be written to the buffer. Alternatively, it can terminate this phase by changing the block address to one outside of the current block’s range. The Program/Verify phase concludes when the programmer writes to a different block address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the device enters the BEFP Exit phase. 11.3.4 BEFP Exit Phase When SR[7] is set, the device has returned to normal operating conditions. A full status check should be performed at this time to ensure the entire block programmed successfully. When exiting the BEFP algorithm with a block address change, the read mode will not change. After BEFP exit, any valid command can be issued to the device. 11.4 Program Suspend Issuing the Program Suspend command while programming suspends the programming operation. This allows data to be accessed from the device other than the one being programmed. The Program Suspend command can be issued to any device address. A program operation can be suspended to perform reads only. Additionally, a program operation that is running during an erase suspend can be suspended to perform a read operation (see Figure 41, “Program Suspend/Resume Flowchart” on page 86). ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 65 1-Gbit P30 Family When a programming operation is executing, issuing the Program Suspend command requests the WSM to suspend the programming algorithm at predetermined points. The device continues to output Status Register data after the Program Suspend command is issued. Programming is suspended when Status Register bits SR[7,2] are set. Suspend latency is specified in Section 7.5, “Program and Erase Characteristics” on page 45. To read data from the device, the Read Array command must be issued. Read Array, Read Status Register, Read Device Identifier, CFI Query, and Program Resume are valid commands during a program suspend. During a program suspend, deasserting CE# places the device in standby, reducing active current. V must remain at its programming level, and WP# must remain unchanged while in program PP suspend. If RST# is asserted, the device is reset. 11.5 Program Resume The Resume command instructs the device to continue programming, and automatically clears Status Register bits SR[7,2]. This command can be written to any address. If error bits are set, the Status Register should be cleared before issuing the next instruction. RST# must remain deasserted (see Figure 41, “Program Suspend/Resume Flowchart” on page 86). 11.6 Program Protection When V = V , absolute hardware write protection is provided for all device blocks. If V is at PP IL PP or below V , programming operations halt and SR[3] is set indicating a V -level error. Block PPLK PP lock registers are not affected by the voltage level on V ; they may still be programmed and read, PP even if V is less than V . PP PPLK Figure 31. Example VPP Supply Connections V V VCC VCC CC CC PROT # V VPP VPP PP ≤ 10K Ω • Low-voltage Programming only • Factory Programming with V = V • Logic Control of Device Protection PP PPH • Complete write/Erase Protection when V ≤ V PP PPLK V V CC VCC CC VCC V =V VPP VPP PP PPH • Low Voltage Programming Only • Low Voltage and Factory Programming • Full Device Protection Unavailable ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 66 Order Number: 306666, Revision: 001 1-Gbit P30 Family 12.0 Erase Operations Flash erasing is performed on a block basis. An entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. When a block is erased, all bits within that block read as logical ones. The following sections describe block erase operations in detail. 12.1 Block Erase Block erase operations are initiated by writing the Block Erase Setup command to the address of the block to be erased (see Section 9.2, “Device Commands” on page 50). Next, the Block Erase Confirm command is written to the address of the block to be erased. If the device is placed in standby (CE# deasserted) during an erase operation, the device completes the erase operation before entering standby.V must be above V and the block must be unlocked (see Figure 44, PP PPLK “Block Erase Flowchart” on page 89). During a block erase, the Write State Machine (WSM) executes a sequence of internally-timed events that conditions, erases, and verifies all bits within the block. Erasing the flash memory array changes “zeros” to “ones”. Memory array bits that are ones can be changed to zeros only by programming the block (see Section 11.0, “Programming Operations” on page 61). The Status Register can be examined for block erase progress and errors by reading any address. The device remains in the Read Status Register state until another command is written. SR[0] indicates whether the addressed block is erasing. Status Register bit SR[7] is set upon erase completion. Status Register bit SR[7] indicates block erase status while the sequence executes. When the erase operation has finished, Status Register bit SR[5] indicates an erase failure if set. SR[3] set would indicate that the WSM could not perform the erase operation because V was outside of its PP acceptable limits. SR[1] set indicates that the erase operation attempted to erase a locked block, causing the operation to abort. Before issuing a new command, the Status Register contents should be examined and then cleared using the Clear Status Register command. Any valid command can follow once the block erase operation has completed. 12.2 Erase Suspend Issuing the Erase Suspend command while erasing suspends the block erase operation. This allows data to be accessed from memory locations other than the one being erased. The Erase Suspend command can be issued to any device address. A block erase operation can be suspended to perform a word or buffer program operation, or a read operation within any block except the block that is erase suspended (see Figure 41, “Program Suspend/Resume Flowchart” on page 86). When a block erase operation is executing, issuing the Erase Suspend command requests the WSM to suspend the erase algorithm at predetermined points. The device continues to output Status Register data after the Erase Suspend command is issued. Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is specified in Section 7.5, “Program and Erase Characteristics” on page 45. ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 67 1-Gbit P30 Family To read data from the device (other than an erase-suspended block), the Read Array command must be issued. During Erase Suspend, a Program command can be issued to any block other than the erase-suspended block. Block erase cannot resume until program operations initiated during erase suspend complete. Read Array, Read Status Register, Read Device Identifier, CFI Query, and Erase Resume are valid commands during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase Suspend. During an erase suspend, deasserting CE# places the device in standby, reducing active current. V must remain at a valid level, and WP# must remain unchanged while in erase suspend. If PP RST# is asserted, the device is reset. 12.3 Erase Resume The Erase Resume command instructs the device to continue erasing, and automatically clears status register bits SR[7,6]. This command can be written to any address. If status register error bits are set, the Status Register should be cleared before issuing the next instruction. RST# must remain deasserted (see Figure 41, “Program Suspend/Resume Flowchart” on page 86). 12.4 Erase Protection When V = V , absolute hardware erase protection is provided for all device blocks. If V is PP IL PP below V , erase operations halt and SR[3] is set indicating a V -level error. PPLK PP ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 68 Order Number: 306666, Revision: 001 1-Gbit P30 Family 13.0 Security Modes The device features security modes used to protect the information stored in the flash memory array. The following sections describe each security mode in detail. 13.1 Block Locking Individual instant block locking is used to protect user code and/or data within the flash memory array. All blocks power up in a locked state to protect array data from being altered during power transitions. Any block can be locked or unlocked with no latency. Locked blocks cannot be programmed or erased; they can only be read. Software-controlled security is implemented using the Block Lock and Block Unlock commands. Hardware-controlled security can be implemented using the Block Lock-Down command along with asserting WP#. Also, V data security can be used to inhibit program and erase operations PP (see Section 11.6, “Program Protection” on page 66 and Section 12.4, “Erase Protection” on page 68). The P30 device also offers four pre-defined areas in the main array that can be configured as One- Time Programmable (OTP) for the highest level of security. These include the four 32 KB parameter blocks together as one and the three adjacent 128 KB main blocks. This is available for top or bottom parameter devices. 13.1.1 Lock Block To lock a block, issue the Lock Block Setup command. The next command must be the Lock Block command issued to the desired block’s address (see Section 9.2, “Device Commands” on page 50 and Figure 46, “Block Lock Operations Flowchart” on page 91). If the Set Read Configuration Register command is issued after the Block Lock Setup command, the device configures the RCR instead. Block lock and unlock operations are not affected by the voltage level on V . The block lock bits PP may be modified and/or read even if V is at or below V . PP PPLK 13.1.2 Unlock Block The Unlock Block command is used to unlock blocks (see Section 9.2, “Device Commands” on page 50). Unlocked blocks can be read, programmed, and erased. Unlocked blocks return to a locked state when the device is reset or powered down. If a block is in a lock-down state, WP# must be deasserted before it can be unlocked (see Figure 32, “Block Locking State Diagram” on page 70). 13.1.3 Lock-Down Block A locked or unlocked block can be locked-down by writing the Lock-Down Block command sequence (see Section 9.2, “Device Commands” on page 50). Blocks in a lock-down state cannot be programmed or erased; they can only be read. However, unlike locked blocks, their locked state cannot be changed by software commands alone. A locked-down block can only be unlocked by issuing the Unlock Block command with WP# deasserted. To return an unlocked block to locked- ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 69 1-Gbit P30 Family down state, a Lock-Down command must be issued prior to changing WP# to V . Locked-down IL blocks revert to the locked state upon reset or power up the device (see Figure 32, “Block Locking State Diagram” on page 70). 13.1.4 Block Lock Status The Read Device Identifier command is used to determine a block’s lock status (see Section 14.2, “Read Device Identifier” on page 76). Data bits DQ[1:0] display the addressed block’s lock status; DQ0 is the addressed block’s lock bit, while DQ1 is the addressed block’s lock-down bit. Figure 32. Block Locking State Diagram Locked- Hardware 4,5 Locked 5 Power-Up/Reset Down Locked [X01] [011] [011] WP# Hardware Control Software Unlocked Unlocked Locked [X00] [111] [110] Software Block Lock (0x60/0x01) or Software Block Unlock (0x60/0xD0) Software Block Lock-Down (0x60/0x2F) WP# hardware control Notes: 1. [a,b,c] represents [WP#, DQ1, DQ0]. X = Don’t Care. 2. DQ1 indicates Block Lock-Down status. DQ1 = ‘0’, Lock-Down has not been issued to this block. DQ1 = ‘1’, Lock-Down has been issued to this block. 3. DQ0 indicates block lock status. DQ0 = ‘0’, block is unlocked. DQ0 = ‘1’, block is locked. 4. Locked-down = Hardware + Software locked. 5. [011] states should be tracked by system software to determine difference between Hardware Locked and Locked-Down states. 13.1.5 Block Locking During Suspend Block lock and unlock changes can be performed during an erase suspend. To change block locking during an erase operation, first issue the Erase Suspend command. Monitor the Status Register until SR[7] and SR[6] are set, indicating the device is suspended and ready to accept another command. Next, write the desired lock command sequence to a block, which changes the lock state of that block. After completing block lock or unlock operations, resume the erase operation using the Erase Resume command. Note: A Lock Block Setup command followed by any command other than Lock Block, Unlock Block, or Lock-Down Block produces a command sequence error and set Status Register bits SR[4] and ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 70 Order Number: 306666, Revision: 001 1-Gbit P30 Family SR[5]. If a command sequence error occurs during an erase suspend, SR[4] and SR[5] remains set, even after the erase operation is resumed. Unless the Status Register is cleared using the Clear Status Register command before resuming the erase operation, possible erase errors may be masked by the command sequence error. If a block is locked or locked-down during an erase suspend of the same block, the lock status bits change immediately. However, the erase operation completes when it is resumed. Block lock operations cannot occur during a program suspend. See Appendix A, “Write State Machine” on page 78, which shows valid commands during an erase suspend. 13.2 Selectable One-Time Programmable Blocks Any of four pre-defined areas from the main array (the four 32 KB parameter blocks together as one and the three adjacent 128 KB main blocks) can be configured as One-Time Programmable (OTP) so further program and erase operations are not allowed. This option is available for top or bottom parameter devices. Table 27. Selectable OTP Block Mapping Density Top Parameter Configuration Bottom Parameter Configuration blocks 258:255 (parameters) blocks 3:0 (parameters) block 254 (main) block 4 (main) 256-Mbit block 253 (main) block 5 (main) block 252 (main) block 6 (main) blocks 130:127 (parameters) blocks 3:0 (parameters) block 126 (main) block 4 (main) 128-Mbit block 125 (main) block 5 (main) block 124 (main) block 6 (main) blocks 66:63 (parameters) blocks 3:0 (parameters) block 62 (main) block 4 (main) 64-Mbit block 61 (main) block 5 (main) block 60 (main) block 6 (main) Note: The 512-Mbit and 1-Gbit devices will have multiple Selectable OTP Areas depending on the number of 256-Mbit dies in the stack and the placement of the parameter blocks. Please see your local Intel representative for details about the Selectable OTP implementation. ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 71 1-Gbit P30 Family 13.3 Protection Registers The device contains 17 Protection Registers (PRs) that can be used to implement system security measures and/or device identification. Each Protection Register can be individually locked. The first 128-bit Protection Register is comprised of two 64-bit (8-word) segments. The lower 64- bit segment is pre-programmed at the Intel factory with a unique 64-bit number. The other 64-bit segment, as well as the other sixteen 128-bit Protection Registers, are blank. Users can program these registers as needed. When programmed, users can then lock the Protection Register(s) to prevent additional bit programming (see Figure 33, “Protection Register Map” on page 73). The user-programmable Protection Registers contain one-time programmable (OTP) bits; when programmed, register bits cannot be erased. Each Protection Register can be accessed multiple times to program individual bits, as long as the register remains unlocked. Each Protection Register has an associated Lock Register bit. When a Lock Register bit is programmed, the associated Protection Register can only be read; it can no longer be programmed. Additionally, because the Lock Register bits themselves are OTP, when programmed, Lock Register bits cannot be erased. Therefore, when a Protection Register is locked, it cannot be unlocked. ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 72 Order Number: 306666, Revision: 001 1-Gbit P30 Family . Figure 33. Protection Register Map 0x109 128-bit Protection Register 16 (User-Programmable) 0x102 0x91 128-bit Protection Register 1 (User-Programmable) 0x8A Lock Register 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x89 0x88 64-bit Segment (User-Programmable) 0x85 128-Bit Protection Register 0 0x84 64-bit Segment (Factory-Programmed) 0x81 Lock Register 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x80 13.3.1 Reading the Protection Registers The Protection Registers can be read from any address. To read the Protection Register, first issue the Read Device Identifier command at any address to place the device in the Read Device Identifier state (see Section 9.2, “Device Commands” on page 50). Next, perform a read operation using the address offset corresponding to the register to be read. Table 29, “Device Identifier Information” on page 77 shows the address offsets of the Protection Registers and Lock Registers. Register data is read 16 bits at a time. 13.3.2 Programming the Protection Registers To program any of the Protection Registers, first issue the Program Protection Register command at the parameter’s base address plus the offset to the desired Protection Register (see Section 9.2, “Device Commands” on page 50). Next, write the desired Protection Register data to the same Protection Register address (see Figure 33, “Protection Register Map” on page 73). ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 73 1-Gbit P30 Family The device programs the 64-bit and 128-bit user-programmable Protection Register data 16 bits at a time (see Figure 47, “Protection Register Programming Flowchart” on page 92). Issuing the Program Protection Register command outside of the Protection Register’s address space causes a program error (SR[4] set). Attempting to program a locked Protection Register causes a program error (SR[4] set) and a lock error (SR[1] set). 13.3.3 Locking the Protection Registers Each Protection Register can be locked by programming its respective lock bit in the Lock Register. To lock a Protection Register, program the corresponding bit in the Lock Register by issuing the Program Lock Register command, followed by the desired Lock Register data (see Section 9.2, “Device Commands” on page 50). The physical addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1. These addresses are used when programming the lock registers (see Table 29, “Device Identifier Information” on page 77). Bit 0 of Lock Register 0 is already programmed at the factory, locking the lower, pre-programmed 64-bit region of the first 128-bit Protection Register containing the unique identification number of the device. Bit 1 of Lock Register 0 can be programmed by the user to lock the user-programmable, 64-bit region of the first 128-bit Protection Register. When programming Bit 1 of Lock Register 0, all other bits need to be left as ‘1’ such that the data programmed is 0xFFFD. Lock Register 1 controls the locking of the upper sixteen 128-bit Protection Registers. Each of the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit Protection Registers. Programming a bit in Lock Register 1 locks the corresponding 128-bit Protection Register. Caution: After being locked, the Protection Registers cannot be unlocked. ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 74 Order Number: 306666, Revision: 001 1-Gbit P30 Family 14.0 Special Read States The following sections describe non-array read states. Non-array reads can be performed in asynchronous read or synchronous burst mode. A non-array read operation occurs as asynchronous single-word mode. When non-array reads are performed in asynchronous page mode only the first data is valid and all subsequent data are undefined. When a non-array read operation occurs as synchronous burst mode, the same word of data requested will be output on successive clock edges until the burst length requirements are satisfied. Refer to the following waveforms for more detailed information: • Figure 16, “Asynchronous Single-Word Read (ADV# Low)” on page 38 • Figure 17, “Asynchronous Single-Word Read (ADV# Latch)” on page 38 • Figure 19, “Synchronous Single-Word Array or Non-array Read Timing” on page 39 14.1 Read Status Register To read the Status Register, issue the Read Status Register command at any address. Status Register information is available to which the Read Status Register, Word Program, or Block Erase command was issued. Status Register data is automatically made available following a Word Program, Block Erase, or Block Lock command sequence. Reads from the device after any of these command sequences outputs the device’s status until another valid command is written (e.g. Read Array command). The Status Register is read using single asynchronous-mode or synchronous burst mode reads. Status Register data is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates and latches the Status Register contents. However, reading the Status Register in synchronous burst mode, CE# or ADV# must be toggled to update status data. The Device Write Status bit (SR[7]) provides overall status of the device. Status register bits SR[6:1] present status and error information about the program, erase, suspend, V , and block- PP locked operations. Table 28. Status Register Description (Sheet 1 of 2) Status Register (SR) Default Value = 0x80 Erase Program Block- Device Erase Program BEFP Suspend V Status Suspend Locked PP Write Status Status Status Status Status Status Status DWS ESS ES PS VPPS PSS BLS BWS 7 654 32 10 Bit Name Description Device Write Status 0 = Device is busy; program or erase cycle in progress; SR[0] valid. 7 (DWS) 1 = Device is ready; SR[6:1] are valid. Erase Suspend Status 0 = Erase suspend not in effect. 6 (ESS) 1 = Erase suspend in effect. ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 75 1-Gbit P30 Family Table 28. Status Register Description (Sheet 2 of 2) Status Register (SR) Default Value = 0x80 0 = Erase successful. 5 Erase Status (ES) 1 = Erase fail or program sequence error when set with SR[4,7]. 0 = Program successful. 4 Program Status (PS) 1 = Program fail or program sequence error when set with SR[5,7] 0 = VPP within acceptable limits during program or erase operation. 3V Status (VPPS) PP 1 = VPP < VPPLK during program or erase operation. Program Suspend Status 0 = Program suspend not in effect. 2 (PSS) 1 = Program suspend in effect. Block-Locked Status 0 = Block not locked during program or erase. 1 (BLS) 1 = Block locked during program or erase; operation aborted. DWS BWS 0 0 = WSM is busy and buffer is available for loading. 0 BEFP Status (BWS) 0 1 = WSM is busy and buffer is not available for loading. 1 0 = WSM is not busy and buffer is available for loading. 1 1 = Reserved for Future Use (RFU). Note: Always clear the Status Register prior to resuming erase operations. It avoids Status Register ambiguity when issuing commands during Erase Suspend. If a command sequence error occurs during an erase-suspend state, the Status Register contains the command sequence error status (SR[7,5,4] set). When the erase operation resumes and finishes, possible errors during the erase operation cannot be detected via the Status Register because it contains the previous error status. 14.1.1 Clear Status Register The Clear Status Register command clears the status register. It functions independent of V . The PP Write State Machine (WSM) sets and clears SR[7,6,2], but it sets bits SR[5:3,1] without clearing them. The Status Register should be cleared before starting a command sequence to avoid any ambiguity. A device reset also clears the Status Register. 14.2 Read Device Identifier The Read Device Identifier command instructs the device to output manufacturer code, device identifier code, block-lock status, protection register data, or configuration register data (see Section 9.2, “Device Commands” on page 50 for details on issuing the Read Device Identifier command). Table 29, “Device Identifier Information” on page 77 and Table 30, “Device ID codes” on page 77 show the address offsets and data values for this device. ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 76 Order Number: 306666, Revision: 001 1-Gbit P30 Family Table 29. Device Identifier Information (1) Item Address Data Manufacturer Code 0x00 0089h Device ID Code 0x01 ID (see Table 30) Block Lock Configuration: Lock Bit: • Block Is Unlocked DQ = 0b0 0 • Block Is Locked BBA + 0x02 DQ = 0b1 0 • Block Is not Locked-Down DQ = 0b0 1 • Block Is Locked-Down DQ = 0b1 1 Configuration Register 0x05 Configuration Register Data Lock Register 0 0x80 PR-LK0 64-bit Factory-Programmed Protection Register 0x81–0x84 Factory Protection Register Data 64-bit User-Programmable Protection Register 0x85–0x88 User Protection Register Data Lock Register 1 0x89 Protection Register Data 128-bit User-Programmable Protection Registers 0x8A–0x109 PR-LK1 Notes: 1. BBA = Block Base Address. Table 30. Device ID codes Device Identifier Codes ID Code Type Device Density –T –B (Top Parameter) (Bottom Parameter) 64-Mbit 8817 881A Device Code 128-Mbit 8818 881B 256-Mbit 8919 891C 14.3 CFI Query The CFI Query command instructs the device to output Common Flash Interface (CFI) data when read. See Section 9.2, “Device Commands” on page 50 for details on issuing the CFI Query command. Appendix C, “Common Flash Interface” on page 93 shows CFI information and address offsets within the CFI database. ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 77 1-Gbit P30 Family Appendix A Write State Machine Figure 34 through Figure 39 show the command state transitions (Next State Table) based on incoming commands. Only one partition can be actively programming or erasing at a time. Each partition stays in its last read state (Read Array, Read Device ID, CFI Query or Read Status Register) until a new command changes it. The next WSM state does not depend on the partition’s output state. Figure 34. Write State Machine—Next State Table (Sheet 1 of 6) Command Input to Chip and resulting Chip Next State BE Confirm, Buffered Buffered P/E BP / Prg / Clear Lock, Unlock, Read Word Erase Enhanced Read Read Program Resume, Erase Status Lock-down, (2) (3,4) (3,4) Current Chip Factory Pgm Status ID/Query Array Program Setup (5) (4) ULB, (BP) Suspend (3, 4) Register CR setup (7) Setup (8) State Confirm (FFH) (10H/40H) (E8H) (20H) (80H) (D0H) (B0H) (70H) (50H) (90H, 98H) (60H) Program Erase Lock/CR Ready Ready BP Setup BEFP Setup Ready Setup Setup Setup Ready Lock/CR Setup Ready (Lock Error) (Unlock Ready (Lock Error) Block) Setup OTP OTP Busy Busy Setup Word Program Busy Word Busy Program Busy Program Word Program Busy Word Suspend Program Word Suspend Word Program Suspend Program Word Program Suspend Busy Setup BP Load 1 BP Load 2 BP Load 1 BP Confirm if Data load into Program Buffer is complete; Else BP Load 2 BP Load 2 BP BP Ready (Error) Ready (Error) BP Busy Confirm BP Busy BP Busy BP Busy BP Suspend BP BP Suspend BP Busy BP Suspend Suspend Setup Ready (Error) Erase Busy Ready (Error) Erase Busy Erase Busy Erase Busy Suspend Erase Word Lock/CR Program BP Setup in Erase Setup in Suspend Setup in Erase Erase Suspend Erase Busy Erase Suspend Suspend Erase Erase Suspend Suspend Suspend ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 78 Order Number: 306666, Revision: 001 1-Gbit P30 Family Figure 35. Write State Machine—Next State Table (Sheet 2 of 6) Command Input to Chip and resulting Chip Next State BE Confirm, Buffered Buffered P/E BP / Prg / Clear Lock, Unlock, Read Word Erase Enhanced Read Read Resume, Status Lock-down, Program Erase (2) (3,4) (3,4) Current Chip Factory Pgm Array Program Setup Status ID/Query (5) (4) (BP) ULB, Suspend Register CR setup (3, 4) (7) Setup (8) State Confirm (FFH) (10H/40H) (E8H) (20H) (80H) (D0H) (B0H) (70H) (50H) (90H, 98H) (60H) Word Program Busy in Erase Suspend Setup Word Program Busy Word Program Busy in Erase Suspend Suspend in Word Program Busy in Erase Suspend Busy Word Erase Program in Suspend Erase Word Suspend Program Suspend Word Program Suspend in Erase Suspend Busy in Word Program Suspend in Erase Suspend Erase Suspend Setup BP Load 1 BP Load 1 BP Load 2 BP Confirm if Data load into Program Buffer is complete; Else BP Load 2 BP Load 2 BP Busy in BP in Erase BP Erase Suspend (Error) Ready (Error in Erase Suspend) Erase Suspend Confirm Suspend BP Suspend BP Busy in Erase Suspend BP Busy in Erase Suspend BP Busy in Erase Suspend BP Busy in BP BP Suspend in Erase Suspend BP Suspend in Erase Suspend Erase Suspend Suspend Erase Lock/CR Setup in Erase Suspend Erase Suspend (Lock Error) Erase Suspend (Lock Error [Botch]) Suspend (Unlock Block) BEFP Buffered Setup Ready (Error) Loading Ready (Error) Enhanced Data (X=32) Factory Program BEFP Mode BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands treated as data. (7) Busy ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 79 1-Gbit P30 Family Figure 36. Write State Machine—Next State Table (Sheet 3 of 6) Command Input to Chip and resulting Chip Next State Lock Lock-Down OTP Write RCR Block Address Illegal Cmds or Block Block WSM (4) (8) 9 (1) Current Chip Setup Confirm (?WA0) BEFP Data (8) (8) Operation Confirm Confirm (7) Completes State (C0H) (01H) (2FH) (03H) (XXXXH) (all other codes) OTP Ready Ready Setup Ready Ready Ready Ready N/A (Lock (Lock (Lock Down Ready (Lock Error) Lock/CR Setup (Set CR) Error) Block) Blk) Setup OTP Busy OTP Ready Busy Word Program Busy N/A Setup Word Program Busy Ready Busy Word Program Word Program Suspend Suspend BP Load 1 Setup BP Load 2 Ready (BP Load 2 BP Load 2 BP Load 1 BP Confirm if N/A Data load into BP Confirm if Data load into Program Buffer is Ready Program Buffer is BP Load 2 complete; ELSE BP load 2 complete; ELSE BP Load 2 BP Ready (Error) BP (Proceed if Ready (Error) Ready (Error) Confirm unlocked or lock error) BP Busy BP Busy Ready BP BP Suspend Suspend N/A Setup Ready (Error) Busy Erase Busy Ready Erase Suspend Erase Suspend N/A ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 80 Order Number: 306666, Revision: 001 1-Gbit P30 Family Figure 37. Write State Machine—Next State Table (Sheet 4 of 6) Command Input to Chip and resulting Chip Next State Lock Lock-Down OTP Write RCR Block Address Illegal Cmds or Block Block WSM (4) (8) 9 (1) Current Chip Setup Confirm (?WA0) BEFP Data (8) (8) Confirm Confirm Operation (7) State Completes (C0H) (01H) (2FH) (03H) (XXXXH) (all other codes) Setup Word Program Busy in Erase Suspend NA Busy Word Program Busy in Erase Suspend Busy Erase Suspend Word Program in Erase Suspend Suspend Word Program Suspend in Erase Suspend N/A Setup BP Load 1 BP Load 2 BP Load 1 Ready (BP Load 2 BP Load 2 BP Confirm if Data load into BP Confirm if Data load into Program Buffer is N/A BP Load 2 Ready Program Buffer is complete; Else BP Load 2 complete; Else BP Load 2 BP in Erase Ready (Error) Suspend BP (Proceed if Ready (Error in Erase Suspend) Ready (Error) Confirm unlocked or lock error) BP Busy BP Busy in Erase Suspend Erase Suspend BP BP Suspend in Erase Suspend Suspend Erase Erase Erase Erase Lock/CR Setup in Erase Suspend Suspend Suspend Suspend Erase Suspend (Lock Error) (Lock (Lock (Lock Down N/A Suspend (Set CR) Error) Block) Block) Ready (BEFP Ready (Error) Ready (Error) Buffered Setup Loading Data) Enhanced Factory BEFP Program and Verify Busy (if Block Address Program BEFP Mode given matches address given on BEFP Setup Ready Ready BEFP Busy Busy command). Commands treated as data. (7) ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 81 1-Gbit P30 Family Figure 38. Write State Machine—Next State Table (Sheet 5 of 6) Output Next State Table Command Input to Chip and resulting Output Mux Next State BE Confirm, Buffered P/E Clear Lock, Unlock, Word Program/ Read Erase Enhanced Read Read Program BP Setup Resume, Erase Status Lock-down, (2) (3,4) Factory Pgm Status ID/Query Array Setup (5) (4) ULB Confirm Current chip state Setup (3,4) Suspend Register CR setup (3, 4) Setup (8) (FFH) (10H/40H) (E8H) (20H) (30H) (D0H) (B0H) (70H) (50H) (90H, 98H) (60H) BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP: Setup, Load 1, Load 2, Confirm, Status Read Word Pgm Setup, Word Pgm Setup in Erase Susp, BP Setup, Load1, Load 2, Confirm in Erase Suspend Lock/CR Setup, Status Read Lock/CR Setup in Erase Susp Status OTP Busy Read Ready, Erase Suspend, BP Suspend BP Busy, Word Program Busy, Output mux Erase Busy, Read Array Status Read Output does not change. Status Read does not Status Read BP Busy change. ID Read BP Busy in Erase Suspend Word Pgm Suspend, Word Pgm Busy in Erase Suspend, Pgm Suspend In Erase Suspend ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 82 Order Number: 306666, Revision: 001 1-Gbit P30 Family Figure 39. Write State Machine—Next State Table (Sheet 6 of 6) Output Next State Table Command Input to Chip and resulting Output Mux Next State Lock Lock-Down OTP Write CR Block Address Illegal Cmds or Block Block WSM (4) (8) (1) (?WA0) Setup Confirm BEFP Data (8) (8) Current chip state Confirm Confirm Operation Completes (C0H) (01H) (2FH) (03H) (FFFFH) (all other codes) BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP: Setup, Load 1, Status Read Load 2, Confirm, Word Pgm Setup, Word Pgm Setup in Erase Susp, BP Setup, Load1, Load 2, Confirm in Erase Suspend Lock/CR Setup, Array Status Read Status Read Lock/CR Setup in Read Erase Susp Output does not change. OTP Busy Ready, Erase Suspend, BP Suspend BP Busy, Word Program Busy, Erase Busy, Status Output does not Output does not change. Array Read Read change. BP Busy BP Busy in Erase Suspend Word Pgm Suspend, Word Pgm Busy in Erase Suspend, Pgm Suspend In Erase Suspend Notes: 1. "Illegal commands" include commands outside of the allowed command set (allowed commands: 40H [pgm], 20H [erase], etc.) 2. If a "Read Array" is attempted from a busy partition, the result will be invalid data. The ID and Query data are located at different locations in the address map. 3. 1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or unexpected results will occur. 4. To protect memory contents against erroneous command sequences, there are specific instances in a multi-cycle command sequence in which the second cycle will be ignored. For example, when the device is program suspended and an erase setup command (0x20) is given followed by a confirm/resume command (0xD0), the second command will be ignored because it is unclear whether the user intends to erase the block or resume the program operation. ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 83 1-Gbit P30 Family 5. The Clear Status command only clears the error bits in the status register if the device is not in the following modes: WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes). 6. BEFP writes are only allowed when the status register bit #0 = 0, or else the data is ignored. 7. The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which output (Array, ID/CFI or Status) it was last pointed to on the last instruction to the "chip", but the next state of the chip does not depend on where the partition's output mux is presently pointing to. 8. Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register) perform the operation and then move to the Ready State. 9. WA0 refers to the block address latched during the first write cycle of the current operation. ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 84 Order Number: 306666, Revision: 001 1-Gbit P30 Family Appendix B Flowcharts Figure 40. Word Program Flowchart WORD PROGRAM PROCEDURE Bus Start Command Comments Operation Program Data = 0x40 Write Write 0x40, Setup Addr = Location to program (Setup) Word Address Data = Data to program Write Data Addr = Location to program Write Data, (Confirm) Word Address Read None Status register data Program Read Status Suspend Register Check SR[7] Loop Idle None 1 = WSM Ready No 0 = WSM Busy Yes 0 SR[7] = Suspend? Repeat for subsequent Word Program operations. Full Status Register check can be done after each program, or 1 after a sequence of program operations. Full Status Write 0xFF after the last operation to set to the Read Array Check state. (if desired) Program Complete FULL STATUS CHECK PROCEDURE Read Status Bus Command Comments Register Operation Check SR[3]: Idle None 1 = V Error PP 1 V Range PP SR[3] = Error Check SR[4]: Idle None 0 1 = Data Program Error Program 1 Check SR[1]: SR[4] = Idle None Error 1 = Block locked; operation aborted 0 If an error is detected, clear the Status Register before continuing operations - only the Clear Staus Register Device 1 SR[1] = command clears the Status Register error bits. Protect Error 0 Program Successful ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 85 1-Gbit P30 Family Figure 41. Program Suspend/Resume Flowchart PROGRAM SUSPEND / RESUME PROCEDURE Start Bus Program Suspend Command Comments Operation Write B0h Any Address Program Data = B0h Write Suspend Addr = Block to suspend (BA) Read Status Write 70h Read Data = 70h Same Partition Write Status Addr = Same partition Read Status Status register data Read Register Addr = Suspended block (BA) Check SR.7 Standby 1 = WSM ready 0 SR.7 = 0 = WSM busy 1 Check SR.2 Standby 1 = Program suspended 0 Program 0 = Program completed SR.2 = Completed Data = FFh 1 Read Write Addr = Any address within the Read Array Array suspended partition Write FFh Susp Partition Read array data from block other than Read the one being programmed Read Array Data Program Data = D0h Write Resume Addr = Suspended block (BA) If the suspended partition was placed in Read Array mode: Done No Reading Return partition to Status mode: Read Write Data = 70h Yes Status Addr = Same partition Program Resume Read Array Write D0h Write FFh Any Address Pgm'd Partition Program Read Array Resumed Data Read Status Write 70h Same Partition PGM_SUS.WMF ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 86 Order Number: 306666, Revision: 001 1-Gbit P30 Family Figure 42. Buffer Program Flowchart Buffer Programming Procedure Start Bus Command Comments Operation Device Use Single Word Buffer Prog. Data = 0xE8 Supports Buffer Write Setup Addr = Word Address No Programming Writes? SR[7] = Valid Read None Yes Addr = Word Address Set Timeout or Check SR[7]: Loop Counter Idle None 1 = Write Buffer available 0 = No Write Buffer available Get Next Data = N-1 = Word Count Target Address Write None N = 0 corresponds to count = 1 (Notes 1, 2) Addr = Word Address Issue Buffer Prog. Cmd. Write Data = Write Buffer Data 0xE8, None (Notes 3, 4) Addr = Start Word Address Word Address Write Data = Write Buffer Data None (Note 3) Addr = Word Address Read Status Register at Word Address Write Buffer Prog. Data = 0xD0 (Notes 5, 6) Conf. Addr = Original Word Address No Status register Data Read None Write Buffer Timeout Addr = Note 7 0 = No or Count Available? Yes Expired? Check SR[7]: SR[7] = Idle None 1 = WSM Ready 1 = Yes 0 = WSM Busy Write Word Count, 1. Word count value on D[7:0] is loaded into the word count Word Address register. Count ranges for this device are N = 0x00 to 0x1F. 2. The device outputs the Status Register when read. 3. Write Buffer contents will be programmed at the issued word Buffer Program Data, X = X + 1 address. Start Word Address 4. Align the start address on a Write Buffer boundary for maximum programming performance (i.e., A[4:0] of the Start Word Address = 0x00). Write Buffer Data, X = 0 Word Address 5. The Buffered Programming Confirm command must be issued to an address in the same block, for example, the No original Start Word Address, or the last address used during the loop that loaded the buffer data. No 6. The Status Register indicates an improper command Abort Buffer X = N? Program? sequence if the Buffer Program command is aborted; use the Clear Status Register command to clear error bits. Yes 7. The Status Register can be read from any address within the programming partition. Yes Write to another Block Address Write Confirm 0xD0 Full status check can be done after all erase and write and Word Address sequences complete. Write 0xFF after the last operation to (Note 5) place the partition in the Read Array state. Issue Read Buffer Program Aborted Status Register Command Read Status Register Suspend (Note 7) Program Loop No 0=No Suspend Yes Is BP finished? Program? SR[7] = 1=Yes Full Status Check if Desired Program Complete ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 87 Other partitions of the device can be read by addressing those partitions 0xFF commands can be issued to read from and driving OE# low. (Any write commands are not allowed during this any blocks in other partitions period.) 1-Gbit P30 Family Figure 43. BEFP Flowchart BUFFERED ENHANCED FACTORY PROGRAMMING (BEFP) PROCEDURE Setup Phase Program & Verify Phase Exit Phase Read Read Start Status Reg. Status Reg. VPP applied No (SR[7]=0) BEFP No (SR[0]=1) Block Unlocked Data Stream Exited? Ready? Yes (SR[0]=0) Yes (SR[7]=1) Write 80h @ st 1 Word Address Initialize Count: Full Status Check X = 0 Procedure Write D0h @ st 1 Word Address st Write Data @ 1 Program Word Address Complete BEFP Setup delay Increment Count: X = X+1 Read Status Reg. N Check X = 32? Yes (SR[7]=0) BEFP Setup Y Done? Read No (SR[7]=1) Status Reg. No (SR[0]=1) Check VPP, Lock errors (SR[3,1]) Program Done? Yes (SR[0]=0) Exit N Last Data? Y Write 0xFFFF, Address Not within Current Block BEFP Setup BEFP Program & Verify BEFP Exit Bus Bus Bus Operation Comments Operation Comments Operation Comments State State State Unlock Status Data = Status Register Data Status Data = Status Register Data Read Write VPPH applied to VPP Read st st Block Register Address = 1 Word Addr. Register Address = 1 Word Addr. st Write BEFP Data = 0x80 @ 1 Word Check SR[0]: Check Check SR[7]: Data Stream (Note 1) Setup Address Standby 0 = Ready for Data Standby Exit 0 = Exit Not Completed Ready? st 1 = Not Ready for Data Status 1 = Exit Completed BEFP Data = 0x80 @ 1 Word Write 1 Confirm Address Initialize Repeat for subsequent blocks ; Standby X = 0 Count Status Data = Status Register Data Read st Register Address = 1 Word Addr. After BEFP exit, a full Status Register check can Write Load Data = Data to Program st determine if any program error occurred; (note 2) Buffer Address = 1 Word Addr. BEFP Check SR[7]: Standby Setup 0 = BEFP Ready Increment See full Status Register check procedure in the Standby X = X+1 Done? 1 = BEFP Not Ready Count Word Program flowchart. X = 32? Error If SR[7] is set, check: Buffer Write 0xFF to enter Read Array state . Standby Yes = Read SR[0] Standby Condition SR[3] set = V Error PP Full? No = Load Next Data Word Check SR[1] set = Locked Block Status Data = Status Reg. Data Read st Register Address = 1 Word Addr. Check SR[0]: Program Standby 0 = Program Done Done? 1 = Program in Progress Last No = Fill buffer again Standby Data? Yes = Exit Exit Prog & Data = 0xFFFF @ address Write Verify Phase not in current block NOTES: 1. First-word address to be programmed within the target block must be aligned on a write -buffer boundary. 2. Write-buffer contents are programmed sequentially to the flash array starting at the first word address (WSM internally increments addressing). ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 88 Order Number: 306666, Revision: 001 1-Gbit P30 Family Figure 44. Block Erase Flowchart BLOCK ERASE PROCEDURE Bus Start Command Comments Operation Block Data = 0x20 Write Erase Addr = Block to be erased (BA) Write 0x20, (Block Erase) Setup Block Address Erase Data = 0xD0 Write Confirm Addr = Block to be erased (BA) Write 0xD0, (Erase Confirm) Block Address Read None Status Register data. Suspend Read Status Erase Register Check SR[7]: Loop Idle None 1 = WSM ready No 0 = WSM busy Suspend 0 Yes SR[7] = Erase Repeat for subsequent block erasures. 1 Full Status register check can be done after each block erase or after a sequence of block erasures. Full Erase Status Check Write 0xFF after the last operation to enter read array mode. (if desired) Block Erase Complete FULL ERASE STATUS CHECK PROCEDURE Read Status Bus Command Comments Register Operation Check SR[3]: Idle None 1 = V Range Error 1 V Range PP PP SR[3] = Error Check SR[4,5]: Idle None 0 Both 1 = Command Sequence Error 1,1 Command Check SR[5]: SR[4,5] = Idle None Sequence Error 1 = Block Erase Error 0 Check SR[1]: 1 Block Erase Idle None 1 = Attempted erase of locked block; SR[5] = erase aborted. Error 0 Only the Clear Status Register command clears SR[1, 3, 4, 5]. 1 Block Locked If an error is detected, clear the Status register before SR[1] = Error attempting an erase retry or other error recovery. 0 Block Erase Successful ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 89 1-Gbit P30 Family Figure 45. Erase Suspend/Resume Flowchart ERASE SUSPEND / RESUME PROCEDURE Start Bus Command Comments Operation Write 0x70, Read Data = 0x70 (Read Status) Write Same Partition Status Addr = Any partition address Data = 0xB0 Erase Write 0xB0, Write Addr = Same partition address as (Erase Suspend) Suspend above Any Address Status Register data. Read None Addr = Same partition Read Status Register Check SR[7]: Idle None 1 = WSM ready 0 = WSM busy 0 SR[7] = Check SR[6]: 1 Idle None 1 = Erase suspended 0 = Erase completed 0 Erase SR[6] = Completed Data = 0xFF or 0x40 Read Array Write Addr = Any address within the 1 or Program suspended partition Read or Read array or program data from/to Read Program Read or None Write block other than the one being erased Program? Read Array Program Program Data = 0xD0 No Write Data Loop Resume Addr = Any address Done If the suspended partition was placed in Read Array mode or a Program Loop: Read Return partition to Status mode: Write 0xD0, Write Status Data = 0x70 (Erase Resume) Any Address Register Addr = Same partition Erase Write 0xFF, (Read Array) Resumed Erased Partition Write 0x70, Read Array (Read Status) Same Partition Data ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 90 Order Number: 306666, Revision: 001 1-Gbit P30 Family Figure 46. Block Lock Operations Flowchart LOCKING OPERATIONS PROCEDURE Start Bus Command Comments Operation Write 0x60, Lock Data = 0x60 (Lock Setup) Write Block Address Setup Addr = Block to lock/unlock/lock-down Lock, Data = 0x01 (Block Lock) Write either Unlock, or 0xD0 (Block Unlock) (Lock Confirm) 0x01/0xD0/0x2F, Write Lock-Down 0x2F (Lock-Down Block) Block Address Confirm Addr = Block to lock/unlock/lock-down Write Read Data = 0x90 (Read Device ID) Write 0x90 (Optional) Device ID Addr = Block address + offset 2 Read Block Lock Block Lock status data Read Block (Optional) Status Addr = Block address + offset 2 Lock Status Idle None Confirm locking change on D[1,0]. Locking No Change? Yes Read Data = 0xFF Write Array Addr = Block address Write 0xFF (Read Array) Partition Address Lock Change Complete ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 91 Optional 1-Gbit P30 Family Figure 47. Protection Register Programming Flowchart PROTECTION REGISTER PROGRAMMING PROCEDURE Bus Start Command Comments Operation Program Data = 0xC0 Write PR Setup Addr = First Location to Program Write 0xC0, (Program Setup) PR Address Protection Data = Data to Program Write Program Addr = Location to Program Write PR (Confirm Data) Address & Data Read None Status Register Data. Read Status Check SR[7]: Register Idle None 1 = WSM Ready 0 = WSM Busy Program Protection Register operation addresses must be 0 SR[7] = within the Protection Register address space. Addresses outside this space will return an error. 1 Repeat for subsequent programming operations. Full Status Full Status Register check can be done after each program, or Check after a sequence of program operations. (if desired) Write 0xFF after the last operation to set Read Array state. Program Complete FULL STATUS CHECK PROCEDURE Read Status Bus Command Comments Register Data Operation Check SR[3]: Idle None 1 =V Range Error PP 1 SR[3] = V Range Error PP Check SR[4]: Idle None 0 1 =Programming Error 1 Check SR[1]: SR[4] = Program Error Idle None 1 =Block locked; operation aborted 0 Only the Clear Staus Register command clears SR[1, 3, 4]. If an error is detected, clear the Status register before 1 Register Locked; SR[1] = attempting a program retry or other error recovery. Program Aborted 0 Program Successful ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 92 Order Number: 306666, Revision: 001 1-Gbit P30 Family Appendix C Common Flash Interface The Common Flash Interface (CFI) is part of an overall specification for multiple command-set and control-interface descriptions. This appendix describes the database structure containing the data returned by a read operation after issuing the CFI Query command (see Section 9.2, “Device Commands” on page 50). System software can parse this database structure to obtain information about the flash device, such as block size, density, bus width, and electrical specifications. The system software will then know which command set(s) to use to properly perform flash writes, block erases, reads and otherwise control the flash device. C.1 Query Structure Output The Query database allows system software to obtain information for controlling the flash device. This section describes the device’s CFI-compliant interface that allows access to Query data. Query data are presented on the lowest-order data outputs (DQ ) only. The numerical offset value 7-0 is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,” appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data on upper bytes. The device outputs ASCII “Q” in the low byte (DQ ) and 00h in the high byte (DQ ). 7-0 15-8 At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. In all of the following tables, addresses and data are represented in hexadecimal notation, so the “h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always “00h,” the leading “00” has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode. Table 31. Summary of Query Structure Output as a Function of Device and Mode Hex Hex ASCII Device Offset Code Value 00010: 51 “Q” Device Addresses 00011: 52 “R” 00012: 59 “Y” Table 32. Example of Query Structure Output of x16- Devices ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 93 1-Gbit P30 Family Word Addressing: Byte Addressing: Offset Hex Code Value Offset Hex Code Value A –A D –D A –A D –D X 0 15 0 X 0 7 0 00010h 0051 "Q" 00010h 51 "Q" 00011h 0052 "R" 00011h 52 "R" 00012h 0059 "Y" 00012h 59 "Y" 00013h P_ID PrVendor 00013h P_ID PrVendor LO LO P_ID P_ID 00014h HI ID # 00014h LO ID # P P_ID 00015h PrVendor 00015h ID # LO HI P 00016h TblAdr 00016h ... ... HI 00017h A_ID AltVendor 00017h LO 00018h A_ID ID # 00018h HI ... ... ... ... C.2 Query Structure Overview The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or “database.” The structure sub-sections and address locations are summarized below. Table 33. Query Structure (1) Offset Sub-Section Name Description 00001-Fh Reserved Reserved for vendor-specific information 00010h CFI query identification string Command set ID and vendor data offset 0001Bh System interface information Device timing & voltage information 00027h Device geometry definition Flash device layout (3) Vendor-defined additional information specific Primary Intel-specific Extended Query Table P Notes: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is 16-KWord). 3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table. ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 94 Order Number: 306666, Revision: 001 1-Gbit P30 Family C.3 CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s). Table 34. CFI Identification Hex Offset Length Description Add. Code Value 10h 3 Query-unique ASCII string “QRY“ 10: --51 "Q" 11: --52 "R" 12: --59 "Y" 13h 2 Primary vendor command set and control interface ID code. 13: --01 16-bit ID code for vendor-specified algorithms 14: --00 15h 2 Extended Query Table primary algorithm address 15: --0A 16: --01 17h 2 Alternate vendor command set and control interface ID code. 17: --00 0000h means no second vendor-specified algorithm exists 18: --00 19h 2 Secondary algorithm Extended Query Table address. 19: --00 0000h means none exists 1A: --00 Table 35. System Interface Information Hex Offset Length Description Add. Code Value 1Bh 1 V logic supply minimum program/erase voltage 1B: --17 1.7V CC bits 0–3 BCD 100 mV bits 4–7 BCD volts 1Ch 1 V logic supply maximum program/erase voltage 1C: --20 2.0V CC bits 0–3 BCD 100 mV bits 4–7 BCD volts 1Dh 1 V [programming] supply minimum program/erase voltage 1D: --85 8.5V PP bits 0–3 BCD 100 mV bits 4–7 HEX volts 1Eh 1 V [programming] supply maximum program/erase voltage 1E: --95 9.5V PP bits 0–3 BCD 100 mV bits 4–7 HEX volts n 1Fh 1 1F: --08 256µs “n” such that typical single word program time-out = 2 µ-sec n 20h 1 20: --09 512µs “n” such that typical max. buffer write time-out = 2 µ-sec n 21h 1 21: --0A 1s “n” such that typical block erase time-out = 2 m-sec n 22h 1 22: --00 NA “n” such that typical full chip erase time-out = 2 m-sec n 23h 1 23: --01 512µs “n” such that maximum word program time-out = 2 times typical n 24h 1 24: --01 1024µs “n” such that maximum buffer write time-out = 2 times typical n 25h 1 25: --02 4s “n” such that maximum block erase time-out = 2 times typical n 26h 1 26: --00 NA “n” such that maximum chip erase time-out = 2 times typical ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 95 1-Gbit P30 Family C.4 Device Geometry Definition Table 36. Device Geometry Definition Offset Length Description Code n 27h 1 “n” such that device size = 2 in number of bytes 27: See table below Flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table: 76 54 3 2 1 0 28h 2 — — — — x64 x32 x16 x8 28: --01 x16 15 14 13 12 11 10 9 8 —— ——— —— — 29: --00 n “n” such that maximum number of bytes in write buffer = 2 2Ah 2 2A: --06 64 2B: --00 2Ch 1 Number of erase block regions (x) within device: 2C: 1. x = 0 means no erase blocking; the device erases in bulk See table below 2. x specifies the number of device regions with one or more contiguous same-size erase blocks. 3. Symmetrically blocked partitions have one blocking region 2Dh 4 Erase Block Region 1 Information 2D: bits 0–15 = y, y+1 = number of identical-size erase blocks 2E: See table below bits 16–31 = z, region erase block(s) size are z x 256 bytes 2F: 30: 4 Erase Block Region 2 Information 31h 31: bits 0–15 = y, y+1 = number of identical-size erase blocks 32: See table below bits 16–31 = z, region erase block(s) size are z x 256 bytes 33: 34: 4 Reserved for future erase block region information 35h 35: 36: See table below 37: 38: Address 64-Mbit 128-Mbit 256-Mbit –B –T –B –T –B –T 27: --17 --17 --18 --18 --19 --19 28: --01 --01 --01 --01 --01 --01 29: --00 --00 --00 --00 --00 --00 2A: --06 --06 --06 --06 --06 --06 2B: --00 --00 --00 --00 --00 --00 2C: --02 --02 --02 --02 --02 --02 2D: --03 --3E --03 --7E --03 --FE 2E: --00 --00 --00 --00 --00 --00 2F: --80 --00 --80 --00 --80 --00 30: --00 --02 --00 --02 --00 --02 31: --3E --03 --7E --03 --FE --03 32: --00 --00 --00 --00 --00 --00 33: --00 --80 --00 --80 --00 --80 34: --02 --00 --02 --00 --02 --00 35: --00 --00 --00 --00 --00 --00 36: --00 --00 --00 --00 --00 --00 37: --00 --00 --00 --00 --00 --00 38: --00 --00 --00 --00 --00 --00 ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 96 Order Number: 306666, Revision: 001 1-Gbit P30 Family C.5 Intel-Specific Extended Query Table Table 37. Primary Vendor-Specific Extended Query (1) Offset Length Description Hex P = 10Ah (Optional flash features and commands) Add. Code Value (P+0)h 3 Primary extended query table 10A --50 "P" (P+1)h Unique ASCII string “PRI“ 10B: --52 "R" (P+2)h 10C: --49 "I" (P+3)h 1 Major version number, ASCII 10D: --31 "1" (P+4)h 1 Minor version number, ASCII 10E: --34 "4" (P+5)h 4 Optional feature and command support (1=yes, 0=no) 10F: --E6 (P+6)h bits 10–31 are reserved; undefined bits are “0.” If bit 31 is 110: --01 (P+7)h “1” then another 31 bit field of Optional features follows at 111: --00 (P+8)h the end of the bit–30 field. 112: --00 bit 0 Chip erase supported bit 0 = 0 No bit 1 Suspend erase supported bit 1 = 1 Yes bit 2 Suspend program supported bit 2 = 1 Yes bit 3 Legacy lock/unlock supported bit 3 = 0 No bit 4 Queued erase supported bit 4 = 0 No bit 5 Instant individual block locking supported bit 5 = 1 Yes bit 6 Protection bits supported bit 6 = 1 Yes bit 7 Pagemode read supported bit 7 = 1 Yes bit 8 Synchronous read supported bit 8 = 1 Yes bit 9 Simultaneous operations supported bit 9 = 0 No bit 10 Extended Flash Array Blocks supported bit 10 = 0 No bit 30 CFI Link(s) to follow bit 30 = 0 No bit 31 Another "Optional Features" field to follow bit 31 = 0 No (P+9)h 1 Supported functions after suspend: read Array, Status, Query 113: --01 Other supported operations are: bits 1–7 reserved; undefined bits are “0” bit 0 Program supported after erase suspend bit 0 = 1 Yes (P+A)h 2 Block status register mask 114: --03 (P+B)h bits 2–15 are Reserved; undefined bits are “0” 115: --00 bit 0 Block Lock-Bit Status register active bit 0 = 1 Yes bit 1 Block Lock-Dow n Bit Status active bit 1 = 1 Yes bit 4 EFA Block Lock-Bit Status register active bit 4 = 0 No bit 5 EFA Block Lock-Dow n Bit Status active bit 5 = 0 No (P+C)h 1 V logic supply highest performance program/erase voltage 116: --18 1.8V CC bits 0–3 BCD value in 100 mV bits 4–7 BCD value in volts (P+D)h 1 V optimum program/erase supply voltage 117: --90 9.0V PP bits 0–3 BCD value in 100 mV bits 4–7 HEX value in volts ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 97 1-Gbit P30 Family Table 38. Protection Register Information (1) Length Description Hex Offset P = 10Ah (Optional flash features and commands) Add. Code Value (P+E)h 1 Number of Protection register fields in JEDEC ID space. 118: --02 2 “00h,” indicates that 256 protection fields are available (P+F)h 4 Protection Field 1: Protection Description 119: --80 80h (P+10)h This field describes user-available One Time Programmable 11A: --00 00h (P+11)h (OTP) Protection register bytes. Some are pre-programmed 11B: --03 8 byte (P+12)h with device-unique serial numbers. Others are user 11C: --03 8 byte programmable. Bits 0–15 point to the Protection register Lock byte, the section’s first byte. The following bytes are factory pre-programmed and user-programmable. bits 0–7 = Lock/bytes Jedec-plane physical low address bits 8–15 = Lock/bytes Jedec-plane physical high address n bits 16–23 = “n” such that 2 = factory pre-programmed bytes n bits 24–31 = “n” such that 2 = user programmable bytes (P+13)h 10 Protection Field 2: Protection Description 11D: --89 89h (P+14)h Bits 0–31 point to the Protection register physical Lock-word 11E: --00 00h (P+15)h address in the Jedec-plane. 11F: --00 00h (P+16)h Following bytes are factory or user-programmable. 120: --00 00h (P+17)h bits 32–39 = “n” ∴ n = factory pgm'd groups (low byte) 121: --00 0 ∴ (P+18)h bits 40–47 = “n” n = factory pgm'd groups (high byte) 122: --00 0 (P+19)h bits 48–55 = “n” \ 2n = factory programmable bytes/group 123: --00 0 bits 56–63 = “n” ∴ n = user pgm'd groups (low byte) (P+1A)h 124: --10 16 --00 (P+1B)h bits 64–71 = “n” ∴ n = user pgm'd groups (high byte) 125: 0 n (P+1C)h 126: 16 ∴ bits 72–79 = “n” 2 = user programmable bytes/group --04 Table 39. Burst Read Information (1) Length Description Hex Offset P = 10Ah (Optional flash features and commands) Add. Code Value (P+1D)h 1 Page Mode Read capability 127: --03 8 byte n bits 0–7 = “n” such that 2 HEX value represents the number of read-page bytes. See offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. (P+1E)h 1 Number of synchronous mode read configuration fields that 128: --04 4 follow. 00h indicates no burst capability. (P+1F)h 1 Synchronous mode read capability configuration 1 129: --01 4 Bits 3–7 = Reserved n+1 bits 0–2 “n” such that 2 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device’s burstable address space. This field’s 3-bit value can be written directly to the Read Configuration Register bits 0–2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width. (P+20)h 1 Synchronous mode read capability configuration 2 12A: --02 8 (P+21)h 1 Synchronous mode read capability configuration 3 12B: --03 16 (P+22)h 1 Synchronous mode read capability configuration 4 12C: --07 Cont ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 98 Order Number: 306666, Revision: 001 1-Gbit P30 Family Table 40. Partition and Erase-block Region Information (1) Offset P= 10Ah Description Hex Bottom Top (Optional flash features and commands) Add. Code Value (P+23)h (P+23)h Number of device hardw are-partition regions w ithin the device. 12D: --00 0 x = 0: a single hardw are partition device (no fields follow ). x specifies the number of device partition regions containing one or more contiguous erase block regions. ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 99 1-Gbit P30 Family Appendix D Additional Information Order/Document Document/Tool Number ® 290667 Intel StrataFlash Memory (J3) Datasheet ® 290737 Intel StrataFlash Synchronous Memory (K3/K18) Datasheet ® 290701 Intel Wireless Flash Memory (W18) Datasheet ® 290702 Intel Wireless Flash Memory (W30) Datasheet ® 252802 Intel Flash Memory Design for a Stacked Chip Scale Package (SCSP) ® 298161 Intel Flash Memory Chip Scale Package User’s Guide ® 253418 Intel Wireless Communications and Computing Package User's Guide ® 296514 Intel Small Outline Package Guide ® 297833 Intel Flash Data Integrator (FDI) User’s Guide ® 298136 Intel Persistent Storage Manager User Guide 300783 Using Intel® Flash Memory: Asynchronous Page Mode and Synchronous Burst Mode ® ® Migration Guide for Intel StrataFlash Memory (J3) to Intel StrataFlash Embedded 306667 Memory (P30) Application Note 812 ® Migration Guide for Spansion* S29GLxxxN to Intel StrataFlash Embedded Memory 306668 (P30) Application Note 813 ® Migration Guide for Intel StrataFlash Synchronous Memory (K3/K18) to Intel 306669 ® StrataFlash Embedded Memory (P30) Application Note 825 Notes: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools. ® 3. For the most current information on Intel Flash Memory, visit our website at http://developer.intel.com/design/flash. ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 100 Order Number: 306666, Revision: 001 1-Gbit P30 Family Appendix E Ordering Information for Discrete Products ® Figure 48. Decoder for Discrete Intel StrataFlash Embedded Memory (P30) T E 2 8 F 6 4 0 P 3 0 B 8 5 Access Speed Package Designator 85 ns TE = 56-Lead TSOP, leaded JS = 56-Lead TSOP, lead-free Parameter Location RC = 64-Ball Easy BGA, leaded PC = 64-Ball Easy BGA, lead-free B = Bottom Parameter T = Top Parameter Product Line Designator 28F = Intel® Flash Memory Product Family P30 = Intel StrataFlash® Embedded Memory Device Density V = 1.7 – 2.0 V CC 640 = 64-Mbit V = 1.7 – 3.6 V CCQ 128 = 128-Mbit 256 = 256-Mbit Table 41. Valid Combinations for Discrete Products 64-Mbit 128-Mbit 256-Mbit TE28F640P30B85 TE28F128P30B85 TE28F256P30B85 TE28F640P30T85 TE28F128P30T85 TE28F256P30T85 JS28F640P30B85 JS28F128P30B85 JS28F256P30B85 JS28F640P30T85 JS28F128P30T85 JS28F256P30T85 RC28F640P30B85 RC28F128P30B85 RC28F256P30B85 RC28F640P30T85 RC28F128P30T85 RC28F256P30T85 PC28F640P30B85 PC28F128P30B85 PC28F256P30B85 PC28F640P30T85 PC28F128P30T85 PC28F256P30T85 ® Datasheet Intel StrataFlash Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 101 1-Gbit P30 Family Appendix F Ordering Information for SCSP Products ® Figure 49. Decoder for SCSP Intel StrataFlash Embedded Memory (P30) R D 4 8 F 4 0 0 0 P 0 Z B Q 0 Package Designator Device Details ® RD = Intel SCSP, leaded 0 = Original version of the product ® PF = Intel SCSP, lead-free (refer to the latest version of the RC = 64-Ball Easy BGA, leaded datasheet for details) PC = 64-Ball Easy BGA, lead-free Group Designator Ballout Designator 48F = Flash Memory only Q = QUAD ballout 0 = Discrete ballout Flash Density 0 = No die Parameter, Mux Configuration 2 = 64-Mbit B = Bottom Parameter, Non Mux 3 = 128-Mbit T = Top Parameter, Non Mux 4 = 256-Mbit Product Family I/O Voltage, CE# Configuration P = Intel StrataFlash® Embedded Memory Z = 3.0 V, Individual Chip Enable(s) 0 = No die V = 3.0 V, Virtual Chip Enable(s) Table 42. Valid Combinations for Stacked Products 64-Mbit 128-Mbit 256-Mbit 512-Mbit 1-Gbit RD48F2000P0ZBQ0 RD48F3000P0ZBQ0 RD48F4000P0ZBQ0 RD48F4400P0VBQ0 RD48F4444PPVBQ0 RD48F2000P0ZTQ0 RD48F3000P0ZTQ0 RD48F4000P0ZTQ0 RD48F4400P0VTQ0 RD48F4444PPVTQ0 PF48F2000P0ZBQ0 PF48F3000P0ZBQ0 PF48F4000P0ZBQ0 PF48F4400P0VBQ0 PF48F4444PPVBQ0 PF48F2000P0ZTQ0 PF48F3000P0ZTQ0 PF48F4000P0ZTQ0 PF48F4400P0VTQ0 PF48F4444PPVTQ0 RC48F4400P0VB00 RC48F4400P0VT00 PC48F4400P0VB00 PC48F4400P0VT00 ® April 2005 Intel StrataFlash Embedded Memory (P30) Datasheet 102 Order Number: 306666, Revision: 001 Flash #1 Flash #2 Flash #3 Flash #4 Flash Family 1/2 Flash Family 3/4