Engineering Specification Engineering Specification Type 18.1 SXGA Color TFT/LCD Module Model Name:ITSX98E Document Control Number : OEM I-98E-03 Note:Specification is subject to change without notice. Consequently it is better to contact to International Display Technology before proceeding with the design of your product incorporating this module. Product Development International Display Technology (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 1/29 Engineering Specification i Contents i Contents ii Record of Revision 1.0 Handling Precautions 2.0 General Description 2.1 Characteristics 2.2 Functional Block Diagram 3.0 Absolute Maximum Ratings 4.0 Optical Characteristics 5.0 Signal Interface 5.1 Connectors 5.2 Interface Signal Connector 5.3 Interface Signal Description 5.4 Interface Signal Electrical Characteristics 5.5 Backlight Connector Signal Description 5.6 Backlight Input Signal Electrical Characteristics 6.0 Pixel format image 7.0 Interface Timings 7.1 Timing Characteristics 7.2 Timing Definition 8.0 Power Consumption 9.0 Power ON/OFF Sequence 10.0 Mechanical Characteristics 11.0 National Test Lab Requirement (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 2/29 Engineering Specification ii Record of Revision Date Document Page Summary Revision June 4,2001 OEM98E-01 All First Edition for customer. Based on Internal Spec. as of May 11,2001. September 28,2001 OEM98E-02 5,8 To update White Luminance. October 19,2001 OEM I-98E-03 Updated by establishment of the New Company as "International Display Technology". Based on Internal Spec. EC H30912 as of October 19,2001. 5 To update Weight, Optical Rise Time + Fall Time and Power Consumption. 7 To update value of Shock Test Criteria. 8 To update Viewing Angle and Response Time. 19 To update Dimming Curve. 21 To add Note for Timing Characteristics. 24,25 To update Power Consumption. 27,28 To update Reference Drawings. (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 3/29 Engineering Specification 1.0 Handling Precautions  Damage to the panel or the panel electronics may result from any deviation from the recommended power on/off sequencing. The panel should not be hot plugged. Refer to the Power On/Off Sequence section in this Specification.  Handle the panel with care. The LCD panel and CCFL (Cold Cathode Fluorescent Lamp)s are made of glass and may crack or break if dropped or subjected to excessive force.  The CCFLs contain a small amount of Mercury so should not be disposed of to landfill. Dispose of as required by local ordinances or regulations.  The LCD module contains small amounts of material having no flammability grade. The exemption conditions of the flammability requirements (4.7.3.4, IEC60950 3rd.Ed. or UL60950 3rd.Ed.) should be applied.  The panel may be damaged by the application of twisting or bending forces to the module assembly.Care should be taken in the design of the monitor housing and the assembly procedure to prevent stress damage to the panel especially the lamp cable and the lamp connector..  Use standard earthing/grounding procedures to prevent damage to the CMOS LSI while handling the module.  Use earthing/grounding procedures, an ionic shower, or similar to prevent static damage while removing the protective front sheet.  The front polarizer can be easily damaged. Take care not to scratch the front surface with any hard or abrasive material. Dust, finger marks, grease etc. can be removed with a soft damp cloth (a small amount of mild detergent can be used on the damp cloth). Do not apply water or datergent directly to the front surface as this may cause staining or damage the electronic components.  Never use any solvent on the front polarizer or module as this may cause permanent damage.  Do not open or modify the module assembly.  Continuous operation of the panel with the same screen content may result in some image sticking. Over 10 hours operation with the same content is not recommended.  Wipe off water drop immediately. Long contact with water may cause discoloration or spots.  When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth. � The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by International Display Technology for any infringements of patents or other right of the third partied which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of International Display Technology or others. � The information contained herein may be changed without prior notice. It is therefore advisable to contact International Display Technology before proceeding with the design of equipment incorporating this product. (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 4/29 Engineering Specification 2.0 General Description This specification applies to the Type 18.1 Color TFT/LCD Module 'ITSX98E'. This module is designed for a LCD monitor style display unit.This module includes inverter card. The screen format and electrical interface are intended to support the VESA SXGA (1280(H) x 1024(V)at 60Hz) screen. Support color is native 16M colors(RGB 8-bit data driver). All input signals are LVDS(Low Voltage Differential Signaling) interface compatible. 2.1 Characteristics The following items are characteristics summary on the table under 25 degree C condition: CHARACTERISTICS ITEMS SPECIFICATIONS Screen Diagonal [mm] 460 Pixels H x V 1280(x3) x 1024 Active Area [mm] 359.0(H) x 287.2(V) Pixel Pitch [mm] 0.2805(per one triad) x 0.2805 Pixel Arrangement R,G,B Vertical Stripe Weight [grams] 2,900 typ. Physical Size [mm] 389.0(W) typ. x 317.2(H) typ. x 35.0 (D) max. Display Mode Normally Black Support Color 16M (RGB 8-bit data) 2 White Luminance [cd/m ] 270 Typ Contrast Ratio 400 : 1 Typ. Optical Rise Time/Fall Time [msec] Rise Time + Fall Time : 40 Typ. (total) Input Voltage [V] +12 +/- 5% Power Consumption [W] 38.8 typ., 46.6 max. LVDS Dual Electrical Interface (Even/Odd R/G/B Data(8bit), 3sync signals, Clock) Temperature Range [degree C] Operating 0 to +50 Storage (Shipping) -20 to +60 Note : Luminance : Rise / Fall Time:Respective 10% -> 90%, 90%->10% (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 5/29 Engineering Specification 2.2 Functional Block Diagram The following diagram shows the functional block of this Type 18.1 Color TFT/LCD Module. LCD module Interface card +12V LVDS Signals Gatearray SELLVDS VcontIN Connector X-card HIROSE DF14-30P-1.25H(59) Mating DF14-30S-1.25C TFT/LCD Y-card Array/Cell 1280x1024 Connector JST S8B-PH-SM3 Mating JST PHR-8 Backlight unit +12V Inverter card VDIM BLON (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 6/29 Engineering Specification 3.0 Absolute Maximum Ratings Absolute maximum ratings of the module is as follows : Item Symbol Min Max Unit Conditions Logic/LCD Drive Voltage Vin -0.3 +13.2 V Backlight Voltage VBL -0.3 +13.2 V Select LVDS data order SELLVDS -0.3 3.3 V Brightness control VDIM -0.3 5.3 V Backlight on signal BLON -0.3 +5.3 V Operating Temperature TOP 0 +50 deg.C Note 1 Operating Humidity HOP 8 80 %RH Note 1 Storage Temperature TST -20 +60 deg.C Note 1 Storage Humidity HST 5 95 %RH Note 1 Vibration 1.5 10-200 G Hz Note 2 Shock 50 11 G ms Note 2 Half sine wave Note 1 : Maximum Wet-Bulb should be 39 degree C and No condensation. Note 2 : Vibration Specification - Sign Vibration:10-200-10Hz, 1.5G, 0.29 Oct/min, 30 min, X, Y, A Axis, Each One Time. Shock Specification - Half sine wave:50G 11msec. -X+/-, -Y+/-, -Z+/- (Total 6 directions), Each two times Shock. (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 7/29 Engineering Specification 4.0 Optical Characteristics The optical characteristics are measured under stable conditions as follows under 25 degree C condition: Item Conditions Specification Typ. Note Viewing Angle Horizontal (Right) 85 - (Degrees) K�15 (Left) 85 - K:Contrast Ratio Vertical (Upper) 85 - K�15 (Lower) 85 - Horizontal (Right) - 85 Min. K�10 (Left) - 85 Min. Vertical (Upper) - 85 Min. K�10 (Lower) - 85 Min. Contrast ratio 400 - Response Time Rising(10%->90%) + 40 - (ms) Falling(90%->10%) Color Red x 0.640 +-0.030 Chromaticity Red y 0.330 +-0.030 (CIE) Green x 0.290 +-0.030 Green y 0.600 +-0.030 Blue x 0.150 +-0.030 Blue y 0.060 +-0.030 White x 0.313 +-0.030 White y 0.329 +-0.030 2 Maximum White Luminance (cd/m ) 270 230 Min. VDIM=0V Note Note:Measure center of the screen. (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 8/29 Engineering Specification 5.0 Signal Interface 5.1 Connectors Physical interface is described as for the connector on module. These connectors are capable of accommodating the following signals and will be following components. Connector Name / Designation Signal Connector Manufacturer HIROSE Type / Part Number DF14-30P-1.25H(59) Mating Type / Part Number DF14-30S-1.25C Contact / Part Number DF14-2628SCFA Connector Name / Designation For Backlight Connector on Inverter card Manufacturer JST Type / Part Number S8B-PH-SM3 Mating Type / Part Number PHR-8 (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 9/29 Engineering Specification 5.2 Interface Signal Connector Pin # Signal Name Pin # Signal Name 30 Vin(+12V) 29 Vin(+12V) 28 Vin(+12V) 27 VinRTN(GND) 26 VinRTN(GND) 25 VinRTN(GND) 24 SELLVDS 23 VcontIN 22 DGND 21 RxOIN3+ 20 RxOIN3- 19 RxOCLKIN+ 18 RxOCLKIN- 17 RxOIN2+ 16 RxOIN2- 15 RxOIN1+ 14 RxOIN1- 13 RxOIN0+ 12 RxOIN0- 11 RxEIN3+ 10 RxEIN3- 9 RxECLKIN+ 8 RxECLKIN- 7 RxEIN2+ 6 RxEIN2- 5 RxEIN1+ 4 RxEIN1- 3 RxEIN0+ 2 RxEIN0- 1 LVDSGND (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 10/29 Engineering Specification 5.3 Interface Signal Description The module uses a pair of LVDS receiver SN75LVDS82(Texas Instruments) or compatible. LVDS is a differential signal technology for LCD interface and high speed data transfer device. Transmitter shall be SN75LVDS83(negative edge sampling) or compatible. The first LVDS port (RxExxx) transmits even pixels while the second LVDS port (RxOxxx) transmits odd pixels. Pin numberings have been changed from previous models of ITSX94, ITSX94N, ITSX94N1, and ITSX96R, due to signal connector type change. Physical order of singals are not changed. Please refer to the chart below for pin #1. LCD Drive Connector No.1 Pin location Pin No.1 Signal Connector Module Back side view (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 11/29 Engineering Specification PIN # SIGNAL NAME Description 30 Vin +12.0V Power Supply 29 Vin +12.0V Power Supply 28 Vin +12.0V Power Supply 27 VinRTN Ground for Vin line 26 VinRTN Ground for Vin line 25 VinRTN Ground for Vin line 24 SELLVDS Select LVDS data order. See the following figure. 23 (RESERVED) This pin should be left open. 22 DGND Signal Ground 21 RxOIN3+ Positive LVDS differential data input (Odd data) 20 RxOIN3- Negative LVDS differential data input (Odd data) 19 RxOCLKIN+ Positive LVDS differential clock input (Odd Clock) 18 RxOCLKIN- Negative LVDS differential clock input (Odd Clock) 17 RxOIN2+ Positive LVDS differential data input (Odd data) 16 RxOIN2- Negative LVDS differential data input (Odd data) 15 RxOIN1+ Positive LVDS differential data input (Odd data) 14 RxOIN1- Negative LVDS differential data input (Odd data) 13 RxOIN0+ Positive LVDS differential data input (Odd data) 12 RxOIN0- Negative LVDS differential data input (Odd data) 11 RxEIN3+ Positive LVDS differential data input (Even data) 10 RxEIN3- Negative LVDS differential data input (Even data) 9 RxECLKIN+ Positive LVDS differential clock input (Even Clock) 8 RxECLKIN- Negative LVDS differential clock input (Even Clock) 7 RxEIN2+ Positive LVDS differential data input (Even data,H-Sync,V-Sync,DSPTMG) 6 RxEIN2- Negative LVDS differential data input (Even data,H-Sync,V-Sync,DSPTMG) 5 RxEIN1+ Positive LVDS differential data input (Even data) 4 RxEIN1- Negative LVDS differential data input (Even data) 3 RxEIN0+ Positive LVDS differential data input (Even data) 2 RxEIN0- Negative LVDS differential data input (Even data) 1 DGND Signal Ground Note: Input signals of odd and even clock shall be the same timing. (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 12/29 Engineering Specification The interface card has a 100ohm resistor between positive and negative lines of each LVDS signal input on the internal circuit. (SELLVDS=Low) RxECLKIN+ RxECLKIN- 1 cycle RxEIN0+ ER1 ER0 EG0 ER5 ER4 ER3 ER2 ER1 ER0 EG0 RxEIN0- RxEIN1+ EG2 EG1 EB1 EB0 EG5 EG4 EG3 EG2 EG1 EB1 RxEIN1- RxEIN2+ EB3 EB2 DSP V-S H-S EB5 EB4 EB3 EB2 DSP RxEIN2- RxEIN3+ ER7 ER6 NA EB7 EB6 EG7 EG6 ER7 ER6 NA RxEIN3- RxOCLKIN+ RxOCLKIN- 1 cycle RxOIN0+ OR1 OR0 OG0 OR5 OR4 OR3 OR2 OR1 OR0 OG0 RxOIN0- RxOIN1+ OG2 OG1 OB1 OB0 OG5 OG4 OG3 OG2 OG1 OB1 RxOIN1- RxOIN2+ OB3 OB2 NA NA NA OB5 OB4 OB3 OB2 NA RxOIN2- RxOIN3+ NA OB7 OB6 OG7 OG6 OR7 OR6 NA OR7 OR6 RxOIN3- Note:R/G/B data 7:MSB, R/G/B data 0:LSB (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 13/29 Engineering Specification (SELLVDS=High) RxECLKIN+ RxECLKIN- 1 cycle RxEIN0+ ER3 ER2 EG2 ER7 ER6 ER5 ER4 ER3 ER2 EG2 RxEIN0- RxEIN1+ EG4 EG3 EB3 EB2 EG7 EG6 EG5 EG4 EG3 EB3 RxEIN1- RxEIN2+ EB5 EB4 DSP V-S H-S EB7 EB6 EB5 EB4 DSP RxEIN2- RxEIN3+ ER1 ER0 NA EB1 EB0 EG1 EG0 ER1 ER0 NA RxEIN3- RxOCLKIN+ RxOCLKIN- 1 cycle RxOIN0+ OR3 OR2 OG2 OR7 OR6 OR5 OR4 OR3 OR2 OG2 RxOIN0- RxOIN1+ OG4 OG3 OB3 OB2 OG7 OG6 OG5 OG4 OG3 OB3 RxOIN1- RxOIN2+ OB5 OB4 NA NA NA OB7 OB6 OB5 OB4 NA RxOIN2- RxOIN3+ OR1 OR0 NA OB1 OB0 OG1 OG0 OR1 OR0 NA RxOIN3- Note:R/G/B data 7:MSB, R/G/B data 0:LSB (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 14/29 Engineering Specification The following is LVDS Signal description. Description LVDS DATA NAME DSP Display Timing When the signal is high, the pixel data shall be valid to be displayed. V-S Vertical Sync Both Positive and negative polarity are acceptable. H-S Horizontal Sync Both Positive and negative polarity are acceptable. TI LVDS X'mitter ITSX98E LVDS Signal ITSX98E LVDS Signal (SN75LVDS83) (SELLVDS=Low) (SELLVDS=High) Signal name D0 Red0 Red2 D1 Red1 Red3 D2 Red2 Red4 D3 Red3 Red5 D4 Red4 Red6 D5 Red7 Red1 D6 Red5 Red7 D7 Green0 Green2 D8 Green1 Green3 D9 Green2 Green4 D10 Green6 Green0 D11 Green7 Green1 D12 Green3 Green5 D13 Green4 Green6 D14 Green5 Green7 D15 Blue0 Blue2 D16 Blue6 Blue0 D17 Blue7 Blue1 D18 Blue1 Blue3 D19 Blue2 Blue4 D20 Blue3 Blue5 D21 Blue4 Blue6 D22 Blue5 Blue7 D23 NA NA D24 H Sync H Sync D25 V Sync V Sync D26 Disp Timing Disp Timing D27 Red6 Red0 Note: SELLVDS: Pin#7 of Signal connector Red0: LSB, Red7: MSB (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 15/29 Engineering Specification 5.4 Interface Signal Electrical Characteristics Input signals shall be low or Hi-Z state when Vin is off. It is recommended to refer the specifications of SN75LVDS82DGG(Texas Instruments) in detail. Signal electrical characteristics are as follows; Parameter Condition Min Max unit Vth Differential Input High Voltage 100 mV (Vcm=+1.2V) Vtl Differential Input High Voltage -100 mV (Vcm=+1.2V) LVDS Timing (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 16/29 Engineering Specification LVDS Macro AC characteristics. Parameter Symbol Min Typ Max Unit LVDS Clock Cycle Trxc 17.6 18.5 20 [ns] LVDS Data Cycle Trxd Trxc/7 [ns] Sample Data Setup Time Trxss 600 [ps] (Trxc=Typ.) Sample Data Hold Time Trxsh 600 [ps] (Trxc=Typ.) Data Sample Time Trxs Trxc/14 [ns] Data Sample Cycle Trxsc Trxc/7 [ns] Name Description Min Typ Max Unit Note SELLVDS High voltage 2 3 3.3 V Low voltage -0.1 0 0.7 V Current -1 - 1 mA (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 17/29 Engineering Specification 5.5 Backlight Connector Signal Description PIN # SIGNAL NAME Description 1 VBL +12.0V Power Supply for backlight 2 VBL +12.0V Power Supply for backlight 3 VBL +12.0V Power Supply for backlihgt 4 RTN Ground for VBL line, VDIM and BLON 5 RTN Ground for VBL line, VDIM and BLON 6 RTN Ground for VBL line, VDIM and BLON 7 VDIM Brightness control voltage input(0-4V), (0V:brightness MAX, 4V:brightness MIN) 8 BLON backlihgt on/off signal(Hi:backlight ON, Low:backlight OFF) TTL level 5.6 Backlight Input Signal Electrical Characteristics Name Description Min Typ Max Unit Note BLON High voltage 2.0 5.0 5.25 V Low voltage -0.1 0 0.8 V Current -1.0 - 1.0 mA VDIM Input Voltage Range 0 - 4.0 V 0V:Brightness Max. 4V:Brightness Min. Current -1.0 - 1.0 mA (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 18/29 Engineering Specification The following chart is the Dimming Signal (VDIM) versus Luminance curve for your reference. ITSX98E Dimming Curve (VDIM vs Lumi.) 120.0% 100.0% 80.0% 60.0% Lumi(%) 40.0% 20.0% 0.0% 00.511.522.5 33.5 4 VDIM(V) (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 19/29 Luminance(%) Engineering Specification 6.0 Pixel format image Following figure shows the relationship of the input signals and LCD pixel format image. Odd and even pair of RGB data are sampled at a time. Even Odd Even Odd 0 1 1278 1279 R B R B R B R B 1st Line G G G G R G B R G B R G B R G B 1024th Line (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 20/29 Engineering Specification 7.0 Interface Timings Basically, interface timings described here is not actual input timing of LCD module but output timing of SN75LVDS82DGG(Texas Instruments) or equivalent. 7.1 Timing Characteristics Signal Item Symbol MIN. TYP. MAX. Unit DTCLK Freq. Fdck 50 54 56.8 MHz DTCLK Cycle Tck 17.6 18.5 20 ns +V-Sync Frame Rate 1/Tv 56.25 60.02 61 Hz +V-Sync Cycle Tv 16.39 16.66 17.78 ms +V-Sync Cycle Tv 1035 1066 2047 lines +V-Sync active level Tva 3 3 lines +V-Sync V-back porch Tvb 7 38 63 lines +V-Sync V-front porch Tvf 1 1 lines +DSPTMG V-Line m - 1024 - lines +H-Sync Scan Rate 1/Th - 63.98 - KHz +H-Sync Cycle Th 844 844 1023 Tck +H-Sync active level Tha(*1) 4 56 Tck +H-Sync Back porch Thb(*1) 4 124 Tck +H-Sync Front porch Thf 4 24 Tck +DSPTMG Display Pixels n - 640 - Tck Note 1 : Typical value is refer to VESA STANDARD. (*1): Tha+Thb should be less than 1024 Tck. Note 2 : When there are invalid timing, Display appears black pattern. Synchronous Signal Defects and enter Auto Refresh for LCD Module Protection Mode. (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 21/29 Engineering Specification 7.2 Timing Definition Vertical Timing DSPTMG T4 T1 T2 T3 T5 T6 -VSYNC +VSYNC Support mode T1 Vertical T2 T3 VSYNC T4 T5 VSYNC T6 VSYNC Blanking Active Field Front Porch Frame Time Width Back Porch 1280 x 1024 at 60Hz 0.656 ms 16.005 ms 0.016 ms 16.661 ms 0.047 ms 0.594 ms (VESA STANDARD) (42 lines) (1024 lines) (1 line) (1066 lines) (3 lines) (38 lines) (H line rate : 15.6 us) Horizontal Timing DSPTMG T10 T7 T8 T9 T11 T12 -HSYNC +HSYNC T7 Horizontal T8 T9 HSYNC T10 T11 HSYNC T12 HSYNC Support mode Blanking Active Field Front Porch H line Time Width Back Porch 1280 x 1024 3.778 us 11.852 us 0.444 us 15.630 us 1.037 us 2.296 us (VESA STANDARD) (408 dots) (1280 dots) (48 dots) (1688 dots) (112 dots) (248 dots) (Dotclock : 108.000 MHz) (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 22/29 Engineering Specification Interface Timing Definition Tv Tva V-Sync H-Sync Tvb Tvf DSPTMG 01 m-1 Vsync, Hsync and Display Timing Th Tha H-Sync Dot clock Thd Tck DSPTMG Thb Thf Video(Even) 0 2 n-2 Video(Odd) 1 3 n-1 Video signal, Hsync and Dot clock (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 23/29 Engineering Specification 8.0 Power Consumption Input power specifications are as follows; SYMB PARAMETER Min Typ Max UNITS CONDITION Vin Logic/LCD Drive 11.4 12 12.6 V Voltage Iin Vin Current 550 mA Vin=11.4V (All White Pattern) (This value indicates long term average.) Pin(1) Vin Power 4.5 W Typical Load Condition (Vertical Gray Bar, 256 Scale) Pin(2) 5.2 6.3 W Maximum Load Condition (All White) Logic/LCD Refer to the Typical Logic/LCD Current Maximum Load DC current Waveform Waveform shown in the following Figure. Condition (All White) Waveform may vary in paticular application. Actual current waveform on user application must be evaluated and make sure the ripple current and/or peak current should be allowable to user power supply. Vin rp Allowable Logic/LCD 500 mVp-p Drive Ripple Voltage VBL Backlight power 11.4 12 12.6 V voltage PBL Backlight Power 33.6 40.3 W Brightness=max consumption (Note) A used DC power supply for this LCD module should be have a over current protection function to safety. (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 24/29 Engineering Specification Figure. Typical Logic/LCD Current Waveform Condition : Maximum Load Condition(All White) Voltage : 12.0V measured at Interface Connector J1 Interface Cable : AWG28, 30 Conductors, L=500mm from Voltage Source to EUT (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 25/29 Engineering Specification 9.0 Power ON/OFF Sequence Vin and VBL power and lamp on/off sequence is as follows. Interface signals are also shown in the chart. Signals from any system shall be Hi-Z state or low level when Vin and VBL are off. It is recommended that the BLON should be supplied after other signals are stable in order to avoid visible screen noise when power-on. 90% 90% Vin 10% 10% 10% 0 V 30ms max. and 1ms min. 10ms min. 0 min. 0 min. Signals 10% 10% 0 V 100ms min. 90% 90% VBL 10% 10% 10% 0 V 30ms max. and 1ms min. 5ms min. 0 min. 1.9V 1.9V BLON 0.9V 0.9V 0 V 1uS max. 1uS max. (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 26/29 Engineering Specification 10.0 Mechanical Characteristics (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 27/29 Engineering Specification (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 28/29 Engineering Specification 11.0 National Test Lab Requirement The display module will satisfy all requirements for compliance to UL60950 3rd. Ed. U.S.A. Information Technology Equipment ****** End Of Page ****** (C) Copyright International Display Technology 2001 All Rights reserved. October 19,2001 OEM I-98E-03 29/29