64Mx64 bits Unbuffered DDR SDRAM DIMM HYMD264646B(L)8J-J DESCRIPTION Hynix HYMD264646B(L)8J-J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 64Mx64 high-speed memory arrays. Hynix HYMD264646B(L)8J-J series consists of sixteen 32Mx8 DDR SDRAM in 400mil TSOPII packages on a184pin glass-epoxy substrate. Hynix HYMD264646B(L)8J-J series provide a high performance 8-byte interface in 5.25" width form factor of industry stan- dard. It is suitable for easy interchange and addition. Hynix HYMD264646B(L)8J-J series is designed for high speed of up to 166MHz and offers fully synchronous opera- tions referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. Hynix HYMD264646B(L)8J-J series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer. FEATURES • 512MB (64M x 64) Unbuffered DDR DIMM based on • Data inputs on DQS centers when write (centered 32Mx8 DDR SDRAM DQ) • JEDEC Standard 184-pin dual in-line memory mod- • Data strobes synchronized with output data for read ule (DIMM) and input data for write • 2.5V +/- 0.2V VDD and VDDQ Power supply • Programmable CAS Latency 2 / 2.5 supported • All inputs and outputs are compatible with SSTL_2 • Programmable Burst Length 2 / 4 / 8 with both interface sequential and interleave mode • Fully differential clock operations (CK & /CK) with • tRAS Lock-out function supported 100MHz/125MHz/133MHz/166MHz • Internal four bank operations with single pulsed RAS • All addresses and control inputs except Data, Data • Auto refresh and self refresh supported strobes and Data masks latched on the rising edges of the clock • 8192 refresh cycles / 64ms • Data(DQ), Data strobes and Write masks latched on both rising and falling edges of the clock ORDERING INFORMATION Part No. Power Supply Clock Frequency Interface Form Factor VDD=2.5V 184pin Unbuffered DIMM HYMD264646B(L)8J-J 166MHz (*DDR333) SSTL_2 VDDQ=2.5V 5.25 x 1.25 x 0.15 inch * JEDEC Defined Specifications compliant This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2/Dec. 02 1 HYMD264646B(L)8J-J PIN DESCRIPTION Pin Pin Description Pin Pin Description CK0,/CK0,CK1,/CK1,CK2,/CK2 Differential Clock Inputs VDDQ DQs Power Supply CS0, CS1 Chip Select Input VSS Ground CKE0, CKE1 Clock Enable Input VREF Reference Power Supply /RAS, /CAS, /WE Commend Sets Inputs VDDSPD Power Supply for SPD 2 A0 ~ A12 Address SA0~SA2 E PROM Address Inputs 2 BA0, BA1 Bank Address SCL E PROM Clock 2 DQ0~DQ63 Data Inputs/Outputs SDA E PROM Data I/O DQS0~DQS7 Data Strobe Inputs/Outputs VDDID VDD Identification Flag DM0~DM7 Data-in Mask DU Do not Use VDD Power Supply NC No Connection PIN ASSIGNMENT Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name 1 VREF 32 A5 62 VDDQ 93 VSS 124 VSS 154 /RAS 2 DQ0 33 DQ24 63 /WE 94 DQ4 125 A6 155 DQ45 3 VSS 34 VSS 64 DQ41 95 DQ5 126 DQ28 156 VDDQ 4 DQ1 35 DQ25 65 /CAS 96 VDDQ 127 DQ29 157 /CS0 5 DQS0 36 DQS3 66 VSS 97 DM0 128 VDDQ 158 /CS1 6 DQ2 37 A4 67 DQS5 98 DQ6 129 DM3 159 DM5 7 VDD 38 VDD 68 DQ42 99 DQ7 130 A3 160 VSS 8 DQ3 39 DQ26 69 DQ43 100 VSS 131 DQ30 161 DQ46 9 NC 40 DQ27 70 VDD 101 NC 132 VSS 162 DQ47 10 NC 41 A2 71 NC 102 NC 133 DQ31 163 NC 11 VSS 42 Vss 72 DQ48 103 A13* 134 CB4* 164 VDDQ 12 DQ8 43 A1 73 DQ49 104 VDDQ 135 CB5* 165 DQ52 13 DQ9 44 CB0* 74 VSS 105 DQ12 136 VDDQ 166 DQ53 14 DQS1 45 CB1* 75 /CK2 106 DQ13 137 CK0 167 NC 15 VDDQ 46 VDD 76 CK2 107 DM1 138 /CK0 168 VDD 16 CK1 47 DQS8* 77 VDDQ 108 VDD 139 VSS 169 DM6 17 /CK1 48 A0 78 DQS6 109 DQ14 140 DM8* 170 DQ54 18 VSS 49 CB2* 79 DQ50 110 DQ15 141 A10 171 DQ55 19 DQ10 50 VSS 80 DQ51 111 CKE1 142 CB6* 172 VDDQ 20 DQ11 51 CB3* 81 VSS 112 VDDQ 143 VDDQ 173 NC 21 CKE0 52 BA1 82 VDDID 113 BA2* 144 CB7* 174 DQ60 22 VDDQ Key 83 DQ56 114 DQ20 key 175 DQ61 23 DQ16 53 DQ32 84 DQ57 115 A12 145 VSS 176 VSS 24 DQ17 54 VDDQ 85 VDD 116 VSS 146 DQ36 177 DM7 25 DQS2 55 DQ33 86 DQS7 117 DQ21 147 DQ37 178 DQ62 26 VSS 56 DQS4 87 DQ58 118 A11 148 VDD 179 DQ63 27 A9 57 DQ34 88 DQ59 119 DM2 149 DM4 180 VDDQ 28 DQ18 58 VSS 89 VSS 120 VDD 150 DQ38 181 SA0 29 A7 59 BA0 90 WP 121 DQ22 151 DQ39 182 SA1 30 VDDQ 60 DQ35 91 SDA 122 A8 152 VSS 183 SA2 31 DQ19 61 DQ40 92 SCL 123 DQ23 153 DQ44 184 VDDSPD * These are not used on this module but may be used for other module in 184pin DIMM family Rev. 0.2/Dec. 02 2 HYMD264646B(L)8J-J FUNCTIONAL BLOCK DIAGRAM /CS1 /CS0 DQS4 DQS0 DM0 DM4 DM /CS DQS DM /CS DQS DM /CS DQS DM /CS DQS I/O0 DQ0 DQ32 I/O0 I/O0 I/O0 I/O1 DQ1 I/O1 DQ33 I/O1 I/O1 I/O2 DQ2 I/O2 DQ34 I/O2 I/O2 I/O3 DQ3 D0 I/O3 D8 DQ35 I/O3 D4 I/O3 D12 D12 I/O4 DQ4 I/O4 DQ36 I/O4 I/O4 I/O5 DQ5 DQ37 I/O5 I/O5 I/O5 I/O6 DQ6 DQ38 I/O6 I/O6 I/O6 I/O7 DQ7 I/O7 DQ39 I/O7 I/O7 DQS1 DQS5 DM5 DM1 DM /CS DQS DM /CS DQS DM /CS DQS DM /CS DQS DQ8 I/O0 DQ40 I/O0 I/O0 I/O0 DQ9 I/O1 I/O1 I/O1 I/O1 DQ41 I/O2 I/O2 I/O2 I/O2 DQ10 DQ42 I/O3 D1 I/O3 D9 I/O3 D5 I/O3 D13 DQ11 DQ43 I/O4 I/O4 I/O4 I/O4 DQ12 DQ44 DQ13 I/O5 I/O5 DQ45 I/O5 I/O5 DQ14 I/O6 I/O6 DQ46 I/O6 I/O6 DQ15 I/O7 I/O7 DQ47 I/O7 I/O7 DQS2 DQS6 DM2 DM6 DM /CS DQS DM /CS DQS DM /CS DQS DM /CS DQS I/O0 DQ48 I/O0 I/O0 DQ16 I/O0 I/O1 DQ49 I/O1 I/O1 DQ17 I/O1 I/O2 DQ50 I/O2 I/O2 DQ18 I/O2 D2 I/O3 D10 DQ51 I/O3 D6 I/O3 D14 DQ19 I/O3 I/O4 DQ52 I/O4 I/O4 DQ20 I/O4 DQ53 I/O5 I/O5 I/O5 DQ21 I/O5 I/O6 DQ54 I/O6 I/O6 DQ22 I/O6 I/O7 DQ55 I/O7 I/O7 DQ23 I/O7 DQS3 DQS7 DM3 DM7 DM /CS DQS DM /CS DQS DM /CS DQS DM /CS DQS I/O0 I/O0 DQ24 I/O0 DQ56 I/O0 I/O1 I/O1 I/O1 I/O1 DQ25 DQ57 I/O2 I/O2 I/O2 I/O2 DQ26 DQ58 I/O3 I/O3 DQ27 I/O3 D3 D11 DQ59 I/O3 D7 D15 I/O4 I/O4 DQ28 I/O4 DQ60 I/O4 I/O5 I/O5 DQ29 I/O5 DQ61 I/O5 I/O6 I/O6 DQ30 I/O6 DQ62 I/O6 I/O7 I/O7 I/O7 I/O7 DQ31 DQ63 VDD SPD SPD *Clock Wiring Serial PD VDD /VDDQ DO-D15 Clock Input SDRAMs SDA SCL WP VREF DO-D15 *CK0, /CK0 4 SDRAMs *CK1, /CK1 6 SDRAMs A0 A1 A2 *CK2, /CK2 6 SDRAMs VSS DO-D15 SA0 SA1 SA2 Strap:see Note 4 VDDID *Wire per Clock Loading Table/Wiring Diagrams Note : BA0-BA1 BA0-BA1 : SDRAMs D0-D15 1. DQ-to-I/O wiring is shown as recommended but may be changed. A0-A13 A0-A13 : SDRAMs D0-D15 2. DQ/DQS/DM/CKE/S relationships must be maintained CKE1 CKE : SDRAMs D8-D15 as shown. ± 3. DQ, DQS, DM/DQS resistors : 22 Ohms 5%. /RAS /RAS : SDRAMs D0-D15 4. VDDID strap connections /CAS /CAS : SDRAMs D0-D15 (for memory device VDD, VDDQ): STRAP OUT (OPEN) : VDD = VDDQ CKE0 CKE : SDRAMs D0-D7 STRAP IN (VSS) : VDD ≠ V DDQ /WE /WE : SDRAMs D0-D15 5. BAx, Ax, RAS, CAS, WE resistors : 3 Ohms ± 5% Rev. 0.2/Dec. 02 3 HYMD264646B(L)8J-J ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit o Ambient Temperature TA 0 ~ 70 C o Storage Temperature TSTG -55 ~ 125 C Voltage on Any Pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD relative to VSS VDD -0.5 ~ 3.6 V Voltage on VDDQ relative to VSS VDDQ -0.5 ~ 3.6 V Output Short Circuit Current IOS 50 mA Power Dissipation PD 16 W o Soldering Temperature Þ Time TSOLDER 260 / 10 C / Sec Note : Operation at above absolute maximum rating can adversely affect device reliability o DC OPERATING CONDITIONS (TA=0 to 70 C, Voltage referenced to VSS= 0V) Parameter Symbol Min Typ. Max Unit Note Power Supply Voltage VDD 2.3 2.5 2.7 V Power Supply Voltage VDDQ 2.3 2.5 2.7 V 1 Input High Voltage VIH VREF + 0.15 - VDDQ + 0.3 V Input Low Voltage VIL -0.3 - VREF - 0.15 V 2 Termination Voltage VTT VREF - 0.04 VREF VREF + 0.04 V Reference Voltage VREF 0.49*VDDQ 0.5*VDDQ 0.51*VDDQ V 3 Note : 1. VDDQ must not exceed the level of VDD. 2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration. 3. The value of VREF is approximately equal to 0.5VDDQ. o AC OPERATING CONDITIONS (TA=0 to 70 C, Voltage referenced to VSS = 0V) Parameter Symbol Min Max Unit Note Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 V Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) VREF - 0.31 V Input Differential Voltage, CK and /CK inputs VID(AC) 0.7 VDDQ + 0.6 V 1 Input Crossing Point Voltage, CK and /CK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 Note : 1. VID is the magnitude of the difference between the input level on CK and the input on /CK. 2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. Rev. 0.2/Dec. 02 4 HYMD264646B(L)8J-J o AC OPERATING TEST CONDITIONS (TA=0 to 70 C, Voltage referenced to VSS = 0V) Parameter Value Unit Reference Voltage VDDQ x 0.5 V Termination Voltage VDDQ x 0.5 V AC Input High Level Voltage (VIH, min) VREF + 0.31 V AC Input Low Level Voltage (VIL, max) VREF - 0.31 V Input Timing Measurement Reference Level Voltage VREF V Output Timing Measurement Reference Level Voltage VTT V Input Signal maximum peak swing 1.5 V Input minimum Signal Slew Rate 1 V/ns Termination Resistor (RT)50W Series Resistor (RS)25W Output Load Capacitance for Access Time Measurement (CL)30 pF Rev. 0.2/Dec. 02 5 HYMD264646B(L)8J-J o CAPACITANCE (TA=25 C, f=100MHz ) Parameter Pin Symbol Min Max Unit Input Capacitance A0 ~ A12, BA0, BA1 CIN1 90 104 pF Input Capacitance /RAS, /CAS, /WE CIN2 90 104 pF Input Capacitance CKE0, CKE1 CIN3 58 72 pF Input Capacitance CS0, CS1 CIN4 58 72 pF Input Capacitance CK0, /CK0, CK1, /CK1, CK2,/CK2 CIN5 30 45 pF Input Capacitance DM0 ~ DM7 CIN6 12 17 pF Data Input / Output Capacitance DQ0 ~ DQ63, DQS0 ~ DQS7 CIO1 12 17 pF Note : 1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V 2. Pins not under test are tied to GND. 3. These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT VTT Ω RT=50 Output Ω Zo=50 VREF CL=30pF Rev. 0.2/Dec. 02 6 HYMD264646B(L)8J-J o DC CHARACTERISTICS I (TA=0 to 70 C, Voltage referenced to VSS = 0V) Parameter Symbol Min. Max Unit Note Add, CMD, /CS, /CKE -32 32 Input Leakage ILI uA 1 Current CK, /CK -12 12 Output Leakage Current ILO -10 10 uA 2 Output High Voltage VOH VTT + 0.76 - V IOH = -15.2mA Output Low Voltage VOL -VTT - 0.76 V IOL = +15.2mA Note : 1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V 2. DOUT is disabled, VOUT=0 to 2.7V Rev. 0.2/Dec. 02 7 HYMD264646B(L)8J-J o DC CHARACTERISTICS II (TA=0 to 70 C, Voltage referenced to VSS = 0V) Speed Parameter Symbol Test Condition Unit Note -J One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs Operating Current IDD0 1440 mA changing twice per clock cycle; address and control inputs changing once per clock cycle One bank; Active - Read - Precharge; Burst Length=2; tRC=tRC(min); tCK=tCK(min); Operating Current IDD1 1440 mA address and control inputs changing once per clock cycle Precharge Power Down All banks idle; Power down mode; CKE=Low, IDD2P 160 mA Standby Current tCK=tCK(min) /CS=High, All banks idle ; tCK=tCK(min); CKE= High; address and control inputs changing IDD2F 800 mA Idle Standby Current once per clock cycle. VIN=VREF for DQ, DQS and DM Active Power Down One bank active; Power down mode; IDD3P 240 mA Standby Current CKE=Low, tCK=tCK(min) /CS=HIGH; CKE=HIGH; One bank; Active- Precharge; tR=tRAS(max); tCK=tCK(min); DQ, IDD3N 960 mA Active Standby Current DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing Operating Current IDD4R 1840 mA once per clock cycle; tCK=tCK(min); IOUT=0mA Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing Operating Current IDD4W 1920 once per clock cycle; tCK=tCK(min); DQ, DM, and DQS inputs changing twice per clock cycle tRC=tRFC(min) - 8*tCK for PC200 at 100Mhz, 1920 Auto Refresh Current IDD5 10*tCK for PC266A & PC266B at 133Mhz; distributed refresh 48 mA Normal CKE=<0.2V; External clock on; Self Refresh Current IDD6 tCK =tCK(min) 24 mA Low Power Operating Current - Four Four bank interleaving with BL=4 Refer to the 2640 mA IDD7 Bank Operation following page for detailed test condition Rev. 0.2/Dec. 02 8 HYMD264646B(L)8J-J AC CHARACTERISTICS (AC operating conditions unless otherwise noted) DDR333 Parameter Symbol Unit Note Min Max Row Cycle Time tRC 60 - ns Auto Refresh Row Cycle Time tRFC 72 - ns Row Active Time tRAS 42 70K ns Active to Read with Auto Precharge Delay tRAP 18 - ns 16 Row Address to Column Address Delay tRCD 18 - ns Row Active to Row Active Delay tRRD 12 - ns Column Address to Column Address Delay tCCD 1- CK Row Precharge Time tRP 18 - ns Write Recovery Time tWR 15 - ns Last Data-In to Read Command tDRL 1- CK (tWR/tCK) Auto Precharge Write Recovery + Precharge Time tDAL + -CK 15 (tRP/tCK) CL = 2.5 612 ns System Clock Cycle Time tCK CL = 2 7.5 12 ns Clock High Level Width tCH 0.45 0.55 CK Clock Low Level Width tCL 0.45 0.55 CK Data-Out edge to Clock edge Skew tAC -0.7 0.7 ns DQS-Out edge to Clock edge Skew tDQSCK -0.6 0.6 ns DQS-Out edge to Data-Out edge Skew tDQSQ -0.45 ns tHP Data-Out hold time from DQS tQH -ns 1, 10 -tQHS min Clock Half Period tHP -ns 1,9 (tCL,tCH) Data Hold Skew Factor tQHS -0.55 ns 10 Valid Data Output Window tDV tQH-tDQSQ ns Data-out high-impedance window from CK, /CK tHZ -0.7 0.7 ns 17 Data-out low-impedance window from CK, /CK tLZ -0.7 0.7 ns 17 Input Setup Time (fast slew rate) tIS 0.75 - ns 2,3,5,6 Input Hold Time (fast slew rate) tIH 0.75 - ns 2,3,5,6 Input Setup Time (slow slew rate) tIS 0.8 - ns 2,4,5,6 Input Hold Time (slow slew rate) tIH 0.8 - ns 2,4,5,6 Rev. 0.2/Dec. 02 9 HYMD264646B(L)8J-J AC CHARACTERISTICS (AC operating conditions unless otherwise noted) - continued - DDR333 Unit Note Parameter Symbol Min Max Input Pulse Width tIPW 2.2 ns 6 Write DQS High Level Width tDQSH 0.35 - CK Write DQS Low Level Width tDQSL 0.35 - CK Clock to First Rising edge of DQS-In tDQSS 0.75 1.25 CK Data-In Setup Time to DQS-In (DQ & DM) tDS 0.45 - ns 6,7, 11~13 Data-in Hold Time to DQS-In (DQ & DM) tDH 0.45 - ns 6,7, 11~13 DQ & DM Input Pulse Width tDIPW 1.75 - ns Read DQS Preamble Time tRPRE 0.9 1.1 CK Read DQS Postamble Time tRPST 0.4 0.6 CK Write DQS Preamble Setup Time tWPRES 0- CK Write DQS Preamble Hold Time tWPREH 0.25 - CK Write DQS Postamble Time tWPST 0.4 0.6 CK Mode Register Set Delay tMRD 2- CK Exit Self Refresh to Any Execute Command tXSC 200 - CK 8 Average Periodic Refresh Interval tREFI -7.8 us Note : 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. 2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE. 3. For command/address input slew rate >=1.0V/ns 4. For command/address input slew rate >=0.5V/ns and <1.0V/ns This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns. Input Setup / Hold Slew-rate Derating Table. Input Setup / Hold Slew-rate Delta tIS Delta tIH V/ns ps ps 0.5 0 0 0.4 +50 0 0.3 +100 0 5. CK, /CK slew rates are >=1.0V/ns 6. These parameters quarantee device timing, but they are not necessarily tested on each device, and they may be quaranteed by design or tester correlation. 7. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM. 8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM. Rev. 0.2/Dec. 02 10 HYMD264646B(L)8J-J 9. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to n-channel variation of the output drivers. 11. This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns. Input Setup / Hold Slew-rate Derating Table. Input Setup / Hold Slew-rate Delta tDS Delta tDH V/ns ps ps 0.5 0 0 0.4 +75 +75 0.3 +150 +150 12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF +/-310mV for a duration of up to 2ns. I/O Input Level Delta tDS Delta tDH mV ps ps +280 +50 +50 13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1=0.5V/ns and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V. (1/SlewRate1)-(1/SlewRate2) Delta tDS Delta tDH ns/V ps ps 00 0 +/-0.25 +50 +50 +/- 0.5 +100 +100 14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotonic. 15. tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. Example: For DDR266B at CL=2.5 and tCK = 7.5 ns, tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67) Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clock 16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be tRAS - BL/2 x tCK. 17. tHZ and tLZ transitions occur in the same access time windows as valid data trasitions. These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ). Rev. 0.2/Dec. 02 11 HYMD264646B(L)8J-J SIMPLIFIED COMMAND TRUTH TABLE A10/ Command CKEn-1 CKEn /CS /RAS /CAS /WE ADDR BA Note AP Extended Mode Register Set H X LLLL OP code 1,2 Mode Register Set H X LLLL OP code 1,2 Device Deselect H XXX HX X1 No Operation L H H H Bank Active H X L L H H RA V 1 Read L 1 H X LHLH CA V Read with Autoprecharge H1,3 Write L 1 HX L H L L CA V Write with Autoprecharge H1,4 Precharge All Banks HX 1,5 HX L L H L X Precharge selected Bank LV 1 Read Burst Stop H X L H H L X 1 Auto Refresh H H L L L H X 1 Entry H L LLL H 1 Self Refresh H XXX X Exit L H 1 L HHH H XXX 1 Entry H L Precharge L HHH 1 Power Down X H XXX 1 Mode Exit L H L HHH 1 H XXX 1 Entry H L Active Power L VVV X 1 Down Mode Exit L H X 1 ( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) Note : 1. DM states are Don’t Care. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Prechagre command. 3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time (tWR) is needed to guarantee that the last data has been completely written. 5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. Rev. 0.2/Dec. 02 12 HYMD264646B(L)8J-J PACKAGE DIMENSIONS Front 133.35 5.25 131.35 5.171 128.95 5.077 31.75 1.250 (2) 0 2.5 0.098 Back Side 4.00 0.157MAX (Front) 1.27+/-0.10 0.050+/-0.004 Rev. 0.2/Dec. 02 13 10.0 0.394 2.30 (2X)4.00 0.91 0.157 17.80 0.700 SERIAL PRESENCE DETECT SPD SPECIFICATION (64Mx64 Unbuffered DDR DIMM) Rev. 0.2/Dec. 02 14 HYMD264646B(L)8J-J SERIAL PRESENCE DETECT Bin Sort : J(DDR333@CL=2.5) Byte# Function Description Function Supported Hexa Value Note 0 Number of Bytes written into serial memory at module manufacturer 128 Bytes 80h 1 Total number of Bytes in SPD device 256 Bytes 08h 2 Fundamental memory type DDR SDRAM 07h 3 Number of row address on this assembly 13 0Dh 1 4 Number of column address on this assembly 10 0Ah 1 5 Number of physical banks on DIMM 2Bank 02h 6 Module data width 64 Bits 40h 7 Module data width (continued) - 00h 8 Module voltage Interface levels(VDDQ) SSTL 2.5V 04h 9 DDR SDRAM cycle time at CAS Latency=2.5(tCK) 6.0ns 60h 2 10 DDR SDRAM access time from clock at CL=2.5 (tAC) +/-0.7ns 70h 2 11 Module configuration type Non-ECC 00h 12 Refresh rate and type 7.8us & Self refresh 82h 13 Primary DDR SDRAM width x8 08h 14 Error checking DDR SDRAM data width N/A 00h Minimum clock delay for back-to-back random column 15 1 CLK 01h address(tCCD) 16 Burst lengths supported 2,4,8 0Eh 17 Number of banks on each DDR SDRAM 4 Banks 04h 18 CAS latency supported 2, 2.5 0Ch 19 CS latency 001h 20 WE latency 102h 21 DDR SDRAM module attributes Differential Clock Input 20h +/-0.2Voltage tolerance, 22 DDR SDRAM device attributes : General Concurrent Auto Precharge C0h tRAS Lock Out 23 DDR SDRAM cycle time at CL=2.0(tCK) 7.5ns 75h 2 24 DDR SDRAM access time from clock at CL=2.0(tAC) +/-0.7ns 70h 2 25 DDR SDRAM cycle time at CL=1.5(tCK) - 00h 2 26 DDR SDRAM access time from clock at CL=1.5(tAC) - 00h 2 27 Minimum row precharge time(tRP) 18ns 48h 28 Minimum row activate to row active delay(tRRD) 12ns 30h 29 Minimum RAS to CAS delay(tRCD) 18ns 48h 30 Minimum active to precharge time(tRAS) 42ns 2Ah 31 Module row density 256MB 40h 32 Command and address signal input setup time(tIS) 0.75ns 75h 33 Command and address signal input hold time(tIH) 0.75ns 75h 34 Data signal input setup time(tDS) 0.45ns 45h 35 Data signal input hold time(tDH) 0.45ns 45h 36~40 Reserved for VCSDRAM Undefined 00h 41 Minimum active / auto-refresh time ( tRC) 60ns 3Ch Minimum auto-refresh to active/auto-refresh 42 72ns 48h command period(tRFC) 43 Maximum cycle time (tCK max) 12ns 30h 44 Maximim DQS-DQ skew time(tDQSQ) 0.45ns 2Dh 45 Maximum read data hold skew factor(tQHS) 0.55ns 55h 46~61 Superset information(may be used in future) Undefined 00h 62 SPD Revision code Initial release 00h 63 Checksum for Bytes 0~62 - 01h 64 Manufacturer JEDEC ID Code Hynix JEDEC ID ADh 65~71 --------- Manufacturer JEDEC ID Code - 00h Rev. 0.2/Dec. 02 15 HYMD264646B(L)8J-J SERIAL PRESENCE DETECT - continued - Byte # Function Description Function Supported Hexa Value Note Hynix(Korea Area) 0*h HSA(United States Area) 1*h HSE(Europe Area) 2*h 72 Manufacturing location 6 HSJ(Japan Area) 3*h Singapore 4*h Asia Area 5*h 73 Manufacture part number(Hynix Memory Module) H 48h 74 -------- Manufacture part number(Hynix Memory Module) Y 59h 75 -------- Manufacture part number(Hynix Memory Module) M 4Dh 76 Manufacture part number (DDR SDRAM) D 44h 77 Manufacture part number(Memory density) 2 32h 78 Manufacture part number(Module Depth) 6 36h 79 ------- Manufacture part number(Module Depth) 4 34h 80 Manufacture part number(Module type) Blank 20h 81 Manufacture part number(Data width) 6 36h 82 -------Manufacture part number(Data width) 4 34h 83 Manufacture part number(Refresh, # of Bank.) 6(8K refresh,4Bank) 36h 84 Manufacture part number(Component Generation) B 42h 85 Manufacture part number(Component configuration) 8 38h 86 Manufacture part number(Module Type) J 4Ah 87 Manufacture part number(Hyphen) ‘-’ 2Dh 88 Manufacture part number(Minimum cycle time) J 4Ah 89~90 Manufacture part number(T.B.D) Blank 20h 91 Manufacture revision code(for Component) - - 92 Manufacture revision code (for PCB) - - 93 Manufacturing date(Year) - - 3 94 Manufacturing date(Week) - - 3 95~98 Module serial number - - 4 99~127 Manufacturer specific data (may be used in future) Undefined 00h 5 128~255 Open for customer use Undefined 00h 5 Note : 1. The bank address is excluded 2. These value is based on the component specification 3. These bytes are programmed by code of date week & date year 4. These bytes apply to Hynix’s own Module Serial Number system 5. These bytes undefined and coded as ‘00h’ 6. Refer to Hynix web site Byte 85~86, Low power part Function Byte # Function Description Hexa Value Note Supported 85 Manufacture part number(Low power part) L 4Ch 86 Manufacture part number(Component configuration) 8 38h Rev. 0.2/Dec. 02 16