Integrated Communications Processors MPC8560/E ™ PowerQUICC III Processor Overview MPC8560 Block Diagram The PowerQUICC™ III is a versatile integrated communications processor designed for a variety of compute-intensive applications, 2 256 KB L2 I C Controller excelling particularly in communications Cache e500 Core and networking products. Freescale’s Interrupt Controller Coherency 32 KB L1 32 KB L1 Module PowerQUICC III processor family is the I cache D cache DDR SDRAM Controller next generation of Freescale’s industry- Core Complex Bus Local Bus Controller leading PowerQUICC line of integrated communications processors. PowerQUICC III CPM ® Serial RapidIO Controller processors provide higher performance DMA MMC in all areas of device operation, including PCI-X/PCI Controller MMC ROM greater flexibility, extended capabilities and FCC DMA Controller I-mem FCC higher integration. FCC DPRAM SCC RISC 10/100/1000 MAC Engine SCC Product Highlights Parallel SCC 10/100/1000 MAC Freescale’s leading PowerQUICC III I/O SCC Baud Rate architecture integrates two processing blocks. Generators SPI 2 One block is a high-performance embedded I C Timers e500 core. With 256 KB of Level 2 cache, the e500 core built on Power Architecture™ technology provides unprecedented levels of hardware and software debugging support. The second block is the Communications Processor Module (CPM). The CPM of the RapidIO Interconnect Technology compatible with existing PCI and CPU PowerQUICC III can support three fast serial As a founding member of the RapidIO Trade architectures. It has a flexible architecture communications controllers (FCCs), two Association, Freescale has been driving the that can easily adapt to changing industry multi-channel controllers (MCCs), four serial industry’s adoption of this high-performance needs without affecting existing infrastructure. communications controllers (SCCs), one 2 switch fabric control plane interconnect. RapidIO technology is an open standard serial peripheral interface (SPI) and one I C RapidIO technology offers significantly greater governed by an industry body, designed interface. The PowerQUICC III also offers two bandwidth, scalability and reliability than specifically for embedded, networking and integrated 10/100/1000 Ethernet controllers, other interconnects in use today, yet is communications applications. a DDR SDRAM memory controller, a 64-bit PCI-X/PCI controller and a ® RapidIO interconnect. This high level of integration helps simplify board design and offers significant bandwidth and performance for high-end control plane and data plane applications. Serial Interfaces TC-Layer Time Slot Assigner Time Slot Assigner PowerQUICC™ III Processor Family MPC8541E MPC8540 MPC8555E MPC8560 Core e500 e500 e500 e500 Frequency 533 MHz–1 GHz 667 MHz–1 GHz 533 MHz–1 GHz 667 MHz–1 GHz I-Cache/D-Cache (KB) 32/32 32/32 32/32 32/32 Integrated L2 Cache (KB) 256 256 256 256 Integrated Security Engine Yes - Yes - Fast Communications Controllers - - 2 3 Serial Communications Controllers - - 3 4 Ethernet (10/100 only) 2 1 Up to 2 Up to 3 Ethernet (10/100/1000) 2 2 2 2 2 I C Controller 2 1 2 2 UTOPIA Level II Ports - - 2 2 Multi-Channel HDLC - - Up to 64 (QMC) Up to 256 PCI Interface 2x 32-bit or 1x 64-bit 1x 32/64-bit 2x 32-bit or 1x 64-bit 1x 32/64-bit PCI-X Interface - Yes - Yes ® RapidIO Interface - Yes - Yes Memory management unit (MMU) ·· LocalT alk (HDLC-based local area Typical Applications SIMD extension with single precision network protocol) • Remote access concentrators/servers floating point ·· Universal asynchronous receiver • Regional office routers transmitter (UART) • T wo TSECs supporting 10/100/1000 • Wireless infrastructure equipment ·· Synchr onous UART (1x clock mode) Mbps Ethernet with two GMII/TBI/RGMII • Telecommunications switching and ·· Binary synchronous communication interfaces transmission equipment ·· T otally transparent operation • High-performance CPM • Ethernet switches Serial peripheral interface support for 32-bit RISC architecture running • T1/E1 and T3/E3 line cards master or slave up to 333 MHz 2 I C bus controller • OC-3 line card One instruction per clock Time-slot assigner (TSA) supports • LAN-to-WAN router Software compatible with other multiplexing of data from any of the • DSLAMs CPM-based offerings SCCs and FCCs onto eight time- • Multi-service access platforms 32 KB dual-port RAM division multiplexed (TDM) interfaces Three full-duplex FCCs supporting: • Optical networking • DDR SDRAM memory controller ·· ATM at up to 155 Mbps • IP networking 166 MHz, 64-bit, 2.5V I/O - Support for two UTOPIA interfaces • SONET transmission controller Full ECC support - AAL0, AAL1, AAL2, AAL3/4, AAL5 • Media gateways • RapidIO controller—500 MHz, 8-bit, ·· 10/100 Mbps Ethernet • IP Virtual Private Networks (VPN) LVDS I/O - Support for up to three PCI, PCI-X controller MII/RMII interfaces PCI 2.2 and PCI-X 1.0 compatible ·· HDLC/transpar ent up to 45 Mbps Technical Specifications 64- or 32-bit PCI from 16 to 66 MHz ATM transmission convergence layer • High-performance embedded e500 core • 64-bit PCI-X support up to 133 MHz capabilities (eight channels) available from 667 MHz to 1 GHz Integrated inverse multiplexing for • Host and agent mode support 32-bit, dual-issue, superscalar, ATM (IMA) functionality • Integrated 4-channel DMA controller seven-stage pipeline Two MCCs 2310 MIPS at 1 GHz • Local bus with memory controller— ·· Up to 256 HDLC/transparent (estimated Dhrystone 2.1) 166 MHz, 32-bit, 3.3V I/O channels at 64 Kbps each 32 KB L1 data and 32 KB L1 instruction • Interrupt controller ·· Eight TDM interfaces cache with line locking support ® • IEEE 1149.1 JTAG test access port Four full-duplex SCCs that support the 256 KB on-chip L2 cache with direct • 1.2V core power supply (1.3V for 1 GHz following protocols: mapped capability operation) with 3.3V and 2.5V I/O ·· High level/synchronous data link Enhanced hardware and software • 783-pin FC-BGA package debug support control (HDLC/SDLC) For current information about Freescale Learn More: products and documentation, please visit www.freescale.com. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © Freescale Semiconductor, Inc. 2007 Document Number: MPC8560FACT REV 9