FAIRCHILD SEMICONDUCTOR MM74C08N

MM74C08 Quad 2-Input AND Gate October 1987 Revised January 2004 MM74C08 Quad 2-Input AND Gate General Description Features The MM74C08 employs complementary MOS (CMOS)Wide supply voltage range: 3.0V to 15V transistors to achieve wide power supply operating range,Guaranteed noise margin: 1.0V low power consumption and high noise margin, these High noise immunity: 0.45 V (typ.) CC gates provide basic functions used in the implementation of Low power TTL compatibility: digital integrated circuit systems. The N- and P-channel enhancement mode transistors provide a symmetrical cir- Fan out of 2 driving 74L cuit with output swing essentially equal to the supply volt- Low power consumption: 10 nW/package (typ.) age. No DC power other than that caused by leakage current is consumed during static condition. All inputs are protected from damage due to static discharge by diode clamps to V and GND. CC Ordering Code: Order Number Package Number Package Description MM74CD8N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram Truth Table Inputs Outputs AB Y LLL LH L HL L HHH H = HIGH Level L = LOW Level Top View © 2004 Fairchild Semiconductor Corporation DS005878 www.fairchildsemi.com Absolute Maximum Ratings(Note 1) Voltage at Any Pin −0.3V to V + 0.3V CC Operating Temperature Range −55°C to +125°C Storage Temperature Range −65°C to +150°C Power Dissipation (P ) D Dual-In-Line 700 mW Small Outline 500 mW Note 1: “Absolute Maximum Ratings” are those values beyond which the Operating V Range 3.0V to 15V safety of the device cannot be guaranteed. Except for “Operating Tempera- CC ture Range” they are not meant to imply that the devices should be oper- Absolute Maximum V 18V CC ated at these limits. The Electrical Characteristics table provides conditions for actual device operation. Lead Temperature (Soldering, 10 seconds) 260°C DC Electrical Characteristics Min/Max limits apply across the guaranteed temperature range, unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS V Logical “1” Input Voltage V = 5.0V 3.5 IN(1) CC V V = 10V 8.0 CC V Logical “0” Input Voltage V = 5.0V 1.5 IN(0) CC V V = 10V 2.0 CC V Logical “1” Output Voltage V = 5.0V, I = −10 μA4.5 OUT(1) CC O V V = 10V, I = −10 μA9.0 CC O V Logical “0” Output Voltage V = 5.0V, I = 10 μA0.5 OUT(0) CC O V V = 10V, I = 10 μA1.0 CC O I Logical “1” Input Current V = 15V, V = 15V 0.005 1.0 μA IN(1) CC IN I Logical “0” Input Current V = 15V, V = 0V −1.0 −0.005 μA IN(0) CC IN I Supply Current V = 15V 0.01 15 μA CC CC CMOS/LPTTL INTERFACE V Logical “1” Input Voltage 74C, V = 4.75V V − 1.5 V IN(1) CC CC V Logical “0” Input Voltage 74C, V = 4.75V 0.8 V IN(0) CC V Logical “1” Output Voltage 74C, V = 4.75V, I = −360 μA2.4 V OUT(1) CC O V Logical “0” Output Voltage 74C, V = 4.75V, I = 360 μA0.4V OUT(0) CC O OUTPUT DRIVE (see Family Characteristics Data Sheet) T = 25°C (short circuit current) A I Output Source Current V = 5.0V, V = 0V −1.75 −3.3 mA SOURCE CC OUT (P-Channel) I Output Source Current V = 10V, V = 0V −8.0 15 mA SOURCE CC OUT (P-Channel) I Output Sink Current V = 5.0V, V = V 1.75 3.6 mA SINK CC OUT CC (N-Channel) I Output Sink Current V = 10V, V = V 8.0 16 mA SINK CC OUT CC (N-Channel) www.fairchildsemi.com 2 MM74C08 MM74C08 AC Electrical Characteristics (Note 2) (MM74C08) T = 25°C, C = 50 pF, unless otherwise specified A L Symbol Parameter Conditions Min Typ Max Units t , t Propagation Delay Time to V = 5.0V 80 140 pd0 pd1 CC ns Logical “1” or “0” V = 10V 40 70 CC C Input Capacitance (Note 3) 5.0 pF IN C Power Dissipation Capacitance (Note 4) Per Gate 14 pF PD Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: C determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note— PD AN-90. Typical Performance Characteristics Propagation Delay Time vs Load Capacitance MMM74C08 AC Test Circuit Note: Delays measured with input t , t = 20 ns r f Switching Time Waveforms 3 www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea- body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support to perform when properly used in accordance with device or system, or to affect its safety or effectiveness. instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the www.fairchildsemi.com user. www.fairchildsemi.com 4 MM74C08 Quad 2-Input AND Gate