SVME/DMV-163 68040 Single Board Computer with MAXPack Interface Features ·68040 CPU at 25 or 33 MHz ·16M bytes or 32M bytes DRAM with parity (up to 64M bytes on SVME levels 000 and 100, and DMV level 100) ·512K bytes Flash™ EPROM, expandable to 4M bytes ·Support for one MAXPack module, providing flexible I/O expansion ·Advanced VME Interface Chip (SCV64) ·A32:D32 VMEbus interface with A64:D64 MBLT support per ANSI/VITA 1-1994, VME64 ·Location monitor with FIFO buffer ® ·Bus Isolation mode (BI-mode ) ·Auto-ID and Auto-SYSCON ·System controller functions ·512 byte serial EEPROM ·One 16-bit counter/timer ·Ethernet™ interface on SVME levels 000 and 100 and DMV level 100 ·Two EIA-423 compatible serial channels ·Real-Time Clock (RTC) ·Tick and watchdog timers ·Built-In-Test (BIT) ·Foundation firmware including: ·Debug monitor ·Diagnostics ·Card Support Services ·Execution Sequencer ·Conduction cooled per IEEE 1101.2 (0.80- inch pitch) for MIL-E-5400/4158, and MIL-STD-2036 applications ·Optional levels of ruggedization available Page 1 SVME/DMV-163 Description â ® 68040 DRAM PROM EEPROM MPU 16MB / 64 MB 512KB / 4MB 32 32 32 1 32 8 32 8 32 SONIC Dual RTC MAXPack DMA Ethernet SCV64 UART 7170 Interface Level 0, 1 88C681 FIFO FIFO VME I/F EIA-423 Buffers P0/ Front Panel P2 I/O VMEbus 01831D Figure 1: SVME/DMV-163 Block Diagram Page 2 address mission-critical demands of military The SVME/DMV-163's design features be self-configuring, based on slot location. in real-time software. Auto-ID allows boards to diagram of the SVME/DMV-163 SBC. processor messaging, to minimize overhead system requirements. Figure 1 shows a block location monitor supports efficient inter- boards has been the only way to fulfill such ease of testing and system fault location. The specialized I/O. Traditionally, using multiple increasescircuits on the module. BI-mode solution for customers whose systems require hardware features verify all operational MAXPack modules provide a single-slot with high sustained throughputs. BIT developing their own custom module. combines low-latency access to the VMEbus standard MAXPack modules, or by with software-programmable features. It functionality by incorporating one of several implements all VMEbus interface functions designers can increase the SBC's 4's custom-designed SCV64 chipDY additional expansion capability. System mezzanine module approach to achieve ance, logistics and maintenance.rmperfo 4's MAXPack interface, a standardDY ID. These features bring benefits in one circuit card. The card is equipped with ), location monitor, and Auto-mode (BI-mode processor and up to 64M bytes of DRAM on interface, Built-In-Test (BIT), Bus Isolation MHz 68040ance 33rmcombines a high-perfo features including an AVICS-based VMEbus (SBC), built with state-of-the-art technology, 4 Systems' standardThe card supports DY The SVME/DMV-163 Single Board Computer, coverage and functional density. ance, self-testrmincreased computing perfo and aerospace systems integrators with SVME/DMV-163 Memory · · · Ô. LAN Interface CPU · · · · · Page 3 interfaces. 4K byte data cache. that provides LAN, SCSI, serial and parallel 4K byte instruction cache 163 SBC will accept the MAX-220 MAXPack data stream accesses board with a LAN interface, the SVME/DMV- Management Units (MMU) for instruction and For users that require a level 200 or 300 dual independent demand-paged Memory SONIC™ device. Processor (FPP) with a National Semiconductor 83932B 68881/68882-compatible Floating Point support. The LAN interface is implemented 68030-compatible integer unit for high speed downloading and debugger integrates the following: require a LAN connection to the target board integrated architecture. The 68040 CPU development systems oftenrnprocess. Mode concurrent execution units and a highly beneficial during the software development memory microprocessor using multiple, P0 connector. Using this LAN interface is generation of the M68000 family. It is a virtual either a front panel connector or a backplane microprocessor from Motorola's third er-coupled interface is routed tormtransfo ance, 32-bitrmThe 68040 CPU is a high-perfo LAN interface at the three-pair AUI level. The SVME/DMV-163 SBC provide an IEEE 802.3 The level 000 and 100 versions of the al connection to the chassis.rmthe Standard wedgelock fasteners give a reliable heat dissipation and vibration resistance. data. electronics. Its integral stiffening ribs improve byte serial EEPROM for storing configuration to the PWB conducts heat away from the The SVME/DMV-163 SBC also has a 512 al plane bondedrmsingle-piece aluminum the STD-2036. On Level 200 and 300 boards a the SVME/DMV-163 SBC. defined by MIL-E-4158, MIL-E-5400, and MIL- tions for1 summarizes the memory configura designed for severe environmental conditions devices may be programmed on-board. Table Systems' conduction-cooled products are possible. Flash EPROM and EEPROM 4fog, sand, and dust contamination. DY EPROM devices. Up to 4M bytes of storage is supports Flash™ EPROM, EEPROM andsealed in a chassis to prevent moisture, salt- storage. This 32-bit wide memory bankmilitary applications where circuit cards are There is a single memory bank for non-volatile, land-mobile, and navalnedesigned for airbor The conduction-cooled DMV version is reads require five. write accesses require four clock periods;ruggedization levels 000, 100, 200 and 300. is 4/3/2/2 for writes; 5/4/3/3 for reads. Random 4environments are available in DY ancermburst mode accesses. The burst perfoSVME versions for use in air-cooled memory interface design supports 68040300 boards, which do not support Ethernet VMEbus, and the MAXPack interface. Thefunctionally identical, except for level 200 and accessible from the on-board CPU, theAll versions of the SVME/DMV-163 are cause an interrupt to the CPU. The DRAM is logistics. protection. A parity error can be made to minimize field maintenance and sparing bytes of DRAM. The DRAM has byte parity detect and isolate faults during operation be configured to support from 16M to 64M systems The memory of the SVME/DMV-163 SBC can build high-performance multi-processor These features allow users to: SVME/DMV-163 Table 1 Memory Configurations Type Quantity Width Note DRAM1 Boot PROM2 Notes: 1. 2. MAXPack Interface · · · · · · ® . VME Interface Page 4 bus grant is received. 4's Single ChipSBC is implemented with DY VMEbus is requested and arbitrated, and theThe VMEbus interface of the SVME/DMV-163 locations without incurring a delay while the SCV64-equipped CPUs can write to VMEbus forward technique of bus decoupling. conceptual view of the assembly. which are used to implement a store-and- SVME/DMV-163 SBC. Figure 2 shows a SCV64 contains transmit and receive FIFO's are brought out to the P2 connector of the the VMEbus to access on-board memory. The All I/O connections of the MAXPack module the CPU to access the VMEbus, and to allow A primary function of the SCV64 is to allow heat removal. al path forrmprovides a low-resistance the extensive BIT support and BI-mode arrangement is structurally rigid, and it levels and vectors. The SCV64 also features along a rib parallel to the card edge. This levels, arbiter modes, bus timers, interrupt board along three stiffening ribs and also full programmability of requester modes and modules are rigidly mounted to the base controller and interrupt functions. It allows for high shock and vibration environments. The The SCV64 provides all VMEbus system The MAXPack mechanical design is suited to Extensive BIT support MAXPack. Interrupter, interrupt handler preserves the software invested in the Location monitor with FIFO message queue ance growth path thatrmproviding a perfo Tx and Rx FIFO's to decouple bus operations based SBCs carry the same MAXPacks, thus Master/slave A64:D64 interface 4's RISC -special function modules. DY itting customers to designrminterface, thus pe System Controller defines the electrical and mechanical rates the following:The SCV64 incorpo to an open specification thatrmmodules confo logistics and reducing sparing requirements. I/O functions to the base board. MAXPack the need for jumpers, thereby simplifying MAXPacks may be used to add a variety of nateprovide programmable features that elimi MAXPack mezzanine module interface. The philosophy of the SCV64 design is to The SVME/DMV-163 SBC is equipped with a face.the elements of a complete VMEbus inter VMEbus Interface, SCV64, which provides all latest availability information. Flash EPROM, EEPROM and availability of components. Contact the factory for The maximum PROM capacity is dependent upon memory technology, EPROM, and 300 boards is 32M bytes.The maximum DRAM capacity of level 200 1M, 2M, 4M bytes 32-bit128K, 512K bytes, 32-bit16M, 32M, 48M, 64M bytes SVME/DMV-163 Figure 2: Base Board with MAXPack Real-Time Clock (RTC) Serial Interface Page 5 tion with EIA-423, EIA-422, andcommunica maintain the time during loss of main power.ittingrmof the serial channels is EIA-423, pe STDBY line, therefore it can continue tonous serial channels. The electrical interface The RTC may be powered from the +5V88C681 UART, which provides two asynchro- The SVME/DMV-163 is equipped with an interrupts to the CPU. /wake-uprmcapable of periodic or ala month are automatically updated. The RTC is interrupt controls. Leap-year and days per FIFO with 31 entries. through to hundredths of seconds, and message queue is organized as a 32-bit wide month, day, day-of-week, and seconds data, and causes an interrupt to the CPU. The day calculations. It contains registers for year, access to the LM results in capture of the Harris 7170 RTC chip to provide for time-of- with a built-in FIFO message queue. A write The SVME/DMV-163 is equipped with a the SCV64 provides a location monitor (LM) To support inter-processor message passing, may be achieved. the SVME version.put of up to 60M bytes/secmode. Real through connector and at the front panel connector ondiscrete, block, or multiplexed block (D64) The serial channels are available at the P2transfers can be configured to occur in also programmable under software control.provides an integral DMAC. Bi-directional mable from 75 to 38.4K baud. Interrupts areboard memory and the VMEbus, the SCV64 EIA-232 interfaces. Baud rates are program-For moving large blocks of data between on- SVME/DMV-163 Timers Foundation Firmware · · , System Status Signals · · MAXPacks Variants / Ordering Information · MAX-220rn · SVME-163-042 rn · SVME-163-044 · MAX-230 · MAX-651 · MAX-654 · SVME-163-045 · SVME-163-047 . Page 6 interfaces includes two dual redundant 1553B the -042 plus the MAX-654 MAXPack which includes all the features of interface. EIA-232/422 serial and a 10-bit parallelBC, RT and BM. includes a dual redundant 1553B, a dual1553A, and 1553B Notice 2. Modes include the -042 plus the MAX-651 MAXPack whichtwo redundant 1553B interfaces. Support for includes all the features of: Dual 1553B Controller, provides SCSI, parallel and 4 EIA-232/422 interfaces. I/O, parallel I/O and non-volatile memory. includes 4MB DRAM, a second Ethernet, : Single 1553B, Utility Bus, serial the -042 plus the MAX-220 MAXPack which : VSB and Ethernet includes all the features of interface. and a real-time clock. serial channels, and a 14-bit parallel timer/counter, two EIA-423 serial channels 422 or two synchronous RS-232/RS-422 512 serial EEPROM, Ethernet, a 16-bit et , four asynchronous RS-232/RS-Ethe CPU, 16MB DRAM, 4MB Flash EPROM, Controller, provides SCSI (single-ended), SBC with a 33 MHz 68040 et serial/parallel: SCSI/Ethe lead-time. are currently in development include: provides the following variants with reduced base boards. MAXPacks that are available or purposes or a quick-turn project, DY4 with both air-cooled and conduction-cooled If an SVME-163 is required for development 4 ruggedization levels, for useall standard DY module. MAXPack modules are available in can be enhanced by adding a MAXPack The capabilities of the SVME/DMV-163 SBC , document MS00181).Execution Sequencer Configuration Items on the card (refer to invocation order of the Software Execution Sequencer (ES) - controls the in a sealed conduction-cooled chassis. , document MS00180)Support Services itting a test connector to be incorporatedrmpe Cardroutines, and Auto-ID services (refer to corresponds to the front panel indicator LED, functions, generic exception processing asserts in the event of a card failure and features on the card, device independent I/O signal on the P2 connector. This signal common software interface to the hardware The SVME/DMV-163 SBC provides a status Card Support Services (CSS) - provides a document MS00050) Card Level Diagnosticsequipment (refer to function in conjunction with the Built-In-Test programmer. diagnostic routines which perform a self-test 88C681 UART is available for use by the Card Level Diagnostics (CLD) - provides An additional 16-bit timer provided by the MS00053) failure. , documentGeneral Purpose Monitor functions for the system integrator (refer toresets the CPU if it detects an execution comprehensive monitoring and debug watchdog timer provides a fail indication and General Purpose Monitor (GPM) - provides interrupt the CPU at regular intervals. A ware package consisting of:rmfoundation fitimers. A tick timer can be programmed to The SVME/DMV-163 SBC is supplied with aThe SCV64 chip provides the user with two SVME/DMV-163 Recommended Variants Other Single Board Computers from DY 4 · · SVME/DMV-162 Special Variants · · SVME/DMV-166 · · SVME/DMV-170 · · SVME/DMV-171 · · · · · SVME/DMV-180 · · · · · · Page 7 Ruggedization levels VxWorks Board Support Package representative. FlashProg Flash EPROM programming utility For more information call your local sales P2 I/O cable for development use Factory installation of MAXPacks Flash EEPROM. bit RISC CPU, up to 8MB SRAM and 16MB PROM memory type and size MIPS R4600 64- SBC with Processor clock frequency (25 or 33 MHz) Flash EEPROM. DRAM parity or no parity Detection And Correction (EDAC) and 8MB 16M bytes to 64M bytes of DRAM RISC CPU, up to 64MB DRAM with Error PowerPC 603 SBC withand accessories include: cost and availability. SVME/DMV-163 options Flash EEPROM. Contact your local sales representative for RISC CPU, up to 12MB SRAM and 4MB PowerPC 603SBC withthe recommended variants is not suitable. Special variants can be provided if the one of 8MB SRAM and 8MB Flash EEPROM. 68040 CPU up toSBC with 8MB SRAM and 8MB Flash EEPROM. 68040 CPU up toSBC with applications options. ruggedization levels required for most RISC single board computers with a variety match the features, performance and DY 4 produces a full line of both CISC and includes a wide variety of configurations to Table 2 is a list of recommended variants. It SVME/DMV-163 Table 2 SVME/DMV-163 Matrix Clock DRAM Flash Serial SCSI 1553B Other Variant MAXPack Ethernet­­ Speed ports 163- MHz 21x21 12x22 ®® 21x37 12x38 ®® 211 x39¬¬ 212x52¬¬ 11x40 ¯¯ 1x69 ¯¯ 1x70 ¯¯ 21x42¬¬ 12x44¬¬ ®® 11x45¬¬ ®® 11x46 ¯¯ 212x47 21x05 12x06 ®® 211x08 21x01 12x02 ®® 211x54 Notes: ¬¬SVME Level 000 versions of marked variants are available with reduced lead times. ­­ ®® ¯¯ °° All SVME/DMV-163 cards include an A64:D64 VME interface, a real-time clock and a 16-bit timer. Page 8 Includes 2 EIA-423 and 2 EIA-422/232 channels Includes 2 EIA-423 and 4 EIA-422/232 channels Only versions with the MAX-220 include Ethernet at level 200 and 300 2M32M33MAX-654 4MB DRAM 2+4 14-bit parallel512K32M33MAX-220 512K32M33 512K16M33MAX-654 4MB DRAM 2+4 14-bit parallel512K16M33MAX-220 512K16M33 4M16M33MAX-654 EEPROM 128k 2+2 10-bit parallel4M16M33MAX-651 2+2 10-bit parallel4M16M33MAX-651 4MB DRAM 2+4 14-bit parallel4M16M33MAX-220 4M16M33 2+2 2M16M33MAX-651 2+2 No parity2M16M33MAX-651 2+2 10-bit parallel2M16M33MAX-651 2M16M33MAX-654 2M16M33MAX-654 4MB DRAM 2+4 14-bit parallel2M16M33MAX-220 2M16M33 4MB DRAM 14-bit parallel 2+4 No parity512K16M25MAX-220 No parity512K16M25 SVME/DMV-163 Table 3 Specifications ENVIRONMENTAL SPECIFICATIONS Temperature (Level 000) 0° °C ° °C Temperature (Level 100) ° °C ° °C Temperature (Levels 200, 300) ° °C ° °C Humidity (DMV CCA and SVME CCA - Levels 100, 300) Vibration (DMV) 2 Shock (DMV) Altitude (DMV) DIMENSIONS DMV CCA SVME CCA POWER REQUIREMENTS maximum typical ° ° ° Page 9 SVME board operating temperature is based on air flow of 11 cfm. C marginally.component's junction temperature may exceed 110 C.) When reliability or performance factors permit, awall temperature is 85 C maximum (when the chassis cold-on the DMV-163 SBC is limited to 110 † As a general design objective, the junction temperature of all components 16 mA-12v (+5%, -2.5%) 16 mA+12v (+5%, -2.5%) 3.5 A (64M bytes)4.2 A (64M bytes) 2.3 A (16M bytes)2.8 A (16M bytes)+5v (+5%, -2.5%) <570g (<1.28 lb)<900g (<2.0 lb)Weight 20.0 mm (0.8 in.)20.0 mm (0.8 in.)(base+MAXPack) 20.0 mm (0.8 in.)16.5 mm (0.65 in.)Thickness (base) 160 mm (6.3 in.)160 mm (6.3 in.)Depth 233.4 mm (9.2 in.)233.4 mm (9.2 in.)Height Method 500.3(70,000 ft) MIL-STD-81021,350m Method 516.4, Proc 1 MIL-STD-81040g/11ms half sine /Hz0.1gRandom Method 514.4 MIL-STD-8105g at 15 to 2,000 HzSine Method 507.30 to 100% condensingNon-Operating MIL-STD-8100 to 95% non-condensingOperating Methods 501.3 & 502.3C to 125-62Storage MIL-STD-810C to 85-55†Operating Methods 501.3 & 502.3C to 85-62Storage MIL-STD-810C to 71-40Operating Methods 501.3 & 502.3C to 85-40Storage MIL-STD-810C to 50Operating SVME/DMV-163 â ã DY 4 Systems Ltd. 98 Alexandria Pike Suite 32 Warrenton, VA 20186-2849 USA Virginia Tel: (540) 341-2101 Fax: (540) 341-2103 New Jersey Tel: (908) 362-5557 Fax: (908) 362-5821 California Tel: (909) 783-0240 Fax: (909) 783-4590 Texas Tel: (972) 680-5201 Fax: (972) 680-5203 DY 4 Asia Pacific Level 15, Corporate Centre One Cdr Bundall Rd & Slatyer Ave Gold Coast QLD 4217 Australia Tel: +61 7 5591 9546 Fax: +61 7 5591 9547 DY 4 Europe 15 Lambourne Crescent Cardiff Business Park Llanishen Cardiff, CF4 5GG Tel: +44 (0) 1222-747927 Fax: +44 (0) 1222 762060 DY 4 Canada 333 Palladium Dr. M/S 252 Kanata, Ontario Canada K2V 1A6 Tel: (613) 599-9191 Fax: (613) 599-7777 World-wide Internet Support Services Sales Support e-mail: sales@dy4.com Customer Support e-mail: support@dy4.com Customer Support Tel: (613) 599-9199 ext. 418 World-wide Web http://www.dy4.com Page 10 Printed in Canada, 1997 owners. All other products shown or mentioned are trademarks or registered trademarks of their respective is a registered trademark of DY 4 Systems Inc.BI-mode specification will be considered a superseding requirement. publication form a part of this specification to the extent referenced herein. In the event of a conflict, this References to other documents of the exact issue, or if not shown, the issue in effect at the time of assumes no responsibility for any errors that may appear in this document. commitment by DY 4 Systems Inc. While reasonable precautions have been taken, DY 4 Systems Inc. The information in this document is subject to change without notice and should not be construed as a