SVME/DMV-181 PowerPC™ 7410 Single Board Computer with Dual PMC Interfaces Features „ PowerPC ™ 7410 (AltiVec Technology ™-enhanced) CPU „ Up to 16 bits (8 in, 8 out) of RS- 422/485 differential discrete I/O, „ CPU core frequency up to 500 MHz with interrupt on inputs „ 100 MHz system bus and SDRAM frequency „ Eight 32-bit general purpose tim- ers „ 512 Mbytes, or 1 Gbyte of Synchronous DRAM with ECC „ Three 16-bit system timers „ 2 Mbytes of L2 cache memory – Cache may be configured as direct-mapped SRAM „ Avionics-style watchdog timer with software programmable up- „ Peak processor-memory bandwidth of 800 Mbytes/sec; peak per and lower bounds L2 cache bandwidth of 1.143 Gbytes/sec „ Real Time Clock with automatic +5V/+5V STDBY switchover „ 48 or 128 Mbytes of direct memory-mapped Flash – hardware write protection provided „ Four general-purpose PCI DMA controllers „ Permanent Alternate Boot Site (PABS) provides backup boot „ Tundra Universe II ™ VME64 master/slave interface with VME capability DMA „ 32 Kbytes of AutoStore nvSRAM „ Support for VME64x geographic addressing „ 512 bytes of Serial EEPROM „ Comprehensive Foundation Firmware with: – debug monitor and non-volatile memory programmer „ Dual 64-bit PCI local buses, 528 Mbytes/sec peak data transfer – suite of card support service routines rate – BIT firmware with 95%fault coverage – Ethernet connection option „ Two 64-bit PMC sites for high-performance I/O expansion – One 66/33 MHz capable, the other 33 MHz capable „ INTEGRITY Board Support Package from Green Hills Software (see separate datasheet for details) „ Two 10/100BaseTX (twisted pair) Ethernet ™ ports „ LynxOS ™ 4.0 reference port (see separate datasheet for de- „ 8- or 16-bit Ultra SCSI interface tails) „ Two EIA-232 serial ports „ TimeSys Linux Support Package from TimeSys (see separate „ Up to four HDLC/SDLC-capable EIA-422/485 serial channels, datasheet for details) each with full DMA support „ VxWorks ® /Tornado BSP and Driver Suite (see separate da- „ Two USB 1.1 interfaces tasheet for details) „ 16 bits of discrete TTL I/O, each with interrupt capability (feature list continued on following page) Revision 6 - July 2004www.cwcembedded.com „ IXLibs-AV AltiVec-optimized DSP Library (see separate datasheet Architecture Based on Advanced for details) Processor and Multiple Independent „ Occupies single .8 ” slot in all configurations 64-bit Busses with Crossbar Fabric „ Baseboard card uses +5 V only, backplane 3.3 V, 5 V and ±12 Figure 1 illustrates the architecture of the SVME/DMV-181. The V are routed to the PMC sites level 2 (L2) cache connects directly to the processor via the back- side 64-bit L2 cache bus of the 7410 processor. A powerful GT- „ Low-power design using switching regulator technology 64260 Discovery™ system controller bridges the processor MPX bus to the SDRAM bus, two 64-bit PCI busses, and a high-per- „ Optimum conduction-cooling with TherMax™ thermal frame formance device bus on which the Flash EPROM and non-PCI „ Supported by a network of regional Field Application Engineers and peripherals are found. The powerful crossbar fabric internal to the a staff of factory-based Customer Support specialists Discovery device allows for concurrent data transfers to take place on the various busses of the ‘181. Examples of data transfers that „ Available in a range of ruggedization levels, both air and conduction- cooled can occur concurrently on the ‘181 include: „ processor accesses to Flash concurrent with PCI-SDRAM transfers on either PCI bus Overview „ processor accesses to one PCI bus concurrent with PCI- SDRAM transfers on the other PCI bus The SVME/DMV-181 single board computer combines a processing core based on the powerful AltiVec-equipped PowerPC 7410 pro- „ processor accesses to on-chip peripherals (Ethernet and cessor with an unmatched I/O complement highlighted by dual 10/ serial ports) concurrent with PCI-SDRAM transfers on 100Base-T Ethernet ports, 6 serial channels, and two USB ports. either PCI bus Jam-packed with features to satisfy the real-world requirements of The SVME/DMV-181 provides hardware-enforced cache coherency defense/aerospace systems integrators around the globe, the with respect to accesses to SDRAM from PCI and bus-mastering SVME/DMV-181 is designed with performance, reliability, and ease peripherals. of use in mind. The SVME/DMV-181 delivers a complete hardware, software, and support-ware solution that is ready for the challenges The Discovery system controller provides a separate device bus for of avionics, tactical ground vehicle, and rugged naval applications. Flash and peripherals, thus the SDRAM bus is reserved expressly for SDRAM devices. This results in reduced bus loading on the For retrofit and technology insertion applications, the SDRAM bus, allowing for higher speed operation. SVME/DMV-181 offers a superset of the I/O features of earlier gen- erations of our PowerPC SBCs and optional pin-out modes for The Board Controller FPGA provides the bridge between the Dis- backplane compatibility as well. As a member of our continuously covery device bus and the Flash and non-PCI peripherals and evolving stream of PowerPC SBCs including the popular implements a number of SVME/DMV-181 features including inter- SVME/DMV-179, the SVME/DMV-181 supports the life-cycle model rupt control, system timers, watchdog timer, discrete I/O registers, of successive technology insertions throughout a platform’s lifetime. and Auto-ID Support Register. To increase the serviceability of the ‘181 over the long life cycles of the military/aerospace programs for which it is designed, the Board Controller FPGA is In-System Pro- grammable (ISP) and can be reprogrammed in the field. 2 Revision 6 - July 2004 Curtiss-Wright Controls Inc., Embedded Computing Discovery Designed for Harsh System Controller Permanent Environments Alternate SDRAM 2 MB Boot Site To cost-effectively address a diverse range CONTROLLER 512 MB / 1 GB L2 Cache/ (PABS) SDRAM w EDC 64 Direct-Mapped of military/aerospace applications, the SRAM 16/64 MB Boot Flash SVME/DMV-181 is available in a range of Hardware Write Protection 32 KB ruggedization levels, both air- and conduc- RTC Flash 32/64 MB nvSRAM Interleaver Application Flash tion-cooled. All versions are functionally MPX Device PowerPC BUS Bus Device identical, with air-cooled versions (SVME) 7410 Controller CPU 16 Differential available in ruggedization levels 0, 100 and Serial Serial 16 TTL Discretes Discretes #1, #2 #3, #4 w Interrupt Board Controller 200 and conduction-cooled versions (DMV) w Interrupt FPGA in levels 100 and 200. Our standard rugge- EIA-232 '422/485 Shared Xceivers Serial 3-6 dization guidelines define the environmental PCI-1 PCI-0 tolerance of each ruggedization level (see 64-bit, 33/66 MHz 64-bit, 33 MHz PCI Ruggedization Guidelines data sheet for Level Shifters more information). 10/100 8/16-BIT 2x Universe PMC Serial Ethernet USB 1.1 Site 1 E'Net SCSI-2 PMC PCI-VME #5, #6 Site 2 To ensure a long in-service life for the prod- uct, we carefully analyse the projected '422/485 fatigue life of all solder joints and intercon- nections. The mounting of all components is P0 Ethernet 2 Ethernet 1 SCSI USB 1 USB 2 P2 A&C VMEbus reviewed to ensure that differential thermal Figure 1: SVME/DMV-181 Block Diagram (See Table 3 for I/O expansion between the component and the Printed Wiring Board routing options) (PWB) does not unduly shorten the fatigue life of the solder joints. In the particular case of ceramic Ball Grid Array (BGA) compo- PCI bus 0 is a 64-bit, 33 MHz PCI bus providing a high-speed data nents, studies have shown that the large difference in coefficient of path to the Universe™ PCI-VME bridge, the LSI Logic 53C885 10/ thermal expansion between the ceramic package and typical PWB 100 Mbit/sec Ethernet/SCSI interface, the USB device, and PMC materials leads to early joint breakage after temperature cycling expansion site 2. PCI bus 1 is a 64-bit, 66 MHz PCI bus that is unless special mounting provisions are used. To solve this problem dedicated to PMC site 1. Offering a peak PCI transfer rate of 528 we convert ceramic BGA components to Column Grid Array (CGA) Mbytes/sec, PMC site 1 has the necessary bandwidth to support components before soldering them to the board. The additional high performance PMC modules such as Fibre Channel NICs, height of the column compared to a collapsed ball relieves tem- graphics controllers, and custom high-speed interfaces. perature-induced stresses and avoids premature fatigue failures. This is a proven approach also used on the SVME/DMV-179 and The innovative use of high-efficiency switching regulators for all SVME/DMV-178 PowerPC SBCs. internal voltage requirements including 3.3V is integral to allowing all the functionality of the ‘181 to be powered by only 20 Watts (typ- ical) of +5V power. Die CBGA Joint Substrate Solder Column PWB DO2037 Figure 2: Conversion of Ceramic Ball Grid Arrays (CBGA) to Ceramic Column Grid Arrays (CCGA) 3 Curtiss-Wright Controls Inc., Embedded Computing Revision 6 - July 2004 The 7410 processor incorporates Motorola’s powerful AltiVec Tech- Enhanced Thermal Management for nology, which enhances the PowerPC architecture through the Conduction Cooled Applications addition of a 128-bit vector execution unit. The vector unit provides Conduction cooling of the DMV-181 is performed by a combination for highly parallel operations, allowing for the simultaneous execu- of thermal management layers within the Printed Wiring Board tion of up to 16 integer operations or 8 floating point operations per (PWB) and an aluminum thermal frame that provides a cooling path clock cycle. At 500 MHz, this translates to a peak computational for the PMC sites and for shunts to selected high-power compo- rate of 4.0 GFLOPS. nents such as the processor and cache. To minimize the thermal resistance to the PMC sites and shunted high-power components, Table 1: Device Manufacturer’s Estimated the DMV-181 employs an innovative thermal frame design Performance approach termed TherMax. A TherMax™ thermal frame provides an unbroken metallic path from the PMC sites and shunted compo- nents to the back-side cooling surface of the card therefore mini- Processor SPECint95 SPECfp95 mizing the temperature rise to these devices. (1) 7410 at 500 MHz 22.8 17.0 The back side of a conduction-cooled VME card is the primary (1) cooling surface due to the fact that the wedgelocks on the top side Motorola 7410 Fact Sheet, MPC7410FACT/D Rev. 0 have a high thermal resistance. A typical thermal frame simply sits on top of the PWB and forces heat to flow through the PWB which has a high thermal resistance compared to aluminum. Two Mbytes of L2 Cache The SVME/DMV-181 provides 2 Mbytes of L2 cache, implemented with synchronous burst RAM. Parity error detection is provided on the L2 data bus. Running at 142.9 MHz, the L2 cache bus is capa- Wedgelock PMC Module Wedgelock PMC Module ble of a peak data transfer rate of 1.143 GBytes/sec. To provide more deterministic code execution times for repetitive algorithms, the 7410 processor can configure the L2 cache memory to be Thermal Frame Thermal Frame Heat Flow Heat Flow treated as high-performance direct-mapped SRAM. This provides T software a straightforward way to load and maintain key code seg- SHIM Basecard PWB Basecard PWB ments and associated data sets in high-speed memory. No PWB Heat Rise Heat Rise Through PWB DO2038 Standard Thermal Frame TherMax Thermal Frame Figure 3: .A TherMax thermal frame eliminates the PWB heat rise Up To 1 Gbyte of SDRAM inherent in a standard thermal frame The main memory for the SVME/DMV-181 SBC is located entirely on the basecard with no need for extra mezzanine modules. The DRAM consists of either 512 Mbytes or 1 Gbyte of high perfor- Advanced 7410 PowerPC™ CPU mance synchronous DRAM (SDRAM). To preserve data integrity, The SVME/DMV-181 is equipped with a high performance PowerPC the SDRAM is provided with Error Checking and Correcting (ECC) 7410 CPU, a fourth generation member of Motorola®’s broad family circuitry that detects and corrects all single-bit data errors, detects of PowerPC family of 32/64-bit RISC microprocessors. Developed all double bit errors, and detects all three and four bit errors within for a wide range of embedded computing applications, the 7410 the same nibble. With ECC enabled, the instantaneous peak data provides industry-leading performance per watt. The ‘181’s Pow- transfer rate to SDRAM is 800 Mbytes/sec. erPC processor runs at speeds of up to 500 MHz on-chip and offers estimated CPU benchmarks as shown in Table 1. The SDRAM is accessible from the processor and from both PCI busses. Via the Universe II™ PCI-to-VME interface device on PCI bus 0, the SDRAM is also accessible from the VMEbus. 4 Revision 6 - July 2004 Curtiss-Wright Controls Inc., Embedded Computing Flash memory is reprogrammable using the Non-Volatile Memory Up To 128 Mbytes of Fast Flash Memory Programmer (NVMP) utility (see NVMP data sheet) embedded into The SVME/DMV-181 has the capacity for up to 128 Mbytes of con- our standard foundation firmware. The Flash memory devices are tiguous, directly accessible, high-speed Flash memory. specified for a minimum of 1,000,000 program-erase cycle and a data retention time of 20 years. To minimize system boot up time for applications such as avionics mission computers where fast restarts after power interruptions are critical, '181 users can run application code directly from Flash with- out first cross loading to DRAM. This is practical due to the high- Permanent Alternate Boot Site (PABS) performance architecture of the Flash array. The PABS provides a backup boot capability in the event that the foundation firmware in the main boot bank (bank 0) becomes cor- The Flash memory of the 181 is implemented two different ways rupted. This can occur because of an error during reprogramming depending on the version of the card. For versions of the 181 with or an incorrect image being loaded. The PABS provides users with 48 MB Flash, the Flash is implemented in three banks of 16 MB a convenient mechanism to recover from corruption of the main each using AMD 29DL323 devices. Bank 0 is considered to be the boot bank without removing the card from the system in which it is boot Flash as this is where the processor reset vector installed. When a P0 backplane pin is asserted, the SVME/DMV- (0xFFF0_0100) is mapped. Banks 1 and 2 together are considered 181 will boot from the PABS, and run a reduced-functionality ver- the application Flash. To provide accelerated bandwidth to Flash, sion of our General Purpose Monitor which can then be used to logic within the Board Controller FPGA accesses the Flash banks restore the main Flash. For convenience in a development envi- 64 bits at a time and multiplexes the data onto the Discovery ronment, there is an on-board jumper to force a boot from PABS. device bus. For versions of the 181 with 128 MB Flash, the Flash is imple- 32 KBytes of AutoStore nvSRAM mented in four 32-bit wide banks of 32 MB each using AMD The AutoStore nvSRAM provides fast, non-volatile storage of mis- 29PDL128G page mode devices. Bank 0 is the boot Flash, the sion state data that must not be lost when power is removed. Dur- other 3 banks together constitute the application Flash. The page ing normal operation, application software reads and writes the mode capability of the Flash device allows for shorter access times AutoStore nvSRAM just like standard SRAM, with no special pro- for accesses that hit the same page as the previous access. The gramming algorithm required. Upon detecting a power loss on the performance improvement is such that read performance with this +5 V rail, an AutoStore cycle is performed and all 32 Kbytes are Flash technology is similar to that of the 48 MB 181s with the 64- automatically transferred from the on-chip SRAM to the on-chip bit multiplexor. EEPROM using energy stored in an on-board capacitor. At the next power-up a recall cycle is performed to transfer the EEPROM con- Two separate software write protect bits are provided for enabling Flash reprogramming. One controls the boot Flash while the other tents back to the SRAM, where the application code can now utilize the stored data to continue normal operation. The number of recall controls the application Flash. To prevent inadvertent enabling, the cycles is unlimited: the maximum number of store cycles is 100,000 two write protect bits are in separate registers. and the data retention period is 10 years. For absolute protection against inadvertent Flash reprogramming or corruption, two hardware jumpers are provided to disable the Write Enable line to the Flash devices. As for the software write protect Serial EEPROM bits, one hardware write protect jumper is provided for the boot The SVME/DME-181 provides 512 bytes of Serial EEPROM for Flash while the other controls the application Flash. Cards are con- storing configuration data used by card initialization firmware. User figured for shipment with Flash reprogramming enabled in hard- access to the Serial EEPROM is also provided. ware. This logical separation of boot and application Flash minimizes Two Ethernet™ Interfaces accidental corruption of the boot firmware when reloading applica- tion code into Flash. However if desired, all but two Mbytes of the The ‘181 is equipped with two IEEE 802.3-compliant 10BASE-T/ boot Flash can also be used for user code, at the expense of mix- 100BASE-TX Ethernet interfaces. Ethernet 1 is implemented with ing boot firmware and user code in the same domain with respect an LSI Logic 53C885 SCSI/Ethernet device connected to PCI bus to Flash write enabling. 0. A powerful chaining DMA controller and a 3 KByte FIFO for both 5 Curtiss-Wright Controls Inc., Embedded Computing Revision 6 - July 2004 receive and transmit channels ensures efficient utilization of the Four EIA-422/485 Serial Ports PCI bus and minimal processor loading. A total of four asynchronous and synchronous-capable EIA-422/485 ports are available on the SVME/DMV-181. Serial channels 3 and Ethernet 2 is implemented within the Discovery bridge device. The 4 are implemented with a Zilog 85C230 ESCC (Enhanced Serial Discovery Ethernet unit integrates powerful DMA engines and an Communications Controller). An input clock of 10 MHz provides for efficient buffer management scheme to keep processor overhead to asynchronous communication at baud rates up to 153.6 Kbaud, and a minimum. synchronous data rates up to 2.5 Mbps. To support high data rate applications without excessive loading of the PowerPC CPU, full On air-cooled cards Ethernet 1 is accessible from the front panel DMA support is provided to the ESCC by four of Discovery’s gen- connector. See Table 3, ‘181 I/O Routing Options, for information eral-purpose DMA controllers. on the routing of the Ethernet channels to backplane connectors. Serial channels 5 and 6 are implemented with Discovery’s Multi- Protocol Serial Controllers (MPSC). These powerful serial control- 8/16-Bit SCSI-2 Interface lers handle standard asynchronous and synchronous HDLC/SDLC modes, and in addition provide a transparent mode. In synchronous The SVME/DMV-181 comes standard with a single-ended, 8-bit mode a full range of data encoding schemes are supported (NRZ, Ultra SCSI (SCSI-2) interface, based on the LSI Logic 53C885 SCSI/Ethernet controller. This configuration is capable of peak NRZI Mark, NRZI Space, FM0, FM1, Manchester, and Differential Manchester). Based on an input clock of 100 MHz, all standard transfer rates on the SCSI bus of 20 Mbytes/sec in synchronous asynchronous baud rates up to 115.2Kbaud are provided as well as mode, or 7 Mbytes/sec asynchronous. synchronous bit rates up to 10 Mbits/sec. The Discovery MPSC The ‘181 is also capable of providing 16-bit Ultra SCSI. See Table includes dedicated serial DMA controllers. 3 in the I/O Routing Options section for information on I/O routing To support multi-drop or half-duplex operation, the output drivers modes that provide 16-bit SCSI. In this configuration the device supports peak transfer rates of 40 Mbytes/sec synchronous and 14 (clock and data) of each channel can be disabled. At power-up the output drivers are enabled for EIA-422 compatibility. Mbytes/sec asynchronous. See Differential Discrete I/O below for information on how the ‘181 The SCSI controller of the 53C885 is highly autonomous and trans- fers data to and from SDRAM via an internal SCSI DMA controller provides the capability to control each of the RS-422/485 drivers and receivers as differential-mode discrete signals for use as serial and an associated 536-byte DMA FIFO, minimizing the loading of control signals or general purpose I/O. the main PowerPC processor by SCSI traffic. As a PCI master the 53C885 is capable of zero wait-state data bursts at 132 Mbytes/ sec, conserving both PCI bus and main memory bandwidth. Two USB 1.1 Ports The 181’s SCSI interface includes a fuzed TERMPWR output and The SVME/DMV-181 incorporates an OPTi 82C861 PCI-to-USB on-board terminators which can be enabled and disabled under device which provides a host controller and root hub driving two software control. independent USB ports (total USB bandwidth 12 Mbits/sec nomi- nal). One USB port is accessible on the front panel connector only, the other is accessible on the P0 connector only. Two EIA-232 Serial Ports Serial channels 1 and 2 are EIA-232 serial ports based on an Exar 16C2550 controller chip. An input clock of 1.8432 MHz allows for 16 Bits of Discrete Digital I/O programmable asynchronous baud rates from 50 baud to 115.2 The SVME/DMV-181 provides 16 bits of LVTTL-compatible discrete Kbaud. The baud rate of each port can be set independently. The digital I/O. Each bit is individually programmable to be an input or DSR signal on serial channel 1 is used as a cable detect signal to output. In addition, each bit is capable of generating an interrupt force the card to boot into the General Purpose Monitor. upon a change of state, with the edge direction (high-to-low, low- to-high) also being programmable. On-board pull-up resistors are On air-cooled cards the two EIA-232 channels are accessible on provided to allow direct connection to simple switch closure inputs. the front panel in addition to being available on the rear-panel on As outputs, the TTL discretes can sink 16 mA and source 12 mA. both air- and conduction-cooled cards. 6 Revision 6 - July 2004 Curtiss-Wright Controls Inc., Embedded Computing Up to 16 Bits of Differential Discrete Real-Time Clock (RTC) The RTC function is provided by a Dallas Semiconductor DS1685 Digital I/O real-time clock chip. It contains registers for century, year, month, The SVME/DMV-181 provides the capability to control each of the day, day-of-week, and seconds. The RTC is capable of periodic RS-422/485 drivers and receivers as differential-mode discrete sig- and alarm/wake-up interrupts to the CPU. nals via registers in the Board Controller FPGA. This allows flex- ibility in how the 8 drivers and 8 receivers are used. For instance, The RTC draws its power from the standard +5 V input during nor- any Tx and Rx Clock signals that are not required on an asyn- mal operation. In the event of loss of +5 V power, the RTC will chronous channel can be used as serial control signals (RTS, CTS, automatically switch over to draw current from the +5 V STDBY etc.,) for that channel or any other. Tx and Rx data signals from line. unused serial channels can be redeployed in the same way. In addition RS-422/485 drivers and receivers can also be used as general-pur- Board Controller FPGA pose differen- Extensive Timing Resources tial-mode The SVME/DMV-181 provides a large number of timing resources Differential Discrete Data Out Register control signals to facilitate precise timing and control of system events. The list of unrelated to available timers is given in Table 2. serial I/O From Serial RS-422/485 Controllers Drivers requirements. Differential dis- crete inputs can Differential Discrete Data In Register generate an interrupt upon a RS-422/ change of state, 485 Receivers with program- mable edge To Serial Controllers direction. DO2039 Figure 4: Option for Discrete Control of RS-422/485 Drivers and Receivers 7 Curtiss-Wright Controls Inc., Embedded Computing Revision 6 - July 2004 Avionics Watchdog Timer The watchdog timer on the SVME/DMV-181 is a presettable down- counter with a resolution of 1 usec. Time periods from 1 usec to 16 seconds can be programmed. Initialization software can select whether a watchdog exception event causes an interrupt or a card reset. Once enabled to cause a reset, the watchdog cannot be dis- abled. A watchdog time-out log bit tells start-up code whether the last card reset was due to a watchdog exception. The watchdog timer can be used in two ways. Used a standard watchdog timer, a single time period is programmed which defines a maximum interval between writes to the watchdog register. For increased system integrity, the watchdog can optionally be config- ured to operate in “Avionics” mode whereby a minimum interval between writes to the watchdog register is also enforced. I.e., writ- ing to the watchdog register either too soon or too late causes an exception event. Table 2: SVME/DMV-181 Timing Resources Implementat Tick Rate/ Timer Facility ion Type Size Period Maximum Duration Time Base Register PowerPC Free running counter 64 bit 25.0 Mhz/40.0 23,398 years nsec. Decrementer PowerPC Presettable, readable downcounter 32 bit 25.0 Mhz/40.0 171.8 sec. nsec. General Purpose Bridge chip Presettable, readable downcounter 32 bit 100.0 Mhz/10 42.95 sec. #0-7 with autoreload or stop options nsec. RTC Periodic Inter- Real-time periodic interrupt generator - from 122 usec. 500 msec. rupt clock to 500 msec. by factors of two Watchdog Timer FPGA Presettable, readable downcounter 24 bit 1 Mhz/1 usec. 16.77 sec with interrupt or reset on terminal count System Timers #1- FPGA Presettable, readable, cascadeable, 16 bit 1 MHz/1 usec. 65.5 msec. for single timer, 71.6 3 downcounters with interrupt on termi- minutes for cascade of two, 8.9 nal count years for cascade of three For transferring large blocks of data over the VMEbus, it is rec- Four General Purpose DMA Controllers ommended that the DMA controllers internal to the Universe II Four DMA controllers provided by the bridge chip are available for device be used rather than the four general purpose DMA control- general purpose use. The four general purpose DMA controllers lers. This is because the Universe II DMA controllers are capable can be used for transferring blocks of data between the SDRAM, of supporting maximum-size MBLT block sizes on the VMEbus. Flash memory, device bus peripherals, and the PCI busses without loading down the PowerPC CPU. The General Purpose DMA con- trollers are capable of sustaining burst transfers using the full 64- bit width of the PCI bus. Advanced features include DMA chaining and the ability to schedule DMA transfers via a general-purpose timer. 8 Revision 6 - July 2004 Curtiss-Wright Controls Inc., Embedded Computing PMC site 1 (centre of card) is served by its own dedicated 64-bit, VME Interface 66/33 MHz-capable PCI bus. Thus high-performance PMC modules The 64-bit PCI architecture of the SVME/DMV-181 combined with such as networking modules or graphics modules can operate at 66 the Universe II’s 64-bit PCI interface and extensive decoupling MHz independent of the speed at which the PMC module in PMC FIFOs allow for high-speed, bandwidth efficient data transfers site 2 operates. PMC site 2 (bottom of card) is served by a 64-bit, between the VMEbus and on-board memory and PCI targets. VME 33 MHz PCI bus. data can be transferred at the full sustained rate of 50+ Mbytes/sec supported by the Universe II while only consuming only a fraction I/O routing is done in accordance with the IEEE P1386 specifica- of the local PCI bus bandwidth of 264 Mbytes/sec. tion, such that PMC site 1’s I/O is routed to the P0 connector, while that of PMC site #2 is routed to A and C rows of the P2 connector. Other key features of the ‘181’s VME interface include: Front panel I/O is supported as a standard feature on air-cooled cards and, on a special order basis, for conduction-cooled cards. „ Full system controller capability with support for our own/ The SVME/DMV-181 conforms fully to the IEEE 1386/1386.1 Tundra Auto-ID method requirement for a component keep-out area at the front of the PMC „ Programmable DMA controller with linked list support site for connectors or high components. „ Wide range of VMEbus address and data transfer modes; The 181 basecard drives 3.3V PCI signalling levels to both PMC > A32/A24/A16 master and slave, (not A64 or A40) sites at all times. > D64/D32/D16/D08 master and slave, (no MD32) > MBLT, BLT, ADOH, RMW, LOCK, and location monitors For PMC site 2, the Vio level is hard-wired to 5V. For PMC site #1 „ Four mailbox registers and four location monitors for inter- the selection of Vio is configurable, with a factory default of 5V. For board communications and synchronization "revision 3" boards (ones with 48 MB Flash), the Vio configuration „ Nine programmable PCI-to-VME windows and four pro- is done with zero-ohm resistors. For "revision 4" boards (ones with grammable VME-to-PCI windows 128 MB Flash), the Vio configuration is done with jumpers or wire- wrap. „ Extensive support for Built-in-Test The SVME/DMV-181 also provides support for five geographical For support of high-bandwidth PMC I/O signals such as Fibre addressing bits as defined by the ANSI/VITA 1.1-1997 (VME64 Channel or digital video, both PMC site #1 and #2 are provided extensions) specification. with five pairs of 150 ohm (nominal) differential impedance traces. Trace length is equalized within pairs. To preserve the Auto-ID context during a card-only reset from either the front panel or P0 input, the Board Controller FPGA con- tains an Auto-ID Support Register that remembers the Auto-ID PMC Power Routing results from the last power-up cycle. This value is used by foun- The PMC sites are provided with 3.3V, +12V, and –12V power fron dation firmware after a card-only reset in order to set the card to the VMEbus backplane. No 3.3V power is provided to the PMC the correct VME address. sites by the regulators on the 181 basecard itself. PCI Mezzanine Card (PMC) Expansion Conduction-Cooled PMC Modules Sites To support the industry drive to open standards on conduction- The functionality of the SVME/DMV-181 SBC can be substantially cooled cards, the PMC site mechanical interfaces follow the VITA expanded via its two PMC sites. The two PMC sites interface to the 20-2001 Conduction Cooled PCI Mezzanine Card draft standard. To outside world via 64-pins of back panel I/O per site. The placement optimize the thermal transfer from PMC modules to the base card of the PMC sites is such that a single, double width PMC module the standard DMV-181 thermal frame incorporates both the Primary can also be fitted. and Secondary thermal interfaces as defined by VITA 20-2001. See Figure 5 for a sketch of the thermal frame. 9 Curtiss-Wright Controls Inc., Embedded Computing Revision 6 - July 2004 To optimize the cooling of high-performance, high power PMCs A card reset signal is available on the backplane connectors and such as our graphics modules, the DMV-181 thermal frame incor- on the front panel connector on air-cooled cards. The front panel porates a mid-plane thermal shunt as illustrated in Figure 5. High and P0 break-out cables for the SVME-181 include a push button power PMC’s can include a mating cooling surface on the PMC switch that interfaces to this signal to allow the card to be reset module to contact the mid-plane thermal shunt. By taking advan- without doing a full system reset. tage of the thermal shunt, suitably designed PMC modules can sig- nificantly lower the heat rise from the DMV-181 card edge to the PMC components. The mid-plane thermal shunt does not impinge COP and JTAG Test and Debug on the VITA 20- specified component height. Interfaces The Control and Observation Port (COP) of the PowerPC processor The combination of the secondary thermal interfaces, the mid-plane is accessible via the front panel on air-cooled cards. The COP thermal shunt, and our own unique TherMax™ thermal frame interface is useful for software debug using a workstation tool such design provides optimum cooling for conduction-cooled PMC mod- as Wind River’s VisionICE emulation system. ules, allowing for higher power PMCs and/or increased long-term reliability through lower component temperatures. To support factory acceptance testing the SVME/DMV-181 provides a JTAG scan chain that is accessible from a 5-pin header. The JTAG test chain coverage includes the processor, VMEbus inter- face chip, L2 cache, Discovery system controller, FPGA, FPGA Boot FLASH, SCSI/Ethernet, and USB. PMC modules are auto- matically added to the JTAG chain when present. Figure 5: Thermal Frame with VITA 20-2001 PMC Cooling Surfaces and Mid-Plane Thermal Shunt Status Indicators and Controls The SVME/DMV-181 SBC provides run/fail status by asserting a backplane signal and illuminating the red front panel LED in the event the diagnostics detect a card failure. There is also a software controlled green LED that the application can use to indicate status. 10 Revision 6 - July 2004 Curtiss-Wright Controls Inc., Embedded Computing I/O Routing Options Table 3 shows the I/O routing for the SVME/DMV-181 in its native To facilitate retrofit and technology insertion, the SVME/DMV-181 (‘178/179-compatible) mode as well as its other modes. offers a superset of features and the option of pin-out compatibility with earlier generations of our PowerPC SBCs. Table 3: SVME/DMV-181 I/O ROUTING OPTIONS Front Panel Mode Description (air cooled only) P0 Connector P2 Rows A & C P2 Rows D & Z #1 Standard 181 Configuration Ser 1, EIA-232 PMC Site #1 I/O PMC Site #2 I/O E’net 1 (LSI Logic) (5-row P1/P2, 95-pin P0) Ser 2, EIA-232 E’net 2 (disco) 8-bit SCSI E’net 1 (LSI Logic) 16 discrete I/O Ser 1, EIA-232 USB 1 USB 2 Ser 2, EIA-232 COP I/F Cardfail status out Ser 3, EIA-422 Ext card reset in Ext card reset in Ser 4, EIA-422 ALT_BOOT input #2 Optional 176/177 P0/P2 Compatibility Same as mode 1 E’net 2 (disco) PMC Site #2 I/O E’net 1 (LSI Logic) Mode 8-bit SCSI 8-bit SCSI (3-row backplane compatible) Ser 1, EIA-232 Ser 1, EIA-232 Ser 2, EIA-232 Ser 2, EIA-232 Ser 3, EIA-422 Ser 3, EIA-422 Ser 4, EIA-422 Ser 4, EIA-422 13 discrete I/O USB 2 Ext card reset in Cardfail status out ALT_BOOT input #3 Optional 176/177 P2-only Compatibility Same as mode 1 P0 connector not E’net 2 (disco) E’net 1 (LSI Logic) Mode installed 8-bit SCSI 8-bit SCSI (3-row backplane compatible) Ser 1, EIA-232 Ser 1, EIA-232 Ser 2, EIA-232 Ser 2, EIA-232 Ser 3, EIA-422 Ser 3, EIA-422 Ser 4, EIA-422 Ser 4, EIA-422 16 discrete I/O Ext card reset in Cardfail status out #4 Optional 16-bit SCSI Mode Same as mode 1 PMC Site #1 I/O PMC Site #2 I/O E’net 1 (LSI Logic) E’net 2 (disco) 16-bit SCSI 16 discrete I/O Ser 1, EIA-232 USB 2 Ser 2, EIA-232 Cardfail status out Ser 3, EIA-422 Ext card reset in (no Tx Clk) ALT_BOOT input #6 Optional 6-serial channel mode Same as mode 1 PMC Site #1 I/O PMC Site #2 I/O E’net 1 (LSI Logic) E’net 2 (disco) Ser 1, EIA-232 16 discrete I/O Ser 2, EIA-232 USB 2 Ser 3, EIA-422 Cardfail status out Ser 4, EIA-422 Ext card reset in Ser 5, EIA-422 ALT_BOOT input Ser 6, EIA-422 #7 Optional Full I/O mode Same as mode 1 PMC Site #1 I/O 16-bit SCSI E’net 1 (LSI Logic) E’net 2 (disco) Ser 1, EIA-232 16 discrete I/O Ser 2, EIA-232 USB 2 Ser 3, EIA-422 Cardfail status out Ser 4, EIA-422 Ext card reset in Ser 5, EIA-422 ALT_BOOT input Ser 6, EIA-422 Note 1: Optional I/O routings are controlled by factory-set configuration links. Boards with other than the standard mode #1 routing are built to order and set-up charges may apply. Note 2: In all modes, the SVME/DMV-181 is equipped with 5-row P1 and P2 connectors. 11 Curtiss-Wright Controls Inc., Embedded Computing Revision 6 - July 2004 „ Execution Sequencer (ES) - controls the invocation order Low Power Consumption of the software configuration items on the card (see Execu- The application of advanced design techniques such as switching tion Sequencer data sheet for more information) regulators for the 3.3 V and CPU core voltage requirements and maximum use of low power devices provides a low typical power „ Non Volatile Memory Programmer (NVMP) - provides for in-circuit and closed chassis reprogramming of Flash mem- of only 20 Watts for a fully populated basecard. ory over serial port or Ethernet (see Non-Volatile Memory Programmer data sheet for more information) „ Programming utility for FPGA Serial EEPROM Power Routing The SVME/DMV-181 basecard uses only +5V and optionally +5V STDBY for the real-time clock. On-board regulators provide all nec- Our BIT firmware is designed to provide 95% fault coverage for essary internal voltages. PMC sites are fed with +5 V, ±12 V, and testable functionality and supports tests in Power-up BIT (PBIT), 3.3V directly from the backplane. Initiated BIT (IBIT), and Continuous BIT (CBIT) modes. PBIT con- sists of a reduced set of tests that provide confidence that the hard- ware is operating correctly while minimizing power-up time. Mechanical Format The IBIT capability allows users to initiate testing with a more com- Conduction-cooled modules conform to the dimensions defined in prehensive suite of tests to provide more robust testing in an off- IEEE 1101.2-1992, Standard for Mechanical Core Specifications for line mode. CBIT allows applications to test hardware components Conduction-Cooled Eurocards. in the background while the mission software operates as a higher priority task. The selection of tests for PBIT, IBIT, and CBIT is con- Air-cooled modules conform to the dimensions defined in ANSI/ figurable. VITA 1-1994, American National Standard for VME64. Front panel hardware on air-cooled modules includes: injector/extractor han- dles, EMC strip, alignment pin, and keying provisions in accordance with ANSI/VITA 1.1, American National Standards for VME64 Operating System Software Extensions (and IEEE 1101.10). The SVME/DMV-181 is supported by the following real-time oper- ating systems: For air-cooled applications where the enclosure is not compatible with the IEEE 1101.10-style front panels, traditional-style front panel kits can be purchased separately and fitted to the card by the „ INTEGRITY Board Support Package from Green Hills Software (see separate customer. datasheet for details) „ LynxOS ™ 4.0 reference port Foundation Firmware and BIT (see separate datasheet for The SVME/DMV-181 SBC is equipped with a comprehensive on- details) board firmware package called Foundation Firmware that includes: „ General Purpose Monitor (GPM) - provides monitoring, „ TimeSys Linux Support Package from TimeSys (see separate diagnostic, and board exerciser functions to facilitate sys- tem startup and integration activities (see General Purpose datasheet for details) Monitor data sheet for more information) „ Built-in-Test (BIT) – a library of Card Level Diagnostic „ Wind River’s VxWorks ® /Tor- nado BSP and Driver Suite (CLD) routines is provided to support Power-up BIT (PBIT), Initiated BIT (IBIT) and Continuous BIT (CBIT) (see Card (see separate datasheet for details) Level Diagnostics data sheet for more information) „ Card Support Services (CSS) - provides a common soft- ware interface to the hardware features of the card (see Card Support Services data sheet for more information) Contact your local representative for updates on support for other operating systems. 12 Revision 6 - July 2004 Curtiss-Wright Controls Inc., Embedded Computing IXLibs-AV DSP Library Integration Support Our IXLibs-AV DSP library allows customers to fully exploit the per- We provide all the supporting items necessary to ensure a smooth formance potential of the ‘181’s AltiVec-equipped ‘7410 processor. system integration process. These include: IXLibs-AV provides a comprehensive set of AltiVec-optimized C- „ Comprehensive hardware, firmware, and software docu- callable functions written primarily in assembly language, yielding a mentation package, in hard copy and on CD-ROM significant performance advantage over equivalent functions written only in a high-level language. This object-format library integrates „ Break-out cables for the front and rear-panel I/O to convert easily with standard software development tools and supports real the ‘181-specific pin-outs to industry standard connectors and complex array, vector, and scalar signal processing functions. for use in laboratory development environments. See Table 4. Table 4: SVME/DMV-181 Cable Set Cable Number Connects To Description CBL-SBC-FPL-000 Front panel in all Front panel break-out cable providing standard RJ-45 10/100BaseT Ethernet jack, con- pin-out modes nectors for two RS-232 channels, USB, JTAG/COP, and push-button switch for card reset. Compatible with SVME-181 and SVME-712 CBL-SBC-P0-000 P0 in modes 1, 4, 6, 7 P0 break-out cable with separate branches and connectors for Ethernet interface 2, (standard) TTL discretes, USB port 2, and PMC I/O on our standard 78-way connector. Also includes reset switch CBL-SBC-P0-001 P0 in mode 2 P0 break-out cable with separate branches and connectors for Ethernet interface 2, 8- bit SCSI interface (using 68-way 16-bit SCSI connector), 2 EIA-232 ports, EIA-422/485 ports 3 and 4, TTL discretes, and USB port 2. Also includes reset switch CBL-SBC-P2-000 P2 in modes 1, 2 P2 break-out cable with separate branches and connectors for 8-bit SCSI interface (standard) (using 68-way 16-bit SCSI connector), 2 EIA-232 ports, EIA-422/485 ports 3 and 4, and PMC I/O on our standard 78-way connector. (No Ethernet branch.) CBL-SBC-P2-001 P2 in mode 3 P2 break-out cable with separate branches and connectors for Ethernet interface 2, 8- bit SCSI (using 68-way 16-bit SCSI connector), 2 EIA-232 ports, EIA-422/485 ports 3 and 4, and TTL discretes. Also includes reset switch CBL-SBC-P2-002 P2 in mode 4 P2 break-out cable with separate branches and connectors for 16-bit SCSI interface (16-bit SCSI) (using 68-way 16-bit SCSI connector), 2 EIA-232 ports, EIA-422/485 port 3, and PMC I/ O on our standard 78-way connector CBL-SBC-P2-003 P2 in mode 6 P2 breakout cable with separate branches and connectors for 2 EIA-232 ports, 4 EIA- (6 serial) 422/485 ports, and PMC I/O on our standard 78-way connector. CBL-SBC-P2-004 P2 in mode 7 P2 breakout cable separate with separate branches and connectors for 16-bit SCSI (Full I/O) interface (using 68-way 16-bit SCSI connector), 2 EIA-232 ports, and 4 EIA-422/485 ports 13 Curtiss-Wright Controls Inc., Embedded Computing Revision 6 - July 2004 Table 5: SVME/DMV-181 Specifications POWER REQUIREMENTS Maximum Typical +5 V (+5.0%, -2.5%) 5.0 A 4.0 A +12 V 0 A Not used by the base card, only routed to the PMC sites. -12 V 0 A Not used by the base card, only routed to the PMC sites. 3.3 V 0 A Not used by the base card, only routed to the PMC sites. +5 V STDBY: - with +5 V present <1 uA <1 uA - without +5 V <2 mA <1 mA DIMENSIONS & WEIGHT Dimensions Weight SVME card per ANSI/VITA 1-1994 <500 g (<1.21 lbs.) DMV card per IEEE 1101.2 <750 g (<1.65 lbs) SVME cardAvailable in levels 0, 100 and 200* DMV cardAvailable in levels 100 and 200* *For the SVME/DMV-181 level 200 temperature range is -40°C to +85°C. Refer to Ruggedization Guidelines datasheet for more details Contact Information The information in this document is subject to change without notice and should not be construed as a commitment by Curtiss-Wright Controls Inc., Embedded Computing (CWCEC) group. While reasonable precautions have been taken, CWCEC assumes no responsibility for any errors that may appear in this document. All products shown or mentioned are trademarks or registered trademarks of their respective owners.  Printed in Canada, 2004. Curtiss-Wright Controls, Embedded Computing Sales Offices North America Alabama Mid-West New Jersey T: +1 256 830 0149 T: +1 314 983 0800 T: +1 201 251 2630 F: +1 256 830 4295 F: +1 314 872 1706 F: +1 201 251 2640 NA West Coast Texas Virginia T: +1 250 653 2350 T: +1 972 494 0888 T: +1 703 779 7800 F: +1 250 653 2319 F: +1 972 494 0882 F: +1 703 779 7805 Europe Asia Pacific T: +44 (0) 29 20 747 927 T: +1 613 254 5121 F: +44 (0) 29 20 762 060 F: +1 613 599 7777 Support and Technical Resources North America Europe Internet support@dy4.com uksupport@dy4.com www.cwcembedded.com T: +1 613 254 5150 T: +44 (0) 870 351 3672 info@cwcembedded.com 14 Revision 6 - July 2004 Curtiss-Wright Controls Inc., Embedded Computing Contact Information To find your appropriate sales representative, please visit: Website: www.cwcembedded.com/sales or Email: sales@cwcembedded.com For technical support, please visit: Website: www.cwcembedded.com/support1 Email: support1@cwcembedded.com The information in this document is subject to change without notice and should not be construed as a commitment by Curtiss-Wright Controls Inc., Embedded Computing (CWCEC) group. While reasonable precautions have been taken, CWCEC assumes no responsibility for any errors that may appear in this document. All products shown or mentioned are trademarks or registered trademarks of their respective owners. © Curtiss-Wright Controls Embedded Computing, Ottawa. 5 Curtiss-Wright Controls Inc., Embedded Computing Revision 1 - October 2004