TM PC/104 STACKABLE SYNCHRO/RESOLVER/LVDT TRACKING INPUT MODULES ~~~~ FEATURES ~~~~ q Dir Dir Direct ect ect Synchro, Resolver and LVDT Inputs Inputs Inputs Dir Direct ect Inputs Inputs q Quad Channel Quad Channel Quad Channel Quad Channel Quad Channel Solid State Input Modules q Transformer Isolated Models, q No external conditioning or components req'd. W Wide band ide band q W W Wide band ide band ide band 47-1K hz. Reference Inputs, Model options to 10Khz. TM q PC/104 Form-Factor, Stack through q True 16 Bit Address Decode q True 16 Bit "Word Level" Data Bus q Bus/Stack Powered Std. q True card level accuracy and test data. q Auto Handshake, no need to Inhibit Converters q BIT/Fault Output Status, w/Loss detect q Forced Angle Test Mode For Self Test Actual Size, True 16 Bit Data Bus, ISOLATED TOO! DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION feature inter inter internal nal nal solid-state or T T Tr r ransf ansf ansfor or ormer mer mer inter internal nal T Tr ransf ansfor ormer mer The PC104 Series” are 3 and 4 Chan- power-ups. 3 seperate test-to angles are Isola Isolated ted dir direct f ect field ield Isola Isola Isolated ted ted Scott T’s that accept dir dir direct f ect f ect field ield ield provided on 3 channel isolated models, nel PC/104 and compatible synchro, re- v v v v volta olta olta olta oltag g g g ge inputs e inputs e inputs e inputs e inputs. solver, and LVDT/RVDT to digital con- and a single test-to 30 degree angle is verters, employing type 2 ratiometric track- provided on 4 channel units. T T T T Tr r r r ransf ansf ansf ansf ansfor or or or ormer mer mer mer mer Isola Isola Isola Isola Isolation tion tion tion tion is offered for all all all all all ing converters specifically suited for high The forced test mode may be activated the reference and signal input lines, This This This This This by setting bits SD0/SD1 in the control completel completely isola y isolates the car tes the card and ef d and eff fec- ec- performance embedded applications. completel completel completely isola y isola y isolates the car tes the car tes the card and ef d and ef d and eff f fec- ec- ec- word, once activated the converters in- ti ti ti ti tiv v v v vel el el el ely the w y the w y the w y the w y the whole computer fr hole computer fr hole computer fr hole computer fr hole computer from all f om all f om all f om all f om all field ield ield ield ield They will accept any group of upto 4 ternally switch their inputs from the field wir wir wir wir wiring ing ing ing ing, ,,, , elimina elimina elimina elimina eliminating concer ting concer ting concer ting concer ting concerns o ns o ns o ns o ns ov v v v ver; er; er; er; er; individual, 3-wire Sync Sync Sync Sync Synchr hr hr hr hro o o o o, or 4-wire Re- Re- Re- Re- Re- I/O and instead insert fixed analog test troublesome ground loops, ground in- troublesome ground loops, ground in- troublesome ground loops, ground in- troublesome ground loops, ground in- troublesome ground loops, ground in- solv solv solv solv solver er er er er inputs, or 2-4 wir or 2-4 wir or 2-4 wir or 2-4 wir or 2-4 wire L e L e L e L e LVDT/R VDT/R VDT/R VDT/R VDT/RVDT VDT VDT VDT VDT angles for validation, when switching to duced noise duced noise duced noise, , , dif dif diff f fer er ering potentials, ing potentials, ing potentials, g g gr r round ound ound duced noise duced noise, , dif diff fer ering potentials, ing potentials, g gr round ound inputs inputs inputs; over a frequency range of 50Hz. 50Hz. 50Hz. inputs inputs 50Hz. 50Hz. or from the forced angle test mode, the interjected spik interjected spikes, es, and ghostl and ghostly f y field noise ield noise interjected spik interjected spik interjected spikes, es, es, and ghostl and ghostl and ghostly f y f y field noise ield noise ield noise to 10KHZ to 10KHZ to 10KHZ to 10KHZ to 10KHZ., and convert them into 10-16 user can either wait the specified settling tha tha tha tha that so fr t so fr t so fr t so fr t so frequentl equentl equentl equentl equently tak y tak y tak y tak y takes do es do es do es do es down, wn, wn, wn, wn, and/or and/or and/or and/or and/or bit words of virtually jitter-and lag free, time rated for those converters (20 to cor cor cor cor corr r r r rupts the oper upts the oper upts the oper upts the oper upts the opera a a a ation of tion of tion of tion of tion of, , , , , entir entir entir entir entire systems. e systems. e systems. e systems. e systems. natural binary data representing the in- 300msec.), or monitor fault/BIT status bits put signals absolute physical position. Transformer isolated units, facilitate as a ready indicator. Test within .15 de- Data is addressable in a single w single w single wor or ord 16 d 16 d 16 single w single wor ord 16 d 16 grees. TM bit f bit f bit f bit f bit for or or or orma ma ma ma mat t t t t over the PC/104 stack-bus. ~~~~ APPLICATIONS ~~~~ Built-In-T Built-In-T Built-In-T Built-In-T Built-In-Test/Loss/F est/Loss/F est/Loss/F est/Loss/F est/Loss/Fault Detect Sta ault Detect Sta ault Detect Sta ault Detect Sta ault Detect Status tus tus tus tus Data made available to the bus is con- q q q q q Synchro/Resolver Test Sets Additionally, a single Sta Sta Status tus tus W W Wor or ord d d is Sta Status tus W Wor ord d tinuously updated (tracking) without in- q q q q q Embedded Display and Inst. Sets BIT/F BIT/Fault ault sta status tus provided to report the BIT/F BIT/F BIT/Fault ault ault sta sta status tus tus terruption; output data is accurate, mono- data is accurate, mono- data is accurate, mono- data is accurate, mono- data is accurate, mono- of each independent channel, indication tonic tonic tonic, , , and al and al and alw w wa a ays fr ys fr ys fresh esh esh up to the maxi- q q q q q OEM Mobile Antenna Gear tonic tonic, , and al and alw wa ays fr ys fresh esh include loss of signal, loss of reference, mum tracking rate of the converter. q q q q q Marine Gyro/GPS Systems overspeed/accel and malfunction alert. F F F F For or or or orced ced ced ced ced T T T T Test Mode: est Mode: est Mode: est Mode: est Mode: q q q Automated Guided Vehicles q q Dir Direct F ect Field ield V Volta oltag ge Inputs e Inputs Dir Dir Direct F ect F ect Field ield ield V V Volta olta oltag g ge Inputs e Inputs e Inputs All modules include a force angle test q q q q q Drones, Radars, Weather Inst's. No e No e No e No e No exter xter xter xter xternal tr nal tr nal tr nal tr nal transf ansf ansf ansf ansfor or or or ormer mer mer mer mers, s, s, s, s, modules or mode for self-test to excersize the con- signal conditioners are r r r r requir equir equir equir equired ed ed ed ed. The syn- q q q q q Surveying & Mapping Apparatus verters for module checks following chro/resolver and LVDT converters used densities upto 4 channels per card, and SSS SS SPP PPEE EECC CCII IIFF FFII IICC CCAA AATT TTIII IOOO ONNN NS S SPECIFICATIONS separate reference inputs are provided for each channel; allowing differing reference 111s 1s1s 00000BBBBBiiiiitttttsss 111s 1s1s 22222BBBBBiiiiitttttss 111s 1s1s 44444BBBBBiiiiitttttss 111s 1s 166666BBBBBiiiiitttttss sources to be used with a single card, and AAA) A)A’ ccccccccccuuuuurrrrraaaaacccccyyyyy(((((11111))) +’/-30+’ /-8.5 +’/-4 +/-4 channel to channel and channel to bus isolation exceeding 500VDC. ---s -s -GGGGGAAAAAmmmmmooooodddddeeeeelllllsss +/-4.5’+/-4.5’ Solid State input units are for price-para- +’ /-21’ +’/-2.7*+/-2.6 --s -s -HHHHAAAAmmmmooooddddeeeellllss -HAmodels mount applications, offering densities upto TTTe Te TrrrrraaaaaccccckkkkkiiiiinnnnngggggRRRRRaaaaattttteee 12.5 10 2.5 0.625 4 channels per module, with separate ref- erence inputs for each channel, and com- (RPS) 40 00Hz. 4040152. mon mode rejection exceeding 70 db.. 2,5KHz.100 80 30 5 Because only "whole complete convert- ers" are used throughout; direct field in- ---s -s -HHHHHSSSSSmmmmmooooodddddeeeeelllllsss 20 .5KHz.200 20 0 501 put voltages are facilitated and neither AAAn An Acccccccccceeeeellllleeeeerrrrraaaaatttttiiiiiooooonnn 60Hz. 770 295 20 external components, conditioning, or field 40 00Hz.10260 40 50 641 12 component selections/changes, are re- quired. 2,5KHz.2500 9000 1620 Accuracy, performance, and 60 0Hz.10 40 30 5 7 dynamiccharacteristics, are specified and specified and specified and specified and specified and TM TM TM TM TM 400Hz.220005500 1100 tested inc tested inc tested inc tested inc tested inclusi lusi lusi lusi lusiv v v v ve of the w e of the w e of the w e of the w e of the whole PC/104 hole PC/104 hole PC/104 hole PC/104 hole PC/104 assemb assemblly y,, and printed test data is provided, assemb assemb assembl l ly y y,,, 2K ,5KHz.10 6040 000 810 and maintained, on all units. SSSe Se SttttteeeeepppppRRRRReeeeessssspppppooooonnnnnccccceee 60Hz.200ms.360ms.800ms.1200ms. Maximum versatility has been em- 2. .5KHz.9.5ms9. 5ms1. 50ms600ms ployed on the PC104 Series' products to assure the universal compatibility in ad- FFe FFFe rrrrreeeeeqqqqquuuuueeeeennnnncccccyyyyyRRRRRaaaaannnnngggggeee60Hz.units47-1000Hz. 400Hz.units360-2KHz. dressing, timing, system, and specific 2. .5KHz.units2000-4800Hz.HigherFreq.Avail computer har har har har hard d d d dw w w w war ar ar ar are and softw e and softw e and softw e and softw e and softwar ar ar ar are inde- e inde- e inde- e inde- e inde- pendence. pendence. pendence. pendence. pendence. RRRs Rs ReeeeefffffeeeeerrrrreeeeennnnnccccceeeeeIIIIInnnnnpppppuuuuutttttsss 26VRMSinto90Kohms The PC104 Series cards are configured 115VRMSinto360Kohms with a full 16 bit range of jumper-plug SSSs Ss SiiiiigggggnnnnnaaaaalllllIIIIInnnnnpppppuuuuutttttsss 11.8VRMSL-Linto26KohmsMinimumL-LBalanced selectable I/O addressing . The interface is a solidly-reliable solidly-reliable solidly-reliable solidly-reliable solidly-reliable, high-speed, true 16 16 16 16 16 26VRMSL-Linto26KohmsMinimumL-LBalanced bit "W bit "W bit "W bit "W bit "Wor or or or ord-Le d-Le d-Le d-Le d-Lev v v v vel" el" el" el" el" register access. Sim- 90VRMSL-Linto200KohmsMinimumL-LBalanced ply address the I/O; and read the data. BBB) B)Bs rrrrreeeeeaaaaakkkkkdddddooooowwwwwnnnnn(((((vvvvvooooollllltttttsssss)))500VDCMinimumtoGroundonTransformerUnit Because 'auto-handshaking auto-handshaking auto-handshaking auto-handshaking auto-handshaking is provided on-board, to pr to pr to pr to pr to pre e e e ev v v v vent f ent f ent f ent f ent false r alse r alse r alse r alse reads, eads, eads, eads, eads, and and and and and a Ce CCCCe ooooommmmmmmmmmooooonnnnnMMMMMooooodddddeee 70Db.MinimumonSolidStateUnits true 16 bit data bus is used; there is no no no no no PPr PrPl oooowwwweeeerr+5VDC@.45Amp.typ,+50ma./channe Power need to emplo need to emplo need to employ an y an y any ad y ad y additional softw ditional softw ditional softwar ar are e e need to emplo need to employ an y any ad y additional softw ditional softwar are e steps to inhibit the converters, or manipu- -12VDC@30ma./ch lating 8 bit bytes; and the user is assured TTTe Te Teeeeemmmmmpppppeeeeerrrrraaaaatttttuuuuurrrrreee Operating:0Cto+70C(-1units),-40Cto+85C(-3units) only the most current, valid and "dynamic" Storage:-55Cto+125C data is presented to the bus. Softw Softwar are e Notes:1)Accuracyappliesforwholeassy.+/-1LSB,overtemperaturerange, Softw Softw Softwar ar are e e code fragments that may be . +/-10%amplitudeandfreq.variations,&+/-5%powervariations, used as dr dr dr dr driiiiiv v v v ver er er er ers s s s s, ar ar ar ar are pr e pr e pr e pr e pro o o o ovided vided vided vided vided in C, and simple inport/outport commands are used 2)Differentinputvoltages,ratesandfrequenciesavailable in assembly. In addition, a C written Demonstration program is provided for Environmental Specifications: Out-Of-The-Box testing, scaling, and off- Temperature: see chart & model # Vibration: 3.5 mm. 5-9Hz. : setting; without any user programming Humidity: 0 to 95% 1.0 G 9 - 150Hz. required, and includes source code . (non-condensing) Shock: 15 g's for 11 msec. PC104's are available in: commercial Wheight: 4-8 ounces = 1-4 Channel o o O O O C to +70 C, industrial -40 C to +85 C. SOFTWARE SUPPORT All cards shipped with Soft- ware Packs having a Demo Program for Out-Of-The-Box Testing & Scaling, and Self- Test features etc. with Source Code provided for extraction. Code fragments for use as Drivers provided in C, As- sembly uses inport/outport see below. NT Drivers are Extra. Notes: 1) All shields to go direct to Earth Ground on the com- puter side only. 2) To reverse direction of rotation swap S1 with S3 or invert data in software. 3) S4 is not used on Synchro BLOCK DIAGRAM PC/104 units. PPP, P, PIIIIINNNNNTTTTTEEEEERRRRRMMMMMIIIIINNNNNAAAAATTTTTIIIIIOOOOONNNNNSSSSS:::::PPPPPCCCCC111110000044444SSSSSeeeeerrrrriiiiieeeeesssss,,, SS SSSSS EEEEETTTTTTTTTTIIIIINNNNNGGGGGBBBBBOOOOOAAAAARRRRRDDDDDBBBBBAAAAASSSSSEEEEEAAAAADDDDDDDDDDRRRRREEEEESSSSSSSS PPPN PNPd IIIIINNN SSSd SSd tttttaaaaannnnndddddaaaaarrrrrdd PPPN PNPd IIIIINNN SSSd Sd Stttttaaaaannnnndddddaaaaarrrrrdd AA. A. AddddddddrrrreeeessssssssBBBBiiiittttssss////PPPPlllluuuuggggssss4444----11115555aaaarrrreeeeuuuusssseeeeddddttttoooosssseeeetttttttthhhheeeebbbbooooaaaarrrrddddssssbbbbaaaasssseeeeaaaaddddddddrrrreeeessssssss.. AddressBits/Plugs4-15areusedtosettheboardsbaseaddress. Exampleshownisasboardsleavethefactory;setto300h(Hex). 1LR 1L 7 R RRRe Re Reeeeefffffeeeeerrrrreeeeennnnnccccceee Re RRRRe eeeeefffffeeeeerrrrreeeeennnnnccccceee RemovingAddressJumper-Plugssetstheaddrestoa1. Channel#0 Channel#2 2 RH 18 RH HH/ H/ HEEEEXXXXffffoooorrrrmmmmaaaatttt// HEXformat/ 31S 11 9 S 00000333330000000000 Representation 4 S2 20 S2 SSs Ss Siiiiggggnnnnaaaallllss SSs Ss Siiiiggggnnnnaaaallllss Signals Signals LL1 L1 LooooggggiiiiccccSSSSeeeetttt,,,,OOOOuuuutttt====1100000000 00000000 00000000 11111111 00000000 00000000 00000000 00000000 LogicSet,Out=10 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 Channel#0 Channel#2 53S123S 6 S4 22 S4 AAAs As AddddddddddrrrrreeeeessssssssssBBBBBiiiiitttttsss 1 1 15 1514 5 55 1 1 14 14 14 4 1 1 13 1312 3 3 3 1 1 12 12 12 2 1 1 11 1110 1 1 1 1 1 10 10 10 0 9 9 9 9988888 7777766666 5555544444 3333322222 11111NNNNN 70V) D) DD3 D)CCCCVVVVeeeellll....((((oooopppptttt....) 22V) DD) D) DCCCCVVVVeeeellll....((((oooopppptttt....) DCVel.(opt.) DCVel.(opt.) PPPP PP PCCC CC111 11000 00444 44SSS SSEEE EERRR RRIIIIIEEE EESSS SSAAA AADDD DDDDD DDRRR RREEE EESSS SSSSS SSMMM MMAAA AAPP P ControlWord 8Gd ndGroun 24Gd ndGroun HHHX HXHs EEEEEXXXAs AAAr As ddddddddddrrrrreeeeessssssssssBBBBBiiiiitttttss CCCrC. Crooooonnnnnvvvvveeeeerrrrrttttteeeeerr C. CCCC.hhhhhaaaaannnnn.. Writetestmode 9LR 2L 5 R RRRe Re Reeeeefffffeeeeerrrrreeeeennnnnccccceee Re RRRRe eeeeefffffeeeeerrrrreeeeennnnnccccceee Chn# versesrunmode Channel#1 Channel#3 SSSt StS1 eeeeellllleeeeeccccctttA1 AAA1An 44444AAAAA33333AAAAA22222AAAAA11 Fn FFFFn uuuuunnnnnccccctttttiiiiiooooonn 10 RH 26 RH BitSD0=LSB CHANNEL 00h 0000 0 11 1 S 21 7 S DATAREAD S0 D1Se DMod 02h 0 0 0 1 1 12 S2 28 S2 ONLY SSSs Ss Siiiiigggggnnnnnaaaaalllllsss SSSs Ss Siiiiigggggnnnnnaaaaalllllsss Channel#1 Channel#3 00 RUN 00 4h 010 2 13 3S923S 06h 0011ReadStatusALL O 01 90 14 S4 30 S4 WriteTest/ 00 8h 100 ALL 11 5V) D) DDD1 D)CCCCCVVVVVeeeeelllll.....(((((ooooopppppttttt.....)) 33V) DDD) D) DCCCCCVVVVVeeeeelllll.....(((((ooooopppppttttt.....)) O 10 Runmode 0 16Gd nd.Groun 32Gd ndGroun Note:On4channelunits06hischan.3,08h=read O 11 30 status,0Ah=writetestmode/angle. NOTES:1)J3ConnectorANSLEY#609-3407 2)J3MATE:Wire:Housing:AMP#102387-8 SSSS SS STTTTTAAAAATTTTTUUUUUSSSSSWWWWWOOOOORRRRRDDDDDBBBBBIIIIITTTTTMMMMMAAAAAPPPPPfffffooooorrrrrPPPPPCCCCC111110000044444SSSSSEEEEERRRRRIIIIIEEEEESSS . Pins:AMP#102348-2or102348-3,(Don’tuseribbon) 3)Velocityoutputnotusedonsolidstateinputunits. MMMB MB MSSSSSBBBBBIIIII/////OOOOOSSSSStttttaaaaatttttuuuuusssssDDDDDaaaaatttttaaaaaBBBBBiiiiitttttsssssLLLLLSSSSSBBB 4)3ChannelIsolatedUnitsusethis,4ChannelsIsol.Differ 1 1 15 15 15 551 1 14 14 14 4 41 1 13 13 13 3 31 1 12 12 12 2 21 1 11 11 11 1 11 1 10 10 10 0 0 9 9 9 9 9 8 8 8 8 8 7 7 7 7 7 6 6 6 6 6 5 5 5 5 5 4 4 4 4433333222221111100000 ASSEMBLY CODE FOR READING REGISTERS Bits4-15=X=Notused,Mask 0=Built-in-TestChannel3Fault/BIT/Loss MOV DX,Port_address in Hex ; place address of port 0=Built-in-TestChannel2Fault/BIT/Loss ; in DX register 0=Built-in-TestChannel1Fault/BIT/Loss INW AX,DX ; place value in AX register TM 0=Built-in-TestChannel0Fault/BIT/Loss PC/104 is a Trademark of the PC/104 Consortium Copyright C 1995 Computer Conversions Corp. TM PC104 SERIES SYNCHRO/RESOLVER Inputs MODEL SELECTION GUIDE MMS MS MOO OODD DDEE EELL LLSS SSEE EELL LLEE EECC CCTT TTII IIOO OONN NNGG GGUU UUII IIDD DDEE EEFF FFOO OORR RRPP PPCC CC11 1100 0044 44UU UUNN NNII IITT TTS S MODELSELECTIONGUIDEFORPC104UNITS MM: M: Mooooddddeeeellll:: Model: PP4 PPP4 CCCCC1111100000444 B B B4 B4B4 444 B B B4 B4B5 44 B B B5 B5B0 55 0000 XXXXXVVVVV 11111 ---- ---- ---- - - - ab b ababa Temp. a:seetablea Comm.-1 b:seetableb Extended-3 C1 H.0C2 H. C3 H. CH. Insert-XforTransformerIsolatedunits Insert-VforDCVelocityoutputsoptionforTransformerIsolatedUnitsonly. bbb) b) b)))))SSSSSEEEEELLLLLEEEEECCCCCTTTTTSSSSSIIIIIGGGGGNNNNNAAAAALLLLLSSSSS(((((IIIIINNNNNSSSSSEEEEERRRRRTTTTTCCCCCOOOOODDDDDEEEEE#####))) aaaD aD a)))))SSSSSEEEEELLLLLEEEEECCCCCTTTTTCCCCCOOOOONNNNNVVVVVEEEEERRRRRTTTTTEEEEERRRRRTTTTTYYYYYPPPPPEEEEEAAAAANNNNNDDD RESOLUTIONCODE REFERENCESIGNALFREQUENCYINSERTTHIS VOLTAGELEVELSINHERTZCODE BBBS BS BIIIIITTTTTSSS 1 1 16 1614 6 66 1 1 14 14 14 4 1 1 12 1210 2 2 2 1 1 10 10 10 0 26VAC11.8V.L-L400Hz.1 SSSL SL SYYY YYNNN NNCCC CCHHH HHRRR RROOO OOTTT TTOOO OODDD DDIII IIGGG GGIII IITTT TTAAA AALL L 2L6VAC1. 1.8V.L-22.6KHz CodeAAAAABBBBB CCCCCDDDDD 26VAC26V.L-L400Hz. 3 RRRL RL REEEEESSSSSOOOOOLLLLLVVVVVEEEEERRRRRTTTTTOOOOODDDDDIIIIIGGGGGIIIIITTTTTAAAAALLL 1L 15VAC9. 0V.L-4400Hz CodeEEEEEFFFFF GGGGGHHHHH 115VAC90V.L-L60Hz. 5 ALLOTHERSREQUESTEXT.MODELGUIDE ALLOTHERSREQUESTEXT’D.MODELGUIDE CABLE DRAWING Example: Model; PC104-B4B4B5-X-1 Includes: 1 PC104 Card, Populated with: 2 - 14 Bit S-D Converters 115/90V. @ 400Hz. 1- 14 Bit S-D Converter 115/90V. @ 60 Hz. All Reference and Signal inputs are Trans- o o former Isolated, 0 C to 70 C oper. temp. Your Local CCC Representative is: Cable Belden 8777 or Equal