Data Sheet CME8000 C-MAX The RF Technology Specialist RC Receiver IC 1 Short Description The CME8000 is a BiCMOS integrated straight through receiver with build in very high sensitivity and a pre-decoding of the time signal transmitted from WWVB, DCF77, JJY, MSF and HBG. The receiver is prepared for multi-mode reception by using an integrated logic. Integrated functions as stand by mode, integrated antenna switching, integrated crystal switching and a hold mode function offer features for universal applications. The power down mode increases the battery lifetime significantly and makes the device ideal for all kinds of radio controlled time pieces. 2 Features o Low power consumption (<100µA) o Automatic protocol recognition o Very high sensitivity (0.4µV) o Pre-decoded protocol information o Build in pulse decoding for different protocols o Fast data transfer to CPU (100ms) o Switchable for 3 different frequencies o Use of the CPU clock (32768Hz) o High selectivity by using crystal filter o Improved noise resistance o Power down mode o Integrated AGC adaptation o Only a few external components necessary Two built-in low impedance antenna switches o AGC hold mode (40 Ohm/3V) o Wide frequency range (40 ... 120 kHz) o True Bit strength indication o Low power applications (1.2 .. 5.0 V) Benefits o Extended Battery operating time o Easy world time piece design o Decoding of the signal extremely simplified o Automatic country recognition o Simplified micro controller software o True signal quality information o Simplified multi frequency handling Block Diagram QIN QLOUT QMOUT QHOUT VCC VL PON GNDL ANT1 Bias crystal switch CLKSEL CLOCK I/O DR Logic Unit DATA IN1 rect.- TCO DT AGC IN2 BSI1 BSI2 contr. unit AGC ANT2 GND DEM PK SS1 SS2 HLD Figure 1. SPEC No. Revision State C-MAX printed Version Page CME8000 B.11 11.03.05 14.03.2005 English 1 of 21 Data Sheet CME8000 C-MAX 3 Ordering Information Extended Type Number Package Remarks CME8000-DDT no die in trays CME8000-TL* yes SSO28 CME8000-TLQ* Yes SSO28 Taped and reeled *The packaged version of CME8000 is prepared for lead-free soldering. Soldering parameters are tbd. 4 Absolute Maximum Ratings Parameters Symbol Value Unit Supply voltage VCC 5.5 V Ambient temperature range 1.2 – 2.49V T -20 to +75 °C amb Ambient temperature range 2.5 – 5.5V T -40 to +85 °C amb Storage temperature range R -55 to +150 °C stg Junction temperature T 125 °C j Electrostatic handling (MIL Standard 883 D HMB) +/- V 4 kV ESD Electrostatic handling (MIL MM ) +/- V 400 V ESD 5 PAD Coordinates The CME8000 is available as die for "chip-on-board" mounting and in SSO28 package. DIE size: 2,73mm x 2,5mm PAD size: contact window 84µm / 84µm Thickness: 300µm±10µm Symbol Function x-axis (µm) y-axis (µm) Pad # (dice) Pin # (SSO28*) ANT2 Antenna switch 2 924.0 2243.6 1 1 IN2 Input antenna 582.4 2243.6 2 2 IN1 Input antenna 395.3 2243.6 3 3 ANT1 Antenna switch 1 156.5 2101.4 4 4 VCC Supply voltage analog part 156.5 1908.1 5 5 QHOUT Crystal 3 output 156.5 1715.3 6 6 QMOUT Crystal 2 output 156.5 1519.2 7 7 QLOUT Crystal 1 output 156.5 1322.0 8 8 GND Ground analog part 153.8 1161.6 9 9 QIN Crystal input 156.5 881.3 10 10 DEM Capacity for peak-detector 505.2 172.4 11 12 PK Capacity for AGC 767.0 172.4 12 13 TEST Test I/O 1547.2 181.6 13 14 PON Power on 1711.3 181.6 14 16 HLD AGC hold 1959.5 181.6 15 17 GNDL Ground logic part 2319.8 174.5 16 18 BSI 2 Bit strength indicator 2 2518.1 355.0 17 19 BSI 1 Bit strength indicator 1 2518.1 805.6 18 20 DT Data send clock 2517.8 1070.3 19 21 Data Data output 2517.8 1468.7 20 22 DR Data ready in register 2518.1 1919.2 21 23 Clock Input 1024 / 4096Hz 2517.5 2185.9 22 24 SS2 Transmitter select 2 2332.0 2243.7 23 25 SS1 Transmitter select 1 1950.1 2243.7 24 26 VL Supply voltage logic part 1574.9 2241.9 25 27 CLKSEL Clock select 1287.4 2243.7 26 28 SPEC No. Revision State C-MAX printed Version Page CME8000 B.11 11.03.05 14.03.2005 English 2 of 21 CME8000 MFB Data Sheet CME8000 C-MAX 6. Pad Layout Pin Layout SSO28 IN1 IN2 ANT2 CLKSEL VL SS1 SS2 ANT2 1 28 CLKSEL 1 3 2 26 25 24 23 22 Clock 4 ANT1 2 27 VL 21 VCC 5 DR 6 QHOUT IN1 3 26 SS1 QMOUT 7 20 Data 8 QLOUT ANT1 4 25 SS2 GND 9 19 DT VCC 5 24 Clock The PAD coordinates 10 QI N 18 BSI1 are referred to the left bottom point of the contact QHOUT 6 23 DR window 17 BSI2 QMOUT Y-axis 7 22 Data 11 12 13 14 15 16 DEM PK TEST PON HLD GNDL DT QLOUT 8 21 X-axis 20 BSI1 9 Reference point GND Figure 2. Pad layout 19 10 BSI2 QIN 11 18 GNDL NC 17 HLD DEM 12 PK 13 16 PON 14 15 TEST NC Figure 3. Pin layout SSO28 SPEC No. Revision State C-MAX printed Version Page CME8000 B.11 11.03.05 14.03.2005 English 3 of 21 Data Sheet CME8000 C-MAX IN1, IN2 QHOUT, QMOUT, QLOUT A ferrite antenna is connected between IN1 and In order to achieve a high selectivity, a crystal is IN2. For high sensitivity, the Q factor of the connected between the Pins QOUT and QIN. It is antenna circuit should be as high as possible. used with the serial resonant frequency according Please note that a high Q factor requires to the time-code transmitter and acts as a serial temperature compensation of the resonant resonator. Up to 3 crystals could be connected frequency in most cases. We recommend a Q from QLOUT, QMOUT and QHOUT to the factor between 40 and 150, depending on the common input QIN. The outputs will be application. An optimal signal-to-noise ratio will be automatically selected by the pin SS1 and SS2 achieved by a resonator resistance of 40 kOhm to (see table). Only one of the outputs is active. Note 100 kOhm. that the output QLOUT is active if JJY40 is selected. QMOUT is active if a 60kHz protocol is selected, and QHOUT is only active for DCF or ANT1, ANT2 HBG. To realize a reception at different frequencies with In applications with less than 3 different one antenna, it is possible to connect additional frequencies, leave the unused output pins open. capacitors between the inputs. An internal MOS- The given parallel capacitor of the filter crystal switch is activated when a 60kHz protocol is (about 1.4 pF) is internally compensated so that activated. A second internal switch is activated the bandwidth of the filter is about 10 Hz. The choosing the JJY40 protocol (see table page 9). impedance of QIN is high. Parasitic loads have to The capacitors have to be connected between be avoided. ANT2 and IN1 for adjusting the 60kHz frequency, and between ANT1 and IN2 to adjust the VCC frequency to 40kHz. Note in this case both switches are active. Pad 5 Pin 5 In applications with supply voltages below 2.5V the impedance of the switches is probably too 110k 110k high for a good Q-factor. Q In applications with less than 3 frequencies leave the unused pins open QHOUT PIN6 Pad6 QMOUT PIN7 Pad7 VCC QLOUT PIN8 Pad8 Pad 5 Pin 5 200k 200k GND ANT1 Pad 9 Pad 4 Pin 9 Pin 4 RF - AMP Figure 5. IN1 QIN Pad 3 VCC Pin 3 IN2 Pad 5 Pin 5 Pad 2 Pin 2 200k from ANT2 AGC Pad 1 QIN Pin 1 Pad 10 1 k GND Pin 10 Pad 9 Pin 9 Figure 4. GND Pad 9 Pin 9 Figure 6. SPEC No. Revision State C-MAX printed Version Page CME8000 B.11 11.03.05 14.03.2005 English 4 of 21 Data Sheet CME8000 C-MAX DEM Demodulator output. To ensure the function, an NOTE: Automatic adjustment of PK and DEM external capacitor has to be connected at this timing output. To realize a good regulation timings of the VCC demodulator and the peak detector the charge and discharge currents for the capacitors at DEM Pad 5 and PK have different values for the different Pin 5 protocols. This is automatically switched internally by choosing the protocol with SS1 and SS2. DEM Pad 10 25k Pin 12 VCC, GND, VL, GNDL V and GND are the supply voltage inputs for the GND CC analog part. V and GNDL are the supply voltage L Pad 9 inputs for the digital part. The positive supplies Pin 9 Figure 7. have to be connected externally, and also the ground pins. To power down the circuitry it is recommended to use the PON input and not to switch the power supply. Switching the power supply results in a long power up waiting time. PK Peak detector output. An external capacitor has to be connected to ensure the function of the peak VCC VL detector. The value of the capacitance influences the AGC regulation time. Pad 5 Pad 25 Pin 5 Pin 27 VCC Pad 5 Pin 5 PK from + GND GNDL - demodulator Pad 12 2k Pad 9 Pad 16 Pin 13 Pin 9 Pin 18 Figure 9. GND Pad 9 Pin 9 Figure 8. SPEC No. Revision State C-MAX printed Version Page CME8000 B.11 11.03.05 14.03.2005 English 5 of 21 Data Sheet CME8000 C-MAX CLOCK, DT, PON, HLD These pins are high impedant MOS-inputs and require MOS-levels for operating BSI1, BSI2, DATA, DR CLOCK These 4 pin are MOS-outputs, which deliver To run the IC it is necessary to apply the clock MOS-level. chosen by CLKSEL. All the timings given referred to this clock cycles. In power down mode a clocking is not necessary. ESD protection HLD VL AGC hold mode: HLD high (V = V ) sets AGC HLD CC Pad 25 HLD off, HLD low (V = 0) or open sets AGC HLD PIN 27 HLD on, that is it holds for a short time the AGC voltage. This can be used to prevent the AGC from peak voltages, created by e.g. a stepper motor. Additional, there will be internal hold function BSI2 PIN 19 PAD 17 generated, especially during read-out of data. BSI1 PIN 20 PAD 18 PON PIN 16 PAD 14 HLD PIN 17 PAD 15 PON PON must be either connected to V or GND. CC GNDL If PON is connected to GND, the receiver will be Pad 16 activated. The set-up time is typically 0.5 s after PIN 18 Figure 11. applying GND at this pin. If PON is connected to V , the receiver will switch to power-down mode. CC A power down period of min. 2msec is necessary after switching on the power supply and before switching to another protocol. ESD protection VL Pad 25 PIN 27 CLOCK PIN 24 PAD 22 DT PIN 21 PAD 19 PON PIN 16 PAD 14 HLD PIN 17 PAD 15 GNDL Pad 16 PIN 18 Figure 10. SPEC No. Revision State C-MAX printed Version Page CME8000 B.11 11.03.05 14.03.2005 English 6 of 21 Data Sheet CME8000 C-MAX SS1, SS2, CLKSEL SS1, SS2 5 different protocols and 2 test modes are selected by this 2 tri-state input pins (see table). The selection is done in the first 20msec after the power down period. Then the selected protocol is internally stored and active until the next power down. CLKSEL The IC can be clocked by 2 different frequencies. A clock 4096Hz (32768Hz / 8) is expected if CLKSEL is connected to VCC. CLKSEL open or connected to GND needs a clock frequency of 1024Hz (32768Hz / 32). The selection is done in the first 20msec after the power down period. Then the selected frequency is fix until the next power down. ESD protection VL Pad 25 PIN 27 300k SS2 PAD 23 PIN 25 SS1 PIN 26 PAD 24 CLKSEL PIN 28 PAD 26 300k GNDL Pad 16 PIN 18 Figure 12. SPEC No. Revision State C-MAX printed Version Page CME8000 B.11 11.03.05 14.03.2005 English 7 of 21 Data Sheet CME8000 C-MAX 7 Electrical Characteristics V = 3V, input signal frequency 77.5 kHz +/- 5 Hz; carrier voltage 100% reduction to 25% for t = 200ms; MOD CC t = 25°C, max./min. limits are at +25...C ambient temperature, unless otherwise specified. amb Test condition / Parameter Symbol Min. Typ. Max. Unit Pin ** Supply voltage range (V , L V CC 1.2 5.0 V V CC No different supply voltages allowed!) Supply current I 90 <120 µA CC Set-up time after V ON* V = 3V 1.5 s t CC CC Reception frequency range F 40 120 kHz in Minimum input voltage V 0.5 0.8 µV IN1, IN2 in Maximum input voltage IN1, IN2 V 30 50 mV in Setup time after PON for t 1.5 s receiver part* Power-ON control; PON Pad/Pin PON Quiescent current receiver V =V , Pad/Pin PON CC I 0.03 0.05 µA CC0 OFF V CC Set-up time after PON* t 0.5 2 s Logical Part (digital inputs: PON, HLD, DT, Clock) Pins PON, HLD, DT, Clock Low level 0.15 V V L High level 0.85 V V L Input leakage current 0