X7R Dielectric General Specifications X7R formulations are called “temperature stable” ceramics and fall into EIA Class II materials. X7R is the most popular of these intermediate dielectric constant materials. Its tem- perature variation of capacitance is within ±15% from -55°C to +125°C. This capacitance change is non-linear. Capacitance for X7R varies under the influence of electrical operating conditions such as voltage and frequency. X7R dielectric chip usage covers the broad spectrum of industrial applications where known changes in capaci- tance due to applied voltages are acceptable. PART NUMBER (see page 2 for complete part number explanation) 0805 5 C 103 M A T 2 A Size Voltage Dielectric Capacitance Capacitance Failure Terminations Packaging Special (L" x W") 4V = 4 X7R = C Code (In pF) Tolerance Rate 2 = 7" Reel Code T = Plated Ni 6.3V = 6 J = ± 5% A = Not 4 = 13" Reel A = Std. 2 Sig. Digits + and Sn 10V = Z K = ±10% Applicable Product 7 = Bulk Cass. Number of 7 = Gold 16V = Y M = ± 20% 9 = Bulk Zeros Plated 25V = 3 50V = 5 Contact 100V = 1 Factory For 200V = 2 500V = 7 Multiples X7R Dielectric Insulation Resistance vs Temperature � Capacitance vs. Frequency Typical Temperature Coefficient 10,000 +30 10 5 +20 0 1,000 +10 -5 0 -10 -10 100 -15 -20 -20 -25 -30 0 -60 -40 -20 0 20 40 60 80 100 120 140 1KHz 10 KHz 100 KHz 1 MHz 10 MHz 0 20 40 60 80 100 120 Frequency Temperature °C Temperature °C Variation of Impedance with Cap Value Variation of Impedance with Chip Size Impedance vs. Frequency Variation of Impedance with Chip Size Impedance vs. Frequency Impedance vs. Frequency 1,000 pF vs. 10,000 pF - X7R 100,000 pF - X7R 0805 10,000 pF - X7R 10 10.00 10 1206 1206 1,000 pF 0805 0805 10,000 pF 1210 1210 1.0 1.00 1.0 0.1 0.10 0.1 .01 0.01 .01 110 100 1,000 10 100 1000 110 100 1,000 Frequency, MHz Frequency, MHz Frequency, MHz 12 Impedance, � % Cap Change % � Capacitance Impedance, � Insulation Resistance (Ohm-Farads) Impedance, � X7R Dielectric Specifications and Test Methods Parameter/Test X7R Specification Limits Measuring Conditions Operating Temperature Range -55ºC to +125ºC Temperature Cycle Chamber Capacitance Within specified tolerance ≤ 2.5% for ≥ 50V DC rating Freq.: 1.0 kHz ± 10% ≤ 3.0% for 25V DC rating Voltage: 1.0Vrms ± .2V Dissipation Factor ≤ 3.5% for 16V DC rating For Cap > 10 µF, 0.5Vrms @ 120Hz ≤ 5.0% for ≤ 10V DC rating 100,000MΩ or 1000MΩ - µF, Charge device with rated voltage for Insulation Resistance whichever is less 120 ± 5 secs @ room temp/humidity Charge device with 300% of rated voltage for Dielectric Strength No breakdown or visual defects 1-5 seconds, w/charge and discharge current limited to 50 mA (max) Note: Charge device with 150% of rated voltage for 500V devices. Appearance No defects Deflection: 2mm Capacitance Test Time: 30 seconds ≤ ±12% Resistance to Variation 1mm/sec Flexure Dissipation Meets Initial Values (As Above) Stresses Factor Insulation ≥ Initial Value x 0.3 90 mm Resistance ≥ 95% of each terminal should be covered Dip device in eutectic solder at 230 ± 5ºC Solderability with fresh solder for 5.0 ± 0.5 seconds Appearance No defects, <25% leaching of either end terminal Capacitance ≤ ±7.5% Variation Dip device in eutectic solder at 260ºC for 60 Dissipation Resistance to seconds. Store at room temperature for 24 ± 2 Meets Initial Values (As Above) Factor hours before measuring electrical properties. Solder Heat Insulation Meets Initial Values (As Above) Resistance Dielectric Meets Initial Values (As Above) Strength Appearance No visual defects Step 1: -55ºC ± 2º 30 ± 3 minutes Capacitance ≤ ±7.5% Step 2: Room Temp ≤ 3 minutes Variation Dissipation Thermal Meets Initial Values (As Above) Step 3: +125ºC ± 2º 30 ± 3 minutes Factor Shock Insulation Meets Initial Values (As Above) Step 4: Room Temp ≤ 3 minutes Resistance Dielectric Repeat for 5 cycles and measure after Meets Initial Values (As Above) Strength 24 ± 2 hours at room temperature Appearance No visual defects Capacitance Charge device with twice rated voltage in ≤ ±12.5% Variation test chamber set at 125ºC ± 2ºC for 1000 hours (+48, -0) Dissipation ≤ Initial Value x 2.0 (See Above) Load Life Factor Insulation Remove from test chamber and stabilize ≥ Initial Value x 0.3 (See Above) Resistance at room temperature for 24 ± 2 hours before measuring. Dielectric Meets Initial Values (As Above) Strength Appearance No visual defects Store in a test chamber set at 85ºC ± 2ºC/ Capacitance ≤ ±12.5% 85% ± 5% relative humidity for 1000 hours Variation (+48, -0) with rated voltage applied. Load Dissipation ≤ Initial Value x 2.0 (See Above) Humidity Factor Remove from chamber and stabilize at Insulation ≥ Initial Value x 0.3 (See Above) room temperature and humidity for Resistance 24 ± 2 hours before measuring. Dielectric Meets Initial Values (As Above) Strength 13 � � � X7R Dielectric Capacitance Range PREFERRED SIZES ARE SHADED SIZE 0201 0402 0603 0805 1206 Soldering Reflow Only Reflow Only Reflow Only Reflow/Wave Reflow/Wave Packaging All Paper All Paper All Paper Paper/Embossed Paper/Embossed MM 0.60 ± 0.03 1.00 ± 0.10 1.60 ± 0.15 2.01 ± 0.20 3.20 ± 0.20 (L) Length (in.) (0.024 ± 0.001) (0.040 ± 0.004) (0.063 ± 0.006) (0.079 ± 0.008) (0.126 ± 0.008) MM 0.30 ± 0.03 0.50 ± 0.10 0.81 ± 0.15 1.25 ± 0.20 1.60 ± 0.20 (W) Width (in.) (0.011 ± 0.001) (0.020 ± 0.004) (0.032 ± 0.006) (0.049 ± 0.008) (0.063 ± 0.008) MM 0.15 ± 0.05 0.25 ± 0.15 0.35 ± 0.15 0.50 ± 0.25 0.50 ± 0.25 (t) Terminal (in.) (0.006 ± 0.002) (0.010 ± 0.006) (0.014 ± 0.006) (0.020 ± 0.010) (0.020 ± 0.010) WVDC 16 16 25 50 10 16 25 50 100 10 16 25 50 100 200 10 16 25 50 100 200 500 Cap 100 A (pF) 150 A 220 A C 330 A C G G J J J J J J K 470 A C G G J J J J J J K 680 A C G G J J J J J J K 1000 A C G G J J J J J J K 1500 C G G J J J J J J J J J J J J M 2200 C G G J J J J J J J J J J J J M 3300 C C G G J J J J J J J J J J J J M 4700 C G J J J J J J J J J J J J M 6800 C C G J J J J J J J J J J J J P Cap 0.010 C G J J J J J J J J J J J J P (µF 0.015 C G G J J J J J J J J J J J M 0.022 C G J J J J J M J J J J J M 0.033 G J J J J M J J J J J M 0.047 G G J J J J M J J J J J M 0.068 G J J J J J J J J J P 0.10 G G G J J J J J J J J M 0.15 G J J J J J J J 0.22 G J J M J J J J 0.33 MM J J M M 0.47 NM M M M 0.68 NMM 1.0 NMMQ W L 1.5 P 2.2 Q T � 3.3 4.7 10 t 22 47 100 WVDC 16 16 25 50 10 16 25 50 100 10 16 25 50 100 200 10 16 25 50 100 200 500 SIZE 0201 0402 0603 0805 1206 Letter A C E G J K M N P Q X Y Z Max. 0.33 0.56 0.71 0.86 0.94 1.02 1.27 1.40 1.52 1.78 2.29 2.54 2.79 Thickness (0.013) (0.022) (0.028) (0.034) (0.037) (0.040) (0.050) (0.055) (0.060) (0.070) (0.090) (0.100) (0.110) PAPER EMBOSSED 14 � � � � � � � X7R Dielectric Capacitance Range PREFERRED SIZES ARE SHADED SIZE 1210 1812 1825 2220 2225 Soldering Reflow Only Reflow Only Reflow Only Reflow Only Reflow Only Packaging Paper/Embossed All Embossed All Embossed All Embossed All Embossed MM 3.20 ± 0.20 4.50 ± 0.30 4.50 ± 0.30 5.70 ± 0.40 5.72 ± 0.25 (L) Length (in.) (0.126 ± 0.008) (0.177 ± 0.012) (0.177 ± 0.012) (0.225 ± 0.016) (0.225 ± 0.010) MM 2.50 ± 0.20 3.20 ± 0.20 6.40 ± 0.40 5.00 ± 0.40 6.35 ± 0.25 (W) Width (in.) (0.098 ± 0.008) (0.126 ± 0.008) (0.252 ± 0.016) (0.197 ± 0.016) (0.250 ± 0.010) MM 0.50 ± 0.25 0.61 ± 0.36 0.61 ± 0.36 0.64 ± 0.39 0.64 ± 0.39 (t) Terminal (in.) (0.020 ± 0.010) (0.024 ± 0.014) (0.024 ± 0.014) (0.025 ± 0.015) (0.025 ± 0.015) WVDC 10 16 25 50 100 200 500 50 100 200 500 50 100 6.3 50 100 200 50 100 Cap 100 (pF) 150 W L 220 330 T � 470 680 1000 t 1500 J J J J J J M 2200 J J J J J J M 3300 J J J J J J M 4700 J J J J J J M 6800 J J J J J J M Cap 0.010 J J J J J J M K K K K M M X X X X M P (µF 0.015 J J J J J J P K K K P M M X X X X M P 0.022 J J J J J J Q K K K P M M X X X X M P 0.033 J J J J J J K K K X M M X X X X M P 0.047 J J J J J J K K K Z M M X X X X M P 0.068 J J J J J M K K K M M X X X X M P 0.10 J J J J J M K K K M M X X X X M P 0.15 J J J J M K K P M M X X X X M P 0.22 J J J J P K K P M M X X X M P 0.33 J J J J Z K M M M X X X M P 0.47 M M M M Z K P M M X X X M P 0.68 M M P X Z M Q M X X X M P 1.0 N N P X Z M X M Z M P 1.5 N N MMX 2.2 X Z M 3.3 4.7 Q Z 10 Z 22 47 100 WVDC 10 16 25 50 100 200 500 50 100 200 500 50 100 6.3 50 100 200 50 100 SIZE 1210 1812 1825 2220 2225 Letter A C E G J K M N P Q X Y Z Max. 0.33 0.56 0.71 0.86 0.94 1.02 1.27 1.40 1.52 1.78 2.29 2.54 2.79 Thickness (0.013) (0.022) (0.028) (0.034) (0.037) (0.040) (0.050) (0.055) (0.060) (0.070) (0.090) (0.100) (0.110) PAPER EMBOSSED 15 � � � � Packaging of Chip Components Automatic Insertion Packaging TAPE & REEL QUANTITIES All tape and reel specifications are in compliance with RS481. 8mm 12mm Paper or Embossed Carrier 0612, 0508, 0805, 1206, 1210 Embossed Only 1812, 1825 1808 2220, 2225 Paper Only 0201, 0306, 0402, 0603 Qty. per Reel/7" Reel 2,000, 3,000 or 4,000, 10,000, 15,000 3,000 500, 1,000 Contact factory for exact quantity Contact factory for exact quantity Qty. per Reel/13" Reel 5,000, 10,000, 50,000 10,000 4,000 Contact factory for exact quantity REEL DIMENSIONS Tape A B* D* N W 2 C W W (1) 1 3 Size Max. Min. Min. Min. Max. 7.90 Min. +1.5 14.4 (0.311) 8.40 -0.0 8mm +0.059 (0.567) 10.9 Max. (0.331 -0.0 ) +0.50 (0.429) 330 1.5 13.0 -0.20 20.2 50.0 +0.020 (12.992) (0.059) (0.512 -0.008 ) (0.795) (1.969) 11.9 Min. +2.0 18.4 (0.469) 12.4 -0.0 12mm +0.079 (0.724) 15.4 Max. (0.488 -0.0 ) (0.607) Metric dimensions will govern. English measurements rounded and for reference only. (1) For tape sizes 16mm and 24mm (used with chip size 3640) consult EIA RS-481 latest revision. 60 Embossed Carrier Configuration 8 & 12mm Tape Only 10 PITCHES CUMULATIVE TOLERANCE ON TAPE P 0 ±0.2mm (±0.008) T 2 EMBOSSMENT D P 0 2 T DEFORMATION Chip Orientation BETWEEN E 1 EMBOSSMENTS A0 W F E TOP COVER 2 B 1 TAPE B K 0 0 P 1 T 1 D FOR COMPONENTS 1 CENTER LINES S 1 MAX. CAVITY 2.00 mm x 1.20 mm AND OF CAVITY SIZE - SEE NOTE 1 LARGER (0.079 x 0.047) B IS FOR TAPE READER REFERENCE ONLY 1 INCLUDING DRAFT CONCENTRIC AROUND B0 User Direction of Feed 8 & 12mm Embossed Tape Metric Dimensions Will Govern CONSTANT DIMENSIONS Tape Size D EP P S Min. T Max. T 0 0 2 1 1 +0.10 8mm 1.50 -0.0 1.75 ± 0.10 4.0 ± 0.10 2.0 ± 0.05 0.60 0.60 0.10 +0.004 (0.059 -0.0 ) (0.069 ± 0.004) (0.157 ± 0.004) (0.079 ± 0.002) (0.024) (0.024) (0.004) and Max. 12mm VARIABLE DIMENSIONS Tape Size B D E FP RT WA B K 1 1 2 1 2 0 0 0 Max. Min. Min. Min. Max. See Note 5 See Note 2 4.35 1.00 6.25 3.50 ± 0.05 4.00 ± 0.10 25.0 2.50 Max. 8.30 8mm See Note 1 (0.171) (0.039) (0.246) (0.138 ± 0.002) (0.157 ± 0.004) (0.984) (0.098) (0.327) 8.20 1.50 10.25 5.50 ± 0.05 4.00 ± 0.10 30.0 6.50 Max. 12.3 12mm See Note 1 (0.323) (0.059) (0.404) (0.217 ± 0.002) (0.157 ± 0.004) (1.181) (0.256) (0.484) 8mm 4.35 1.00 6.25 3.50 ± 0.05 2.00 ± 0.10 25.0 2.50 Max. 8.30 See Note 1 1/2 Pitch (0.171) (0.039) (0.246) (0.138 ± 0.002) (0.079 ± 0.004) (0.984) (0.098) (0.327) 12mm 8.20 1.50 10.25 5.50 ± 0.05 8.00 ± 0.10 30.0 6.50 Max. 12.3 See Note 1 Double (0.323) (0.059) (0.404) (0.217 ± 0.002) (0.315 ± 0.004) (1.181) (0.256) (0.484) Pitch NOTES: 2. Tape with or without components shall pass around radius “R” without damage. 1. The cavity defined by A , B , and K shall be configured to provide the following: 0 0 0 3. Bar code labeling (if required) shall be on the side of the reel opposite the round sprocket holes. Surround the component with sufficient clearance such that: Refer to EIA-556. a) the component does not protrude beyond the sealing plane of the cover tape. 4. B dimension is a reference dimension for tape feeder clearance only. 1 b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the cover tape has been removed. 5. If P = 2.0mm, the tape may not properly index in all tape feeders. 1 c) rotation of the component is limited to 20º maximum (see Sketches D & E). d) lateral movement of the component is restricted to 0.5mm maximum (see Sketch F). Top View, Sketch "F" Component Lateral Movements 0.50mm (0.020) Maximum 0.50mm (0.020) Maximum 61 Paper Carrier Configuration 8 & 12mm Tape Only 10 PITCHES CUMULATIVE P TOLERANCE ON TAPE 0 ±0.20mm (±0.008) D P 0 2 T E 1 BOTTOM TOP COVER COVER F W TAPE TAPE E 2 B 0 G T 1 A P 0 1 CAVITY SIZE T1 CENTER LINES SEE NOTE 1 User Direction of Feed OF CAVITY 8 & 12mm Paper Tape Metric Dimensions Will Govern CONSTANT DIMENSIONS Tape Size D EP P T G. Min. R Min. 0 0 2 1 +0.10 8mm 1.50 -0.0 1.75 ± 0.10 4.00 ± 0.10 2.00 ± 0.05 0.10 0.75 25.0 (0.984) +0.004 (0.059 -0.0 ) (0.069 ± 0.004) (0.157 ± 0.004) (0.079 ± 0.002) (0.004) (0.030) See Note 2 and Max. Min. Min. 12mm VARIABLE DIMENSIONS P1 Tape Size E Min. F W A B T 2 0 0 See Note 4 +0.30 8mm 4.00 ± 0.10 6.25 3.50 ± 0.05 8.00 -0.10 See Note 1 +0.012 (0.157 ± 0.004) (0.246) (0.138 ± 0.002) (0.315 -0.004 ) 1.10mm (0.043) Max. for Paper Base 4.00 ± 0.010 10.25 5.50 ± 0.05 12.0 ± 0.30 12mm Tape and (0.157 ± 0.004) (0.404) (0.217 ± 0.002) (0.472 ± 0.012) +0.30 1.60mm 8mm 2.00 ± 0.05 6.25 3.50 ± 0.05 8.00 -0.10 +0.012 (0.063) Max. 1/2 Pitch (0.079 ± 0.002) (0.246) (0.138 ± 0.002) (0.315 -0.004 ) for Non-Paper Base Compositions 12mm 8.00 ± 0.10 10.25 5.50 ± 0.05 12.0 ± 0.30 Double (0.315 ± 0.004) (0.404) (0.217 ± 0.002) (0.472 ± 0.012) Pitch NOTES: 2. Tape with or without components shall pass around radius “R” without damage. 1. The cavity defined by A , B , and T shall be configured to provide sufficient clearance 0 0 3. Bar code labeling (if required) shall be on the side of the reel opposite the sprocket surrounding the component so that: holes. Refer to EIA-556. a) the component does not protrude beyond either surface of the carrier tape; 4. If P = 2.0mm, the tape may not properly index in all tape feeders. b) the component can be removed from the cavity in a vertical direction without 1 mechanical restriction after the top cover tape has been removed; c) rotation of the component is limited to 20º maximum (see Sketches A & B); d) lateral movement of the component is restricted to 0.5mm maximum (see Sketch C). Top View, Sketch "C" Component Lateral 0.50mm (0.020) Maximum 0.50mm (0.020) Maximum Bar Code Labeling Standard AVX bar code labeling is available and follows latest version of EIA-556 62 Bulk Case Packaging BENEFITS BULK FEEDER • Easier handling • Smaller packaging volume (1/20 of T/R packaging) • Easier inventory control Case • Flexibility Cassette • Recyclable Gate Shooter CASE DIMENSIONS Shutter Slider 12mm 36mm Mounter Head Expanded Drawing 110mm Chips Attachment Base CASE QUANTITIES Part Size 0402 0603 0805 1206 Qty. 10,000 (T=.023") 5,000 (T=.023") 80,000 15,000 (pcs / cassette) 8,000 (T=.031") 4,000 (T=.032") 6,000 (T=.043") 3,000 (T=.044") 63 Basic Capacitor Formulas I. Capacitance (farads) XI. Equivalent Series Resistance (ohms) .224 K A E.S.R. = (D.F.) (Xc) = (D.F.) / (2 π fC) English: C = T D XII. Power Loss (watts) .0884 K A 2 Metric: C = Power Loss = (2 π fCV ) (D.F.) T D XIII. KVA (Kilowatts) II. Energy stored in capacitors (Joules, watt - sec) 2 -3 KVA = 2 π fCV x 10 1 2 E = ⁄2 CV XIV. Temperature Characteristic (ppm/°C) III. Linear charge of a capacitor (Amperes) Ct – C 6 25 dV T.C. = x 10 I = C C25 (T – 25) t dt XV. Cap Drift (%) IV. Total Impedance of a capacitor (ohms) C – C 1 2 2 2 � C.D. = x 100 Z = R + (X - X ) S C L C 1 V. Capacitive Reactance (ohms) XVI. Reliability of Ceramic Capacitors 1 x = L V XT Y c 0 t t = 2 π fC ()( ) L V T t o o VI. Inductive Reactance (ohms) XVII. Capacitors in Series (current the same) x = 2 π fL L Any Number: 1 1 1 1 = + --- VII. Phase Angles: C C C C 1 2 T N Ideal Capacitors: Current leads voltage 90° C C 1 2 Two: C = Ideal Inductors: Current lags voltage 90° T C + C 1 2 Ideal Resistors: Current in phase with voltage XVIII. Capacitors in Parallel (voltage the same) VIII. Dissipation Factor (%) C = C + C --- + C 1 2 T N E.S.R. D.F.= tan � (loss angle) = = (2 πfC) (E.S.R.) X XIX. Aging Rate c IX. Power Factor (%) A.R. = % C/decade of time D P.F. = Sine � (loss angle) = Cos (phase angle) f XX. Decibels P.F. = (when less than 10%) = DF V 1 db = 20 log X. Quality Factor (dimensionless) V 2 1 Q = Cotan � (loss angle) = D.F. METRIC PREFIXES SYMBOLS -12 K = Dielectric Constant f = frequency L = Test life Pico X 10 t -9 Nano X 10 A = Area L = Inductance V = Test voltage -6 t Micro X 10 -3 Milli X 10 T = Dielectric thickness � = Loss angle V = Operating voltage o D -1 Deci X 10 +1 Deca X 10 V = Voltage = Phase angle T = Test temperature t f +3 Kilo X 10 +6 Mega X 10 t = time X & Y = exponent effect of voltage and temp. T = Operating temperature o +9 Giga X 10 +12 R = Series Resistance L = Operating life Tera X 10 s o 64 General Description Basic Construction – A multilayer ceramic (MLC) capaci- structure requires a considerable amount of sophistication, tor is a monolithic block of ceramic containing two sets of both in material and manufacture, to produce it in the quality offset, interleaved planar electrodes that extend to two and quantities needed in today’s electronic equipment. opposite surfaces of the ceramic dielectric. This simple Electrode Ceramic Layer End Terminations Terminated Edge Terminated Edge Margin Electrodes Multilayer Ceramic Capacitor Figure 1 Formulations – Multilayer ceramic capacitors are available Class 2 – EIA Class 2 capacitors typically are based on the in both Class 1 and Class 2 formulations. Temperature chemistry of barium titanate and provide a wide range of compensating formulation are Class 1 and temperature capacitance values and temperature stability. The most stable and general application formulations are classified commonly used Class 2 dielectrics are X7R and Y5V. The as Class 2. X7R provides intermediate capacitance values which vary only ±15% over the temperature range of -55°C to 125°C. It finds applications where stability over a wide temperature Class 1 – Class 1 capacitors or temperature compensating range is required. capacitors are usually made from mixtures of titanates The Y5V provides the highest capacitance values and is where barium titanate is normally not a major part of the used in applications where limited temperature changes are mix. They have predictable temperature coefficients and expected. The capacitance value for Y5V can vary from in general, do not have an aging characteristic. Thus they 22% to -82% over the -30°C to 85°C temperature range. are the most stable capacitor available. The most popular Class 1 multilayer ceramic capacitors are C0G (NP0) All Class 2 capacitors vary in capacitance value under the temperature compensating capacitors (negative-positive influence of temperature, operating voltage (both AC and 0 ppm/°C). DC), and frequency. For additional information on perfor- mance changes with operating conditions, consult AVX’s software, SpiCap. 65 General Description Effects of Voltage – Variations in voltage have little effect Table 1: EIA and MIL Temperature Stable and General on Class 1 dielectric but does affect the capacitance and Application Codes dissipation factor of Class 2 dielectrics. The application of DC voltage reduces both the capacitance and dissipation EIA CODE factor while the application of an AC voltage within a Percent Capacity Change Over Temperature Range reasonable range tends to increase both capacitance and RS198 Temperature Range dissipation factor readings. If a high enough AC voltage is applied, eventually it will reduce capacitance just as a DC X7 -55°C to +125°C voltage will. Figure 2 shows the effects of AC voltage. X6 -55°C to +105°C X5 -55°C to +85°C Cap. Change vs. A.C. Volts Y5 -30°C to +85°C X7R Z5 +10°C to +85°C Code Percent Capacity Change 50 D ±3.3% 40 E ±4.7% F ±7.5% 30 P ±10% R ±15% 20 S ±22% 10 T +22%, -33% U +22%, - 56% 0 V +22%, -82% 12.5 25 37.5 50 EXAMPLE – A capacitor is desired with the capacitance value at 25°C Volts AC at 1.0 KHz to increase no more than 7.5% or decrease no more than 7.5% from -30°C to +85°C. EIA Code will be Y5F. Figure 2 Capacitor specifications specify the AC voltage at which to MIL CODE measure (normally 0.5 or 1 VAC) and application of the wrong voltage can cause spurious readings. Figure 3 gives Symbol Temperature Range the voltage coefficient of dissipation factor for various AC voltages at 1 kilohertz. Applications of different frequencies A -55°C to +85°C will affect the percentage changes versus voltages. B -55°C to +125°C C -55°C to +150°C D.F. vs. A.C. Measurement Volts Cap. Change Cap. Change X7R Symbol Zero Volts Rated Volts 10.0 Curve 1 - 100 VDC Rated Capacitor Curve 3 R +15%, -15% +15%, -40% 8.0 Curve 2 - 50 VDC Rated Capacitor S +22%, -22% +22%, -56% Curve 3 - 25 VDC Rated Capacitor W +22%, -56% +22%, -66% Curve 2 6.0 X +15%, -15% +15%, -25% Y +30%, -70% +30%, -80% 4.0 Z +20%, -20% +20%, -30% Curve 1 2.0 Temperature characteristic is specified by combining range and change symbols, for example BR or AW. Specification slash sheets 0 indicate the characteristic applicable to a given style of capacitor. .5 1.0 1.5 2.0 2.5 AC Measurement Volts at 1.0 KHz In specifying capacitance change with temperature for Class Figure 3 2 materials, EIA expresses the capacitance change over an operating temperature range by a 3 symbol code. The first Typical effect of the application of DC voltage is shown in symbol represents the cold temperature end of the temper- Figure 4. The voltage coefficient is more pronounced for ature range, the second represents the upper limit of the higher K dielectrics. These figures are shown for room tem- operating temperature range and the third symbol repre- perature conditions. The combination characteristic known sents the capacitance change allowed over the as voltage temperature limits which shows the effects of operating temperature range. Table 1 provides a detailed rated voltage over the operating temperature range is explanation of the EIA system. shown in Figure 5 for the military BX characteristic. 66 Dissipation Factor Percent Capacitance Change Percent General Description tends to de-age capacitors and is why re-reading of capaci- Typical Cap. Change vs. D.C. Volts tance after 12 or 24 hours is allowed in military specifica- X7R tions after dielectric strength tests have been performed. 2.5 Typical Curve of Aging Rate 0 X7R +1.5 -2.5 -5 0 -7.5 -1.5 -10 25% 50% 75% 100% -3.0 Percent Rated Volts Figure 4 -4.5 Typical Cap. Change vs. Temperature X7R -6.0 -7.5 +20 1 10 100 1000 10,000 100,000 Hours +10 0VDC Characteristic Max. Aging Rate %/Decade 0 None C0G (NP0) 2 X7R, X5R 7 -10 Y5V -20 Figure 6 -30 Effects of Frequency – Frequency affects capacitance -55 -35 -15 +5 +25 +45 +65 +85 +105 +125 and impedance characteristics of capacitors. This effect is much more pronounced in high dielectric constant ceramic Temperature Degrees Centigrade formulation than in low K formulations. AVX’s SpiCap soft- Figure 5 ware generates impedance, ESR, series inductance, series resonant frequency and capacitance all as functions of Effects of Time – Class 2 ceramic capacitors change frequency, temperature and DC bias for standard chip sizes capacitance and dissipation factor with time as well as tem- and styles. It is available free from AVX and can be down- perature, voltage and frequency. This change with time is loaded for free from AVX website: www.avx.com. known as aging. Aging is caused by a gradual re-alignment of the crystalline structure of the ceramic and produces an exponential loss in capacitance and decrease in dissipation factor versus time. A typical curve of aging rate for semi- stable ceramics is shown in Figure 6. If a Class 2 ceramic capacitor that has been sitting on the shelf for a period of time, is heated above its curie point, 1 (125°C for 4 hours or 150°C for ⁄2 hour will suffice) the part will de-age and return to its initial capacitance and dissi- pation factor readings. Because the capacitance changes rapidly, immediately after de-aging, the basic capacitance measurements are normally referred to a time period some- time after the de-aging process. Various manufacturers use different time bases but the most popular one is one day or twenty-four hours after “last heat.” Change in the aging curve can be caused by the application of voltage and other stresses. The possible changes in capacitance due to de-aging by heating the unit explain why capacitance changes are allowed after test, such as temperature cycling, moisture resistance, etc., in MIL specs. The application of high voltages such as dielectric withstanding voltages also 67 Capacitance Change Percent Capacitance Change Percent Capacitance Change Percent General Description Effects of Mechanical Stress – High “K” dielectric Energy Stored – The energy which can be stored in a ceramic capacitors exhibit some low level piezoelectric capacitor is given by the formula: reactions under mechanical stress. As a general statement, the piezoelectric output is higher, the higher the dielectric 2 1 E = ⁄2CV constant of the ceramic. It is desirable to investigate this effect before using high “K” dielectrics as coupling capaci- tors in extremely low level applications. E = energy in joules (watts-sec) V = applied voltage Reliability – Historically ceramic capacitors have been one C = capacitance in farads of the most reliable types of capacitors in use today. The approximate formula for the reliability of a ceramic Potential Change – A capacitor is a reactive component capacitor is: which reacts against a change in potential across it. This is shown by the equation for the linear charge of a capacitor: L V X T Y o t t = � � L V T t o o dV I = ideal C dt where L = operating life T = test temperature and o t where L = test life T = operating temperature t o I = Current V = test voltage in °C t C = Capacitance V = operating voltage X,Y = see text o dV/dt = Slope of voltage transition across capacitor Thus an infinite current would be required to instantly Historically for ceramic capacitors exponent X has been change the potential across a capacitor. The amount of considered as 3. The exponent Y for temperature effects current a capacitor can “sink” is determined by the above typically tends to run about 8. equation. Equivalent Circuit – A capacitor, as a practical device, A capacitor is a component which is capable of storing exhibits not only capacitance but also resistance and electrical energy. It consists of two conductive plates (elec- inductance. A simplified schematic for the equivalent circuit trodes) separated by insulating material which is called the is: dielectric. A typical formula for determining capacitance is: C = Capacitance L = Inductance R = Series Resistance R = Parallel Resistance .224 KA s p C = t R P C = capacitance (picofarads) K = dielectric constant (Vacuum = 1) A = area in square inches t = separation between the plates in inches L R S (thickness of dielectric) .224 = conversion constant C (.0884 for metric system in cm) Reactance – Since the insulation resistance (R ) is normal- p Capacitance – The standard unit of capacitance is the ly very high, the total impedance of a capacitor is: farad. A capacitor has a capacitance of 1 farad when 1 coulomb charges it to 1 volt. One farad is a very large unit 2 2 Z = R + (X - X ) -6 S C L and most capacitors have values in the micro (10 ), nano � where -9 -12 (10 ) or pico (10 ) farad level. Z = Total Impedance Dielectric Constant – In the formula for capacitance given R = Series Resistance s above the dielectric constant of a vacuum is arbitrarily cho- X = Capacitive Reactance = 1 C sen as the number 1. Dielectric constants of other materials 2 π fC are then compared to the dielectric constant of a vacuum. X = Inductive Reactance = 2 π fL L Dielectric Thickness – Capacitance is indirectly propor- The variation of a capacitor’s impedance with frequency tional to the separation between electrodes. Lower voltage determines its effectiveness in many applications. requirements mean thinner dielectrics and greater capaci- tance per volume. Phase Angle – Power Factor and Dissipation Factor are often confused since they are both measures of the loss in Area – Capacitance is directly proportional to the area of a capacitor under AC application and are often almost the electrodes. Since the other variables in the equation are identical in value. In a “perfect” capacitor the current in the usually set by the performance desired, area is the easiest capacitor will lead the voltage by 90°. parameter to modify to obtain a specific capacitance within a material group. 68 � � General Description di dt The seen in current microprocessors can be as high as I (Ideal) 0.3 A/ns, and up to 10A/ns. At 0.3 A/ns, 100pH of parasitic I (Actual) inductance can cause a voltage spike of 30mV. While this does not sound very drastic, with the Vcc for microproces- Loss sors decreasing at the current rate, this can be a fairly large Phase Angle � percentage. Angle Another important, often overlooked, reason for knowing the parasitic inductance is the calculation of the resonant f frequency. This can be important for high frequency, by- pass capacitors, as the resonant point will give the most V signal attenuation. The resonant frequency is calculated IR s from the simple equation: In practice the current leads the voltage by some other fres = 1 phase angle due to the series resistance R . The comple- S � 2� LC ment of this angle is called the loss angle and: Insulation Resistance – Insulation Resistance is the resistance measured across the terminals of a capacitor Power Factor (P.F.) = Cos or Sine � f and consists principally of the parallel resistance R P shown Dissipation Factor (D.F.) = tan � in the equivalent circuit. As capacitance values and hence the area of dielectric increases, the I.R. decreases and hence the product (C x IR or RC) is often specified in ohm for small values of � the tan and sine are essentially equal faradsor more commonly megohm-microfarads. Leakage which has led to the common interchangeability of the two current is determined by dividing the rated voltage by IR terms in the industry. (Ohm’s Law). Equivalent Series Resistance – The term E.S.R. or Dielectric Strength – Dielectric Strength is an expression Equivalent Series Resistance combines all losses both of the ability of a material to withstand an electrical stress. series and parallel in a capacitor at a given frequency so Although dielectric strength is ordinarily expressed in volts, it that the equivalent circuit is reduced to a simple R-C series is actually dependent on the thickness of the dielectric and connection. thus is also more generically a function of volts/mil. Dielectric Absorption – A capacitor does not discharge instantaneously upon application of a short circuit, but drains gradually after the capacitance proper has been dis- charged. It is common practice to measure the dielectric E.S.R. C absorption by determining the “reappearing voltage” which appears across a capacitor at some point in time after it has Dissipation Factor – The DF/PF of a capacitor tells what been fully discharged under short circuit conditions. percent of the apparent power input will turn to heat in the Corona – Corona is the ionization of air or other vapors capacitor. which causes them to conduct current. It is especially E.S.R. Dissipation Factor = = (2 π fC) (E.S.R.) prevalent in high voltage units but can occur with low voltages X C as well where high voltage gradients occur. The energy discharged degrades the performance of the capacitor and The watts loss are: can in time cause catastrophic failures. 2 Watts loss = (2 π fCV ) (D.F.) Very low values of dissipation factor are expressed as their reciprocal for convenience. These are called the “Q” or Quality factor of capacitors. Parasitic Inductance – The parasitic inductance of capac- itors is becoming more and more important in the decou- pling of today’s high speed digital systems. The relationship between the inductance and the ripple voltage induced on the DC voltage line can be seen from the simple inductance equation: di V = L dt 69 Surface Mounting Guide MLC Chip Capacitors REFLOW SOLDERING Case Size D1 D2 D3 D4 D5 D2 0402 1.70 (0.07) 0.60 (0.02) 0.50 (0.02) 0.60 (0.02) 0.50 (0.02) 0603 2.30 (0.09) 0.80 (0.03) 0.70 (0.03) 0.80 (0.03) 0.75 (0.03) 0805 3.00 (0.12) 1.00 (0.04) 1.00 (0.04) 1.00 (0.04) 1.25 (0.05) D1 D3 1206 4.00 (0.16) 1.00 (0.04) 2.00 (0.09) 1.00 (0.04) 1.60 (0.06) 1210 4.00 (0.16) 1.00 (0.04) 2.00 (0.09) 1.00 (0.04) 2.50 (0.10) D4 1808 5.60 (0.22) 1.00 (0.04) 3.60 (0.14) 1.00 (0.04) 2.00 (0.08) 1812 5.60 (0.22) 1.00 (0.04)) 3.60 (0.14) 1.00 (0.04) 3.00 (0.12) 1825 5.60 (0.22) 1.00 (0.04) 3.60 (0.14) 1.00 (0.04) 6.35 (0.25) D5 2220 6.60 (0.26) 1.00 (0.04) 4.60 (0.18) 1.00 (0.04) 5.00 (0.20) 2225 6.60 (0.26) 1.00 (0.04) 4.60 (0.18) 1.00 (0.04) 6.35 (0.25) Dimensions in millimeters (inches) Component Pad Design Component pads should be designed to achieve good • Pad width equal to component width. It is permissible to solder filets and minimize component movement during decrease this to as low as 85% of component width but it reflow soldering. Pad designs are given below for the most is not advisable to go below this. common sizes of multilayer ceramic capacitors for both • Pad overlap 0.5mm beneath component. wave and reflow soldering. The basis of these designs is: • Pad extension 0.5mm beyond components for reflow and 1.0mm for wave soldering. WAVE SOLDERING D2 Case Size D1 D2 D3 D4 D5 D1 D3 0603 3.10 (0.12) 1.20 (0.05) 0.70 (0.03) 1.20 (0.05) 0.75 (0.03) 0805 4.00 (0.15) 1.50 (0.06) 1.00 (0.04) 1.50 (0.06) 1.25 (0.05) D4 1206 5.00 (0.19) 1.50 (0.06) 2.00 (0.09) 1.50 (0.06) 1.60 (0.06) Dimensions in millimeters (inches) D5 Component Spacing Preheat & Soldering For wave soldering components, must be spaced sufficiently The rate of preheat should not exceed 4°C/second to far apart to avoid bridging or shadowing (inability of solder prevent thermal shock. A better maximum figure is about to penetrate properly into small spaces). This is less impor- 2°C/second. tant for reflow soldering but sufficient space must be For capacitors size 1206 and below, with a maximum allowed to enable rework should it be required. thickness of 1.25mm, it is generally permissible to allow a temperature differential from preheat to soldering of 150°C. In all other cases this differential should not exceed 100°C. For further specific application or process advice, please consult AVX. Cleaning ≥1.5mm (0.06) Care should be taken to ensure that the capacitors are thoroughly cleaned of flux residues especially the space ≥1mm (0.04) beneath the capacitor. Such residues may otherwise become conductive and effectively offer a low resistance bypass to the capacitor. ≥1mm (0.04) Ultrasonic cleaning is permissible, the recommended conditions being 8 Watts/litre at 20-45 kHz, with a process cycle of 2 minutes vapor rinse, 2 minutes immersion in the ultrasonic solvent bath and finally 2 minutes vapor rinse. 70 Surface Mounting Guide MLC Chip Capacitors Wave APPLICATION NOTES 300 Storage Preheat Natural Good solderability is maintained for at least twelve months, Cooling 250 provided the components are stored in their “as received” packaging at less than 40°C and 70% RH. 200 T Solderability 230°C Terminations to be well soldered after immersion in a 60/40 150 to 250°C tin/lead solder bath at 235 ± 5°C for 2 ± 1 seconds. 100 Leaching Terminations will resist leaching for at least the immersion 50 times and conditions shown below. Solder Solder Immersion Time 0 Termination Type Tin/Lead/Silver Temp. °C Seconds 1 to 2 min 3 sec. max Nickel Barrier 60/40/0 260 ± 5 30 ± 1 (Preheat chips before soldering) T/maximum 150°C Recommended Soldering Profiles Lead-Free Wave Soldering The recommended peak temperature for lead-free wave Reflow soldering is 250°C-260°C for 3-5 seconds. The other para- 300 meters of the profile remains the same as above. Natural Preheat Cooling The following should be noted by customers changing from 250 lead based systems to the new lead free pastes. a) The visual standards used for evaluation of solder joints 200 will need to be modified as lead free joints are not as bright as with tin-lead pastes and the fillet may not be as 220°C 150 to large. 250°C b) Resin color may darken slightly due to the increase in 100 temperature required for the new pastes. c) Lead-free solder pastes do not allow the same self align- 50 ment as lead containing systems. Standard mounting pads are acceptable, but machine set up may need to be 0 modified. 1min 1min 10 sec. max General (Minimize soldering time) Surface mounting chip multilayer ceramic capacitors are designed for soldering to printed circuit boards or other Lead-Free Reflow Profile substrates. The construction of the components is such that 300 they will withstand the time/temperature profiles used in both 250 wave and reflow soldering methods. 200 Handling 150 Chip multilayer ceramic capacitors should be handled with 100 care to avoid damage or contamination from perspiration 50 and skin oils. The use of tweezers or vacuum pick ups 0 0 50 100 150 200 250 300 is strongly recommended for individual components. Bulk handling should ensure that abrasion and mechanical shock Time (s)  Pre-heating: 150°C ±15°C / 60-90s  Max. Peak Gradient 2.5°C/s are minimized. Taped and reeled components provides the  Peak Temperature: 245°C ±5°C ideal medium for direct presentation to the placement  Time at >230°C: 40s Max. machine. Any mechanical shock should be minimized during handling chip multilayer ceramic capacitors. Preheat It is important to avoid the possibility of thermal shock during soldering and carefully controlled preheat is therefore required. The rate of preheat should not exceed 4°C/second 71 Temperature °C Solder Temp. Solder Temp. Surface Mounting Guide MLC Chip Capacitors and a target figure 2°C/second is recommended. Although POST SOLDER HANDLING an 80°C to 120°C temperature differential is preferred, Once SMP components are soldered to the board, any recent developments allow a temperature differential bending or flexure of the PCB applies stresses to the sol- between the component surface and the soldering temper- dered joints of the components. For leaded devices, the ature of 150°C (Maximum) for capacitors of 1210 size and stresses are absorbed by the compliancy of the metal leads below with a maximum thickness of 1.25mm. The user is and generally don’t result in problems unless the stress is cautioned that the risk of thermal shock increases as chip large enough to fracture the soldered connection. size or temperature differential increases. Ceramic capacitors are more susceptible to such stress Soldering because they don’t have compliant leads and are brittle in Mildly activated rosin fluxes are preferred. The minimum nature. The most frequent failure mode is low DC resistance amount of solder to give a good joint should be used. or short circuit. The second failure mode is significant loss Excessive solder can lead to damage from the stresses of capacitance due to severing of contact between sets of caused by the difference in coefficients of expansion the internal electrodes. between solder, chip and substrate. AVX terminations are Cracks caused by mechanical flexure are very easily identi- suitable for all wave and reflow soldering systems. If hand fied and generally take one of the following two general soldering cannot be avoided, the preferred technique is the forms: utilization of hot air soldering tools. Cooling Natural cooling in air is preferred, as this minimizes stresses within the soldered joint. When forced air cooling is used, cooling rate should not exceed 4°C/second. Quenching is not recommended but if used, maximum temperature differentials should be observed according to the preheat conditions above. Cleaning Type A: Flux residues may be hygroscopic or acidic and must be Angled crack between bottom of device to top of solder joint. removed. AVX MLC capacitors are acceptable for use with all of the solvents described in the specifications MIL-STD- 202 and EIA-RS-198. Alcohol based solvents are acceptable and properly controlled water cleaning systems are also acceptable. Many other solvents have been proven successful, and most solvents that are acceptable to other components on circuit assemblies are equally acceptable for use with ceramic capacitors. Type B: Fracture from top of device to bottom of device. Mechanical cracks are often hidden underneath the termi- nation and are difficult to see externally. However, if one end termination falls off during the removal process from PCB, this is one indication that the cause of failure was excessive mechanical stress due to board warping. 72 Surface Mounting Guide MLC Chip Capacitors COMMON CAUSES OF REWORKING OF MLCs MECHANICAL CRACKING Thermal shock is common in MLCs that are manually attached or reworked with a soldering iron. AVX strongly The most common source for mechanical stress is board recommends that any reworking of MLCs be done with hot depanelization equipment, such as manual breakapart, v- air reflow rather than soldering irons. It is practically impossi- cutters and shear presses. Improperly aligned or dull cutters ble to cause any thermal shock in ceramic capacitors when may cause torqueing of the PCB resulting in flex stresses using hot air reflow. being transmitted to components near the board edge. However direct contact by the soldering iron tip often caus- Another common source of flexural stress is contact during es thermal cracks that may fail at a later date. If rework by parametric testing when test points are probed. If the PCB soldering iron is absolutely necessary, it is recommended is allowed to flex during the test cycle, nearby ceramic that the wattage of the iron be less than 30 watts and the capacitors may be broken. tip temperature be <300ºC. Rework should be performed A third common source is board to board connections at by applying the solder iron tip to the pad and not directly vertical connectors where cables or other PCBs are con- contacting any part of the ceramic capacitor. nected to the PCB. If the board is not supported during the plug/unplug cycle, it may flex and cause damage to nearby components. Special care should also be taken when handling large (>6" on a side) PCBs since they more easily flex or warp than smaller boards. Solder Tip Solder Tip Preferred Method - No Direct Part Contact Poor Method - Direct Contact with Part PCB BOARD DESIGN To avoid many of the handling problems, AVX recommends that MLCs be located at least .2" away from nearest edge of board. However when this is not possible, AVX recommends that the panel be routed along the cut line, adjacent to where the MLC is located. No Stress Relief for MLCs Routed Cut Line Relieves Stress on MLC 73