C0G (NP0) Dielectric General Specifications C0G (NP0) is the most popular formulation of the “tempera- ture-compensating,” EIA Class I ceramic materials. Modern C0G (NP0) formulations contain neodymium, samarium and other rare earth oxides. C0G (NP0) ceramics offer one of the most stable capacitor dielectrics available. Capacitance change with temperature is 0 ±30ppm/°C which is less than ±0.3% ∆ C from -55°C to +125°C. Capacitance drift or hysteresis for C0G (NP0) ceramics is negligible at less than ±0.05% versus up to ±2% for films. Typical capacitance change with life is less than ±0.1% for C0G (NP0), one-fifth that shown by most other dielectrics. C0G (NP0) formulations show no aging characteristics. The C0G (NP0) formulation usually has a “Q” in excess of 1000 and shows little capacitance or “Q” changes with frequency. Their dielectric absorption is typically less than 0.6% which is similar to mica and most films. PART NUMBER (see page 2 for complete part number explanation) 0805 A 101 J A T 2 A 5 Size Dielectric Capacitance Capacitance Failure Terminations Packaging Special Voltage (L" x W") C0G (NP0) = A Code (In pF) Tolerance Rate 2 = 7" Reel Code 6.3V = 6 T = Plated Ni A = Not 4 = 13" Reel A = Std. 10V = Z 2 Sig. Digits + B= ±.10 pF (<10pF) and Sn Applicable 7 = Bulk Cass. Product 16V = Y Number of 7 = Gold Plated C= ±.25 pF (<10pF) 9 = Bulk 25V = 3 Zeros D= ±.50 pF (<10pF) 50V = 5 Contact F= ±1% (≥ 25 pF) 100V = 1 Contact Factory For 200V = 2 Factory G= ±2% (≥ 13 pF) 1 = Pd/Ag Term For J= ±5% Multiples K= ±10% Temperature Coefficient � Capacitance vs. Frequency Insulation Resistance vs Temperature 10,000 +2 Typical Capacitance Change Envelope: 0 ± 30 ppm/°C +1 1,000 +0.5 0 0 -1 100 -0.5 -2 0 1KHz -55 -35 -15 +5 +25 +45 +65 +85 +105 +125 10 KHz 100 KHz 1 MHz 10 MHz 0 20 40 60 80 100 Frequency Temperature °C Temperature °C Variation of Impedance with Cap Value Variation of Impedance with Ceramic Formulation Variation of Impedance with Chip Size Impedance vs. Frequency Impedance vs. Frequency Impedance vs. Frequency 0805 - C0G (NP0) 1000 pF - C0G (NP0) 1000 pF - C0G (NP0) vs X7R 10 pF vs. 100 pF vs. 1000 pF 0805 100,000 10 10.00 1206 X7R 10,000 0805 NPO 1812 1210 1,000 1.00 1.0 100 0.10 10 pF 10.0 0.1 1.0 100 1000 100 pF 10 0.01 10 100 1000 1000 pF Frequency, MHz 0.1 1 10 100 1000 Frequency, MHz Frequency, MHz 4 % � Capacitance Impedance, � % � Capacitance Impedance, � Insulation Resistance (Ohm-Farads) Impedance, � C0G (NP0) Dielectric Specifications and Test Methods Parameter/Test NP0 Specification Limits Measuring Conditions Operating Temperature Range -55ºC to +125ºC Temperature Cycle Chamber Capacitance Within specified tolerance Freq.: 1.0 MHz ± 10% for cap ≤ 1000 pF <30 pF: Q≥ 400+20 x Cap Value 1.0 kHz ± 10% for cap > 1000 pF Q ≥30 pF: Q≥ 1000 Voltage: 1.0Vrms ± .2V 100,000MΩ or 1000MΩ - µF, Charge device with rated voltage for Insulation Resistance whichever is less 60 ± 5 secs @ room temp/humidity Charge device with 300% of rated voltage for Dielectric Strength No breakdown or visual defects 1-5 seconds, w/charge and discharge current limited to 50 mA (max) Appearance No defects Deflection: 2mm Capacitance Test Time: 30 seconds ±5% or ±.5 pF, whichever is greater Resistance to Variation 1mm/sec Flexure QMeets Initial Values (As Above) Stresses Insulation ≥ Initial Value x 0.3 90 mm Resistance ≥ 95% of each terminal should be covered Dip device in eutectic solder at 230 ± 5ºC Solderability with fresh solder for 5.0 ± 0.5 seconds Appearance No defects, <25% leaching of either end terminal Capacitance ≤ ±2.5% or ±.25 pF, whichever is greater Variation Dip device in eutectic solder at 260ºC for 60 Resistance to seconds. Store at room temperature for 24 ± 2 QMeets Initial Values (As Above) hours before measuring electrical properties. Solder Heat Insulation Meets Initial Values (As Above) Resistance Dielectric Meets Initial Values (As Above) Strength Appearance No visual defects Step 1: -55ºC ± 2º 30 ± 3 minutes Capacitance ≤ ±2.5% or ±.25 pF, whichever is greater Step 2: Room Temp ≤ 3 minutes Variation Thermal QMeets Initial Values (As Above) Step 3: +125ºC ± 2º 30 ± 3 minutes Shock Insulation Meets Initial Values (As Above) Step 4: Room Temp ≤ 3 minutes Resistance Dielectric Repeat for 5 cycles and measure after Meets Initial Values (As Above) Strength 24 hours at room temperature Appearance No visual defects Capacitance ≤ ±3.0% or ± .3 pF, whichever is greater Variation Charge device with twice rated voltage in ≥ 30 pF: Q≥ 350 test chamber set at 125ºC ± 2ºC Q Load Life ≥10 pF, <30 pF: Q≥ 275 +5C/2 for 1000 hours (+48, -0). (C=Nominal Cap) <10 pF: Q≥ 200 +10C Insulation Remove from test chamber and stabilize at ≥ Initial Value x 0.3 (See Above) Resistance room temperature for 24 hours Dielectric before measuring. Meets Initial Values (As Above) Strength Appearance No visual defects Capacitance ≤ ±5.0% or ± .5 pF, whichever is greater Variation Store in a test chamber set at 85ºC ± 2ºC/ ≥ 30 pF: Q≥ 350 85% ± 5% relative humidity for 1000 hours Load Q ≥10 pF, <30 pF: Q≥ 275 +5C/2 (+48, -0) with rated voltage applied. Humidity <10 pF: Q≥ 200 +10C Insulation Remove from chamber and stabilize at ≥ Initial Value x 0.3 (See Above) Resistance room temperature for 24 ± 2 hours Dielectric before measuring. Meets Initial Values (As Above) Strength 5 � � � C0G (NP0) Dielectric Capacitance Range PREFERRED SIZES ARE SHADED SIZE 0201 0402 0603 0805 1206 Soldering Reflow Only Reflow Only Reflow/Wave Reflow/Wave Reflow/Wave Packaging All Paper All Paper All Paper Paper/Embossed Paper/Embossed MM 0.60 ± 0.03 1.00 ± 0.10 1.60 ± 0.15 2.01 ± 0.20 3.20 ± 0.20 L) Length (in.) (0.024 ± 0.001) (0.040 ± 0.004) (0.063 ± 0.006) (0.079 ± 0.008) (0.126 ± 0.008) MM 0.30 ± 0.03 0.50 ± 0.10 0.81 ± 0.15 1.25 ± 0.20 1.60 ± 0.20 (W) Width (in.) (0.011 ± 0.001) (0.020 ± 0.004) (0.032 ± 0.006) (0.049 ± 0.008) (0.063 ± 0.008) MM 0.15 ± 0.05 0.25 ± 0.15 0.35 ± 0.15 0.50 ± 0.25 0.50 ± 0.25 (t) Terminal (in.) (0.006 ± 0.002) (0.010 ± 0.006) (0.014 ± 0.006) (0.020 ± 0.010) (0.020 ± 0.010) WVDC 10 16 25 16 25 50 6.3 25 50 100 16 25 50 100 200 16 25 50 100 200 Cap 0.5 A A A C C C G G G G E E E E J J J J J J (pF) 1.0 A A A C C C G G G G E E E E J J J J J J 1.2 A A A C C C G G G G E E E E J J J J J J 1.5 A A A C C C G G G G E E E E J J J J J J 1.8 A A A C C C G G G G E E E E J J J J J J 2.2 A A A C C C G G G G E E E E J J J J J J 2.7 A A A C C C G G G G E E E E J J J J J J 3.3 A A A C C C G G G G E E E E J J J J J J 3.9 A A A C C C G G G G E E E E J J J J J J 4.7 A A A C C C G G G G E E E E J J J J J J 5.6 A A A C C C G G G G E E E E J J J J J J 6.8 A A A C C C G G G G E E E E J J J J J J 8.2 A A A C C C G G G G E E E E J J J J J J 10 A A A C C C G G G G E E E E J J J J J J 12 A A A C C C G G G G E E E E J J J J J J 15 A A A C C C G G G G E E E E J J J J J J 18 A A A C C C G G G G E E E E J J J J J J 22 A A A C C C G G G G E E E E J J J J J J 27 A A A C C C G G G G E E E E J J J J J J 33 A A A C C C G G G G E E E E J J J J J J 39 A A C C C G G G G E E E E J J J J J J 47 A A C C C G G G G E E E E J J J J J J 56 A A C C C G G G G E E E E J J J J J J 68 A A C C C G G G G E E E E J J J J J J 82 A C C C G G G G E E E E J J J J J J 100 A C C C G G G G E E E E J J J J J J 120 C C C G G G G E E E E J J J J J J 150 C C C G G G G E E E E J J J J J J 180 C C C G G G G E E E E J J J J J J 220 C C C G G G G E E E E J J J J J J 270 C C G G G G E E E J M J J J J J 330 C C G G G G E E E J M J J J J J 390 G G G J J J J M J J J J J 470 G G G J J J J M J J J J J 560 G G G J J J J J J J J J 680 G G G J J J J J J J J J 820 G G G J J J J J J J J M 1000 G G G J J J J J J J J Q 1200 G G J J J J J J J Q 1500 G G J J J J J J M Q 1800 JJ J J J M M 2200 JJ M J J M P 2700 JJ M J J M P 3300 NN M J J M P 3900 NN M J J M P 4700 NN J J M P 5600 NN J J M 6800 NMM W 8200 L NMM Cap 0.010 NMM T � (µF) 0.012 MM 0.015 MM 0.018 0.022 t 0.027 0.033 0.039 0.047 0.068 0.082 0.1 WVDC 10 16 25 16 25 50 6.3 25 50 100 16 25 50 100 200 16 25 50 100 200 SIZE 0201 0402 0603 0805 1206 Letter A C E G J K M N P Q X Y Z BB CC Max. 0.33 0.56 0.71 0.86 0.94 1.02 1.27 1.40 1.52 1.78 2.29 2.54 2.79 3.05 3.175 Thickness (0.013) (0.022) (0.028) (0.034) (0.037) (0.040) (0.050) (0.055) (0.060) (0.070) (0.090) (0.100) (0.110) (0.120) (0.125) PAPER EMBOSSED Contact Factory for Multiples 6 � � � � � � � C0G (NP0) Dielectric Capacitance Range PREFERRED SIZES ARE SHADED SIZE 1210 1812 1825 2220 2225 Soldering Reflow/Wave Reflow Only Reflow Only Reflow Only Reflow Only Packaging Paper/Embossed All Embossed All Embossed All Embossed All Embossed MM 3.20 ± 0.20 4.50 ± 0.30 4.50 ± 0.30 5.70 ± 0.40 5.72 ± 0.25 (L) Length (in.) (0.126 ± 0.008) (0.177 ± 0.012) (0.177 ± 0.012) (0.224 ± 0.016) (0.225 ± 0.010) MM 2.50 ± 0.20 3.20 ± 0.20 6.40 ± 0.40 5.00 ± 0.40 6.35 ± 0.25 (W) Width (in.) (0.098 ± 0.008) (0.126 ± 0.008) (0.252 ± 0.016) (0.197 ± 0.016) (0.250 ± 0.010) MM 0.50 ± 0.25 0.61 ± 0.36 0.61 ± 0.36 0.64 ± 0.39 0.64 ± 0.39 (t) Terminal (in.) (0.020 ± 0.010) (0.024 ± 0.014) (0.024 ± 0.014) (0.025 ± 0.015) (0.025 ± 0.015) WVDC 25 50 100 200 25` 50 100 200 50 100 200 50 100 200 50 100 200 Cap 0.5 (pF) 1.0 1.2 1.5 1.8 2.2 W L 2.7 3.3 T � 3.9 4.7 5.6 6.8 t 8.2 10 12 15 18 22 27 33 39 47 56 68 82 100 120 150 180 220 270 330 390 470 560 J J J J 680 J J J J 820 J J J J 1000 J J J J K K K K M M M X X X P P P 1200 J J J M K K K K M M M X X X P P P 1500 J J J M K K K K M M M X X X P P P 1800 J J J M K K K K M M M X X X P P P 2200 J J M Q K K K K M M M X X X P P P 2700 J J M Q K K K P M M M X X X P P P 3300 J J M K K K P M M M X X X P P P 3900 J J M K K K P M M M X X X P P P 4700 J J M K K K P M M M X X X P P P 5600 J J M K M M P M M M X X X P P P 6800 J J M K M M X M M M X X X P P P 8200 J J K P X X M M X X X P P P Cap 0.010 N N K P X X M M X X X P P P (µF) 0.012 N N K P X M M X X X P P P 0.015 M P X P M X X X P P Y 0.018 M P P M X X X P P Y 0.022 M CC P X X P Y Y 0.027 M CC P X X P Y Y 0.033 M CC P X X P Y Y 0.039 M CC P P Y Y 0.047 CC CC P P 0.068 CC CC P 0.082 CC CC P 0.1 CC CC P WVDC 25 50 100 200 25 50 100 200 50 100 200 50 100 200 50 100 200 SIZE 1210 1812 1825 2220 2225 Letter A C E G J K M N P Q X Y Z BB CC Max. 0.33 0.56 0.71 0.86 0.94 1.02 1.27 1.40 1.52 1.78 2.29 2.54 2.79 3.05 3.175 Thickness (0.013) (0.022) (0.028) (0.034) (0.037) (0.040) (0.050) (0.055) (0.060) (0.070) (0.090) (0.100) (0.110) (0.120) (0.125) PAPER EMBOSSED Contact Factory for Multiples 7 � � � � High Voltage Chips For 500V to 5000V Applications High value, low leakage and small size are difficult parameters to obtain in capacitors for high voltage systems. AVX special high voltage MLC chips capacitors meet these performance characteristics and are designed for applications such as snubbers in high frequency power converters, resonators in SMPS, and high voltage coupling/DC blocking. These high voltage chip designs exhibit low ESRs at high frequencies. Larger physical sizes than normally encountered chips are used to make high voltage chips. These larger sizes require that special pre- cautions be taken in applying these chips in surface mount assem- blies. This is due to differences in the coefficient of thermal expansion (CTE) between the substrate materials and chip capacitors. Apply heat at less than 4°C per second during the preheat. Maximum preheat temperature must be within 50°C of the soldering temperature. The solder temperature should not exceed 230°C. Chips 1808 and larger to use reflow soldering only. Capacitors with X7R Dielectrics are not intended for AC line filtering applications. Contact plant for recommendations. Capacitors may require protective surface coating to prevent external arcing. PART NUMBER (see page 2 for complete information and options) 1808 A A 271 K A 1 1A AVX Voltage Temperature Capacitance Capacitance Failure Termination Packaging/Marking Style 7 = 500V Coefficient Code Tolerance Rate 1= Pd/Ag 1A = 7" Reel (2 significant digits 1206 C = 600V A = C0G C0G: J = ±5% A=Not T = Plated Ni Unmarked + no. of zeros) 1210 A = 1000V C = X7R K = ±10% Applicable and Solder 3A = 13" Reel Examples: 1808 S = 1500V M = ±20% Unmarked 10 pF = 100 1812 G = 2000V X7R: K = ±10% 9A = Bulk/Unmarked 100 pF = 101 1825 W = 2500V M = ±20% 1,000 pF = 102 2220 H = 3000V Z = +80%, 22,000 pF = 223 2225 J = 4000V -20% 220,000 pF = 224 3640 K = 5000V 1 µF = 105 W L T t DIMENSIONS millimeters (inches) SIZE 1206 1210 1808* 1812* 1825* 2220* 2225* 3640* (L) Length 3.20 ± 0.2 3.20 ± 0.2 4.57 ± 0.25 4.50 ± 0.3 4.50 ± 0.3 5.7 ± 0.4 5.72 ± 0.25 9.14 ± 0.25 (0.126 ± 0.008) (0.126 ± 0.008) (0.180 ± 0.010) (0.177 ± 0.012) (0.177 ± 0.012) (0.224 ± 0.016) (0.225 ± 0.010) (0.360 ± 0.010) (W) Width 1.60 ± 0.2 2.50 ± 0.2 2.03 ± 0.25 3.20 ± 0.2 6.40 ± 0.3 5.0 ± 0.4 6.35 ± 0.25 10.2 ± 0.25 (0.063 ± 0.008) (0.098 ± 0.008) (0.080 ± 0.010) (0.126 ± 0.008) (0.252 ± 0.012) (0.197 ± 0.016) (0.250 ± 0.010) (0.400 ± 0.010) (T) Thickness 1.52 1.70 2.03 2.54 2.54 3.3 2.54 2.54 Max. (0.060) (0.067) (0.080) (0.100) (0.100) (0.130) (0.100) (0.100) (t) terminal min. 0.25 (0.010) 0.25 (0.010) 0.25 (0.010) 0.25 (0.010) 0.25 (0.010) 0.25 (0.010) 0.25 (0.010) 0.76 (0.030) max. 0.75 (0.030) 0.75 (0.030) 1.02 (0.040) 1.02 (0.040) 1.02 (0.040) 1.02 (0.040) 1.02 (0.040) 1.52 (0.060) *Reflow Soldering Only 39 High Voltage Chips For 500V to 5000V Applications C0G Dielectric PERFORMANCE CHARACTERISTICS Capacitance Range 10 pF to 0.047 µF (25°C, 1.0 ±0.2 Vrms at 1kHz, for ≤ 1000 pF use 1 MHz) Capacitance Tolerances ±5%, ±10%, ±20% Dissipation Factor 0.1% max. (+25°C, 1.0 ±0.2 Vrms, 1kHz, for ≤ 1000 pF use 1 MHz) Operating Temperature Range -55°C to +125°C Temperature Characteristic 0 ±30 ppm/°C (0 VDC) Voltage Ratings 500, 600, 1000, 1500, 2000, 2500, 3000, 4000 & 5000 VDC (+125°C) Insulation Resistance (+25°C, at 500 VDC) 100K MΩ min. or 1000 MΩ - µF min., whichever is less Insulation Resistance (+125°C, at 500 VDC) 10K MΩ min. or 100 MΩ - µF min., whichever is less Dielectric Strength 500V, 150% rated voltage for 5 seconds at 50 mA max. current ≥ 600V, 120% rated voltage for 5 seconds at 50 mA max. current HIGH VOLTAGE C0G CAPACITANCE VALUES VOLTAGE 1206 1210 1808 1812 1825 2220 2225 3640 min. — — — — — — — — 500 max. 680 pF 1500 pF 3300 pF 5600 pF 0.012 µF — 0.018 µF — min. 100 pF 100 pF 100 pF 100 pF 1000 pF 1000 pF 1000 pF 1000 pF 600 max. 680 pF 1500 pF 2700 pF 5600 pF 0.012 µF 0.012 µF 0.015 µF 0.047 µF min. 10 pF 100 pF 100 pF 100 pF 100 pF 1000 pF 1000 pF 1000 pF 1000 max. 470 pF 820 pF 1500 pF 2700 pF 6800 pF 0.010 µF 0.010 µF 0.018 µF min. 10 pF 100 pF 10 pF 10 pF 100 pF 1000 pF 1000 pF 100 pF 1500 max. 150 pF 330 pF 470 pF 1000 pF 2700 pF 2700 pF 3300 pF 8200 pF min. 10 pF 10 pF 10 pF 10 pF 100 pF 1000 pF 1000 pF 100 pF 2000 max. 68 pF 150 pF 270 pF 680 pF 1800 pF 2200 pF 2200 pF 5600 pF min. — — 10 pF 10 pF 10 pF 100 pF 100 pF 100 pF 2500 max. — — 150 pF 390 pF 1000 pF 1000 pF 1200 pF 3900 pF min. — — 10 pF 10 pF 10 pF 10 pF 10 pF 100 pF 3000 max. — — 100 pF 330 pF 680 pF 680 pF 820 pF 2200 pF min. — — 10 pF 10 pF 10 pF 10 pF 10 pF 100 pF 4000 max. — — 39 pF 100 pF 220 pF 220 pF 330 pF 1000 pF min. — — — — — — — 10 pF 5000 max. — — — — — — — 680 pF X7R Dielectric PERFORMANCE CHARACTERISTICS Capacitance Range 10 pF to 0.56 µF (25°C, 1.0 ±0.2 Vrms at 1kHz) Capacitance Tolerances ±10%; ±20%; +80%, -20% Dissipation Factor 2.5% max. (+25°C, 1.0 ±0.2 Vrms, 1kHz) Operating Temperature Range -55°C to +125°C Temperature Characteristic ±15% (0 VDC) Voltage Ratings 500,600, 1000, 1500, 2000, 2500, 3000, 4000 & 5000 VDC (+125°C) Insulation Resistance (+25°C, at 500 VDC) 100K MΩ min. or 1000 MΩ - µF min., whichever is less Insulation Resistance (+125°C, at 500 VDC) 10K MΩ min. or 100 MΩ - µF min., whichever is less Dielectric Strength 500V, 150% rated voltage for 5 seconds at 50 mA max. current ≥ 600V, 120% rated voltage for 5 seconds at 50 mA max. current HIGH VOLTAGE X7R MAXIMUM CAPACITANCE VALUES VOLTAGE 1206 1210 1808 1812 1825 2220 2225 3640 min. — — — — — — — — 500 max. 0.010 µF 0.027 µF — 0.056 µF — — — — min. 1000 pF 1000 pF .01 µF .01 µF .01 µF .01 µF .01 µF .01 µF 600 max. 0.015 µF 0.027 µF 0.033 µF 0.068 µF 0.15 µF 0.15 µF 0.22 µF 0.56 µF min. 1000 pF 1000 pF 1000 pF 1000 pF 1000 pF .01 µF .01 µF .01 µF 1000 max. 4700 pF 0.010 µF 0.015 µF 0.027 µF 0.068 µF 0.068 µF 0.082 µF 0.22 µF min. 100 pF 100 pF 100 pF 100 pF 1000 pF 1000 pF 1000 pF .01 µF 1500 max. 1200 pF 2700 pF 3900 pF 8200 pF 0.018 µF 0.022 µF 0.027 µF 0.068 µF min. 10 pF 100 pF 100 pF 100 pF 100 pF 1000 pF 1000 pF 1000 pF 2000 max. 470 pF 1000 pF 1800 pF 4700 pF 8200 pF 0.010 µF 0.012 µF 0.027 µF min. — — 10 pF 10 pF 100 pF 1000 pF 1000 pF 1000 pF 2500 max. — — 1200 pF 2200 pF 5600 pF 6800 pF 8200 pF 0.022 µF min. — — 10 pF 10 pF 100 pF 1000 pF 1000 pF 1000 pF 3000 max. — — 560 pF 1200 pF 2700 pF 3300pF 4700 pF 0.018 µF min. — — — — — — — 100 pF 4000 max. — — — — — — — 6800 pF min. — — — — — — — 100 pF 5000 max. — — — — 3300 pF —— — 40 Packaging of Chip Components Automatic Insertion Packaging TAPE & REEL QUANTITIES All tape and reel specifications are in compliance with RS481. 8mm 12mm Paper or Embossed Carrier 0612, 0508, 0805, 1206, 1210 Embossed Only 1812, 1825 0306 1808 2220, 2225 Paper Only 0201, 0402, 0603 Qty. per Reel/7" Reel 2,000, 3,000 or 4,000, 10,000, 15,000 3,000 500, 1,000 Contact factory for exact quantity Contact factory for exact quantity Qty. per Reel/13" Reel 5,000, 10,000, 50,000 10,000 4,000 Contact factory for exact quantity REEL DIMENSIONS Tape A B* D* N W 2 C W W (1) 1 3 Size Max. Min. Min. Min. Max. 7.90 Min. +1.5 14.4 (0.311) 8.40 -0.0 8mm +0.059 (0.567) 10.9 Max. (0.331 -0.0 ) +0.50 (0.429) 330 1.5 13.0 -0.20 20.2 50.0 +0.020 (12.992) (0.059) (0.512 -0.008 ) (0.795) (1.969) 11.9 Min. +2.0 18.4 (0.469) 12.4 -0.0 12mm +0.079 (0.724) 15.4 Max. (0.488 -0.0 ) (0.607) Metric dimensions will govern. English measurements rounded and for reference only. (1) For tape sizes 16mm and 24mm (used with chip size 3640) consult EIA RS-481 latest revision. 47 Embossed Carrier Configuration 8 & 12mm Tape Only 10 PITCHES CUMULATIVE TOLERANCE ON TAPE P 0 ±0.2mm (±0.008) T 2 EMBOSSMENT D P 0 2 T DEFORMATION BETWEEN E 1 EMBOSSMENTS A 0 W F E2 TOP COVER B 1 TAPE B0 K 0 P1 T 1 D FOR COMPONENTS CENTER LINES 1 S 1 MAX. CAVITY 2.00 mm x 1.20 mm AND OF CAVITY SIZE - SEE NOTE 1 LARGER (0.079 x 0.047) B IS FOR TAPE READER REFERENCE ONLY 1 INCLUDING DRAFT CONCENTRIC AROUND B User Direction of Feed 0 8 & 12mm Embossed Tape Metric Dimensions Will Govern CONSTANT DIMENSIONS Tape Size D EP P S Min. T Max. T 0 0 2 1 1 +0.10 8mm 1.50 -0.0 1.75 ± 0.10 4.0 ± 0.10 2.0 ± 0.05 0.60 0.60 0.10 +0.004 (0.059 -0.0 ) (0.069 ± 0.004) (0.157 ± 0.004) (0.079 ± 0.002) (0.024) (0.024) (0.004) and Max. 12mm VARIABLE DIMENSIONS Tape Size B D E FP RT WA B K 1 1 2 1 2 0 0 0 Max. Min. Min. Min. Max. See Note 5 See Note 2 4.35 1.00 6.25 3.50 ± 0.05 4.00 ± 0.10 25.0 2.50 Max. 8.30 8mm See Note 1 (0.171) (0.039) (0.246) (0.138 ± 0.002) (0.157 ± 0.004) (0.984) (0.098) (0.327) 8.20 1.50 10.25 5.50 ± 0.05 4.00 ± 0.10 30.0 6.50 Max. 12.3 12mm See Note 1 (0.323) (0.059) (0.404) (0.217 ± 0.002) (0.157 ± 0.004) (1.181) (0.256) (0.484) 8mm 4.35 1.00 6.25 3.50 ± 0.05 2.00 ± 0.10 25.0 2.50 Max. 8.30 See Note 1 1/2 Pitch (0.171) (0.039) (0.246) (0.138 ± 0.002) (0.079 ± 0.004) (0.984) (0.098) (0.327) 12mm 8.20 1.50 10.25 5.50 ± 0.05 8.00 ± 0.10 30.0 6.50 Max. 12.3 See Note 1 Double (0.323) (0.059) (0.404) (0.217 ± 0.002) (0.315 ± 0.004) (1.181) (0.256) (0.484) Pitch NOTES: 2. Tape with or without components shall pass around radius “R” without damage. 1. The cavity defined by A , B , and K shall be configured to provide the following: 0 0 0 3. Bar code labeling (if required) shall be on the side of the reel opposite the round sprocket holes. Surround the component with sufficient clearance such that: Refer to EIA-556. a) the component does not protrude beyond the sealing plane of the cover tape. 4. B dimension is a reference dimension for tape feeder clearance only. 1 b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the cover tape has been removed. 5. If P = 2.0mm, the tape may not properly index in all tape feeders. 1 c) rotation of the component is limited to 20º maximum (see Sketches D & E). d) lateral movement of the component is restricted to 0.5mm maximum (see Sketch F). Top View, Sketch "F" Component Lateral Movements 0.50mm (0.020) Maximum 0.50mm (0.020) Maximum 48 Paper Carrier Configuration 8 & 12mm Tape Only 10 PITCHES CUMULATIVE P TOLERANCE ON TAPE 0 ±0.20mm (±0.008) D P 0 2 T E 1 BOTTOM TOP COVER COVER F W TAPE TAPE E 2 B 0 G T 1 A P 0 1 CAVITY SIZE T1 CENTER LINES SEE NOTE 1 User Direction of Feed OF CAVITY 8 & 12mm Paper Tape Metric Dimensions Will Govern CONSTANT DIMENSIONS Tape Size D EP P T G. Min. R Min. 0 0 2 1 +0.10 8mm 1.50 -0.0 1.75 ± 0.10 4.00 ± 0.10 2.00 ± 0.05 0.10 0.75 25.0 (0.984) +0.004 (0.059 -0.0 ) (0.069 ± 0.004) (0.157 ± 0.004) (0.079 ± 0.002) (0.004) (0.030) See Note 2 and Max. Min. Min. 12mm VARIABLE DIMENSIONS P1 Tape Size E Min. F W A B T 2 0 0 See Note 4 +0.30 8mm 4.00 ± 0.10 6.25 3.50 ± 0.05 8.00 -0.10 See Note 1 +0.012 (0.157 ± 0.004) (0.246) (0.138 ± 0.002) (0.315 -0.004 ) 1.10mm (0.043) Max. for Paper Base 4.00 ± 0.010 10.25 5.50 ± 0.05 12.0 ± 0.30 12mm Tape and (0.157 ± 0.004) (0.404) (0.217 ± 0.002) (0.472 ± 0.012) +0.30 1.60mm 8mm 2.00 ± 0.05 6.25 3.50 ± 0.05 8.00 -0.10 +0.012 (0.063) Max. 1/2 Pitch (0.079 ± 0.002) (0.246) (0.138 ± 0.002) (0.315 -0.004 ) for Non-Paper Base Compositions 12mm 8.00 ± 0.10 10.25 5.50 ± 0.05 12.0 ± 0.30 Double (0.315 ± 0.004) (0.404) (0.217 ± 0.002) (0.472 ± 0.012) Pitch NOTES: 2. Tape with or without components shall pass around radius “R” without damage. 1. The cavity defined by A , B , and T shall be configured to provide sufficient clearance 0 0 3. Bar code labeling (if required) shall be on the side of the reel opposite the sprocket surrounding the component so that: holes. Refer to EIA-556. a) the component does not protrude beyond either surface of the carrier tape; 4. If P = 2.0mm, the tape may not properly index in all tape feeders. b) the component can be removed from the cavity in a vertical direction without 1 mechanical restriction after the top cover tape has been removed; c) rotation of the component is limited to 20º maximum (see Sketches A & B); d) lateral movement of the component is restricted to 0.5mm maximum (see Sketch C). Top View, Sketch "C" Component Lateral 0.50mm (0.020) Maximum 0.50mm (0.020) Maximum Bar Code Labeling Standard AVX bar code labeling is available and follows latest version of EIA-556 49 Bulk Case Packaging BENEFITS BULK FEEDER • Easier handling • Smaller packaging volume (1/20 of T/R packaging) • Easier inventory control Case • Flexibility Cassette • Recyclable Gate Shooter CASE DIMENSIONS Shutter Slider 12mm 36mm Mounter Head Expanded Drawing 110mm Chips Attachment Base CASE QUANTITIES Part Size 0402 0603 0805 1206 Qty. 10,000 (T=.023") 5,000 (T=.023") 80,000 15,000 (pcs / cassette) 8,000 (T=.031") 4,000 (T=.032") 6,000 (T=.043") 3,000 (T=.044") 50 Basic Capacitor Formulas I. Capacitance (farads) XI. Equivalent Series Resistance (ohms) .224 K A E.S.R. = (D.F.) (Xc) = (D.F.) / (2 π fC) English: C = T D XII. Power Loss (watts) .0884 K A 2 Metric: C = Power Loss = (2 π fCV ) (D.F.) T D XIII. KVA (Kilowatts) II. Energy stored in capacitors (Joules, watt - sec) 2 -3 KVA = 2 π fCV x 10 1 2 E = ⁄2 CV XIV. Temperature Characteristic (ppm/°C) III. Linear charge of a capacitor (Amperes) Ct – C 6 25 dV T.C. = x 10 I = C C25 (T – 25) t dt XV. Cap Drift (%) IV. Total Impedance of a capacitor (ohms) C – C 1 2 2 2 � C.D. = x 100 Z = R + (X - X ) S C L C 1 V. Capacitive Reactance (ohms) XVI. Reliability of Ceramic Capacitors 1 x = L V XT Y c 0 t t = 2 π fC ()( ) L V T t o o VI. Inductive Reactance (ohms) XVII. Capacitors in Series (current the same) x = 2 π fL L Any Number: 1 1 1 1 = + --- VII. Phase Angles: C C C C 1 2 T N Ideal Capacitors: Current leads voltage 90° C C 1 2 Two: C = Ideal Inductors: Current lags voltage 90° T C + C 1 2 Ideal Resistors: Current in phase with voltage XVIII. Capacitors in Parallel (voltage the same) VIII. Dissipation Factor (%) C = C + C --- + C 1 2 T N E.S.R. D.F.= tan � (loss angle) = = (2 πfC) (E.S.R.) X XIX. Aging Rate c IX. Power Factor (%) A.R. = % C/decade of time D P.F. = Sine � (loss angle) = Cos (phase angle) f XX. Decibels P.F. = (when less than 10%) = DF V 1 db = 20 log X. Quality Factor (dimensionless) V 2 1 Q = Cotan � (loss angle) = D.F. METRIC PREFIXES SYMBOLS -12 K= Dielectric Constant f = frequency L = Test life Pico X 10 t -9 Nano X 10 A= Area L = Inductance V = Test voltage -6 t Micro X 10 -3 Milli X 10 T = Dielectric thickness � = Loss angle V = Operating voltage o D -1 Deci X 10 +1 Deca X 10 V= Voltage = Phase angle T = Test temperature t f +3 Kilo X 10 +6 Mega X 10 t= time X & Y = exponent effect of voltage and temp. T = Operating temperature o +9 Giga X 10 +12 R = Series Resistance L = Operating life Tera X 10 s o 51 General Description Basic Construction – A multilayer ceramic (MLC) capaci- structure requires a considerable amount of sophistication, tor is a monolithic block of ceramic containing two sets of both in material and manufacture, to produce it in the quality offset, interleaved planar electrodes that extend to two and quantities needed in today’s electronic equipment. opposite surfaces of the ceramic dielectric. This simple Electrode Ceramic Layer End Terminations Terminated Edge Terminated Edge Margin Electrodes Multilayer Ceramic Capacitor Figure 1 Formulations – Multilayer ceramic capacitors are available Class 2 – EIA Class 2 capacitors typically are based on the in both Class 1 and Class 2 formulations. Temperature chemistry of barium titanate and provide a wide range of compensating formulation are Class 1 and temperature capacitance values and temperature stability. The most stable and general application formulations are classified commonly used Class 2 dielectrics are X7R and Y5V. The as Class 2. X7R provides intermediate capacitance values which vary only ±15% over the temperature range of -55°C to 125°C. It finds applications where stability over a wide temperature Class 1 – Class 1 capacitors or temperature compensating range is required. capacitors are usually made from mixtures of titanates The Y5V provides the highest capacitance values and is where barium titanate is normally not a major part of the used in applications where limited temperature changes are mix. They have predictable temperature coefficients and expected. The capacitance value for Y5V can vary from in general, do not have an aging characteristic. Thus they 22% to -82% over the -30°C to 85°C temperature range. are the most stable capacitor available. The most popular The Z5U dielectric is between X7R and Y5V in both stability Class 1 multilayer ceramic capacitors are C0G (NP0) and capacitance range. temperature compensating capacitors (negative-positive 0 ppm/°C). All Class 2 capacitors vary in capacitance value under the influence of temperature, operating voltage (both AC and DC), and frequency. For additional information on perfor- mance changes with operating conditions, consult AVX’s software, SpiCap. 52 General Description Effects of Voltage – Variations in voltage have little effect Table 1: EIA and MIL Temperature Stable and General on Class 1 dielectric but does affect the capacitance and Application Codes dissipation factor of Class 2 dielectrics. The application of DC voltage reduces both the capacitance and dissipation EIA CODE factor while the application of an AC voltage within a Percent Capacity Change Over Temperature Range reasonable range tends to increase both capacitance and RS198 Temperature Range dissipation factor readings. If a high enough AC voltage is applied, eventually it will reduce capacitance just as a DC X7 -55°C to +125°C voltage will. Figure 2 shows the effects of AC voltage. X5 -55°C to +85°C Y5 -30°C to +85°C Cap. Change vs. A.C. Volts Z5 +10°C to +85°C X7R Code Percent Capacity Change 50 D±3.3% E±4.7% 40 F±7.5% P±10% 30 R±15% S±22% 20 T +22%, -33% 10 U +22%, - 56% V +22%, -82% 0 EXAMPLE – A capacitor is desired with the capacitance value at 25°C 12.5 25 37.5 50 to increase no more than 7.5% or decrease no more than 7.5% from Volts AC at 1.0 KHz -30°C to +85°C. EIA Code will be Y5F. Figure 2 MIL CODE Capacitor specifications specify the AC voltage at which to measure (normally 0.5 or 1 VAC) and application of the wrong voltage can cause spurious readings. Figure 3 gives Symbol Temperature Range the voltage coefficient of dissipation factor for various AC A -55°C to +85°C voltages at 1 kilohertz. Applications of different frequencies B -55°C to +125°C will affect the percentage changes versus voltages. C -55°C to +150°C D.F. vs. A.C. Measurement Volts Cap. Change Cap. Change Symbol X7R Zero Volts Rated Volts 10.0 R +15%, -15% +15%, -40% Curve 1 - 100 VDC Rated Capacitor Curve 3 W +22%, -56% +22%, -66% 8.0 Curve 2 - 50 VDC Rated Capacitor X +15%, -15% +15%, -25% Curve 3 - 25 VDC Rated Capacitor Curve 2 Y +30%, -70% +30%, -80% 6.0 Z +20%, -20% +20%, -30% 4.0 Temperature characteristic is specified by combining range and change symbols, for example BR or AW. Specification slash sheets Curve 1 2.0 indicate the characteristic applicable to a given style of capacitor. 0 .5 1.0 1.5 2.0 2.5 In specifying capacitance change with temperature for Class AC Measurement Volts at 1.0 KHz 2 materials, EIA expresses the capacitance change over an operating temperature range by a 3 symbol code. The first Figure 3 symbol represents the cold temperature end of the temper- Typical effect of the application of DC voltage is shown in ature range, the second represents the upper limit of the Figure 4. The voltage coefficient is more pronounced for operating temperature range and the third symbol repre- higher K dielectrics. These figures are shown for room tem- sents the capacitance change allowed over the perature conditions. The combination characteristic known operating temperature range. Table 1 provides a detailed as voltage temperature limits which shows the effects of explanation of the EIA system. rated voltage over the operating temperature range is shown in Figure 5 for the military BX characteristic. 53 Dissipation Factor Percent Capacitance Change Percent General Description tends to de-age capacitors and is why re-reading of capaci- Typical Cap. Change vs. D.C. Volts tance after 12 or 24 hours is allowed in military specifica- X7R tions after dielectric strength tests have been performed. 2.5 Typical Curve of Aging Rate 0 X7R +1.5 -2.5 -5 0 -7.5 -1.5 -10 25% 50% 75% 100% Percent Rated Volts -3.0 Figure 4 -4.5 Typical Cap. Change vs. Temperature X7R -6.0 +20 -7.5 1 10 100 1000 10,000 100,000 Hours +10 0VDC Characteristic Max. Aging Rate %/Decade 0 None C0G (NP0) 2 X7R, X5R 7 -10 Y5V -20 Figure 6 -30 Effects of Frequency – Frequency affects capacitance -55 -35 -15 +5 +25 +45 +65 +85 +105 +125 and impedance characteristics of capacitors. This effect is much more pronounced in high dielectric constant ceramic Temperature Degrees Centigrade formulation that is low K formulations. AVX’s SpiCap soft- Figure 5 ware generates impedance, ESR, series inductance, series resonant frequency and capacitance all as functions of Effects of Time – Class 2 ceramic capacitors change frequency, temperature and DC bias for standard chip sizes capacitance and dissipation factor with time as well as tem- and styles. It is available free from AVX and can be down- perature, voltage and frequency. This change with time is loaded for free from AVX website: www.avxcorp.com. known as aging. Aging is caused by a gradual re-alignment of the crystalline structure of the ceramic and produces an exponential loss in capacitance and decrease in dissipation factor versus time. A typical curve of aging rate for semi- stable ceramics is shown in Figure 6. If a Class 2 ceramic capacitor that has been sitting on the shelf for a period of time, is heated above its curie point, 1 (125°C for 4 hours or 150°C for ⁄2 hour will suffice) the part will de-age and return to its initial capacitance and dissi- pation factor readings. Because the capacitance changes rapidly, immediately after de-aging, the basic capacitance measurements are normally referred to a time period some- time after the de-aging process. Various manufacturers use different time bases but the most popular one is one day or twenty-four hours after “last heat.” Change in the aging curve can be caused by the application of voltage and other stresses. The possible changes in capacitance due to de-aging by heating the unit explain why capacitance changes are allowed after test, such as temperature cycling, moisture resistance, etc., in MIL specs. The application of high voltages such as dielectric withstanding voltages also 54 Capacitance Change Percent Capacitance Change Percent Capacitance Change Percent General Description Effects of Mechanical Stress – High “K” dielectric Energy Stored – The energy which can be stored in a ceramic capacitors exhibit some low level piezoelectric capacitor is given by the formula: reactions under mechanical stress. As a general statement, the piezoelectric output is higher, the higher the dielectric 2 1 E = ⁄2CV constant of the ceramic. It is desirable to investigate this effect before using high “K” dielectrics as coupling capaci- tors in extremely low level applications. E = energy in joules (watts-sec) V = applied voltage Reliability – Historically ceramic capacitors have been one C = capacitance in farads of the most reliable types of capacitors in use today. The approximate formula for the reliability of a ceramic Potential Change – A capacitor is a reactive component capacitor is: which reacts against a change in potential across it. This is shown by the equation for the linear charge of a capacitor: L V X T Y o t t = � � L V T t o o dV I = ideal C dt where L = operating life T = test temperature and o t where L = test life T = operating temperature t o I = Current V = test voltage in °C t C = Capacitance V = operating voltage X,Y = see text o dV/dt = Slope of voltage transition across capacitor Thus an infinite current would be required to instantly Historically for ceramic capacitors exponent X has been change the potential across a capacitor. The amount of considered as 3. The exponent Y for temperature effects current a capacitor can “sink” is determined by the above typically tends to run about 8. equation. Equivalent Circuit – A capacitor, as a practical device, A capacitor is a component which is capable of storing exhibits not only capacitance but also resistance and electrical energy. It consists of two conductive plates (elec- inductance. A simplified schematic for the equivalent circuit trodes) separated by insulating material which is called the is: dielectric. A typical formula for determining capacitance is: C = Capacitance L = Inductance R = Series Resistance R = Parallel Resistance .224 KA s p C = t R P C = capacitance (picofarads) K = dielectric constant (Vacuum = 1) A = area in square inches t = separation between the plates in inches L R S (thickness of dielectric) .224 = conversion constant C (.0884 for metric system in cm) Reactance – Since the insulation resistance (R ) is normal- p Capacitance – The standard unit of capacitance is the ly very high, the total impedance of a capacitor is: farad. A capacitor has a capacitance of 1 farad when 1 coulomb charges it to 1 volt. One farad is a very large unit 2 2 Z = R + (X - X ) -6 S C L and most capacitors have values in the micro (10 ), nano � where -9 -12 (10 ) or pico (10 ) farad level. Z = Total Impedance Dielectric Constant – In the formula for capacitance given R = Series Resistance s above the dielectric constant of a vacuum is arbitrarily cho- X = Capacitive Reactance = 1 C sen as the number 1. Dielectric constants of other materials 2 π fC are then compared to the dielectric constant of a vacuum. X = Inductive Reactance = 2 π fL L Dielectric Thickness – Capacitance is indirectly propor- The variation of a capacitor’s impedance with frequency tional to the separation between electrodes. Lower voltage determines its effectiveness in many applications. requirements mean thinner dielectrics and greater capaci- tance per volume. Phase Angle – Power Factor and Dissipation Factor are often confused since they are both measures of the loss in Area – Capacitance is directly proportional to the area of a capacitor under AC application and are often almost the electrodes. Since the other variables in the equation are identical in value. In a “perfect” capacitor the current in the usually set by the performance desired, area is the easiest capacitor will lead the voltage by 90°. parameter to modify to obtain a specific capacitance within a material group. 55 � � General Description di dt The seen in current microprocessors can be as high as I (Ideal) 0.3 A/ns, and up to 10A/ns. At 0.3 A/ns, 100pH of parasitic I (Actual) inductance can cause a voltage spike of 30mV. While this does not sound very drastic, with the Vcc for microproces- Loss sors decreasing at the current rate, this can be a fairly large Phase Angle � percentage. Angle Another important, often overlooked, reason for knowing the parasitic inductance is the calculation of the resonant f frequency. This can be important for high frequency, by- pass capacitors, as the resonant point will give the most V signal attenuation. The resonant frequency is calculated IR s from the simple equation: In practice the current leads the voltage by some other fres = 1 phase angle due to the series resistance R . The comple- S � 2� LC ment of this angle is called the loss angle and: Insulation Resistance – Insulation Resistance is the resistance measured across the terminals of a capacitor Power Factor (P.F.) = Cos or Sine � f and consists principally of the parallel resistance R P shown Dissipation Factor (D.F.) = tan � in the equivalent circuit. As capacitance values and hence the area of dielectric increases, the I.R. decreases and hence the product (C x IR or RC) is often specified in ohm for small values of � the tan and sine are essentially equal faradsor more commonly megohm-microfarads. Leakage which has led to the common interchangeability of the two current is determined by dividing the rated voltage by IR terms in the industry. (Ohm’s Law). Equivalent Series Resistance – The term E.S.R. or Dielectric Strength – Dielectric Strength is an expression Equivalent Series Resistance combines all losses both of the ability of a material to withstand an electrical stress. series and parallel in a capacitor at a given frequency so Although dielectric strength is ordinarily expressed in volts, it that the equivalent circuit is reduced to a simple R-C series is actually dependent on the thickness of the dielectric and connection. thus is also more generically a function of volts/mil. Dielectric Absorption – A capacitor does not discharge instantaneously upon application of a short circuit, but drains gradually after the capacitance proper has been dis- charged. It is common practice to measure the dielectric E.S.R. C absorption by determining the “reappearing voltage” which appears across a capacitor at some point in time after it has Dissipation Factor – The DF/PF of a capacitor tells what been fully discharged under short circuit conditions. percent of the apparent power input will turn to heat in the Corona – Corona is the ionization of air or other vapors capacitor. which causes them to conduct current. It is especially E.S.R. Dissipation Factor = = (2 π fC) (E.S.R.) prevalent in high voltage units but can occur with low voltages X C as well where high voltage gradients occur. The energy discharged degrades the performance of the capacitor and The watts loss are: can in time cause catastrophic failures. 2 Watts loss = (2 π fCV ) (D.F.) Very low values of dissipation factor are expressed as their reciprocal for convenience. These are called the “Q” or Quality factor of capacitors. Parasitic Inductance – The parasitic inductance of capac- itors is becoming more and more important in the decou- pling of today’s high speed digital systems. The relationship between the inductance and the ripple voltage induced on the DC voltage line can be seen from the simple inductance equation: di V = L dt 56 Surface Mounting Guide MLC Chip Capacitors REFLOW SOLDERING Case Size D1 D2 D3 D4 D5 D2 0402 1.70 (0.07) 0.60 (0.02) 0.50 (0.02) 0.60 (0.02) 0.50 (0.02) 0603 2.30 (0.09) 0.80 (0.03) 0.70 (0.03) 0.80 (0.03) 0.75 (0.03) 0805 3.00 (0.12) 1.00 (0.04) 1.00 (0.04) 1.00 (0.04) 1.25 (0.05) D1 D3 1206 4.00 (0.16) 1.00 (0.04) 2.00 (0.09) 1.00 (0.04) 1.60 (0.06) 1210 4.00 (0.16) 1.00 (0.04) 2.00 (0.09) 1.00 (0.04) 2.50 (0.10) D4 1808 5.60 (0.22) 1.00 (0.04) 3.60 (0.14) 1.00 (0.04) 2.00 (0.08) 1812 5.60 (0.22) 1.00 (0.04)) 3.60 (0.14) 1.00 (0.04) 3.00 (0.12) 1825 5.60 (0.22) 1.00 (0.04) 3.60 (0.14) 1.00 (0.04) 6.35 (0.25) D5 2220 6.60 (0.26) 1.00 (0.04) 4.60 (0.18) 1.00 (0.04) 5.00 (0.20) 2225 6.60 (0.26) 1.00 (0.04) 4.60 (0.18) 1.00 (0.04) 6.35 (0.25) Dimensions in millimeters (inches) Component Pad Design Component pads should be designed to achieve good • Pad width equal to component width. It is permissible to solder filets and minimize component movement during decrease this to as low as 85% of component width but it reflow soldering. Pad designs are given below for the most is not advisable to go below this. common sizes of multilayer ceramic capacitors for both • Pad overlap 0.5mm beneath component. wave and reflow soldering. The basis of these designs is: • Pad extension 0.5mm beyond components for reflow and 1.0mm for wave soldering. WAVE SOLDERING D2 Case Size D1 D2 D3 D4 D5 0603 3.10 (0.12) 1.20 (0.05) 0.70 (0.03) 1.20 (0.05) 0.75 (0.03) D1 D3 0805 4.00 (0.15) 1.50 (0.06) 1.00 (0.04) 1.50 (0.06) 1.25 (0.05) D4 1206 5.00 (0.19) 1.50 (0.06) 2.00 (0.09) 1.50 (0.06) 1.60 (0.06) 1210 5.00 (0.19) 1.50 (0.06) 2.00 (0.09) 1.50 (0.06) 2.50 (0.10) D5 Dimensions in millimeters (inches) Component Spacing Preheat & Soldering For wave soldering components, must be spaced sufficiently The rate of preheat should not exceed 4°C/second to far apart to avoid bridging or shadowing (inability of solder prevent thermal shock. A better maximum figure is about to penetrate properly into small spaces). This is less impor- 2°C/second. tant for reflow soldering but sufficient space must be For capacitors size 1206 and below, with a maximum allowed to enable rework should it be required. thickness of 1.25mm, it is generally permissible to allow a temperature differential from preheat to soldering of 150°C. In all other cases this differential should not exceed 100°C. For further specific application or process advice, please consult AVX. Cleaning ≥1.5mm (0.06) Care should be taken to ensure that the capacitors are thoroughly cleaned of flux residues especially the space ≥1mm (0.04) beneath the capacitor. Such residues may otherwise become conductive and effectively offer a low resistance bypass to the capacitor. ≥1mm (0.04) Ultrasonic cleaning is permissible, the recommended conditions being 8 Watts/litre at 20-45 kHz, with a process cycle of 2 minutes vapor rinse, 2 minutes immersion in the ultrasonic solvent bath and finally 2 minutes vapor rinse. 57 Surface Mounting Guide MLC Chip Capacitors General APPLICATION NOTES Surface mounting chip multilayer ceramic capacitors Storage are designed for soldering to printed circuit boards or other Good solderability is maintained for at least twelve months, substrates. The construction of the components is such that provided the components are stored in their “as received” they will withstand the time/temperature profiles used in both packaging at less than 40°C and 70% RH. wave and reflow soldering methods. Solderability Handling Terminations to be well soldered after immersion in a 60/40 Chip multilayer ceramic capacitors should be handled with tin/lead solder bath at 235 ± 5°C for 2 ± 1 seconds. care to avoid damage or contamination from perspiration and skin oils. The use of tweezers or vacuum pick ups Leaching is strongly recommended for individual components. Bulk Terminations will resist leaching for at least the immersion handling should ensure that abrasion and mechanical shock times and conditions shown below. are minimized. Taped and reeled components provides the ideal medium for direct presentation to the placement Solder Solder Immersion Time Termination Type machine. Any mechanical shock should be minimized during Tin/Lead/Silver Temp. °C Seconds handling chip multilayer ceramic capacitors. Nickel Barrier 60/40/0 260 ± 5 30 ± 1 Preheat It is important to avoid the possibility of thermal shock during Recommended Soldering Profiles soldering and carefully controlled preheat is therefore required. The rate of preheat should not exceed 4°C/second Reflow and a target figure 2°C/second is recommended. Although 300 an 80°C to 120°C temperature differential is preferred, Natural Preheat Cooling recent developments allow a temperature differential 250 between the component surface and the soldering temper- ature of 150°C (Maximum) for capacitors of 1210 size and 200 below with a maximum thickness of 1.25mm. The user is cautioned that the risk of thermal shock increases as chip 220°C size or temperature differential increases. 150 to 250°C Soldering 100 Mildly activated rosin fluxes are preferred. The minimum amount of solder to give a good joint should be used. 50 Excessive solder can lead to damage from the stresses caused by the difference in coefficients of expansion 0 between solder, chip and substrate. AVX terminations are 1min suitable for all wave and reflow soldering systems. If hand 1min 10 sec. max soldering cannot be avoided, the preferred technique is the (Minimize soldering time) utilization of hot air soldering tools. Wave Cooling Natural cooling in air is preferred, as this minimizes stresses 300 within the soldered joint. When forced air cooling is used, Preheat Natural cooling rate should not exceed 4°C/second. Quenching Cooling 250 is not recommended but if used, maximum temperature differentials should be observed according to the preheat 200 T conditions above. 230°C 150 Cleaning to 250°C Flux residues may be hygroscopic or acidic and must be removed. AVX MLC capacitors are acceptable for use with 100 all of the solvents described in the specifications MIL-STD- 202 and EIA-RS-198. Alcohol based solvents are acceptable 50 and properly controlled water cleaning systems are also acceptable. Many other solvents have been proven successful, 0 and most solvents that are acceptable to other components 1 to 2 min 3 sec. max on circuit assemblies are equally acceptable for use with ceramic capacitors. (Preheat chips before soldering) T/maximum 150°C 58 Solder Temp. Solder Temp. Surface Mounting Guide MLC Chip Capacitors POST SOLDER HANDLING COMMON CAUSES OF Once SMP components are soldered to the board, any MECHANICAL CRACKING bending or flexure of the PCB applies stresses to the sol- The most common source for mechanical stress is board dered joints of the components. For leaded devices, the depanelization equipment, such as manual breakapart, v- stresses are absorbed by the compliancy of the metal leads cutters and shear presses. Improperly aligned or dull cutters and generally don’t result in problems unless the stress is may cause torqueing of the PCB resulting in flex stresses large enough to fracture the soldered connection. being transmitted to components near the board edge. Ceramic capacitors are more susceptible to such stress Another common source of flexural stress is contact during because they don’t have compliant leads and are brittle in parametric testing when test points are probed. If the PCB nature. The most frequent failure mode is low DC resistance is allowed to flex during the test cycle, nearby ceramic or short circuit. The second failure mode is significant loss capacitors may be broken. of capacitance due to severing of contact between sets of A third common source is board to board connections at the internal electrodes. vertical connectors where cables or other PCBs are con- Cracks caused by mechanical flexure are very easily identi- nected to the PCB. If the board is not supported during the fied and generally take one of the following two general plug/unplug cycle, it may flex and cause damage to nearby forms: components. Special care should also be taken when handling large (>6" on a side) PCBs since they more easily flex or warp than smaller boards. REWORKING OF MLCs Thermal shock is common in MLCs that are manually attached or reworked with a soldering iron. AVX strongly recommends that any reworking of MLCs be done with hot Type A: air reflow rather than soldering irons. It is practically impossi- Angled crack between bottom of device to top of solder joint. ble to cause any thermal shock in ceramic capacitors when using hot air reflow. However direct contact by the soldering iron tip often caus- es thermal cracks that may fail at a later date. If rework by soldering iron is absolutely necessary, it is recommended that the wattage of the iron be less than 30 watts and the tip temperature be <300ºC. Rework should be performed by applying the solder iron tip to the pad and not directly contacting any part of the ceramic capacitor. Type B: Fracture from top of device to bottom of device. Mechanical cracks are often hidden underneath the termi- nation and are difficult to see externally. However, if one end termination falls off during the removal process from PCB, this is one indication that the cause of failure was excessive mechanical stress due to board warping. 59 Surface Mounting Guide MLC Chip Capacitors Solder Tip Solder Tip Preferred Method - No Direct Part Contact Poor Method - Direct Contact with Part PCB BOARD DESIGN To avoid many of the handling problems, AVX recommends that MLCs be located at least .2" away from nearest edge of board. However when this is not possible, AVX recommends that the panel be routed along the cut line, adjacent to where the MLC is located. No Stress Relief for MLCs Routed Cut Line Relieves Stress on MLC 60