Main Features • High Sensitivity Full Frame CCD Sensor • 2300 x 3500 Resolution with 10 µm Square Pixels • 100% Aperture Pixels • 12-bit Dynamic Range • Very Low Noise: 65 dB SNR • Binning and ROI Modes • LVDS or CameraLink Data Format (Base Configuration) • High Data Rate: 25 Mpixels/s • Flexible and Easy to Operate via RS-232 Control – Trigger Mode: Free Run or External Trigger Modes B & W 8 Megapixels – Binning 2 x 2 and 4 x 4, Up to 5 ROI LVDS and – Exposure Time ™ – Gain: -5 to 29 dB by Step of 0.04 dB CameraLink – Offset: 0 to 255 LSB – 3-Shot Color Operation Digital Cameras – Test Pattern Generation • Single Power Supply: 24V DC • High Reliability – CE and FCC Compliant CAMELIA M1 LV 8M • F (Nikon) Mount Adapter (Lens Not Supplied) CAMELIA M1 CL 8M Product Description Preliminary This camera is designed to meet high performance and quality requirements while providing ease of use. • Atmel manages the entire process, from the sensor to the camera. The result is a camera able to work in 12 bits, with dedicated electronics that provide excellent signal to noise ratio. • Because of the 100% aperture pixel the sensitivity of the camera is fairly high even in near infrared. • The programmable settings let the user work with different integration times, gains and offsets. The external trigger allows the user to synchronize the camera on an external event while the 3-shot color mode allows very high resolution for color image acquisition. Applications The performance and reliability of this camera make it well suited for the most demanding applications such as film and document scanning, semiconductor and PCB inspection, DNA analysis, metrology, X-ray imaging, etc... Rev. 5 53 31 19 9A– A–IIM MAG AGE– E–0 04 4//0 03 3 1 Improvements The Camelia 8M has been redesigned: • To add new features: – Gain: 928 steps from -5 to 29 dB – Offset: 0 to 255 LSB – Test pattern: ramps up from 0 to 2298 pixel values on each line – Median filter: to remove 1 x 1 and columns defects • To improve the electro-optical performances, in particular by: – Reducing power consumption from 8.5W down to 5.5W, using a new front panel and internal heat sink. This lowers the CCD temperature by 5°C thus decreasing the magnitude of “white pixels”. – Decreasing the typical temporal noise from 2.7 to 2.4 LSB • To interface with more standard and more cost effective cables • To improve reliability • Camelia M1 8M is CE and FCC compliant What changes for the user? • New additional commands for gain, offset and test pattern • RS-232 transmission speed increased from 9600 to 19200 bauds for LVDS cameras (9600 bauds for CameraLink cameras) • Interface connectors: – DATA & SYNC is a 3M MDR connector with better availability, the same pinout but different mechanic – RS-232 is a D-Sub 9 female for full-duplex transmission – The power supply connector has a camera standard pinout – TTL CONTROL is a new D-Sub 9 male connector avoiding the use of a Y cable • New rear panel (see position of connectors) 2 CAMELIA M1 8M LVDS and CameraLink Camera 5319A–IMAGE–04/03 CAMELIA M1 8M LVDS and CameraLink Camera Imaging System Description Figure 1. LVDS Camera Imaging System Figure 2. CameraLink Camera Imaging System 3 5319A–IMAGE–04/03 The Camelia camera is powered by a single +24V power supply. It is configurable via the serial port of the computer (by using either CommCam software or standard RS-232 communicator as TTY or Hyperterminal) for LSD cameras. Camelia is configurable via the serial communication of CameraLink for CameraLink cameras. It also sends digital video. As Camelia's CCD is a full frame sensor, the user must use either pulsed lighting or a chopper/shutter in front of the camera in order to have only incident lighting on the CCD during integration time. The user must design an electro-optical interface to drive the camera, the shutter/chopper or lighting by using the SHUTTER signal delivered by the camera. If required, the system can send an external trigger or external ITC (integration time control signal) to the camera. The BG38 Filter is essential to have a correct white balance on Color Cameras and for use with standard optics (for achromaticity purpose). Note that the following Elements are not provided by Atmel: • Shutter (LCD or Mechanical) • BG38 (Anti-infra Red) Filter • Control Box • Lens • Light Source • +24V Power Supply •Computer For a complete explanation of the utility of the BG38 Filter and the Shutter, please con- sult the associated FAQ and the sample images on the Atmel’s "Camera Documentation & Software" CD-Rom. 4 CAMELIA M1 8M LVDS and CameraLink Camera 5319A–IMAGE–04/03 CAMELIA M1 8M LVDS and CameraLink Camera CCD Description Image Format 35.0 mm (V) x 23.0 mm (H) Figure 3. Sensor Organization MPP Photosensitive Zone 2300 Columns - 100% aperture 16 Dark References - 10 µm square pixels 3500 Lines Output Register Note: The camera does not output to the 16 dark references. Active Pixels Table 1. Active Pixels Mode (set via serial com) Image Size (H x V) Timing Diagram Correspondence No binning 2300 x 3500 H = M 2 x 2 pixel binning 1150 x 1750 V = N 4 x 4 pixel binning 574 x 875 Readout Register The readout register is along the small side of the image area (vertical image). Pixel Geometry Pixels are 10 µm x 10 µm with an aperture ratio of 100%. Antiblooming by Antiblooming can be activated or inhibited (see “Serial Communication” on page 12): Clocking • Antiblooming OFF: antiblooming inhibited. This position is recommended if antiblooming is not required for the application. • Antiblooming ON: antiblooming activated. • When binning is disabled, the antiblooming is typically efficient up to 8 times saturation light. 5 5319A–IMAGE–04/03 Camera LSB (Least Significant Bit): 12-bit corresponds to 4095 LSB. Specifications Absolute Maximum Storage temperature: -20 to +70°C Operating temperature: 0 to +50°C Ratings Operating humidity (non condensing): < 80% at +35°C Vibration: 2 g sinusoidal, from 10 to 100 Hz Power supply: +20 to +28V Weight • Camera with F mount ring: 1400 g • Camera without F mount ring: 1200 g Electro-optical Conditions: Performance • Camera operating at ambient temperature: 20°C. • Camera operating in binning 1 x 1 mode, nominal gain 0 dB (G = 173) and no processing filter. Table 2. Electro-optical Performance Typical Parameter Symbol Value Unit (1) Full scale value VPE 4095 LSB (2)(3) Temporal noise VN 2.4 LSB (3)(4) Dark signal non-uniformity DSNU 2 LSB.s (5) Dynamic range DY 1700 64.6 dB (6) 2 Responsivity R 51.43 LSB/(nJ/cm ) (7) Resolution Horizontal Transfer function at Nyquist CTFh 20% – Vertical Contrast Transfer function at Nyquist CTFv 20% – (8) Antiblooming (over illumination capability) – 8x – Electrons to LSB conversion – 15 e-/LSB (9) Current consumption I 230 mA Notes: 1. Full scale value VPE: maximum digital video signal 2. Temporal noise VN: rms value in darkness; measured by subtracting 2 images, pixel to pixel, at 40 ms of integration time 3. This parameter depends on integration time and on the CCD temperature. Thermal noise doubles with every increase of 16°C temperature. Dark signal doubles with every increase of 8°C temperature. An internal clamp can correct the mean value of this phenomena. 4. Dark signal non-uniformity: rms value; excludes blemishes 5. Dynamic range DY = VPE/VN measured at 40 ms of integration time 6. Responsitivity conditions: 3200K, light source powered between 200 and 1100 nm, measured on the sensor 7. Resolution conditions: VIDEO = 2000 LSB and red light source used 8. Antiblooming ON and integration time = 100 ms 9. Measured at 24V 6 CAMELIA M1 8M LVDS and CameraLink Camera 5319A–IMAGE–04/03 CAMELIA M1 8M LVDS and CameraLink Camera Spectral Responsivity Figure 4. Spectral Responsivity 100 80 60 40 20 0 400 500 600 700 800 900 1000 1100 Wavelength (nm) 2 Note: nJ/cm measured on the sensor Image Grade • Defect Sizes Specification – Blemish: 1 x 1 defect – Cluster: blemish grouping of not more than a given number of adjacent defects: 1 x 1 < cluster 1 size ≤ 2 x 2 2 x 2 < cluster 2 size ≤ 5 x 5 – Column: one-pixel-wide column with more than 7 contiguous defective pixels – Defect separation: defects are separated by no less than D min pixels in any direction • Defects in Darkness – Blemish or cluster: pixel(s) whose signal deviate(s) more than 150 LSB – Column: column whose signal deviates more than 15 LSB • Defects under Illumination – Blemish or cluster: pixel(s) that deviate(s) by more than +20% or -30% from the average pixel – Column: column which deviates by more than 10% from the average column. Defect Test Conditions • Room temperature = 20°C • Integration time in darkness = 100 ms • Camera operating in binning 1 x 1 mode • Light source: Halogen 3200K with BG38 (2 mm thick) IR cut- off with f/11 aperture • Test under illumination at 50% saturation level • No software correction performed 7 5319A–IMAGE–04/03 2 Responsivity LSB/(nJ/cm ) Classifications Table 3. Image Grade Classifications Blemishes Cluster 1 Cluster 2 Column Grade Total D min Total D min Total D min Total D min E ≤ 500 3 ≤ 30 50 ≤ 6 100 ≤ 5 150 H ≤ 300 3 ≤ 10 50 0 – 0 – CCD Window • Thickness = 1.2 mm ± 0.05 Specification • Glass index at 588 nm: n = 1.5255 • Admitted defects rate: 0 inclusions > 10 µm • Transmittance > 98% in the range of 400-700 nm • Transmittance > 82% in the range of 700-1000 nm • Flatness of the CCD Window < 100 um (concave) • Flatness of the CCD chip must be within 30 µm 8 CAMELIA M1 8M LVDS and CameraLink Camera 5319A–IMAGE–04/03 CAMELIA M1 8M LVDS and CameraLink Camera Camera Features Regions Of Interest Caution: This function has been available since October 2001 starting with Camera S/N: 01321093. For older Cameras, these commands aren’t available and can corrupt (ROI ) the EEPROM (see “Camera Identification” on page 14). Camelia 8M can operate in multi ROI mode, allowing masking of regions of the image and thus increasing frame rate by a reduced readout time. The user defines up to 5 windows to be masked. In addition the starting and ending addresses for each window can be specified. Time reduction: about 92 µs per masked line. Two steps (under serial communication): • Enter the list of starting and ending addresses with the command: Y=ssss/eeee/ssss/eeee/…/eeee/ • Enter the number of regions masked with the command: F=X (X=0 to 5) The line addresses must be a multiple of 4 (to be compliant with the binning). Rules The Image starts at Line 0 and ends at Line 3499 and the smallest area consists of 4 lines. The commands must be send in the following order: “Y=…” then “F=…”. For FGT software users, the user has to resize the number of lines in the FGT settings. In order to mask 3 regions in the wafer image defined as follows: Example • The first 304 lines at the top of the image (blue background) • 748 lines in the center of the image (two center lines of the wafer) • The last 304 lines of the image (blue background): – "Y=0/304/1376/2124/3196/3499/" –"F=3" In this example readout time will be reduced by 1356 lines which are equivalent to 125 ms. Figure 5. Readout Time 9 5319A–IMAGE–04/03 Gain & Offset Video signal processing gain and offset can be adjusted by setting the Gain and the Offset via serial communication: • Gain adjusted from -5.1 to 28.9 dB: G = code 0 to 928 • Nominal gain (factory configuration) is 0 dB: G = code 173 • Offset adjusted from 0 to 255 LSB: O = code 0 to 255 • Gain is applied to the video signal before the addition of offset Antiblooming by Antiblooming can be activated or inhibited (set via serial communication): Clocking • Antiblooming OFF: this position is recommended if antiblooming is not required for the application. • Antiblooming ON: antiblooming is activated and is effective up to 8 times the saturation level of the sensor. Test Pattern In normal mode, the digital video signal from the CCD sensor is available at the LVDS output interface. For test purpose a fixed digital pattern is generated and can be available instead of the video signal at the LVDS output interface. The digital pattern is ramped up from 0 to 2298 LSB code (line width); each line pre- sents the same pattern: This is useful to validate the connection to the acquisition system before adjustment operations relative to image capture. Selection is set by the Test Pattern Generation command: • CCD sensor : M = 0 • Test Pattern : M = 1 Median Filter A median filter can be applied to sensor signals in order to remove 1 x 1 defect pixels or 1 pixel width columns avoiding subsequent software processing. This filter produces a smoothing effect on the image. • Median filter OFF: M = 0 • Median filter ON: M = 2 10 CAMELIA M1 8M LVDS and CameraLink Camera 5319A–IMAGE–04/03 CAMELIA M1 8M LVDS and CameraLink Camera 3-Shot Color Operation In 3-shot color mode, each image is made of 3 frames: red, green, blue + 1 optional additional frame (infra red for example): • The camera must be operated either in external trigger mode or in Integration Time Control (ITC) mode. • For each image, the user selects the color of the next frame by setting COLOUR_I1 and COLOUR_I2 input signals. COLOUR_I1, _I2 must be valid during both the TRIG signal’s rising edge (or ITC signal falling edge) and the SHUTTER signal’s falling edge (see Figure 6). • Color definition is: COLOUR_I2 COLOUR_I1 Frame Color 0 0 Red 0 1 Green 1 0 Blue 1 1 User defined i.e. Infra Red • Integration time can be adjusted differently for each color (set via serial communication). This provides better signal to noise ratio for the colour with the lowest sensitivity (i.e the blue). • Each frame requires a TRIG_ITC signal. • Camelia 8M camera synchronizes COLOUR_I1, _I2 with the rest of the timing and sends COLOUR_O1, _O2 to: – FGT frame grabber for LVDS cameras – CameraLink frame grabber as the 2 most significant bit of data PDATA(13,12) Figure 6. Color Timing Diagram Red Green Blue integration integration integration time time time TRIG COLOUR_I 00 01 10 > 0 > 0 > 0 > 0 > 0 > 0 SHUTTER FEN 00 01 10 COLOUR_O Frame 00 Frame 01 Frame 10 (red) (green) (blue) 11 5319A–IMAGE–04/03 Serial Communication Serial Configuration The camera configuration is set by an RS-232 or CameraLink serial interface. The RS-232 configuration is: • Full duplex/without handshaking (the camera is configured in DCE/Modem) • 19200 baud, 8-bit data, no parity bit, 1 stop bit The CameraLink configuration is: • 9600 baud, 8-bit data, no parity bit, 1 stop bit Serial Commands The following features are available: Table 4. Serial Commands Serial Function Serial Configuration Comment Command 3 modes: - continuous (free running) T=0 Timing mode - external trigger T=1 - external ITC T=2 3 modes: - no binning Image size: 2300 (H) x 3500 (V) B=0 Binning - 2 x 2 pixel binning Image size: 1150 (H) x 1750 (V) B=1 - 4 x 4 pixel binning Image size: 574 (H) x 875 (V) B=2 Range from: Steps of around 37 mdB (gain Gain - G = 5.1 dB G=0 curve is not fully linear) - G = 28.9 dB G=928 Range from: Offset - 0 LSB Steps of 1 LSB O=0 - 255 LSB O=255 3 modes: - inactive (always open) S=0 Shutter - active S=1 - inactive (always closed) S=2 4 positions: - 1 ms D=0 Shutter delay - 10 ms D=1 - 20 ms D=2 - 40 ms D=3 2 modes: Antiblooming - active A=0 control - inactive A=1 2 modes: Black & white or 3-shot color - black and white C=0 mode - 3-shot color C=1 12 CAMELIA M1 8M LVDS and CameraLink Camera 5319A–IMAGE–04/03 CAMELIA M1 8M LVDS and CameraLink Camera Table 4. Serial Commands (Continued) Serial Function Serial Configuration Comment Command Value: 1 to 2000 Black & white Must be an integer Ex: integration time Unit: ms Ex: 120 for 120 ms th or 4 color I=120 Active modes: Monochrome 120.4 not allowed integration time and 3-shot color Value: 1 to 2000 Must be an integer Ex: Red integration Unit: ms time Ex: 120 for 120 ms J=120 Active mode: 3-shot color Value: 1 to 2000 Must be an integer Ex: Green Unit: ms integration time Ex: 120 for 120 ms K=120 Active mode: 3-shot color Value: 1 to 2000 Must be an integer Ex: Blue integration Unit: ms time Ex: 120 for 120 ms L=120 Active mode: 3-shot color Ex: ROI: Number of 0 to 5 windows Windows F=2 Must be an integer divisible by 4 Ex: ROI: Windows Line start/Line Stop … Line Stop >3 Y=1824/2252/ Addresses 3156/3499/ First Line = 0; Last Line = 3499 Test pattern M=0: Sensor image M=0 generation M=1: Pattern image To check power, transmission... M=1 medial filter M=2: Sensor image filtered To remove 1 x 1 pixel defects M=2 processing Camera identification readout !=0 User camera identification !=1 readout Software version readout !=2 Special Camera configuration readout !=3 commands Current camera configuration !=4 record Default camera configuration !=5 restoration Writing and record of the user User camera ID $= String of Char $= camera identification Note: ROI commands have been available since October 2001 starting with Camera S/N: 01321093. For older Cameras, these commands aren’t available and can corrupt the EEPROM. If in doubt, please contact our hotline before using ROI function (See “Camera Identification” on page 14). 13 5319A–IMAGE–04/03 Command Syntax • Valid syntax is: S=n(CR) where: – S: command identification (S is a single character in upper case) – n: setting value – (CR): means "carriage return" (ASCII code = 13) – No spaces, nor tabs may be inserted between S, =, n and (CR) – For the Camelia 8M only, each address value is followed by “/”: Y=ssss/eeee/….eeee/ • Example of a valid command: I=500(CR) (sets the integration time to 500 ms) • Example of non valid commands: – I=500(CR): no space – i=500(CR): i instead of I – I=3000(CR): 3000 is out of range – Y=ssss/eeee/sssseeee/: a “/” is missing Settings Validation New settings are clocked and become valid for the camera at the end of the readout phase. This means that new settings written before the end of readout of image N will be used for image N+1. New settings written after the readout of image N and before the end of readout of image N+1 will be used for image N+2. Camera Identification A character string stored in the EEPROM contains the product model, its version and its serial number. Example: CAMEL_8M_01_9851002 stands for: CAMELIA 8M, version 01, serial number 9851002 It is read by sending: !=0(CR) The serial number is detailed as follows: Figure 7. Serial Number 98 51 002 Year Number in the week Week in the year Customer Identification Customer identification is a character string (25 characters max). • It is set and stored in the EEPROM by sending $=xx..xx • It is read by sending !=1(CR) Reading Firmware When receiving !=2(CR) the camera returns the version of the firmware. Version Reading Current Settings When receiving !=3(CR) the camera returns its current settings. 14 CAMELIA M1 8M LVDS and CameraLink Camera 5319A–IMAGE–04/03 CAMELIA M1 8M LVDS and CameraLink Camera Storing the Current When receiving !=4(CR) the camera stores the current configuration in the EEPROM. Configuration Factory Configuration When receiving !=5(CR), the camera sends back its factory configured settings: A=0(CR) C=0(CR) G=173(CR) O=16(CR) S=1(CR) B=0(CR) T=0(CR) I=0100(CR) J=0100(CR) K=0100(CR) L=0100(CR) D=2(CR) M=0(CR) F=0(CR) Y=(CR)(not set) >OK(CR) 15 5319A–IMAGE–04/03 Timing 2 x 2 and 4 x 4 pixel binning can be used to enable previewing modes. The preview mode is only available in black and white, otherwise the user has to use Overlay mode (correction and software LUT are not applicable on displayed images). Table 5. Timing Mode Mode Frame Readout Time Line Readout Time Max Frame Rate No binning B=0 370 ms 104 µs 2.67 f/s 2 x 2 pixel binning B=1 200 ms 114 µs 4.91 f/s 4 x 4 pixel binning B=2 110 ms 134 µs 8.82 f/s LVDS Camera Timing Three timing modes are available: continuous, external triggered and Integration Time Control (ITC). The signals in the following drawings are described in Table 6: Table 6. LVDS Frame Timing DATA & TTL Cam. SYNC CONTROL Signal Name Description In/Out Pins Pins LEN Line ENable Low state active when pixel Out 26/27 – is part of line FEN Frame Low state active when lines Out 3/4 – ENable are part of frame (1) (1) SHUTTER SHUTTER External shutter Trig output Out 21/22 1 sync Signal (high level active) (1) (1) TRIG TRIGger External Trigger Input In 46/47 2 Signal (Rising Edge) (1) (1) ITC Integration External ITC Input Signal In 46/47 2 Time Control (Falling/Rising Edges) PCK Pixel ClocK Internal Master Data Clock Out 1/2 – Signal at 25 MHz Notes: 1. Signal present on both connectors. 2. Pixel is defined as valid (part of the Frame) when both LEN and FEN signals are at a low level. 3. The maximum latency (called Td) after of 1 readout line time defined below depends on the binning mode. In binning 1 x 1 mode, this delay is around 104 µs. 4. Minimum time at high level of the LEN signal is 10 µs (transfer time between two lines). 5. Minimum time at high level of the FEN signal is 4 lines readout time (around 416 µs). 6. Shutter delay is adjustable via Commcam or RS-232 commands (1, 5, 10 or 20 ms). 16 CAMELIA M1 8M LVDS and CameraLink Camera 5319A–IMAGE–04/03 CAMELIA M1 8M LVDS and CameraLink Camera Continuous: T=0 The camera delivers frames continuously: • Frame N+1 integration starts as soon as frame N readout has been completed. • Integration time is set by RS-232. • Video Lines (before and after valid frame) are 4 + 4 for Binning 1 x 1 (and also 1 + 1 for Binning 4 x 4). Figure 8. LVDS Continuous Timing Diagram Frame Shutter Frame readout 2 ms integration delay M Pixels LEN ... ... ... ... Time set by RS-232 Video lines Video lines ... ... ... FEN ... ... ... ... ... SHUTTER Operation with External Integration start is controlled by the user by the external signal TRIG: Trigger: T=1 • The rising edge of TRIG activates the start of frame integration. This rising edge is synchronized by the camera with a latency of Td (time delay equivalent to a readout time for a line: see notes in Table 6 on page 16). • Integration time is set by RS-232. • Note: The TRIG signal period must be greater than the sum of the integration time and frame readout time. • Video Lines (before and after valid frame) are 4 + 4 for Binning 1 x 1 (and also 1 + 1 for Binning 4 x 4). Figure 9. LVDS External Trigger Timing Diagram Frame Shutter integration delay Frame readout Waiting Td ... ... ... ... TRIG M Pixels LEN ... ... ... ... Time set by RS-232 Video lines Video lines ... ... FEN ... ... ... ... ... ... SHUTTER 17 5319A–IMAGE–04/03 Line 1 Line 2 Line 1 Line 2 Line N-1 Line N Line N-1 Line N Operation with Integration Integration is fully controlled by the user by the external signal ITC: Time Control: T=2 • The falling edge of ITC activates the start of frame integration. This falling edge is synchronized by the camera with a latency of Td (time delay equivalent to a readout time for a line: see notes in Table 6 on page 16). • The rising edge of ITC activates the stop of frame integration. This rising edge is synchronized by the camera with the same latency as Td. • Note: The ITC signal period must be greater than the sum of the integration time (defined by ITC low) and frame readout time. • Video Lines (before and after valid frame) are 4 + 4 for Binning 1 x 1 (and also 1 + 1 for Binning 4 x 4). Figure 10. LVDS Integration Time Control Timing Diagram Frame Shutter integration delay Frame readout Waiting Td Td ... ... ... ITC ... M Pixels LEN ... ... ... ... Time set by RS-232 Video lines Video lines ... ... ... FEN ... ... ... ... ... SHUTTER Line Timing • Duty cycle of the PCK is 50% • Rising and falling edges: 1.5 ns • Pixel clock PCK and Data rate are: 25 MHz in binning mode 1 x 1, 12.5 MHz in binning mode 2 x 2 and 6.25 MHz in binning mode 4 x 4 • Minimum setup time of Data, LEN and FEN, to the rising edge of PCK: 10 ns • Minimum hold time of Data, LEN and FEN, after the rising edge of PCK: 10 ns Figure 11. LVDS Line Timing Diagram LEN ... ... PCK ... DATA ... 1st Valid Pixel Last Valid Pixel 18 CAMELIA M1 8M LVDS and CameraLink Camera 5319A–IMAGE–04/03 Line 1 Line 2 Line N-1 Line N CAMELIA M1 8M LVDS and CameraLink Camera CameraLink Camera Three timing modes are available: continuous, external triggered and Integration Time Control (ITC). Timing The signals in the following drawings are described in Table 7: Table 7. CameraLink Frame Timing Camera TTL Cam. Link CONTROL Signal Name Description In/Out Connector Connector LVAL Line VALid High state active when pixel Out yes no is part of line FVAL Frame High state active when lines Out yes no VALid are part of frame (1) SHUTTER SHUTTER External shutter Trig output Out no Pin 1 sync Sig. (high level active) (1) TRIG TRIGger External Trigger Input In CC1+/ Pin 2 (1) Signal (Rising Edge) CC1- (1) ITC Integration External ITC Input Signal In CC1+/ Pin 2 (1) Time Control (Falling/Rising Edges) CC1- PCK Pixel ClocK Internal Master Data Clock Out yes no Signal at 25 MHz Notes: 1. Signal present on both connectors. 2. Pixel is defined as valid (part of the Frame) when both LVAL and FVAL signals are at a high level. 3. The maximum latency (Td) of 1 readout line time defined below depends on the bin- ning mode. In binning 1 x 1 mode, this delay is around 104 µs. 4. Minimum time at low level of LVAL signal is 10 µs (transfer time between two lines). 5. Minimum time at low level of FVAL signal is 4 lines readout time (around 416 µs). 6. Shutter delay is adjustable via serial communication commands (1, 5, 10 or 20 ms). Continuous: T=0 The camera delivers frames continuously: • Frame N+1 integration starts as soon as frame N readout has been completed. • Integration time is set by serial communication. • Video Lines (before and after valid frame) are 4 + 4 for Binning 1 x 1 (and also 1 + 1 for Binning 4 x 4). Figure 12. CameraLink Continuous Timing Diagram Frame Shutter Frame readout 2 ms integration delay M Pixels ... ... ... ... LEN Time set by RS-232 Video lines Video lines ... ... ... ... FEN ... ... ... ... SHUTTER 19 5319A–IMAGE–04/03 Line 1 Line 2 Line N-1 Line N Operation with External Integration start is controlled by the user with the external signal TRIG: Trigger: T=1 • The rising edge of TRIG activates the start of frame integration. This rising edge is synchronized by the camera with a latency of Td (time delay equivalent to a readout time for a line: see notes in Table 7 on page 19). • Integration time is set by serial communication. • Note: The TRIG signal period must be greater than the sum of the integration time and frame readout time. • Video Lines (before and after valid frame) are 4 + 4 for Binning 1 x 1 (and also 1 + 1 for Binning 4 x 4). Figure 13. CameraLink External Trigger Timing Diagram Frame Shutter integration delay Frame readout Waiting Td ... ... ... ... TRIG M Pixels ... ... ... ... LEN Time set by RS-232 Video lines Video lines ... ... ... ... FEN ... ... ... ... SHUTTER Operation with Integration Integration is fully controlled by the user with the external signal ITC: Time Control: T=2 • The falling edge of ITC activates the start of frame integration. This falling edge is synchronized by the camera with a latency of Td (time delay equivalent to a readout time for a line: see notes in Table 7 on page 19). • The rising edge of ITC activates the stop of the frame integration. This rising edge is synchronized by the camera with the same latency of Td. • Note: The ITC signal period must be greater than the sum of the integration time (defined by ITC low) and frame readout time. • Video Lines (before and after valid frame) are 4 + 4 for Binning 1 x 1 (and also 1 + 1 for Binning 4 x 4). Figure 14. CameraLink Integration Time Control Timing Diagram Frame Shutter integration delay Frame readout Waiting Td Td ... ... ... ITC ... M Pixels ... ... ... ... LEN Time set by RS-232 Video lines Video lines ... ... ... ... FEN ... ... ... ... SHUTTER 20 CAMELIA M1 8M LVDS and CameraLink Camera 5319A–IMAGE–04/03 Line 1 Line 1 Line 2 Line 2 Line N-1 Line N-1 Line N Line N CAMELIA M1 8M LVDS and CameraLink Camera Line Timing • Duty cycle of the PCK is 50% • PCK clock rate is 25 MHz • Data rate (Internal pixel clock) is 25 MHz in binning mode 1 x 1 • Mode binning 1 x 1: – Data rate is 25 MHz – DVAL is always in high state Figure 15. CameraLink Line Timing Diagram for Binning 1 x 1 ... LEN ... PCK ... DATA ... 1st Valid Pixel Last Valid Pixel • Mode binning 2 x 2 (and 4 x 4): – Data rate is 12.5 MHz (or 6.25 MHz) Figure 16. CameraLink Line Timing Diagram for Binning 2 x 2 (and 4 x 4) ... LEN ... PCK ... DVAL ... DATA ... 1st Valid Pixel Last Valid Pixel 21 5319A–IMAGE–04/03 Electrical Interfaces DATA & SYNC and TTL CONTROL for LVDS Table 8. Specifications Camera Symbol I/O Definition Level Timing control: - TRIG_ITC is either an external trigger or integration time control (ITC) depending on the timing mode configured via RS-232. (1) Operation with external trigger: LVDS TRIG_ITC I - TRIG_ITC = TRIG and TTL Operation with ITC: - TRIG_ITC = ITC - TRIG_ITC is synchronized by the camera line clock (jitter: 104 µs) PDATA(11..0) O Digital video output: 12-bit LVDS Frame enable: FEN O - FEN = 0: frame data valid: active lines LVDS - FEN = 1: frame data not valid Line enable: LEN O - LEN = 0: line data valid: active pixels LVDS - LEN = 1: line data not valid PCK O Pixel clock LVDS Shutter open/close: - shutter open = 1 - shutter closed = 0 LVDS SHUTTER O and TTL Delay between the falling edge of SHUTTER and the start of readout: - 4 positions: 1, 10, 20 or 40 ms (set via RS-232) Color selection of the next frame (in color mode): - 00: red LVDS COLOUR_I(1..0) I - 01: green and TTL - 10: blue - 11: user defined Color identification of the current frame (in color mode): - 00: red LVDS COLOUR_O(1..0) O - 01: green and TTL - 10: blue - 11: user defined Note: 1. LVDS (Low Voltage differential Signal): EIA 644 standard. All digital I/Os are differential: (signal+, signal-). Specifications are given for signal +. LVDS drivers/receivers: • Manufacturer NS • Driver: DS90LVO47ATMTC (SO16 package) • Receiver: DS90LVO48ATMTC (SO16 package) 22 CAMELIA M1 8M LVDS and CameraLink Camera 5319A–IMAGE–04/03 CAMELIA M1 8M LVDS and CameraLink Camera DATA & SYNC Cabling 50-pin connector: • Connector reference on camera: 3M 10250-6212JL (or 3M 10250-6212VC) • Mating connector on cable side: 3M 10150-6000EL; shell: 3M 10350-A200-00 • We recommend using a twisted pair shielded cable. Table 9. Pinout Pin Pin Number Signal I/O Number Signal I/O 1 PCK+ O 26 LEN+ O 2 PCK- O 27 LEN- O 3 FEN+ O 28 COLOUR_O1+ O 4 FEN- O 29 COLOUR_O1- O 5 COLOUR_O2+ O 30 GROUND O 6 COLOUR_O2- O 31 GROUND O 7 PDATA0+ O 32 PDATA1+ O 8 PDATA0- O 33 PDATA1- O 9 PDATA2+ O 34 PDATA3+ O 10 PDATA2- O 35 PDATA3- O 11 PDATA4+ O 36 PDATA5+ O 12 PDATA4- O 37 PDATA5- O 13 PDATA6+ O 38 PDATA7+ O 14 PDATA6- O 39 PDATA7- O 15 PDATA8+ O 40 PDATA9+ O 16 PDATA8- O 41 PDATA9- O 17 PDATA10+ O 42 PDATA11+ O 18 PDATA10- O 43 PDATA11- O 19 GROUND – 44 NC – 20 GROUND – 45 NC – 21 SHUTTER+ O 46 TRIG_ITC+ I 22 SHUTTER- O 47 TRIG_ITC- I 23 COLOUR_I1+ I 48 COLOUR_I2+ I 24 COLOUR_I1- I 49 COLOUR_I2- I 25 NC – 50 NC – Note: NC: not connected 23 5319A–IMAGE–04/03 TTL CONTROL Cabling The connector on the camera is D-sub 9 pins male. Table 10. Pinout Pin Number At Camera Output Signal Direction 1 SHUTTER Out 2 TRIG-ITC In 3 COLOUR-I1 In 4 COLOUR-I2 In 5 NC – 6 NC – 7 COLOUR-O1 Out 8 COLOUR-O2 Out 9 GROUND – Notes: 1. The following signals: TRIG-ITC, COLOUR-I1, COLOUR-I2 are provided by the DATA & SYNC (MDR50) Connector in LVDS format or by the TTL CONTROL con- nector; the two different signals are logically “anded” as follows: TRIG-ITC from LVDS and TRIG-ITC from TTL. The inputs left open are internally tied to a high level. 2. The SHUTTER, COLOUR-O1 and COLOUR-O2 Outputs are available on both DATA & SYNC and TTL Output Connectors. 24 CAMELIA M1 8M LVDS and CameraLink Camera 5319A–IMAGE–04/03 CAMELIA M1 8M LVDS and CameraLink Camera CAMERALINK and TTL CONTROL for Table 11. Specifications CameraLink Camera Symbol I/O Definition Level Timing control: - TRIG_ITC is either an external trigger or integration time control (ITC) depending on the timing mode configured via serial communication. (5) Operation with external trigger: LVDS (1) TRIG_ITC I - TRIG_ITC = TRIG and TTL Operation with ITC: - TRIG_ITC = ITC - TRIG_ITC is synchronized by the camera line clock (jitter: 104 µs) PDATA(11..0) O Digital video output: 12-bit LVDS Frame enable: FVAL O - FVAL = 1: frame data valid: active lines LVDS - FVAL = 0: frame data not valid Line enable: LVAL O - LVAL = 1: line data valid: active pixels LVDS - LVAL = 0: line data not valid Data Strobe: DVAL O - DVAL = 1: pixel data valid LVDS - DVAL = 0: pixel data not valid PCK O Pixel clock LVDS Shutter open/close: - shutter open = 1 - shutter closed = 0 SHUTTER O TTL Delay between the falling edge of SHUTTER and the start of readout: - 4 positions: 1, 10, 20 or 40 ms (set via serial communication) Color selection of the next frame (in 3-shot color mode): - 00: red LVDS (2)(3) COLOUR_I(1..0) I - 01: green and TTL - 10: blue - 11: user defined Color identification of the current frame (in 3-shot color mode): - 00: red LVDS (4) COLOUR_O(1..0) O - 01: green and TTL - 10: blue - 11: user defined Notes: 1. TRIG_ITC signal is connected on CC1 differential inputs 2. COLOUR_I0 signal is connected on CC2 differential inputs 3. COLOUR_I1 signal is connected on CC3 differential inputs 4. COLOUR_O0 and COLOUR_O1 signals are coded as outputs PDATA(13,12) 5. LVDS (Low Voltage differential Signal): EIA 644 standard 25 5319A–IMAGE–04/03 All digital I/Os are differential: (signal+, signal-). Specifications are given for signal +. CameraLink drivers/receivers: • Driver: NS DS90CR285MTD (SO56 package) • Receiver: NS DS90LVO48ATMTC (SO16 package) CAMERALINK Cabling 26-pin connector: • Connector reference on camera: 3M 10226-2210VE • We recommend using a CameraLink Standard shielded cable such as the 3M 14X26-SZLB-XXX-0LC. Table 12. Pinout Pin Pin Number Signal I/O Number Signal I/O 1 GROUND – 14 GROUND – 2 X0- O 15 X0+ O 3 X1- O 16 X1+ O 4 X2- O 17 X2+ O 5 XCLK- O 18 XCLK+ O 6 X3- O 19 X3+ O 7 SERTC+ I 20 SERTC- I 8 SERTFG- O 21 SERTFG+ O 9 CC1- I 22 CC1+ I 10 CC2+ I 23 CC2- I 11 CC3- I 24 CC3+ I 12 CC4+ I 25 CC4- I 13 GROUND – 26 GROUND – Note: NC: not connected 26 CAMELIA M1 8M LVDS and CameraLink Camera 5319A–IMAGE–04/03 CAMELIA M1 8M LVDS and CameraLink Camera TTL CONTROL Cabling The connector on the camera is D-sub 9 pins male. Table 13. Pinout Pin Number At Camera Output Signal Direction 1 SHUTTER Out 2 TRIG-ITC In 3 COLOUR-I1 In 4 COLOUR-I2 In 5 NC – 6 NC – 7 COLOUR-O1 Out 8 COLOUR-O2 Out 9 GROUND – Notes: 1. The following signals: TRIG-ITC, COLOUR-I1, COLOUR-I2 are provided by the DATA & SYNC (MDR26) connector in LVDS format or by the TTL CONTROL con- nector; the two different signals are logically “anded” as follows: TRIG-ITC from LVDS and TRIG-ITC from TTL. The inputs left open are internally tied to a high level. 2. COLOUR-O1 and COLOUR-O2 Outputs are available on both CameraLink and TTL Output Connectors. RS-232 for LVDS Camera • On camera side: D-sub 9 pins female • On computer: side Dsub9 male, pin out compatible with computer serial port • Note: the cable to be used is a straight pin to pin male-female Table 14. Pinout Pin Number At camera output Signal 1 NC 2 TX 3 RX 4 NC 5 GROUND 6 NC 7 NC 8 NC 9 NC Notes: 1. NC: not connected 2. Pin 7 and 8 are internally shorted. 27 5319A–IMAGE–04/03 Power Supply Specifications Table 15. Power Supply Specifications Parameter Nominal Value Min Value Max Value Voltage +24V +20V +28V Current 0.23A 0.26A 0.20A • Camera connector type: Hirose HR10A-7R-6PB (male) Cabling • Cable connector type: Hirose HR10A-7P-6S (female) Table 16. Pinout Pin Number Signal Pin Number Signal 1 PWR 4 GND 2 NC 5 NC 3 PWR 6 GND Note: NC: not connected Figure 17. Receptacle Viewed from behind the Camera 1 6 2 5 3 4 Caution: Power supply cabling is fully compatible with Atmel’s AviivA Linescan Cam- eras. The cabling is NOT compatible with old Camelia 8M. An internal 1A fuse protects the camera against high currents. An internal diode protects the camera against cabling inversion. Kits of Cable • LVDS-FGT: FGT frame grabber B&W + DATA & SYNC for FGT frame grabber (length 3 meters) + Power Supply (length 10 meters, open on power supply side) + RS-232 (length 3 meters) • CameraLink: CameraLink (length 5 meters) + Power Supply (length 10 meters, open on power supply side) • Connectors LVDS: 3M MDR 50 + HR10A-7P-6S + D-Sub9 male 28 CAMELIA M1 8M LVDS and CameraLink Camera 5319A–IMAGE–04/03 CAMELIA M1 8M LVDS and CameraLink Camera Mechanical Interface LVDS Camera with F Mount Ring Figure 18. With F Mount Ring FRONT PANEL 74 ±0.1 mm 46.5 mm Factory adjusted 37 ± 0.2mm 4 mm 4 x M3 2 x ∅ 2h7 ∅ 66 mm First pixel First line 2 x 1/4 − 20 UNC 2B 25.6 mm 64 ±0.2 mm 5 ±0.3 mm 108 mm 114 mm REAR PANEL 144.5 mm DC 24V LVDS Data & Sync TTL Control RS-232 110.5 mm 29 5319A–IMAGE–04/03 26 ±0.3 mm 6 ±0.2 mm 112 mm // 0.3 64 ±0.2 mm LVDS Camera without F Mount Ring Figure 19. Without F Mount Ring FRONT PANEL 74 ±0.1 mm 37 ± 0.2 mm 4 mm 4 x M3 2 x ∅ 2h7 6.9 ±0.6 mm ∅ 66 mm First pixel 8.9 ±0.45 mm First line 2 x 1/4 − 20 UNC 2B 64 ±0.2 mm 25.6 mm 5 ±0.3 mm 108 mm 114 mm REAR PANEL DC 24V LVDS Data & Sync TTL Control RS-232 110.5 mm 30 CAMELIA M1 8M LVDS and CameraLink Camera 5319A–IMAGE–04/03 26 ±0.3 mm 112 mm 6 ±0.2 mm // 0.3 64 ±0.2 mm M 51 - 5 H pas 0.75 ∅ 56 ±0.1 mm CAMELIA M1 8M LVDS and CameraLink Camera CameraLink Camera with F Mount Ring Figure 20. With F Mount Ring FRONT PANEL 74 ±0.1 mm 46.5 mm Factory adjusted 37 ±0.2 mm 4 mm 4 x M3 2 x ∅ 2h7 ∅ 66 mm First pixel First line 2 x 1/4 − 20 UNC 2B 25.6 mm 64 ±0.2 mm 5 ±0.3 mm 108 mm 114 mm REAR PANEL 144.5 mm CameraLink DC 24V TTL Control 110.5 mm 31 5319A–IMAGE–04/03 26 ±0.3 mm 6 ±0.2 mm 112 mm // 0.3 64 ±0.2 mm CameraLink Camera without F Mount Ring Figure 21. Without F Mount Ring FRONT PANEL 74 ± 0.1 mm 37 ± 0.2 mm 4 mm 4 x M3 2 x ∅ 2h7 6.9 ±0.6 mm ∅ 66 mm First pixel 8.9 ±0.45 mm First line 2 x 1/4 − 20 UNC 2B 64 ±0.2 mm 25.6 mm 5 ±0.3 mm 108 mm 114 mm REAR PANEL CameraLink DC 24V TTL Control 110.5 mm 32 CAMELIA M1 8M LVDS and CameraLink Camera 5319A–IMAGE–04/03 26 ±0.3 mm 6 ±0.2 mm 112 mm // 0.3 64 ±0.2 mm M 51 - 5 H pas 0.75 ∅ 56 ±0.1 mm CAMELIA M1 8M LVDS and CameraLink Camera Mechanical Mounting • Position in the X, Y plan: References – The center pixel of the CCD sensor is positioned within a circle centered on the optical axis and with a diameter of 0.35 mm. The optical axis is defined by the mechanical thread for the optical adapter. – The center pixel of the CCD sensor is referenced to the two needles on the front panel with a tolerance of ±0.125 mm. • Position in the Z plan: – For cameras delivered with an F mount ring, the distance from the CCD sensor plan to the Nikon mount is adjusted in factory at 46.5 mm. – For cameras delivered without the F mount ring, the distance from the CCD sensor plan to the front plan of the thread is 8.9 ±0.45 mm. • Tilt around the Z axis: – All the pixels of the CCD sensor are located between two plans, perpendicular to the optical axis and separated by a maximum distance of 0.26 mm. 33 5319A–IMAGE–04/03 Standard Conformity The cameras have been tested in the following conditions: • Camera with complete Atmel housing • Shielded power supply cable • Shielded and twisted pair data transfer cable • TTL CONTROL cable • Linear AC-DC power supply We recommend using the same configuration to ensure compliance with the following standards. CE conformity The Camelia Camera complies with the European directive 89/336/CEE (EN55022 B/CISPR22 B, EN55024). Class A of EN55022 is obtained without condition. Class B of EN55022 is obtained with ferrite beads on the DATA/SYNC and TTL CONTROL cables. FCC conformity The Camelia Camera complies with Part 15 of FCC rules. Operation is subject to the following two conditions: 1. This device may not cause harmful interference, and 2. This device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide rea- sonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio fre- quency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense. Warning: Changes or modifications to this unit not expressly approved by the party responsible for compliance could void the user's authority to operate this equipment. Ordering Information Table 17. Ordering Code Part Number Description AT71XM1LV8MFERCB0 CAMELIA 8M M1 LVDS Grade E with Housing and F-Mount AT71XM1LV8MFERCA0 CAMELIA 8M M1 LVDS Grade E with Housing and no F-Mount AT71XM1LV8MFERAA0 CAMELIA 8M M1 LVDS Grade E without Mechanics AT71XM1CL8MFERCB0 CAMELIA 8M M1 CameraLink Grade E with Housing and F-Mount AT71XM1CL8MFERCA0 CAMELIA 8M M1 CameraLink Grade E with Housing and no F-Mount AT71XM1CL8MFERAA0 CAMELIA 8M M1 CameraLink Grade E without Mechanics AT71-LV-P2C1D1B2 LVDS-FGT Kit (see “Kits of Cable” on page 28) AT71-LV-P8C8D8A0 Set of LVDS connectors (see “Kits of Cable” on page 28) AT71-CL-P2C0D3A0 CL Kit (see “Kits of Cable” on page 28) 34 CAMELIA M1 8M LVDS and CameraLink Camera 5319A–IMAGE–04/03 Atmel Corporation Atmel Operations 2325 Orchard Parkway Memory RF/Automotive San Jose, CA 95131 2325 Orchard Parkway Theresienstrasse 2 Tel: 1(408) 441-0311 San Jose, CA 95131 Postfach 3535 Fax: 1(408) 487-2600 Tel: 1(408) 441-0311 74025 Heilbronn, Germany Fax: 1(408) 436-4314 Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Regional Headquarters Microcontrollers 2325 Orchard Parkway 1150 East Cheyenne Mtn. Blvd. Europe San Jose, CA 95131 Colorado Springs, CO 80906 Atmel Sarl Tel: 1(408) 441-0311 Tel: 1(719) 576-3300 Route des Arsenaux 41 Fax: 1(408) 436-4314 Fax: 1(719) 540-1759 Case Postale 80 CH-1705 Fribourg La Chantrerie Biometrics/Imaging/Hi-Rel MPU/ Switzerland BP 70602 High Speed Converters/RF Datacom Tel: (41) 26-426-5555 44306 Nantes Cedex 3, France Avenue de Rochepleine Fax: (41) 26-426-5500 Tel: (33) 2-40-18-18-18 BP 123 Fax: (33) 2-40-18-19-60 38521 Saint-Egreve Cedex, France Asia Tel: (33) 4-76-58-30-00 Room 1219 ASIC/ASSP/Smart Cards Fax: (33) 4-76-58-34-80 Chinachem Golden Plaza Zone Industrielle 77 Mody Road Tsimshatsui 13106 Rousset Cedex, France East Kowloon Tel: (33) 4-42-53-60-00 Hong Kong Fax: (33) 4-42-53-60-01 Tel: (852) 2721-9778 Fax: (852) 2722-1369 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 Japan Tel: 1(719) 576-3300 9F, Tonetsu Shinkawa Bldg. Fax: 1(719) 540-1759 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Scottish Enterprise Technology Park Japan Maxwell Building Tel: (81) 3-3523-3551 East Kilbride G75 0QR, Scotland Fax: (81) 3-3523-7581 Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 e-mail literature@atmel.com Web Site http://www.atmel.com Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ® ™ © Atmel Corporation 2003. All rights reserved. Atmel is a registered trademark, and CameraLink and ™ Camelia are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others. Printed on recycled paper. 5319A–IMAGE–04/03 0M